2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
35 #include "dce/dce_10_0_d.h"
36 #include "dce/dce_10_0_sh_mask.h"
37 #include "dce/dce_10_0_enum.h"
38 #include "oss/oss_3_0_d.h"
39 #include "oss/oss_3_0_sh_mask.h"
40 #include "gmc/gmc_8_1_d.h"
41 #include "gmc/gmc_8_1_sh_mask.h"
43 static void dce_v10_0_set_display_funcs(struct amdgpu_device
*adev
);
44 static void dce_v10_0_set_irq_funcs(struct amdgpu_device
*adev
);
46 static const u32 crtc_offsets
[] =
48 CRTC0_REGISTER_OFFSET
,
49 CRTC1_REGISTER_OFFSET
,
50 CRTC2_REGISTER_OFFSET
,
51 CRTC3_REGISTER_OFFSET
,
52 CRTC4_REGISTER_OFFSET
,
53 CRTC5_REGISTER_OFFSET
,
57 static const u32 hpd_offsets
[] =
67 static const uint32_t dig_offsets
[] = {
83 } interrupt_status_offsets
[] = { {
84 .reg
= mmDISP_INTERRUPT_STATUS
,
85 .vblank
= DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK
,
86 .vline
= DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK
,
87 .hpd
= DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
89 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE
,
90 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK
,
91 .vline
= DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK
,
92 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
94 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE2
,
95 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK
,
96 .vline
= DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK
,
97 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
99 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE3
,
100 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK
,
101 .vline
= DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK
,
102 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
104 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE4
,
105 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK
,
106 .vline
= DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK
,
107 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
109 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE5
,
110 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK
,
111 .vline
= DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK
,
112 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
115 static const u32 golden_settings_tonga_a11
[] =
117 mmDCI_CLK_CNTL
, 0x00000080, 0x00000000,
118 mmFBC_DEBUG_COMP
, 0x000000f0, 0x00000070,
119 mmFBC_MISC
, 0x1f311fff, 0x12300000,
120 mmHDMI_CONTROL
, 0x31000111, 0x00000011,
123 static const u32 tonga_mgcg_cgcg_init
[] =
125 mmXDMA_CLOCK_GATING_CNTL
, 0xffffffff, 0x00000100,
126 mmXDMA_MEM_POWER_CNTL
, 0x00000101, 0x00000000,
129 static const u32 golden_settings_fiji_a10
[] =
131 mmDCI_CLK_CNTL
, 0x00000080, 0x00000000,
132 mmFBC_DEBUG_COMP
, 0x000000f0, 0x00000070,
133 mmFBC_MISC
, 0x1f311fff, 0x12300000,
134 mmHDMI_CONTROL
, 0x31000111, 0x00000011,
137 static const u32 fiji_mgcg_cgcg_init
[] =
139 mmXDMA_CLOCK_GATING_CNTL
, 0xffffffff, 0x00000100,
140 mmXDMA_MEM_POWER_CNTL
, 0x00000101, 0x00000000,
143 static void dce_v10_0_init_golden_registers(struct amdgpu_device
*adev
)
145 switch (adev
->asic_type
) {
147 amdgpu_program_register_sequence(adev
,
149 (const u32
)ARRAY_SIZE(fiji_mgcg_cgcg_init
));
150 amdgpu_program_register_sequence(adev
,
151 golden_settings_fiji_a10
,
152 (const u32
)ARRAY_SIZE(golden_settings_fiji_a10
));
155 amdgpu_program_register_sequence(adev
,
156 tonga_mgcg_cgcg_init
,
157 (const u32
)ARRAY_SIZE(tonga_mgcg_cgcg_init
));
158 amdgpu_program_register_sequence(adev
,
159 golden_settings_tonga_a11
,
160 (const u32
)ARRAY_SIZE(golden_settings_tonga_a11
));
167 static u32
dce_v10_0_audio_endpt_rreg(struct amdgpu_device
*adev
,
168 u32 block_offset
, u32 reg
)
173 spin_lock_irqsave(&adev
->audio_endpt_idx_lock
, flags
);
174 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
175 r
= RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA
+ block_offset
);
176 spin_unlock_irqrestore(&adev
->audio_endpt_idx_lock
, flags
);
181 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device
*adev
,
182 u32 block_offset
, u32 reg
, u32 v
)
186 spin_lock_irqsave(&adev
->audio_endpt_idx_lock
, flags
);
187 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
188 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA
+ block_offset
, v
);
189 spin_unlock_irqrestore(&adev
->audio_endpt_idx_lock
, flags
);
192 static bool dce_v10_0_is_in_vblank(struct amdgpu_device
*adev
, int crtc
)
194 if (RREG32(mmCRTC_STATUS
+ crtc_offsets
[crtc
]) &
195 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK
)
201 static bool dce_v10_0_is_counter_moving(struct amdgpu_device
*adev
, int crtc
)
205 pos1
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
206 pos2
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
215 * dce_v10_0_vblank_wait - vblank wait asic callback.
217 * @adev: amdgpu_device pointer
218 * @crtc: crtc to wait for vblank on
220 * Wait for vblank on the requested crtc (evergreen+).
222 static void dce_v10_0_vblank_wait(struct amdgpu_device
*adev
, int crtc
)
226 if (crtc
>= adev
->mode_info
.num_crtc
)
229 if (!(RREG32(mmCRTC_CONTROL
+ crtc_offsets
[crtc
]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK
))
232 /* depending on when we hit vblank, we may be close to active; if so,
233 * wait for another frame.
235 while (dce_v10_0_is_in_vblank(adev
, crtc
)) {
236 if (i
++ % 100 == 0) {
237 if (!dce_v10_0_is_counter_moving(adev
, crtc
))
242 while (!dce_v10_0_is_in_vblank(adev
, crtc
)) {
243 if (i
++ % 100 == 0) {
244 if (!dce_v10_0_is_counter_moving(adev
, crtc
))
250 static u32
dce_v10_0_vblank_get_counter(struct amdgpu_device
*adev
, int crtc
)
252 if (crtc
>= adev
->mode_info
.num_crtc
)
255 return RREG32(mmCRTC_STATUS_FRAME_COUNT
+ crtc_offsets
[crtc
]);
259 * dce_v10_0_page_flip - pageflip callback.
261 * @adev: amdgpu_device pointer
262 * @crtc_id: crtc to cleanup pageflip on
263 * @crtc_base: new address of the crtc (GPU MC address)
265 * Does the actual pageflip (evergreen+).
266 * During vblank we take the crtc lock and wait for the update_pending
267 * bit to go high, when it does, we release the lock, and allow the
268 * double buffered update to take place.
269 * Returns the current update pending status.
271 static void dce_v10_0_page_flip(struct amdgpu_device
*adev
,
272 int crtc_id
, u64 crtc_base
)
274 struct amdgpu_crtc
*amdgpu_crtc
= adev
->mode_info
.crtcs
[crtc_id
];
275 u32 tmp
= RREG32(mmGRPH_UPDATE
+ amdgpu_crtc
->crtc_offset
);
278 /* Lock the graphics update lock */
279 tmp
= REG_SET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
, 1);
280 WREG32(mmGRPH_UPDATE
+ amdgpu_crtc
->crtc_offset
, tmp
);
282 /* update the scanout addresses */
283 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
284 upper_32_bits(crtc_base
));
285 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
286 lower_32_bits(crtc_base
));
288 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
289 upper_32_bits(crtc_base
));
290 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
291 lower_32_bits(crtc_base
));
293 /* Wait for update_pending to go high. */
294 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
295 if (RREG32(mmGRPH_UPDATE
+ amdgpu_crtc
->crtc_offset
) &
296 GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK
)
300 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
302 /* Unlock the lock, so double-buffering can take place inside vblank */
303 tmp
= REG_SET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
, 0);
304 WREG32(mmGRPH_UPDATE
+ amdgpu_crtc
->crtc_offset
, tmp
);
307 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device
*adev
, int crtc
,
308 u32
*vbl
, u32
*position
)
310 if ((crtc
< 0) || (crtc
>= adev
->mode_info
.num_crtc
))
313 *vbl
= RREG32(mmCRTC_V_BLANK_START_END
+ crtc_offsets
[crtc
]);
314 *position
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
320 * dce_v10_0_hpd_sense - hpd sense callback.
322 * @adev: amdgpu_device pointer
323 * @hpd: hpd (hotplug detect) pin
325 * Checks if a digital monitor is connected (evergreen+).
326 * Returns true if connected, false if not connected.
328 static bool dce_v10_0_hpd_sense(struct amdgpu_device
*adev
,
329 enum amdgpu_hpd_id hpd
)
332 bool connected
= false;
357 if (RREG32(mmDC_HPD_INT_STATUS
+ hpd_offsets
[idx
]) &
358 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK
)
365 * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
367 * @adev: amdgpu_device pointer
368 * @hpd: hpd (hotplug detect) pin
370 * Set the polarity of the hpd pin (evergreen+).
372 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device
*adev
,
373 enum amdgpu_hpd_id hpd
)
376 bool connected
= dce_v10_0_hpd_sense(adev
, hpd
);
402 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[idx
]);
404 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_POLARITY
, 0);
406 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_POLARITY
, 1);
407 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[idx
], tmp
);
411 * dce_v10_0_hpd_init - hpd setup callback.
413 * @adev: amdgpu_device pointer
415 * Setup the hpd pins used by the card (evergreen+).
416 * Enable the pin, set the polarity, and enable the hpd interrupts.
418 static void dce_v10_0_hpd_init(struct amdgpu_device
*adev
)
420 struct drm_device
*dev
= adev
->ddev
;
421 struct drm_connector
*connector
;
425 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
426 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
428 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
||
429 connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
430 /* don't try to enable hpd on eDP or LVDS avoid breaking the
431 * aux dp channel on imac and help (but not completely fix)
432 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
433 * also avoid interrupt storms during dpms.
438 switch (amdgpu_connector
->hpd
.hpd
) {
461 tmp
= RREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[idx
]);
462 tmp
= REG_SET_FIELD(tmp
, DC_HPD_CONTROL
, DC_HPD_EN
, 1);
463 WREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[idx
], tmp
);
465 tmp
= RREG32(mmDC_HPD_TOGGLE_FILT_CNTL
+ hpd_offsets
[idx
]);
466 tmp
= REG_SET_FIELD(tmp
, DC_HPD_TOGGLE_FILT_CNTL
,
467 DC_HPD_CONNECT_INT_DELAY
,
468 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS
);
469 tmp
= REG_SET_FIELD(tmp
, DC_HPD_TOGGLE_FILT_CNTL
,
470 DC_HPD_DISCONNECT_INT_DELAY
,
471 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS
);
472 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL
+ hpd_offsets
[idx
], tmp
);
474 dce_v10_0_hpd_set_polarity(adev
, amdgpu_connector
->hpd
.hpd
);
475 amdgpu_irq_get(adev
, &adev
->hpd_irq
,
476 amdgpu_connector
->hpd
.hpd
);
481 * dce_v10_0_hpd_fini - hpd tear down callback.
483 * @adev: amdgpu_device pointer
485 * Tear down the hpd pins used by the card (evergreen+).
486 * Disable the hpd interrupts.
488 static void dce_v10_0_hpd_fini(struct amdgpu_device
*adev
)
490 struct drm_device
*dev
= adev
->ddev
;
491 struct drm_connector
*connector
;
495 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
496 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
498 switch (amdgpu_connector
->hpd
.hpd
) {
521 tmp
= RREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[idx
]);
522 tmp
= REG_SET_FIELD(tmp
, DC_HPD_CONTROL
, DC_HPD_EN
, 0);
523 WREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[idx
], tmp
);
525 amdgpu_irq_put(adev
, &adev
->hpd_irq
,
526 amdgpu_connector
->hpd
.hpd
);
530 static u32
dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device
*adev
)
532 return mmDC_GPIO_HPD_A
;
535 static bool dce_v10_0_is_display_hung(struct amdgpu_device
*adev
)
541 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
542 tmp
= RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]);
543 if (REG_GET_FIELD(tmp
, CRTC_CONTROL
, CRTC_MASTER_EN
)) {
544 crtc_status
[i
] = RREG32(mmCRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
545 crtc_hung
|= (1 << i
);
549 for (j
= 0; j
< 10; j
++) {
550 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
551 if (crtc_hung
& (1 << i
)) {
552 tmp
= RREG32(mmCRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
553 if (tmp
!= crtc_status
[i
])
554 crtc_hung
&= ~(1 << i
);
565 static void dce_v10_0_stop_mc_access(struct amdgpu_device
*adev
,
566 struct amdgpu_mode_mc_save
*save
)
568 u32 crtc_enabled
, tmp
;
571 save
->vga_render_control
= RREG32(mmVGA_RENDER_CONTROL
);
572 save
->vga_hdp_control
= RREG32(mmVGA_HDP_CONTROL
);
574 /* disable VGA render */
575 tmp
= RREG32(mmVGA_RENDER_CONTROL
);
576 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 0);
577 WREG32(mmVGA_RENDER_CONTROL
, tmp
);
579 /* blank the display controllers */
580 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
581 crtc_enabled
= REG_GET_FIELD(RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]),
582 CRTC_CONTROL
, CRTC_MASTER_EN
);
588 save
->crtc_enabled
[i
] = true;
589 tmp
= RREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
]);
590 if (REG_GET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
) == 0) {
591 amdgpu_display_vblank_wait(adev
, i
);
592 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
593 tmp
= REG_SET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
, 1);
594 WREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
], tmp
);
595 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
597 /* wait for the next frame */
598 frame_count
= amdgpu_display_vblank_get_counter(adev
, i
);
599 for (j
= 0; j
< adev
->usec_timeout
; j
++) {
600 if (amdgpu_display_vblank_get_counter(adev
, i
) != frame_count
)
604 tmp
= RREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
]);
605 if (REG_GET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
) == 0) {
606 tmp
= REG_SET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
, 1);
607 WREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
], tmp
);
609 tmp
= RREG32(mmMASTER_UPDATE_LOCK
+ crtc_offsets
[i
]);
610 if (REG_GET_FIELD(tmp
, MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
) == 0) {
611 tmp
= REG_SET_FIELD(tmp
, MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
, 1);
612 WREG32(mmMASTER_UPDATE_LOCK
+ crtc_offsets
[i
], tmp
);
615 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
616 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
617 tmp
= RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]);
618 tmp
= REG_SET_FIELD(tmp
, CRTC_CONTROL
, CRTC_MASTER_EN
, 0);
619 WREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
], tmp
);
620 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
621 save
->crtc_enabled
[i
] = false;
625 save
->crtc_enabled
[i
] = false;
630 static void dce_v10_0_resume_mc_access(struct amdgpu_device
*adev
,
631 struct amdgpu_mode_mc_save
*save
)
633 u32 tmp
, frame_count
;
636 /* update crtc base addresses */
637 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
638 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ crtc_offsets
[i
],
639 upper_32_bits(adev
->mc
.vram_start
));
640 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ crtc_offsets
[i
],
641 upper_32_bits(adev
->mc
.vram_start
));
642 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ crtc_offsets
[i
],
643 (u32
)adev
->mc
.vram_start
);
644 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS
+ crtc_offsets
[i
],
645 (u32
)adev
->mc
.vram_start
);
647 if (save
->crtc_enabled
[i
]) {
648 tmp
= RREG32(mmMASTER_UPDATE_MODE
+ crtc_offsets
[i
]);
649 if (REG_GET_FIELD(tmp
, MASTER_UPDATE_MODE
, MASTER_UPDATE_MODE
) != 3) {
650 tmp
= REG_SET_FIELD(tmp
, MASTER_UPDATE_MODE
, MASTER_UPDATE_MODE
, 3);
651 WREG32(mmMASTER_UPDATE_MODE
+ crtc_offsets
[i
], tmp
);
653 tmp
= RREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
]);
654 if (REG_GET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
)) {
655 tmp
= REG_SET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
, 0);
656 WREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
], tmp
);
658 tmp
= RREG32(mmMASTER_UPDATE_LOCK
+ crtc_offsets
[i
]);
659 if (REG_GET_FIELD(tmp
, MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
)) {
660 tmp
= REG_SET_FIELD(tmp
, MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
, 0);
661 WREG32(mmMASTER_UPDATE_LOCK
+ crtc_offsets
[i
], tmp
);
663 for (j
= 0; j
< adev
->usec_timeout
; j
++) {
664 tmp
= RREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
]);
665 if (REG_GET_FIELD(tmp
, GRPH_UPDATE
, GRPH_SURFACE_UPDATE_PENDING
) == 0)
669 tmp
= RREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
]);
670 tmp
= REG_SET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
, 0);
671 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
672 WREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
], tmp
);
673 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
674 /* wait for the next frame */
675 frame_count
= amdgpu_display_vblank_get_counter(adev
, i
);
676 for (j
= 0; j
< adev
->usec_timeout
; j
++) {
677 if (amdgpu_display_vblank_get_counter(adev
, i
) != frame_count
)
684 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH
, upper_32_bits(adev
->mc
.vram_start
));
685 WREG32(mmVGA_MEMORY_BASE_ADDRESS
, lower_32_bits(adev
->mc
.vram_start
));
687 /* Unlock vga access */
688 WREG32(mmVGA_HDP_CONTROL
, save
->vga_hdp_control
);
690 WREG32(mmVGA_RENDER_CONTROL
, save
->vga_render_control
);
693 static void dce_v10_0_set_vga_render_state(struct amdgpu_device
*adev
,
698 /* Lockout access through VGA aperture*/
699 tmp
= RREG32(mmVGA_HDP_CONTROL
);
701 tmp
= REG_SET_FIELD(tmp
, VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
, 0);
703 tmp
= REG_SET_FIELD(tmp
, VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
, 1);
704 WREG32(mmVGA_HDP_CONTROL
, tmp
);
706 /* disable VGA render */
707 tmp
= RREG32(mmVGA_RENDER_CONTROL
);
709 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 1);
711 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 0);
712 WREG32(mmVGA_RENDER_CONTROL
, tmp
);
715 static void dce_v10_0_program_fmt(struct drm_encoder
*encoder
)
717 struct drm_device
*dev
= encoder
->dev
;
718 struct amdgpu_device
*adev
= dev
->dev_private
;
719 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
720 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
721 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
724 enum amdgpu_connector_dither dither
= AMDGPU_FMT_DITHER_DISABLE
;
727 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
728 bpc
= amdgpu_connector_get_monitor_bpc(connector
);
729 dither
= amdgpu_connector
->dither
;
732 /* LVDS/eDP FMT is set up by atom */
733 if (amdgpu_encoder
->devices
& ATOM_DEVICE_LCD_SUPPORT
)
736 /* not needed for analog */
737 if ((amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
) ||
738 (amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
))
746 if (dither
== AMDGPU_FMT_DITHER_ENABLE
) {
747 /* XXX sort out optimal dither settings */
748 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_FRAME_RANDOM_ENABLE
, 1);
749 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_HIGHPASS_RANDOM_ENABLE
, 1);
750 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_EN
, 1);
751 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_DEPTH
, 0);
753 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_EN
, 1);
754 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_DEPTH
, 0);
758 if (dither
== AMDGPU_FMT_DITHER_ENABLE
) {
759 /* XXX sort out optimal dither settings */
760 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_FRAME_RANDOM_ENABLE
, 1);
761 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_HIGHPASS_RANDOM_ENABLE
, 1);
762 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_RGB_RANDOM_ENABLE
, 1);
763 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_EN
, 1);
764 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_DEPTH
, 1);
766 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_EN
, 1);
767 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_DEPTH
, 1);
771 if (dither
== AMDGPU_FMT_DITHER_ENABLE
) {
772 /* XXX sort out optimal dither settings */
773 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_FRAME_RANDOM_ENABLE
, 1);
774 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_HIGHPASS_RANDOM_ENABLE
, 1);
775 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_RGB_RANDOM_ENABLE
, 1);
776 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_EN
, 1);
777 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_DEPTH
, 2);
779 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_EN
, 1);
780 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_DEPTH
, 2);
788 WREG32(mmFMT_BIT_DEPTH_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
792 /* display watermark setup */
794 * dce_v10_0_line_buffer_adjust - Set up the line buffer
796 * @adev: amdgpu_device pointer
797 * @amdgpu_crtc: the selected display controller
798 * @mode: the current display mode on the selected display
801 * Setup up the line buffer allocation for
802 * the selected display controller (CIK).
803 * Returns the line buffer size in pixels.
805 static u32
dce_v10_0_line_buffer_adjust(struct amdgpu_device
*adev
,
806 struct amdgpu_crtc
*amdgpu_crtc
,
807 struct drm_display_mode
*mode
)
809 u32 tmp
, buffer_alloc
, i
, mem_cfg
;
810 u32 pipe_offset
= amdgpu_crtc
->crtc_id
;
813 * There are 6 line buffers, one for each display controllers.
814 * There are 3 partitions per LB. Select the number of partitions
815 * to enable based on the display width. For display widths larger
816 * than 4096, you need use to use 2 display controllers and combine
817 * them using the stereo blender.
819 if (amdgpu_crtc
->base
.enabled
&& mode
) {
820 if (mode
->crtc_hdisplay
< 1920) {
823 } else if (mode
->crtc_hdisplay
< 2560) {
826 } else if (mode
->crtc_hdisplay
< 4096) {
828 buffer_alloc
= (adev
->flags
& AMD_IS_APU
) ? 2 : 4;
830 DRM_DEBUG_KMS("Mode too big for LB!\n");
832 buffer_alloc
= (adev
->flags
& AMD_IS_APU
) ? 2 : 4;
839 tmp
= RREG32(mmLB_MEMORY_CTRL
+ amdgpu_crtc
->crtc_offset
);
840 tmp
= REG_SET_FIELD(tmp
, LB_MEMORY_CTRL
, LB_MEMORY_CONFIG
, mem_cfg
);
841 WREG32(mmLB_MEMORY_CTRL
+ amdgpu_crtc
->crtc_offset
, tmp
);
843 tmp
= RREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
);
844 tmp
= REG_SET_FIELD(tmp
, PIPE0_DMIF_BUFFER_CONTROL
, DMIF_BUFFERS_ALLOCATED
, buffer_alloc
);
845 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
, tmp
);
847 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
848 tmp
= RREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
);
849 if (REG_GET_FIELD(tmp
, PIPE0_DMIF_BUFFER_CONTROL
, DMIF_BUFFERS_ALLOCATION_COMPLETED
))
854 if (amdgpu_crtc
->base
.enabled
&& mode
) {
866 /* controller not enabled, so no lb used */
871 * cik_get_number_of_dram_channels - get the number of dram channels
873 * @adev: amdgpu_device pointer
875 * Look up the number of video ram channels (CIK).
876 * Used for display watermark bandwidth calculations
877 * Returns the number of dram channels
879 static u32
cik_get_number_of_dram_channels(struct amdgpu_device
*adev
)
881 u32 tmp
= RREG32(mmMC_SHARED_CHMAP
);
883 switch (REG_GET_FIELD(tmp
, MC_SHARED_CHMAP
, NOOFCHAN
)) {
906 struct dce10_wm_params
{
907 u32 dram_channels
; /* number of dram channels */
908 u32 yclk
; /* bandwidth per dram data pin in kHz */
909 u32 sclk
; /* engine clock in kHz */
910 u32 disp_clk
; /* display clock in kHz */
911 u32 src_width
; /* viewport width */
912 u32 active_time
; /* active display time in ns */
913 u32 blank_time
; /* blank time in ns */
914 bool interlaced
; /* mode is interlaced */
915 fixed20_12 vsc
; /* vertical scale ratio */
916 u32 num_heads
; /* number of active crtcs */
917 u32 bytes_per_pixel
; /* bytes per pixel display + overlay */
918 u32 lb_size
; /* line buffer allocated to pipe */
919 u32 vtaps
; /* vertical scaler taps */
923 * dce_v10_0_dram_bandwidth - get the dram bandwidth
925 * @wm: watermark calculation data
927 * Calculate the raw dram bandwidth (CIK).
928 * Used for display watermark bandwidth calculations
929 * Returns the dram bandwidth in MBytes/s
931 static u32
dce_v10_0_dram_bandwidth(struct dce10_wm_params
*wm
)
933 /* Calculate raw DRAM Bandwidth */
934 fixed20_12 dram_efficiency
; /* 0.7 */
935 fixed20_12 yclk
, dram_channels
, bandwidth
;
938 a
.full
= dfixed_const(1000);
939 yclk
.full
= dfixed_const(wm
->yclk
);
940 yclk
.full
= dfixed_div(yclk
, a
);
941 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
942 a
.full
= dfixed_const(10);
943 dram_efficiency
.full
= dfixed_const(7);
944 dram_efficiency
.full
= dfixed_div(dram_efficiency
, a
);
945 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
946 bandwidth
.full
= dfixed_mul(bandwidth
, dram_efficiency
);
948 return dfixed_trunc(bandwidth
);
952 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
954 * @wm: watermark calculation data
956 * Calculate the dram bandwidth used for display (CIK).
957 * Used for display watermark bandwidth calculations
958 * Returns the dram bandwidth for display in MBytes/s
960 static u32
dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params
*wm
)
962 /* Calculate DRAM Bandwidth and the part allocated to display. */
963 fixed20_12 disp_dram_allocation
; /* 0.3 to 0.7 */
964 fixed20_12 yclk
, dram_channels
, bandwidth
;
967 a
.full
= dfixed_const(1000);
968 yclk
.full
= dfixed_const(wm
->yclk
);
969 yclk
.full
= dfixed_div(yclk
, a
);
970 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
971 a
.full
= dfixed_const(10);
972 disp_dram_allocation
.full
= dfixed_const(3); /* XXX worse case value 0.3 */
973 disp_dram_allocation
.full
= dfixed_div(disp_dram_allocation
, a
);
974 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
975 bandwidth
.full
= dfixed_mul(bandwidth
, disp_dram_allocation
);
977 return dfixed_trunc(bandwidth
);
981 * dce_v10_0_data_return_bandwidth - get the data return bandwidth
983 * @wm: watermark calculation data
985 * Calculate the data return bandwidth used for display (CIK).
986 * Used for display watermark bandwidth calculations
987 * Returns the data return bandwidth in MBytes/s
989 static u32
dce_v10_0_data_return_bandwidth(struct dce10_wm_params
*wm
)
991 /* Calculate the display Data return Bandwidth */
992 fixed20_12 return_efficiency
; /* 0.8 */
993 fixed20_12 sclk
, bandwidth
;
996 a
.full
= dfixed_const(1000);
997 sclk
.full
= dfixed_const(wm
->sclk
);
998 sclk
.full
= dfixed_div(sclk
, a
);
999 a
.full
= dfixed_const(10);
1000 return_efficiency
.full
= dfixed_const(8);
1001 return_efficiency
.full
= dfixed_div(return_efficiency
, a
);
1002 a
.full
= dfixed_const(32);
1003 bandwidth
.full
= dfixed_mul(a
, sclk
);
1004 bandwidth
.full
= dfixed_mul(bandwidth
, return_efficiency
);
1006 return dfixed_trunc(bandwidth
);
1010 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
1012 * @wm: watermark calculation data
1014 * Calculate the dmif bandwidth used for display (CIK).
1015 * Used for display watermark bandwidth calculations
1016 * Returns the dmif bandwidth in MBytes/s
1018 static u32
dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params
*wm
)
1020 /* Calculate the DMIF Request Bandwidth */
1021 fixed20_12 disp_clk_request_efficiency
; /* 0.8 */
1022 fixed20_12 disp_clk
, bandwidth
;
1025 a
.full
= dfixed_const(1000);
1026 disp_clk
.full
= dfixed_const(wm
->disp_clk
);
1027 disp_clk
.full
= dfixed_div(disp_clk
, a
);
1028 a
.full
= dfixed_const(32);
1029 b
.full
= dfixed_mul(a
, disp_clk
);
1031 a
.full
= dfixed_const(10);
1032 disp_clk_request_efficiency
.full
= dfixed_const(8);
1033 disp_clk_request_efficiency
.full
= dfixed_div(disp_clk_request_efficiency
, a
);
1035 bandwidth
.full
= dfixed_mul(b
, disp_clk_request_efficiency
);
1037 return dfixed_trunc(bandwidth
);
1041 * dce_v10_0_available_bandwidth - get the min available bandwidth
1043 * @wm: watermark calculation data
1045 * Calculate the min available bandwidth used for display (CIK).
1046 * Used for display watermark bandwidth calculations
1047 * Returns the min available bandwidth in MBytes/s
1049 static u32
dce_v10_0_available_bandwidth(struct dce10_wm_params
*wm
)
1051 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1052 u32 dram_bandwidth
= dce_v10_0_dram_bandwidth(wm
);
1053 u32 data_return_bandwidth
= dce_v10_0_data_return_bandwidth(wm
);
1054 u32 dmif_req_bandwidth
= dce_v10_0_dmif_request_bandwidth(wm
);
1056 return min(dram_bandwidth
, min(data_return_bandwidth
, dmif_req_bandwidth
));
1060 * dce_v10_0_average_bandwidth - get the average available bandwidth
1062 * @wm: watermark calculation data
1064 * Calculate the average available bandwidth used for display (CIK).
1065 * Used for display watermark bandwidth calculations
1066 * Returns the average available bandwidth in MBytes/s
1068 static u32
dce_v10_0_average_bandwidth(struct dce10_wm_params
*wm
)
1070 /* Calculate the display mode Average Bandwidth
1071 * DisplayMode should contain the source and destination dimensions,
1075 fixed20_12 line_time
;
1076 fixed20_12 src_width
;
1077 fixed20_12 bandwidth
;
1080 a
.full
= dfixed_const(1000);
1081 line_time
.full
= dfixed_const(wm
->active_time
+ wm
->blank_time
);
1082 line_time
.full
= dfixed_div(line_time
, a
);
1083 bpp
.full
= dfixed_const(wm
->bytes_per_pixel
);
1084 src_width
.full
= dfixed_const(wm
->src_width
);
1085 bandwidth
.full
= dfixed_mul(src_width
, bpp
);
1086 bandwidth
.full
= dfixed_mul(bandwidth
, wm
->vsc
);
1087 bandwidth
.full
= dfixed_div(bandwidth
, line_time
);
1089 return dfixed_trunc(bandwidth
);
1093 * dce_v10_0_latency_watermark - get the latency watermark
1095 * @wm: watermark calculation data
1097 * Calculate the latency watermark (CIK).
1098 * Used for display watermark bandwidth calculations
1099 * Returns the latency watermark in ns
1101 static u32
dce_v10_0_latency_watermark(struct dce10_wm_params
*wm
)
1103 /* First calculate the latency in ns */
1104 u32 mc_latency
= 2000; /* 2000 ns. */
1105 u32 available_bandwidth
= dce_v10_0_available_bandwidth(wm
);
1106 u32 worst_chunk_return_time
= (512 * 8 * 1000) / available_bandwidth
;
1107 u32 cursor_line_pair_return_time
= (128 * 4 * 1000) / available_bandwidth
;
1108 u32 dc_latency
= 40000000 / wm
->disp_clk
; /* dc pipe latency */
1109 u32 other_heads_data_return_time
= ((wm
->num_heads
+ 1) * worst_chunk_return_time
) +
1110 (wm
->num_heads
* cursor_line_pair_return_time
);
1111 u32 latency
= mc_latency
+ other_heads_data_return_time
+ dc_latency
;
1112 u32 max_src_lines_per_dst_line
, lb_fill_bw
, line_fill_time
;
1113 u32 tmp
, dmif_size
= 12288;
1116 if (wm
->num_heads
== 0)
1119 a
.full
= dfixed_const(2);
1120 b
.full
= dfixed_const(1);
1121 if ((wm
->vsc
.full
> a
.full
) ||
1122 ((wm
->vsc
.full
> b
.full
) && (wm
->vtaps
>= 3)) ||
1124 ((wm
->vsc
.full
>= a
.full
) && wm
->interlaced
))
1125 max_src_lines_per_dst_line
= 4;
1127 max_src_lines_per_dst_line
= 2;
1129 a
.full
= dfixed_const(available_bandwidth
);
1130 b
.full
= dfixed_const(wm
->num_heads
);
1131 a
.full
= dfixed_div(a
, b
);
1133 b
.full
= dfixed_const(mc_latency
+ 512);
1134 c
.full
= dfixed_const(wm
->disp_clk
);
1135 b
.full
= dfixed_div(b
, c
);
1137 c
.full
= dfixed_const(dmif_size
);
1138 b
.full
= dfixed_div(c
, b
);
1140 tmp
= min(dfixed_trunc(a
), dfixed_trunc(b
));
1142 b
.full
= dfixed_const(1000);
1143 c
.full
= dfixed_const(wm
->disp_clk
);
1144 b
.full
= dfixed_div(c
, b
);
1145 c
.full
= dfixed_const(wm
->bytes_per_pixel
);
1146 b
.full
= dfixed_mul(b
, c
);
1148 lb_fill_bw
= min(tmp
, dfixed_trunc(b
));
1150 a
.full
= dfixed_const(max_src_lines_per_dst_line
* wm
->src_width
* wm
->bytes_per_pixel
);
1151 b
.full
= dfixed_const(1000);
1152 c
.full
= dfixed_const(lb_fill_bw
);
1153 b
.full
= dfixed_div(c
, b
);
1154 a
.full
= dfixed_div(a
, b
);
1155 line_fill_time
= dfixed_trunc(a
);
1157 if (line_fill_time
< wm
->active_time
)
1160 return latency
+ (line_fill_time
- wm
->active_time
);
1165 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1166 * average and available dram bandwidth
1168 * @wm: watermark calculation data
1170 * Check if the display average bandwidth fits in the display
1171 * dram bandwidth (CIK).
1172 * Used for display watermark bandwidth calculations
1173 * Returns true if the display fits, false if not.
1175 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params
*wm
)
1177 if (dce_v10_0_average_bandwidth(wm
) <=
1178 (dce_v10_0_dram_bandwidth_for_display(wm
) / wm
->num_heads
))
1185 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
1186 * average and available bandwidth
1188 * @wm: watermark calculation data
1190 * Check if the display average bandwidth fits in the display
1191 * available bandwidth (CIK).
1192 * Used for display watermark bandwidth calculations
1193 * Returns true if the display fits, false if not.
1195 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params
*wm
)
1197 if (dce_v10_0_average_bandwidth(wm
) <=
1198 (dce_v10_0_available_bandwidth(wm
) / wm
->num_heads
))
1205 * dce_v10_0_check_latency_hiding - check latency hiding
1207 * @wm: watermark calculation data
1209 * Check latency hiding (CIK).
1210 * Used for display watermark bandwidth calculations
1211 * Returns true if the display fits, false if not.
1213 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params
*wm
)
1215 u32 lb_partitions
= wm
->lb_size
/ wm
->src_width
;
1216 u32 line_time
= wm
->active_time
+ wm
->blank_time
;
1217 u32 latency_tolerant_lines
;
1221 a
.full
= dfixed_const(1);
1222 if (wm
->vsc
.full
> a
.full
)
1223 latency_tolerant_lines
= 1;
1225 if (lb_partitions
<= (wm
->vtaps
+ 1))
1226 latency_tolerant_lines
= 1;
1228 latency_tolerant_lines
= 2;
1231 latency_hiding
= (latency_tolerant_lines
* line_time
+ wm
->blank_time
);
1233 if (dce_v10_0_latency_watermark(wm
) <= latency_hiding
)
1240 * dce_v10_0_program_watermarks - program display watermarks
1242 * @adev: amdgpu_device pointer
1243 * @amdgpu_crtc: the selected display controller
1244 * @lb_size: line buffer size
1245 * @num_heads: number of display controllers in use
1247 * Calculate and program the display watermarks for the
1248 * selected display controller (CIK).
1250 static void dce_v10_0_program_watermarks(struct amdgpu_device
*adev
,
1251 struct amdgpu_crtc
*amdgpu_crtc
,
1252 u32 lb_size
, u32 num_heads
)
1254 struct drm_display_mode
*mode
= &amdgpu_crtc
->base
.mode
;
1255 struct dce10_wm_params wm_low
, wm_high
;
1258 u32 latency_watermark_a
= 0, latency_watermark_b
= 0;
1261 if (amdgpu_crtc
->base
.enabled
&& num_heads
&& mode
) {
1262 pixel_period
= 1000000 / (u32
)mode
->clock
;
1263 line_time
= min((u32
)mode
->crtc_htotal
* pixel_period
, (u32
)65535);
1265 /* watermark for high clocks */
1266 if (adev
->pm
.dpm_enabled
) {
1268 amdgpu_dpm_get_mclk(adev
, false) * 10;
1270 amdgpu_dpm_get_sclk(adev
, false) * 10;
1272 wm_high
.yclk
= adev
->pm
.current_mclk
* 10;
1273 wm_high
.sclk
= adev
->pm
.current_sclk
* 10;
1276 wm_high
.disp_clk
= mode
->clock
;
1277 wm_high
.src_width
= mode
->crtc_hdisplay
;
1278 wm_high
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
1279 wm_high
.blank_time
= line_time
- wm_high
.active_time
;
1280 wm_high
.interlaced
= false;
1281 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1282 wm_high
.interlaced
= true;
1283 wm_high
.vsc
= amdgpu_crtc
->vsc
;
1285 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
)
1287 wm_high
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1288 wm_high
.lb_size
= lb_size
;
1289 wm_high
.dram_channels
= cik_get_number_of_dram_channels(adev
);
1290 wm_high
.num_heads
= num_heads
;
1292 /* set for high clocks */
1293 latency_watermark_a
= min(dce_v10_0_latency_watermark(&wm_high
), (u32
)65535);
1295 /* possibly force display priority to high */
1296 /* should really do this at mode validation time... */
1297 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high
) ||
1298 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high
) ||
1299 !dce_v10_0_check_latency_hiding(&wm_high
) ||
1300 (adev
->mode_info
.disp_priority
== 2)) {
1301 DRM_DEBUG_KMS("force priority to high\n");
1304 /* watermark for low clocks */
1305 if (adev
->pm
.dpm_enabled
) {
1307 amdgpu_dpm_get_mclk(adev
, true) * 10;
1309 amdgpu_dpm_get_sclk(adev
, true) * 10;
1311 wm_low
.yclk
= adev
->pm
.current_mclk
* 10;
1312 wm_low
.sclk
= adev
->pm
.current_sclk
* 10;
1315 wm_low
.disp_clk
= mode
->clock
;
1316 wm_low
.src_width
= mode
->crtc_hdisplay
;
1317 wm_low
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
1318 wm_low
.blank_time
= line_time
- wm_low
.active_time
;
1319 wm_low
.interlaced
= false;
1320 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1321 wm_low
.interlaced
= true;
1322 wm_low
.vsc
= amdgpu_crtc
->vsc
;
1324 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
)
1326 wm_low
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1327 wm_low
.lb_size
= lb_size
;
1328 wm_low
.dram_channels
= cik_get_number_of_dram_channels(adev
);
1329 wm_low
.num_heads
= num_heads
;
1331 /* set for low clocks */
1332 latency_watermark_b
= min(dce_v10_0_latency_watermark(&wm_low
), (u32
)65535);
1334 /* possibly force display priority to high */
1335 /* should really do this at mode validation time... */
1336 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low
) ||
1337 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low
) ||
1338 !dce_v10_0_check_latency_hiding(&wm_low
) ||
1339 (adev
->mode_info
.disp_priority
== 2)) {
1340 DRM_DEBUG_KMS("force priority to high\n");
1345 wm_mask
= RREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1346 tmp
= REG_SET_FIELD(wm_mask
, DPG_WATERMARK_MASK_CONTROL
, URGENCY_WATERMARK_MASK
, 1);
1347 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1348 tmp
= RREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1349 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_LOW_WATERMARK
, latency_watermark_a
);
1350 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_HIGH_WATERMARK
, line_time
);
1351 WREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1353 tmp
= REG_SET_FIELD(wm_mask
, DPG_WATERMARK_MASK_CONTROL
, URGENCY_WATERMARK_MASK
, 2);
1354 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1355 tmp
= RREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1356 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_LOW_WATERMARK
, latency_watermark_a
);
1357 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_HIGH_WATERMARK
, line_time
);
1358 WREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1359 /* restore original selection */
1360 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, wm_mask
);
1362 /* save values for DPM */
1363 amdgpu_crtc
->line_time
= line_time
;
1364 amdgpu_crtc
->wm_high
= latency_watermark_a
;
1365 amdgpu_crtc
->wm_low
= latency_watermark_b
;
1369 * dce_v10_0_bandwidth_update - program display watermarks
1371 * @adev: amdgpu_device pointer
1373 * Calculate and program the display watermarks and line
1374 * buffer allocation (CIK).
1376 static void dce_v10_0_bandwidth_update(struct amdgpu_device
*adev
)
1378 struct drm_display_mode
*mode
= NULL
;
1379 u32 num_heads
= 0, lb_size
;
1382 amdgpu_update_display_priority(adev
);
1384 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
1385 if (adev
->mode_info
.crtcs
[i
]->base
.enabled
)
1388 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
1389 mode
= &adev
->mode_info
.crtcs
[i
]->base
.mode
;
1390 lb_size
= dce_v10_0_line_buffer_adjust(adev
, adev
->mode_info
.crtcs
[i
], mode
);
1391 dce_v10_0_program_watermarks(adev
, adev
->mode_info
.crtcs
[i
],
1392 lb_size
, num_heads
);
1396 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device
*adev
)
1401 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1402 offset
= adev
->mode_info
.audio
.pin
[i
].offset
;
1403 tmp
= RREG32_AUDIO_ENDPT(offset
,
1404 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
);
1406 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
) >>
1407 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
) == 1)
1408 adev
->mode_info
.audio
.pin
[i
].connected
= false;
1410 adev
->mode_info
.audio
.pin
[i
].connected
= true;
1414 static struct amdgpu_audio_pin
*dce_v10_0_audio_get_pin(struct amdgpu_device
*adev
)
1418 dce_v10_0_audio_get_connected_pins(adev
);
1420 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1421 if (adev
->mode_info
.audio
.pin
[i
].connected
)
1422 return &adev
->mode_info
.audio
.pin
[i
];
1424 DRM_ERROR("No connected audio pins found!\n");
1428 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder
*encoder
)
1430 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1431 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1432 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1435 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1438 tmp
= RREG32(mmAFMT_AUDIO_SRC_CONTROL
+ dig
->afmt
->offset
);
1439 tmp
= REG_SET_FIELD(tmp
, AFMT_AUDIO_SRC_CONTROL
, AFMT_AUDIO_SRC_SELECT
, dig
->afmt
->pin
->id
);
1440 WREG32(mmAFMT_AUDIO_SRC_CONTROL
+ dig
->afmt
->offset
, tmp
);
1443 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder
*encoder
,
1444 struct drm_display_mode
*mode
)
1446 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1447 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1448 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1449 struct drm_connector
*connector
;
1450 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1454 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1457 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1458 if (connector
->encoder
== encoder
) {
1459 amdgpu_connector
= to_amdgpu_connector(connector
);
1464 if (!amdgpu_connector
) {
1465 DRM_ERROR("Couldn't find encoder's connector\n");
1469 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1471 if (connector
->latency_present
[interlace
]) {
1472 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1473 VIDEO_LIPSYNC
, connector
->video_latency
[interlace
]);
1474 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1475 AUDIO_LIPSYNC
, connector
->audio_latency
[interlace
]);
1477 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1479 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1482 WREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
,
1483 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
, tmp
);
1486 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder
*encoder
)
1488 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1489 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1490 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1491 struct drm_connector
*connector
;
1492 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1497 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1500 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1501 if (connector
->encoder
== encoder
) {
1502 amdgpu_connector
= to_amdgpu_connector(connector
);
1507 if (!amdgpu_connector
) {
1508 DRM_ERROR("Couldn't find encoder's connector\n");
1512 sad_count
= drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector
), &sadb
);
1513 if (sad_count
< 0) {
1514 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count
);
1518 /* program the speaker allocation */
1519 tmp
= RREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
,
1520 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
);
1521 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1524 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1525 HDMI_CONNECTION
, 1);
1527 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1528 SPEAKER_ALLOCATION
, sadb
[0]);
1530 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1531 SPEAKER_ALLOCATION
, 5); /* stereo */
1532 WREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
,
1533 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
, tmp
);
1538 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder
*encoder
)
1540 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1541 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1542 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1543 struct drm_connector
*connector
;
1544 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1545 struct cea_sad
*sads
;
1548 static const u16 eld_reg_to_type
[][2] = {
1549 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
, HDMI_AUDIO_CODING_TYPE_PCM
},
1550 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
, HDMI_AUDIO_CODING_TYPE_AC3
},
1551 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
, HDMI_AUDIO_CODING_TYPE_MPEG1
},
1552 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
, HDMI_AUDIO_CODING_TYPE_MP3
},
1553 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
, HDMI_AUDIO_CODING_TYPE_MPEG2
},
1554 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
, HDMI_AUDIO_CODING_TYPE_AAC_LC
},
1555 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
, HDMI_AUDIO_CODING_TYPE_DTS
},
1556 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
, HDMI_AUDIO_CODING_TYPE_ATRAC
},
1557 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
, HDMI_AUDIO_CODING_TYPE_EAC3
},
1558 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
, HDMI_AUDIO_CODING_TYPE_DTS_HD
},
1559 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
, HDMI_AUDIO_CODING_TYPE_MLP
},
1560 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
, HDMI_AUDIO_CODING_TYPE_WMA_PRO
},
1563 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1566 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1567 if (connector
->encoder
== encoder
) {
1568 amdgpu_connector
= to_amdgpu_connector(connector
);
1573 if (!amdgpu_connector
) {
1574 DRM_ERROR("Couldn't find encoder's connector\n");
1578 sad_count
= drm_edid_to_sad(amdgpu_connector_edid(connector
), &sads
);
1579 if (sad_count
<= 0) {
1580 DRM_ERROR("Couldn't read SADs: %d\n", sad_count
);
1585 for (i
= 0; i
< ARRAY_SIZE(eld_reg_to_type
); i
++) {
1587 u8 stereo_freqs
= 0;
1588 int max_channels
= -1;
1591 for (j
= 0; j
< sad_count
; j
++) {
1592 struct cea_sad
*sad
= &sads
[j
];
1594 if (sad
->format
== eld_reg_to_type
[i
][1]) {
1595 if (sad
->channels
> max_channels
) {
1596 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1597 MAX_CHANNELS
, sad
->channels
);
1598 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1599 DESCRIPTOR_BYTE_2
, sad
->byte2
);
1600 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1601 SUPPORTED_FREQUENCIES
, sad
->freq
);
1602 max_channels
= sad
->channels
;
1605 if (sad
->format
== HDMI_AUDIO_CODING_TYPE_PCM
)
1606 stereo_freqs
|= sad
->freq
;
1612 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1613 SUPPORTED_FREQUENCIES_STEREO
, stereo_freqs
);
1614 WREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
, eld_reg_to_type
[i
][0], tmp
);
1620 static void dce_v10_0_audio_enable(struct amdgpu_device
*adev
,
1621 struct amdgpu_audio_pin
*pin
,
1627 WREG32_AUDIO_ENDPT(pin
->offset
, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
,
1628 enable
? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
: 0);
1631 static const u32 pin_offsets
[] =
1633 AUD0_REGISTER_OFFSET
,
1634 AUD1_REGISTER_OFFSET
,
1635 AUD2_REGISTER_OFFSET
,
1636 AUD3_REGISTER_OFFSET
,
1637 AUD4_REGISTER_OFFSET
,
1638 AUD5_REGISTER_OFFSET
,
1639 AUD6_REGISTER_OFFSET
,
1642 static int dce_v10_0_audio_init(struct amdgpu_device
*adev
)
1649 adev
->mode_info
.audio
.enabled
= true;
1651 adev
->mode_info
.audio
.num_pins
= 7;
1653 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1654 adev
->mode_info
.audio
.pin
[i
].channels
= -1;
1655 adev
->mode_info
.audio
.pin
[i
].rate
= -1;
1656 adev
->mode_info
.audio
.pin
[i
].bits_per_sample
= -1;
1657 adev
->mode_info
.audio
.pin
[i
].status_bits
= 0;
1658 adev
->mode_info
.audio
.pin
[i
].category_code
= 0;
1659 adev
->mode_info
.audio
.pin
[i
].connected
= false;
1660 adev
->mode_info
.audio
.pin
[i
].offset
= pin_offsets
[i
];
1661 adev
->mode_info
.audio
.pin
[i
].id
= i
;
1662 /* disable audio. it will be set up later */
1663 /* XXX remove once we switch to ip funcs */
1664 dce_v10_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
1670 static void dce_v10_0_audio_fini(struct amdgpu_device
*adev
)
1674 if (!adev
->mode_info
.audio
.enabled
)
1677 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++)
1678 dce_v10_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
1680 adev
->mode_info
.audio
.enabled
= false;
1684 * update the N and CTS parameters for a given pixel clock rate
1686 static void dce_v10_0_afmt_update_ACR(struct drm_encoder
*encoder
, uint32_t clock
)
1688 struct drm_device
*dev
= encoder
->dev
;
1689 struct amdgpu_device
*adev
= dev
->dev_private
;
1690 struct amdgpu_afmt_acr acr
= amdgpu_afmt_acr(clock
);
1691 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1692 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1695 tmp
= RREG32(mmHDMI_ACR_32_0
+ dig
->afmt
->offset
);
1696 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_32_0
, HDMI_ACR_CTS_32
, acr
.cts_32khz
);
1697 WREG32(mmHDMI_ACR_32_0
+ dig
->afmt
->offset
, tmp
);
1698 tmp
= RREG32(mmHDMI_ACR_32_1
+ dig
->afmt
->offset
);
1699 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_32_1
, HDMI_ACR_N_32
, acr
.n_32khz
);
1700 WREG32(mmHDMI_ACR_32_1
+ dig
->afmt
->offset
, tmp
);
1702 tmp
= RREG32(mmHDMI_ACR_44_0
+ dig
->afmt
->offset
);
1703 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_44_0
, HDMI_ACR_CTS_44
, acr
.cts_44_1khz
);
1704 WREG32(mmHDMI_ACR_44_0
+ dig
->afmt
->offset
, tmp
);
1705 tmp
= RREG32(mmHDMI_ACR_44_1
+ dig
->afmt
->offset
);
1706 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_44_1
, HDMI_ACR_N_44
, acr
.n_44_1khz
);
1707 WREG32(mmHDMI_ACR_44_1
+ dig
->afmt
->offset
, tmp
);
1709 tmp
= RREG32(mmHDMI_ACR_48_0
+ dig
->afmt
->offset
);
1710 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_48_0
, HDMI_ACR_CTS_48
, acr
.cts_48khz
);
1711 WREG32(mmHDMI_ACR_48_0
+ dig
->afmt
->offset
, tmp
);
1712 tmp
= RREG32(mmHDMI_ACR_48_1
+ dig
->afmt
->offset
);
1713 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_48_1
, HDMI_ACR_N_48
, acr
.n_48khz
);
1714 WREG32(mmHDMI_ACR_48_1
+ dig
->afmt
->offset
, tmp
);
1719 * build a HDMI Video Info Frame
1721 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder
*encoder
,
1722 void *buffer
, size_t size
)
1724 struct drm_device
*dev
= encoder
->dev
;
1725 struct amdgpu_device
*adev
= dev
->dev_private
;
1726 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1727 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1728 uint8_t *frame
= buffer
+ 3;
1729 uint8_t *header
= buffer
;
1731 WREG32(mmAFMT_AVI_INFO0
+ dig
->afmt
->offset
,
1732 frame
[0x0] | (frame
[0x1] << 8) | (frame
[0x2] << 16) | (frame
[0x3] << 24));
1733 WREG32(mmAFMT_AVI_INFO1
+ dig
->afmt
->offset
,
1734 frame
[0x4] | (frame
[0x5] << 8) | (frame
[0x6] << 16) | (frame
[0x7] << 24));
1735 WREG32(mmAFMT_AVI_INFO2
+ dig
->afmt
->offset
,
1736 frame
[0x8] | (frame
[0x9] << 8) | (frame
[0xA] << 16) | (frame
[0xB] << 24));
1737 WREG32(mmAFMT_AVI_INFO3
+ dig
->afmt
->offset
,
1738 frame
[0xC] | (frame
[0xD] << 8) | (header
[1] << 24));
1741 static void dce_v10_0_audio_set_dto(struct drm_encoder
*encoder
, u32 clock
)
1743 struct drm_device
*dev
= encoder
->dev
;
1744 struct amdgpu_device
*adev
= dev
->dev_private
;
1745 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1746 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1747 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1748 u32 dto_phase
= 24 * 1000;
1749 u32 dto_modulo
= clock
;
1752 if (!dig
|| !dig
->afmt
)
1755 /* XXX two dtos; generally use dto0 for hdmi */
1756 /* Express [24MHz / target pixel clock] as an exact rational
1757 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1758 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1760 tmp
= RREG32(mmDCCG_AUDIO_DTO_SOURCE
);
1761 tmp
= REG_SET_FIELD(tmp
, DCCG_AUDIO_DTO_SOURCE
, DCCG_AUDIO_DTO0_SOURCE_SEL
,
1762 amdgpu_crtc
->crtc_id
);
1763 WREG32(mmDCCG_AUDIO_DTO_SOURCE
, tmp
);
1764 WREG32(mmDCCG_AUDIO_DTO0_PHASE
, dto_phase
);
1765 WREG32(mmDCCG_AUDIO_DTO0_MODULE
, dto_modulo
);
1769 * update the info frames with the data from the current display mode
1771 static void dce_v10_0_afmt_setmode(struct drm_encoder
*encoder
,
1772 struct drm_display_mode
*mode
)
1774 struct drm_device
*dev
= encoder
->dev
;
1775 struct amdgpu_device
*adev
= dev
->dev_private
;
1776 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1777 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1778 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
1779 u8 buffer
[HDMI_INFOFRAME_HEADER_SIZE
+ HDMI_AVI_INFOFRAME_SIZE
];
1780 struct hdmi_avi_infoframe frame
;
1785 if (!dig
|| !dig
->afmt
)
1788 /* Silent, r600_hdmi_enable will raise WARN for us */
1789 if (!dig
->afmt
->enabled
)
1792 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1793 if (encoder
->crtc
) {
1794 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1795 bpc
= amdgpu_crtc
->bpc
;
1798 /* disable audio prior to setting up hw */
1799 dig
->afmt
->pin
= dce_v10_0_audio_get_pin(adev
);
1800 dce_v10_0_audio_enable(adev
, dig
->afmt
->pin
, false);
1802 dce_v10_0_audio_set_dto(encoder
, mode
->clock
);
1804 tmp
= RREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
);
1805 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_NULL_SEND
, 1);
1806 WREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
); /* send null packets when required */
1808 WREG32(mmAFMT_AUDIO_CRC_CONTROL
+ dig
->afmt
->offset
, 0x1000);
1810 tmp
= RREG32(mmHDMI_CONTROL
+ dig
->afmt
->offset
);
1817 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_ENABLE
, 0);
1818 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 0);
1819 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1820 connector
->name
, bpc
);
1823 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_ENABLE
, 1);
1824 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 1);
1825 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1829 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_ENABLE
, 1);
1830 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 2);
1831 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1835 WREG32(mmHDMI_CONTROL
+ dig
->afmt
->offset
, tmp
);
1837 tmp
= RREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
);
1838 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_NULL_SEND
, 1); /* send null packets when required */
1839 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_GC_SEND
, 1); /* send general control packets */
1840 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_GC_CONT
, 1); /* send general control packets every frame */
1841 WREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1843 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
);
1844 /* enable audio info frames (frames won't be set until audio is enabled) */
1845 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AUDIO_INFO_SEND
, 1);
1846 /* required for audio info values to be updated */
1847 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AUDIO_INFO_CONT
, 1);
1848 WREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, tmp
);
1850 tmp
= RREG32(mmAFMT_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
);
1851 /* required for audio info values to be updated */
1852 tmp
= REG_SET_FIELD(tmp
, AFMT_INFOFRAME_CONTROL0
, AFMT_AUDIO_INFO_UPDATE
, 1);
1853 WREG32(mmAFMT_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, tmp
);
1855 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
);
1856 /* anything other than 0 */
1857 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL1
, HDMI_AUDIO_INFO_LINE
, 2);
1858 WREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
, tmp
);
1860 WREG32(mmHDMI_GC
+ dig
->afmt
->offset
, 0); /* unset HDMI_GC_AVMUTE */
1862 tmp
= RREG32(mmHDMI_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
);
1863 /* set the default audio delay */
1864 tmp
= REG_SET_FIELD(tmp
, HDMI_AUDIO_PACKET_CONTROL
, HDMI_AUDIO_DELAY_EN
, 1);
1865 /* should be suffient for all audio modes and small enough for all hblanks */
1866 tmp
= REG_SET_FIELD(tmp
, HDMI_AUDIO_PACKET_CONTROL
, HDMI_AUDIO_PACKETS_PER_LINE
, 3);
1867 WREG32(mmHDMI_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1869 tmp
= RREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
);
1870 /* allow 60958 channel status fields to be updated */
1871 tmp
= REG_SET_FIELD(tmp
, AFMT_AUDIO_PACKET_CONTROL
, AFMT_60958_CS_UPDATE
, 1);
1872 WREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1874 tmp
= RREG32(mmHDMI_ACR_PACKET_CONTROL
+ dig
->afmt
->offset
);
1876 /* clear SW CTS value */
1877 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_PACKET_CONTROL
, HDMI_ACR_SOURCE
, 0);
1879 /* select SW CTS value */
1880 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_PACKET_CONTROL
, HDMI_ACR_SOURCE
, 1);
1881 /* allow hw to sent ACR packets when required */
1882 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_PACKET_CONTROL
, HDMI_ACR_AUTO_SEND
, 1);
1883 WREG32(mmHDMI_ACR_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1885 dce_v10_0_afmt_update_ACR(encoder
, mode
->clock
);
1887 tmp
= RREG32(mmAFMT_60958_0
+ dig
->afmt
->offset
);
1888 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_0
, AFMT_60958_CS_CHANNEL_NUMBER_L
, 1);
1889 WREG32(mmAFMT_60958_0
+ dig
->afmt
->offset
, tmp
);
1891 tmp
= RREG32(mmAFMT_60958_1
+ dig
->afmt
->offset
);
1892 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_1
, AFMT_60958_CS_CHANNEL_NUMBER_R
, 2);
1893 WREG32(mmAFMT_60958_1
+ dig
->afmt
->offset
, tmp
);
1895 tmp
= RREG32(mmAFMT_60958_2
+ dig
->afmt
->offset
);
1896 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_2
, 3);
1897 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_3
, 4);
1898 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_4
, 5);
1899 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_5
, 6);
1900 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_6
, 7);
1901 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_7
, 8);
1902 WREG32(mmAFMT_60958_2
+ dig
->afmt
->offset
, tmp
);
1904 dce_v10_0_audio_write_speaker_allocation(encoder
);
1906 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2
+ dig
->afmt
->offset
,
1907 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT
));
1909 dce_v10_0_afmt_audio_select_pin(encoder
);
1910 dce_v10_0_audio_write_sad_regs(encoder
);
1911 dce_v10_0_audio_write_latency_fields(encoder
, mode
);
1913 err
= drm_hdmi_avi_infoframe_from_display_mode(&frame
, mode
);
1915 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err
);
1919 err
= hdmi_avi_infoframe_pack(&frame
, buffer
, sizeof(buffer
));
1921 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err
);
1925 dce_v10_0_afmt_update_avi_infoframe(encoder
, buffer
, sizeof(buffer
));
1927 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
);
1928 /* enable AVI info frames */
1929 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AVI_INFO_SEND
, 1);
1930 /* required for audio info values to be updated */
1931 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AVI_INFO_CONT
, 1);
1932 WREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, tmp
);
1934 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
);
1935 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL1
, HDMI_AVI_INFO_LINE
, 2);
1936 WREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
, tmp
);
1938 tmp
= RREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
);
1939 /* send audio packets */
1940 tmp
= REG_SET_FIELD(tmp
, AFMT_AUDIO_PACKET_CONTROL
, AFMT_AUDIO_SAMPLE_SEND
, 1);
1941 WREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1943 WREG32(mmAFMT_RAMP_CONTROL0
+ dig
->afmt
->offset
, 0x00FFFFFF);
1944 WREG32(mmAFMT_RAMP_CONTROL1
+ dig
->afmt
->offset
, 0x007FFFFF);
1945 WREG32(mmAFMT_RAMP_CONTROL2
+ dig
->afmt
->offset
, 0x00000001);
1946 WREG32(mmAFMT_RAMP_CONTROL3
+ dig
->afmt
->offset
, 0x00000001);
1948 /* enable audio after to setting up hw */
1949 dce_v10_0_audio_enable(adev
, dig
->afmt
->pin
, true);
1952 static void dce_v10_0_afmt_enable(struct drm_encoder
*encoder
, bool enable
)
1954 struct drm_device
*dev
= encoder
->dev
;
1955 struct amdgpu_device
*adev
= dev
->dev_private
;
1956 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1957 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1959 if (!dig
|| !dig
->afmt
)
1962 /* Silent, r600_hdmi_enable will raise WARN for us */
1963 if (enable
&& dig
->afmt
->enabled
)
1965 if (!enable
&& !dig
->afmt
->enabled
)
1968 if (!enable
&& dig
->afmt
->pin
) {
1969 dce_v10_0_audio_enable(adev
, dig
->afmt
->pin
, false);
1970 dig
->afmt
->pin
= NULL
;
1973 dig
->afmt
->enabled
= enable
;
1975 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1976 enable
? "En" : "Dis", dig
->afmt
->offset
, amdgpu_encoder
->encoder_id
);
1979 static void dce_v10_0_afmt_init(struct amdgpu_device
*adev
)
1983 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++)
1984 adev
->mode_info
.afmt
[i
] = NULL
;
1986 /* DCE10 has audio blocks tied to DIG encoders */
1987 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++) {
1988 adev
->mode_info
.afmt
[i
] = kzalloc(sizeof(struct amdgpu_afmt
), GFP_KERNEL
);
1989 if (adev
->mode_info
.afmt
[i
]) {
1990 adev
->mode_info
.afmt
[i
]->offset
= dig_offsets
[i
];
1991 adev
->mode_info
.afmt
[i
]->id
= i
;
1996 static void dce_v10_0_afmt_fini(struct amdgpu_device
*adev
)
2000 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++) {
2001 kfree(adev
->mode_info
.afmt
[i
]);
2002 adev
->mode_info
.afmt
[i
] = NULL
;
2006 static const u32 vga_control_regs
[6] =
2016 static void dce_v10_0_vga_enable(struct drm_crtc
*crtc
, bool enable
)
2018 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2019 struct drm_device
*dev
= crtc
->dev
;
2020 struct amdgpu_device
*adev
= dev
->dev_private
;
2023 vga_control
= RREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
]) & ~1;
2025 WREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
], vga_control
| 1);
2027 WREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
], vga_control
);
2030 static void dce_v10_0_grph_enable(struct drm_crtc
*crtc
, bool enable
)
2032 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2033 struct drm_device
*dev
= crtc
->dev
;
2034 struct amdgpu_device
*adev
= dev
->dev_private
;
2037 WREG32(mmGRPH_ENABLE
+ amdgpu_crtc
->crtc_offset
, 1);
2039 WREG32(mmGRPH_ENABLE
+ amdgpu_crtc
->crtc_offset
, 0);
2042 static int dce_v10_0_crtc_do_set_base(struct drm_crtc
*crtc
,
2043 struct drm_framebuffer
*fb
,
2044 int x
, int y
, int atomic
)
2046 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2047 struct drm_device
*dev
= crtc
->dev
;
2048 struct amdgpu_device
*adev
= dev
->dev_private
;
2049 struct amdgpu_framebuffer
*amdgpu_fb
;
2050 struct drm_framebuffer
*target_fb
;
2051 struct drm_gem_object
*obj
;
2052 struct amdgpu_bo
*rbo
;
2053 uint64_t fb_location
, tiling_flags
;
2054 uint32_t fb_format
, fb_pitch_pixels
;
2055 u32 fb_swap
= REG_SET_FIELD(0, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
, ENDIAN_NONE
);
2057 u32 tmp
, viewport_w
, viewport_h
;
2059 bool bypass_lut
= false;
2062 if (!atomic
&& !crtc
->primary
->fb
) {
2063 DRM_DEBUG_KMS("No FB bound\n");
2068 amdgpu_fb
= to_amdgpu_framebuffer(fb
);
2072 amdgpu_fb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
2073 target_fb
= crtc
->primary
->fb
;
2076 /* If atomic, assume fb object is pinned & idle & fenced and
2077 * just update base pointers
2079 obj
= amdgpu_fb
->obj
;
2080 rbo
= gem_to_amdgpu_bo(obj
);
2081 r
= amdgpu_bo_reserve(rbo
, false);
2082 if (unlikely(r
!= 0))
2086 fb_location
= amdgpu_bo_gpu_offset(rbo
);
2088 r
= amdgpu_bo_pin(rbo
, AMDGPU_GEM_DOMAIN_VRAM
, &fb_location
);
2089 if (unlikely(r
!= 0)) {
2090 amdgpu_bo_unreserve(rbo
);
2095 amdgpu_bo_get_tiling_flags(rbo
, &tiling_flags
);
2096 amdgpu_bo_unreserve(rbo
);
2098 pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
2100 switch (target_fb
->pixel_format
) {
2102 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 0);
2103 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
2105 case DRM_FORMAT_XRGB4444
:
2106 case DRM_FORMAT_ARGB4444
:
2107 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
2108 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 2);
2110 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2114 case DRM_FORMAT_XRGB1555
:
2115 case DRM_FORMAT_ARGB1555
:
2116 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
2117 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
2119 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2123 case DRM_FORMAT_BGRX5551
:
2124 case DRM_FORMAT_BGRA5551
:
2125 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
2126 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 5);
2128 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2132 case DRM_FORMAT_RGB565
:
2133 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
2134 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 1);
2136 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2140 case DRM_FORMAT_XRGB8888
:
2141 case DRM_FORMAT_ARGB8888
:
2142 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
2143 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
2145 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2149 case DRM_FORMAT_XRGB2101010
:
2150 case DRM_FORMAT_ARGB2101010
:
2151 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
2152 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 1);
2154 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2157 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2160 case DRM_FORMAT_BGRX1010102
:
2161 case DRM_FORMAT_BGRA1010102
:
2162 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
2163 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 4);
2165 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2168 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2172 DRM_ERROR("Unsupported screen format %s\n",
2173 drm_get_format_name(target_fb
->pixel_format
));
2177 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == ARRAY_2D_TILED_THIN1
) {
2178 unsigned bankw
, bankh
, mtaspect
, tile_split
, num_banks
;
2180 bankw
= AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
2181 bankh
= AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
2182 mtaspect
= AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
2183 tile_split
= AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
);
2184 num_banks
= AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
2186 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_NUM_BANKS
, num_banks
);
2187 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_ARRAY_MODE
,
2188 ARRAY_2D_TILED_THIN1
);
2189 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_TILE_SPLIT
,
2191 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_BANK_WIDTH
, bankw
);
2192 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_BANK_HEIGHT
, bankh
);
2193 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_MACRO_TILE_ASPECT
,
2195 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_MICRO_TILE_MODE
,
2196 ADDR_SURF_MICRO_TILING_DISPLAY
);
2197 } else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == ARRAY_1D_TILED_THIN1
) {
2198 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_ARRAY_MODE
,
2199 ARRAY_1D_TILED_THIN1
);
2202 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_PIPE_CONFIG
,
2205 dce_v10_0_vga_enable(crtc
, false);
2207 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2208 upper_32_bits(fb_location
));
2209 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2210 upper_32_bits(fb_location
));
2211 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2212 (u32
)fb_location
& GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
);
2213 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2214 (u32
) fb_location
& GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
);
2215 WREG32(mmGRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
, fb_format
);
2216 WREG32(mmGRPH_SWAP_CNTL
+ amdgpu_crtc
->crtc_offset
, fb_swap
);
2219 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2220 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2221 * retain the full precision throughout the pipeline.
2223 tmp
= RREG32(mmGRPH_LUT_10BIT_BYPASS
+ amdgpu_crtc
->crtc_offset
);
2225 tmp
= REG_SET_FIELD(tmp
, GRPH_LUT_10BIT_BYPASS
, GRPH_LUT_10BIT_BYPASS_EN
, 1);
2227 tmp
= REG_SET_FIELD(tmp
, GRPH_LUT_10BIT_BYPASS
, GRPH_LUT_10BIT_BYPASS_EN
, 0);
2228 WREG32(mmGRPH_LUT_10BIT_BYPASS
+ amdgpu_crtc
->crtc_offset
, tmp
);
2231 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2233 WREG32(mmGRPH_SURFACE_OFFSET_X
+ amdgpu_crtc
->crtc_offset
, 0);
2234 WREG32(mmGRPH_SURFACE_OFFSET_Y
+ amdgpu_crtc
->crtc_offset
, 0);
2235 WREG32(mmGRPH_X_START
+ amdgpu_crtc
->crtc_offset
, 0);
2236 WREG32(mmGRPH_Y_START
+ amdgpu_crtc
->crtc_offset
, 0);
2237 WREG32(mmGRPH_X_END
+ amdgpu_crtc
->crtc_offset
, target_fb
->width
);
2238 WREG32(mmGRPH_Y_END
+ amdgpu_crtc
->crtc_offset
, target_fb
->height
);
2240 fb_pitch_pixels
= target_fb
->pitches
[0] / (target_fb
->bits_per_pixel
/ 8);
2241 WREG32(mmGRPH_PITCH
+ amdgpu_crtc
->crtc_offset
, fb_pitch_pixels
);
2243 dce_v10_0_grph_enable(crtc
, true);
2245 WREG32(mmLB_DESKTOP_HEIGHT
+ amdgpu_crtc
->crtc_offset
,
2250 WREG32(mmVIEWPORT_START
+ amdgpu_crtc
->crtc_offset
,
2252 viewport_w
= crtc
->mode
.hdisplay
;
2253 viewport_h
= (crtc
->mode
.vdisplay
+ 1) & ~1;
2254 WREG32(mmVIEWPORT_SIZE
+ amdgpu_crtc
->crtc_offset
,
2255 (viewport_w
<< 16) | viewport_h
);
2257 /* pageflip setup */
2258 /* make sure flip is at vb rather than hb */
2259 tmp
= RREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2260 tmp
= REG_SET_FIELD(tmp
, GRPH_FLIP_CONTROL
,
2261 GRPH_SURFACE_UPDATE_H_RETRACE_EN
, 0);
2262 WREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2264 /* set pageflip to happen only at start of vblank interval (front porch) */
2265 WREG32(mmMASTER_UPDATE_MODE
+ amdgpu_crtc
->crtc_offset
, 3);
2267 if (!atomic
&& fb
&& fb
!= crtc
->primary
->fb
) {
2268 amdgpu_fb
= to_amdgpu_framebuffer(fb
);
2269 rbo
= gem_to_amdgpu_bo(amdgpu_fb
->obj
);
2270 r
= amdgpu_bo_reserve(rbo
, false);
2271 if (unlikely(r
!= 0))
2273 amdgpu_bo_unpin(rbo
);
2274 amdgpu_bo_unreserve(rbo
);
2277 /* Bytes per pixel may have changed */
2278 dce_v10_0_bandwidth_update(adev
);
2283 static void dce_v10_0_set_interleave(struct drm_crtc
*crtc
,
2284 struct drm_display_mode
*mode
)
2286 struct drm_device
*dev
= crtc
->dev
;
2287 struct amdgpu_device
*adev
= dev
->dev_private
;
2288 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2291 tmp
= RREG32(mmLB_DATA_FORMAT
+ amdgpu_crtc
->crtc_offset
);
2292 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
2293 tmp
= REG_SET_FIELD(tmp
, LB_DATA_FORMAT
, INTERLEAVE_EN
, 1);
2295 tmp
= REG_SET_FIELD(tmp
, LB_DATA_FORMAT
, INTERLEAVE_EN
, 0);
2296 WREG32(mmLB_DATA_FORMAT
+ amdgpu_crtc
->crtc_offset
, tmp
);
2299 static void dce_v10_0_crtc_load_lut(struct drm_crtc
*crtc
)
2301 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2302 struct drm_device
*dev
= crtc
->dev
;
2303 struct amdgpu_device
*adev
= dev
->dev_private
;
2307 DRM_DEBUG_KMS("%d\n", amdgpu_crtc
->crtc_id
);
2309 tmp
= RREG32(mmINPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2310 tmp
= REG_SET_FIELD(tmp
, INPUT_CSC_CONTROL
, INPUT_CSC_GRPH_MODE
, 0);
2311 tmp
= REG_SET_FIELD(tmp
, INPUT_CSC_CONTROL
, INPUT_CSC_OVL_MODE
, 0);
2312 WREG32(mmINPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2314 tmp
= RREG32(mmPRESCALE_GRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2315 tmp
= REG_SET_FIELD(tmp
, PRESCALE_GRPH_CONTROL
, GRPH_PRESCALE_BYPASS
, 1);
2316 WREG32(mmPRESCALE_GRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2318 tmp
= RREG32(mmPRESCALE_OVL_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2319 tmp
= REG_SET_FIELD(tmp
, PRESCALE_OVL_CONTROL
, OVL_PRESCALE_BYPASS
, 1);
2320 WREG32(mmPRESCALE_OVL_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2322 tmp
= RREG32(mmINPUT_GAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2323 tmp
= REG_SET_FIELD(tmp
, INPUT_GAMMA_CONTROL
, GRPH_INPUT_GAMMA_MODE
, 0);
2324 tmp
= REG_SET_FIELD(tmp
, INPUT_GAMMA_CONTROL
, OVL_INPUT_GAMMA_MODE
, 0);
2325 WREG32(mmINPUT_GAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2327 WREG32(mmDC_LUT_CONTROL
+ amdgpu_crtc
->crtc_offset
, 0);
2329 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE
+ amdgpu_crtc
->crtc_offset
, 0);
2330 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN
+ amdgpu_crtc
->crtc_offset
, 0);
2331 WREG32(mmDC_LUT_BLACK_OFFSET_RED
+ amdgpu_crtc
->crtc_offset
, 0);
2333 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2334 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2335 WREG32(mmDC_LUT_WHITE_OFFSET_RED
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2337 WREG32(mmDC_LUT_RW_MODE
+ amdgpu_crtc
->crtc_offset
, 0);
2338 WREG32(mmDC_LUT_WRITE_EN_MASK
+ amdgpu_crtc
->crtc_offset
, 0x00000007);
2340 WREG32(mmDC_LUT_RW_INDEX
+ amdgpu_crtc
->crtc_offset
, 0);
2341 for (i
= 0; i
< 256; i
++) {
2342 WREG32(mmDC_LUT_30_COLOR
+ amdgpu_crtc
->crtc_offset
,
2343 (amdgpu_crtc
->lut_r
[i
] << 20) |
2344 (amdgpu_crtc
->lut_g
[i
] << 10) |
2345 (amdgpu_crtc
->lut_b
[i
] << 0));
2348 tmp
= RREG32(mmDEGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2349 tmp
= REG_SET_FIELD(tmp
, DEGAMMA_CONTROL
, GRPH_DEGAMMA_MODE
, 0);
2350 tmp
= REG_SET_FIELD(tmp
, DEGAMMA_CONTROL
, OVL_DEGAMMA_MODE
, 0);
2351 tmp
= REG_SET_FIELD(tmp
, DEGAMMA_CONTROL
, CURSOR_DEGAMMA_MODE
, 0);
2352 WREG32(mmDEGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2354 tmp
= RREG32(mmGAMUT_REMAP_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2355 tmp
= REG_SET_FIELD(tmp
, GAMUT_REMAP_CONTROL
, GRPH_GAMUT_REMAP_MODE
, 0);
2356 tmp
= REG_SET_FIELD(tmp
, GAMUT_REMAP_CONTROL
, OVL_GAMUT_REMAP_MODE
, 0);
2357 WREG32(mmGAMUT_REMAP_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2359 tmp
= RREG32(mmREGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2360 tmp
= REG_SET_FIELD(tmp
, REGAMMA_CONTROL
, GRPH_REGAMMA_MODE
, 0);
2361 tmp
= REG_SET_FIELD(tmp
, REGAMMA_CONTROL
, OVL_REGAMMA_MODE
, 0);
2362 WREG32(mmREGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2364 tmp
= RREG32(mmOUTPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2365 tmp
= REG_SET_FIELD(tmp
, OUTPUT_CSC_CONTROL
, OUTPUT_CSC_GRPH_MODE
, 0);
2366 tmp
= REG_SET_FIELD(tmp
, OUTPUT_CSC_CONTROL
, OUTPUT_CSC_OVL_MODE
, 0);
2367 WREG32(mmOUTPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2369 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2370 WREG32(mmDENORM_CONTROL
+ amdgpu_crtc
->crtc_offset
, 0);
2371 /* XXX this only needs to be programmed once per crtc at startup,
2372 * not sure where the best place for it is
2374 tmp
= RREG32(mmALPHA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2375 tmp
= REG_SET_FIELD(tmp
, ALPHA_CONTROL
, CURSOR_ALPHA_BLND_ENA
, 1);
2376 WREG32(mmALPHA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2379 static int dce_v10_0_pick_dig_encoder(struct drm_encoder
*encoder
)
2381 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
2382 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
2384 switch (amdgpu_encoder
->encoder_id
) {
2385 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2391 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2397 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2403 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2407 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder
->encoder_id
);
2413 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2417 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2418 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2419 * monitors a dedicated PPLL must be used. If a particular board has
2420 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2421 * as there is no need to program the PLL itself. If we are not able to
2422 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2423 * avoid messing up an existing monitor.
2425 * Asic specific PLL information
2429 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2431 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2434 static u32
dce_v10_0_pick_pll(struct drm_crtc
*crtc
)
2436 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2437 struct drm_device
*dev
= crtc
->dev
;
2438 struct amdgpu_device
*adev
= dev
->dev_private
;
2442 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
))) {
2443 if (adev
->clock
.dp_extclk
)
2444 /* skip PPLL programming if using ext clock */
2445 return ATOM_PPLL_INVALID
;
2447 /* use the same PPLL for all DP monitors */
2448 pll
= amdgpu_pll_get_shared_dp_ppll(crtc
);
2449 if (pll
!= ATOM_PPLL_INVALID
)
2453 /* use the same PPLL for all monitors with the same clock */
2454 pll
= amdgpu_pll_get_shared_nondp_ppll(crtc
);
2455 if (pll
!= ATOM_PPLL_INVALID
)
2459 /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2460 pll_in_use
= amdgpu_pll_get_use_mask(crtc
);
2461 if (!(pll_in_use
& (1 << ATOM_PPLL2
)))
2463 if (!(pll_in_use
& (1 << ATOM_PPLL1
)))
2465 if (!(pll_in_use
& (1 << ATOM_PPLL0
)))
2467 DRM_ERROR("unable to allocate a PPLL\n");
2468 return ATOM_PPLL_INVALID
;
2471 static void dce_v10_0_lock_cursor(struct drm_crtc
*crtc
, bool lock
)
2473 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2474 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2477 cur_lock
= RREG32(mmCUR_UPDATE
+ amdgpu_crtc
->crtc_offset
);
2479 cur_lock
= REG_SET_FIELD(cur_lock
, CUR_UPDATE
, CURSOR_UPDATE_LOCK
, 1);
2481 cur_lock
= REG_SET_FIELD(cur_lock
, CUR_UPDATE
, CURSOR_UPDATE_LOCK
, 0);
2482 WREG32(mmCUR_UPDATE
+ amdgpu_crtc
->crtc_offset
, cur_lock
);
2485 static void dce_v10_0_hide_cursor(struct drm_crtc
*crtc
)
2487 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2488 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2491 tmp
= RREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2492 tmp
= REG_SET_FIELD(tmp
, CUR_CONTROL
, CURSOR_EN
, 0);
2493 WREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2496 static void dce_v10_0_show_cursor(struct drm_crtc
*crtc
)
2498 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2499 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2502 tmp
= RREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2503 tmp
= REG_SET_FIELD(tmp
, CUR_CONTROL
, CURSOR_EN
, 1);
2504 tmp
= REG_SET_FIELD(tmp
, CUR_CONTROL
, CURSOR_MODE
, 2);
2505 WREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2508 static void dce_v10_0_set_cursor(struct drm_crtc
*crtc
, struct drm_gem_object
*obj
,
2511 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2512 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2514 WREG32(mmCUR_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2515 upper_32_bits(gpu_addr
));
2516 WREG32(mmCUR_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2517 lower_32_bits(gpu_addr
));
2520 static int dce_v10_0_crtc_cursor_move(struct drm_crtc
*crtc
,
2523 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2524 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2525 int xorigin
= 0, yorigin
= 0;
2527 /* avivo cursor are offset into the total surface */
2530 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x
, y
, crtc
->x
, crtc
->y
);
2533 xorigin
= min(-x
, amdgpu_crtc
->max_cursor_width
- 1);
2537 yorigin
= min(-y
, amdgpu_crtc
->max_cursor_height
- 1);
2541 dce_v10_0_lock_cursor(crtc
, true);
2542 WREG32(mmCUR_POSITION
+ amdgpu_crtc
->crtc_offset
, (x
<< 16) | y
);
2543 WREG32(mmCUR_HOT_SPOT
+ amdgpu_crtc
->crtc_offset
, (xorigin
<< 16) | yorigin
);
2544 WREG32(mmCUR_SIZE
+ amdgpu_crtc
->crtc_offset
,
2545 ((amdgpu_crtc
->cursor_width
- 1) << 16) | (amdgpu_crtc
->cursor_height
- 1));
2546 dce_v10_0_lock_cursor(crtc
, false);
2551 static int dce_v10_0_crtc_cursor_set(struct drm_crtc
*crtc
,
2552 struct drm_file
*file_priv
,
2557 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2558 struct drm_gem_object
*obj
;
2559 struct amdgpu_bo
*robj
;
2564 /* turn off cursor */
2565 dce_v10_0_hide_cursor(crtc
);
2570 if ((width
> amdgpu_crtc
->max_cursor_width
) ||
2571 (height
> amdgpu_crtc
->max_cursor_height
)) {
2572 DRM_ERROR("bad cursor width or height %d x %d\n", width
, height
);
2576 obj
= drm_gem_object_lookup(crtc
->dev
, file_priv
, handle
);
2578 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle
, amdgpu_crtc
->crtc_id
);
2582 robj
= gem_to_amdgpu_bo(obj
);
2583 ret
= amdgpu_bo_reserve(robj
, false);
2584 if (unlikely(ret
!= 0))
2586 ret
= amdgpu_bo_pin_restricted(robj
, AMDGPU_GEM_DOMAIN_VRAM
,
2588 amdgpu_bo_unreserve(robj
);
2592 amdgpu_crtc
->cursor_width
= width
;
2593 amdgpu_crtc
->cursor_height
= height
;
2595 dce_v10_0_lock_cursor(crtc
, true);
2596 dce_v10_0_set_cursor(crtc
, obj
, gpu_addr
);
2597 dce_v10_0_show_cursor(crtc
);
2598 dce_v10_0_lock_cursor(crtc
, false);
2601 if (amdgpu_crtc
->cursor_bo
) {
2602 robj
= gem_to_amdgpu_bo(amdgpu_crtc
->cursor_bo
);
2603 ret
= amdgpu_bo_reserve(robj
, false);
2604 if (likely(ret
== 0)) {
2605 amdgpu_bo_unpin(robj
);
2606 amdgpu_bo_unreserve(robj
);
2608 drm_gem_object_unreference_unlocked(amdgpu_crtc
->cursor_bo
);
2611 amdgpu_crtc
->cursor_bo
= obj
;
2614 drm_gem_object_unreference_unlocked(obj
);
2619 static void dce_v10_0_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
2620 u16
*blue
, uint32_t start
, uint32_t size
)
2622 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2623 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
2625 /* userspace palettes are always correct as is */
2626 for (i
= start
; i
< end
; i
++) {
2627 amdgpu_crtc
->lut_r
[i
] = red
[i
] >> 6;
2628 amdgpu_crtc
->lut_g
[i
] = green
[i
] >> 6;
2629 amdgpu_crtc
->lut_b
[i
] = blue
[i
] >> 6;
2631 dce_v10_0_crtc_load_lut(crtc
);
2634 static void dce_v10_0_crtc_destroy(struct drm_crtc
*crtc
)
2636 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2638 drm_crtc_cleanup(crtc
);
2639 destroy_workqueue(amdgpu_crtc
->pflip_queue
);
2643 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs
= {
2644 .cursor_set
= dce_v10_0_crtc_cursor_set
,
2645 .cursor_move
= dce_v10_0_crtc_cursor_move
,
2646 .gamma_set
= dce_v10_0_crtc_gamma_set
,
2647 .set_config
= amdgpu_crtc_set_config
,
2648 .destroy
= dce_v10_0_crtc_destroy
,
2649 .page_flip
= amdgpu_crtc_page_flip
,
2652 static void dce_v10_0_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2654 struct drm_device
*dev
= crtc
->dev
;
2655 struct amdgpu_device
*adev
= dev
->dev_private
;
2656 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2660 case DRM_MODE_DPMS_ON
:
2661 amdgpu_crtc
->enabled
= true;
2662 amdgpu_atombios_crtc_enable(crtc
, ATOM_ENABLE
);
2663 dce_v10_0_vga_enable(crtc
, true);
2664 amdgpu_atombios_crtc_blank(crtc
, ATOM_DISABLE
);
2665 dce_v10_0_vga_enable(crtc
, false);
2666 /* Make sure VBLANK interrupt is still enabled */
2667 type
= amdgpu_crtc_idx_to_irq_type(adev
, amdgpu_crtc
->crtc_id
);
2668 amdgpu_irq_update(adev
, &adev
->crtc_irq
, type
);
2669 drm_vblank_post_modeset(dev
, amdgpu_crtc
->crtc_id
);
2670 dce_v10_0_crtc_load_lut(crtc
);
2672 case DRM_MODE_DPMS_STANDBY
:
2673 case DRM_MODE_DPMS_SUSPEND
:
2674 case DRM_MODE_DPMS_OFF
:
2675 drm_vblank_pre_modeset(dev
, amdgpu_crtc
->crtc_id
);
2676 if (amdgpu_crtc
->enabled
) {
2677 dce_v10_0_vga_enable(crtc
, true);
2678 amdgpu_atombios_crtc_blank(crtc
, ATOM_ENABLE
);
2679 dce_v10_0_vga_enable(crtc
, false);
2681 amdgpu_atombios_crtc_enable(crtc
, ATOM_DISABLE
);
2682 amdgpu_crtc
->enabled
= false;
2685 /* adjust pm to dpms */
2686 amdgpu_pm_compute_clocks(adev
);
2689 static void dce_v10_0_crtc_prepare(struct drm_crtc
*crtc
)
2691 /* disable crtc pair power gating before programming */
2692 amdgpu_atombios_crtc_powergate(crtc
, ATOM_DISABLE
);
2693 amdgpu_atombios_crtc_lock(crtc
, ATOM_ENABLE
);
2694 dce_v10_0_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
2697 static void dce_v10_0_crtc_commit(struct drm_crtc
*crtc
)
2699 dce_v10_0_crtc_dpms(crtc
, DRM_MODE_DPMS_ON
);
2700 amdgpu_atombios_crtc_lock(crtc
, ATOM_DISABLE
);
2703 static void dce_v10_0_crtc_disable(struct drm_crtc
*crtc
)
2705 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2706 struct drm_device
*dev
= crtc
->dev
;
2707 struct amdgpu_device
*adev
= dev
->dev_private
;
2708 struct amdgpu_atom_ss ss
;
2711 dce_v10_0_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
2712 if (crtc
->primary
->fb
) {
2714 struct amdgpu_framebuffer
*amdgpu_fb
;
2715 struct amdgpu_bo
*rbo
;
2717 amdgpu_fb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
2718 rbo
= gem_to_amdgpu_bo(amdgpu_fb
->obj
);
2719 r
= amdgpu_bo_reserve(rbo
, false);
2721 DRM_ERROR("failed to reserve rbo before unpin\n");
2723 amdgpu_bo_unpin(rbo
);
2724 amdgpu_bo_unreserve(rbo
);
2727 /* disable the GRPH */
2728 dce_v10_0_grph_enable(crtc
, false);
2730 amdgpu_atombios_crtc_powergate(crtc
, ATOM_ENABLE
);
2732 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2733 if (adev
->mode_info
.crtcs
[i
] &&
2734 adev
->mode_info
.crtcs
[i
]->enabled
&&
2735 i
!= amdgpu_crtc
->crtc_id
&&
2736 amdgpu_crtc
->pll_id
== adev
->mode_info
.crtcs
[i
]->pll_id
) {
2737 /* one other crtc is using this pll don't turn
2744 switch (amdgpu_crtc
->pll_id
) {
2748 /* disable the ppll */
2749 amdgpu_atombios_crtc_program_pll(crtc
, amdgpu_crtc
->crtc_id
, amdgpu_crtc
->pll_id
,
2750 0, 0, ATOM_DISABLE
, 0, 0, 0, 0, 0, false, &ss
);
2756 amdgpu_crtc
->pll_id
= ATOM_PPLL_INVALID
;
2757 amdgpu_crtc
->adjusted_clock
= 0;
2758 amdgpu_crtc
->encoder
= NULL
;
2759 amdgpu_crtc
->connector
= NULL
;
2762 static int dce_v10_0_crtc_mode_set(struct drm_crtc
*crtc
,
2763 struct drm_display_mode
*mode
,
2764 struct drm_display_mode
*adjusted_mode
,
2765 int x
, int y
, struct drm_framebuffer
*old_fb
)
2767 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2769 if (!amdgpu_crtc
->adjusted_clock
)
2772 amdgpu_atombios_crtc_set_pll(crtc
, adjusted_mode
);
2773 amdgpu_atombios_crtc_set_dtd_timing(crtc
, adjusted_mode
);
2774 dce_v10_0_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
2775 amdgpu_atombios_crtc_overscan_setup(crtc
, mode
, adjusted_mode
);
2776 amdgpu_atombios_crtc_scaler_setup(crtc
);
2777 /* update the hw version fpr dpm */
2778 amdgpu_crtc
->hw_mode
= *adjusted_mode
;
2783 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc
*crtc
,
2784 const struct drm_display_mode
*mode
,
2785 struct drm_display_mode
*adjusted_mode
)
2787 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2788 struct drm_device
*dev
= crtc
->dev
;
2789 struct drm_encoder
*encoder
;
2791 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2792 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2793 if (encoder
->crtc
== crtc
) {
2794 amdgpu_crtc
->encoder
= encoder
;
2795 amdgpu_crtc
->connector
= amdgpu_get_connector_for_encoder(encoder
);
2799 if ((amdgpu_crtc
->encoder
== NULL
) || (amdgpu_crtc
->connector
== NULL
)) {
2800 amdgpu_crtc
->encoder
= NULL
;
2801 amdgpu_crtc
->connector
= NULL
;
2804 if (!amdgpu_crtc_scaling_mode_fixup(crtc
, mode
, adjusted_mode
))
2806 if (amdgpu_atombios_crtc_prepare_pll(crtc
, adjusted_mode
))
2809 amdgpu_crtc
->pll_id
= dce_v10_0_pick_pll(crtc
);
2810 /* if we can't get a PPLL for a non-DP encoder, fail */
2811 if ((amdgpu_crtc
->pll_id
== ATOM_PPLL_INVALID
) &&
2812 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
)))
2818 static int dce_v10_0_crtc_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2819 struct drm_framebuffer
*old_fb
)
2821 return dce_v10_0_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
2824 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc
*crtc
,
2825 struct drm_framebuffer
*fb
,
2826 int x
, int y
, enum mode_set_atomic state
)
2828 return dce_v10_0_crtc_do_set_base(crtc
, fb
, x
, y
, 1);
2831 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs
= {
2832 .dpms
= dce_v10_0_crtc_dpms
,
2833 .mode_fixup
= dce_v10_0_crtc_mode_fixup
,
2834 .mode_set
= dce_v10_0_crtc_mode_set
,
2835 .mode_set_base
= dce_v10_0_crtc_set_base
,
2836 .mode_set_base_atomic
= dce_v10_0_crtc_set_base_atomic
,
2837 .prepare
= dce_v10_0_crtc_prepare
,
2838 .commit
= dce_v10_0_crtc_commit
,
2839 .load_lut
= dce_v10_0_crtc_load_lut
,
2840 .disable
= dce_v10_0_crtc_disable
,
2843 static int dce_v10_0_crtc_init(struct amdgpu_device
*adev
, int index
)
2845 struct amdgpu_crtc
*amdgpu_crtc
;
2848 amdgpu_crtc
= kzalloc(sizeof(struct amdgpu_crtc
) +
2849 (AMDGPUFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
2850 if (amdgpu_crtc
== NULL
)
2853 drm_crtc_init(adev
->ddev
, &amdgpu_crtc
->base
, &dce_v10_0_crtc_funcs
);
2855 drm_mode_crtc_set_gamma_size(&amdgpu_crtc
->base
, 256);
2856 amdgpu_crtc
->crtc_id
= index
;
2857 amdgpu_crtc
->pflip_queue
= create_singlethread_workqueue("amdgpu-pageflip-queue");
2858 adev
->mode_info
.crtcs
[index
] = amdgpu_crtc
;
2860 amdgpu_crtc
->max_cursor_width
= 128;
2861 amdgpu_crtc
->max_cursor_height
= 128;
2862 adev
->ddev
->mode_config
.cursor_width
= amdgpu_crtc
->max_cursor_width
;
2863 adev
->ddev
->mode_config
.cursor_height
= amdgpu_crtc
->max_cursor_height
;
2865 for (i
= 0; i
< 256; i
++) {
2866 amdgpu_crtc
->lut_r
[i
] = i
<< 2;
2867 amdgpu_crtc
->lut_g
[i
] = i
<< 2;
2868 amdgpu_crtc
->lut_b
[i
] = i
<< 2;
2871 switch (amdgpu_crtc
->crtc_id
) {
2874 amdgpu_crtc
->crtc_offset
= CRTC0_REGISTER_OFFSET
;
2877 amdgpu_crtc
->crtc_offset
= CRTC1_REGISTER_OFFSET
;
2880 amdgpu_crtc
->crtc_offset
= CRTC2_REGISTER_OFFSET
;
2883 amdgpu_crtc
->crtc_offset
= CRTC3_REGISTER_OFFSET
;
2886 amdgpu_crtc
->crtc_offset
= CRTC4_REGISTER_OFFSET
;
2889 amdgpu_crtc
->crtc_offset
= CRTC5_REGISTER_OFFSET
;
2893 amdgpu_crtc
->pll_id
= ATOM_PPLL_INVALID
;
2894 amdgpu_crtc
->adjusted_clock
= 0;
2895 amdgpu_crtc
->encoder
= NULL
;
2896 amdgpu_crtc
->connector
= NULL
;
2897 drm_crtc_helper_add(&amdgpu_crtc
->base
, &dce_v10_0_crtc_helper_funcs
);
2902 static int dce_v10_0_early_init(void *handle
)
2904 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2906 adev
->audio_endpt_rreg
= &dce_v10_0_audio_endpt_rreg
;
2907 adev
->audio_endpt_wreg
= &dce_v10_0_audio_endpt_wreg
;
2909 dce_v10_0_set_display_funcs(adev
);
2910 dce_v10_0_set_irq_funcs(adev
);
2912 switch (adev
->asic_type
) {
2915 adev
->mode_info
.num_crtc
= 6; /* XXX 7??? */
2916 adev
->mode_info
.num_hpd
= 6;
2917 adev
->mode_info
.num_dig
= 7;
2920 /* FIXME: not supported yet */
2927 static int dce_v10_0_sw_init(void *handle
)
2930 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2932 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2933 r
= amdgpu_irq_add_id(adev
, i
+ 1, &adev
->crtc_irq
);
2938 for (i
= 8; i
< 20; i
+= 2) {
2939 r
= amdgpu_irq_add_id(adev
, i
, &adev
->pageflip_irq
);
2945 r
= amdgpu_irq_add_id(adev
, 42, &adev
->hpd_irq
);
2949 adev
->mode_info
.mode_config_initialized
= true;
2951 adev
->ddev
->mode_config
.funcs
= &amdgpu_mode_funcs
;
2953 adev
->ddev
->mode_config
.max_width
= 16384;
2954 adev
->ddev
->mode_config
.max_height
= 16384;
2956 adev
->ddev
->mode_config
.preferred_depth
= 24;
2957 adev
->ddev
->mode_config
.prefer_shadow
= 1;
2959 adev
->ddev
->mode_config
.fb_base
= adev
->mc
.aper_base
;
2961 r
= amdgpu_modeset_create_props(adev
);
2965 adev
->ddev
->mode_config
.max_width
= 16384;
2966 adev
->ddev
->mode_config
.max_height
= 16384;
2968 /* allocate crtcs */
2969 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2970 r
= dce_v10_0_crtc_init(adev
, i
);
2975 if (amdgpu_atombios_get_connector_info_from_object_table(adev
))
2976 amdgpu_print_display_setup(adev
->ddev
);
2981 dce_v10_0_afmt_init(adev
);
2983 r
= dce_v10_0_audio_init(adev
);
2987 drm_kms_helper_poll_init(adev
->ddev
);
2992 static int dce_v10_0_sw_fini(void *handle
)
2994 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2996 kfree(adev
->mode_info
.bios_hardcoded_edid
);
2998 drm_kms_helper_poll_fini(adev
->ddev
);
3000 dce_v10_0_audio_fini(adev
);
3002 dce_v10_0_afmt_fini(adev
);
3004 drm_mode_config_cleanup(adev
->ddev
);
3005 adev
->mode_info
.mode_config_initialized
= false;
3010 static int dce_v10_0_hw_init(void *handle
)
3013 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3015 dce_v10_0_init_golden_registers(adev
);
3017 /* init dig PHYs, disp eng pll */
3018 amdgpu_atombios_encoder_init_dig(adev
);
3019 amdgpu_atombios_crtc_set_disp_eng_pll(adev
, adev
->clock
.default_dispclk
);
3021 /* initialize hpd */
3022 dce_v10_0_hpd_init(adev
);
3024 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
3025 dce_v10_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
3031 static int dce_v10_0_hw_fini(void *handle
)
3034 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3036 dce_v10_0_hpd_fini(adev
);
3038 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
3039 dce_v10_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
3045 static int dce_v10_0_suspend(void *handle
)
3047 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3049 amdgpu_atombios_scratch_regs_save(adev
);
3051 dce_v10_0_hpd_fini(adev
);
3056 static int dce_v10_0_resume(void *handle
)
3058 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3060 dce_v10_0_init_golden_registers(adev
);
3062 amdgpu_atombios_scratch_regs_restore(adev
);
3064 /* init dig PHYs, disp eng pll */
3065 amdgpu_atombios_encoder_init_dig(adev
);
3066 amdgpu_atombios_crtc_set_disp_eng_pll(adev
, adev
->clock
.default_dispclk
);
3067 /* turn on the BL */
3068 if (adev
->mode_info
.bl_encoder
) {
3069 u8 bl_level
= amdgpu_display_backlight_get_level(adev
,
3070 adev
->mode_info
.bl_encoder
);
3071 amdgpu_display_backlight_set_level(adev
, adev
->mode_info
.bl_encoder
,
3075 /* initialize hpd */
3076 dce_v10_0_hpd_init(adev
);
3081 static bool dce_v10_0_is_idle(void *handle
)
3086 static int dce_v10_0_wait_for_idle(void *handle
)
3091 static void dce_v10_0_print_status(void *handle
)
3093 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3095 dev_info(adev
->dev
, "DCE 10.x registers\n");
3099 static int dce_v10_0_soft_reset(void *handle
)
3101 u32 srbm_soft_reset
= 0, tmp
;
3102 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3104 if (dce_v10_0_is_display_hung(adev
))
3105 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK
;
3107 if (srbm_soft_reset
) {
3108 dce_v10_0_print_status((void *)adev
);
3110 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3111 tmp
|= srbm_soft_reset
;
3112 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
3113 WREG32(mmSRBM_SOFT_RESET
, tmp
);
3114 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3118 tmp
&= ~srbm_soft_reset
;
3119 WREG32(mmSRBM_SOFT_RESET
, tmp
);
3120 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3122 /* Wait a little for things to settle down */
3124 dce_v10_0_print_status((void *)adev
);
3129 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device
*adev
,
3131 enum amdgpu_interrupt_state state
)
3133 u32 lb_interrupt_mask
;
3135 if (crtc
>= adev
->mode_info
.num_crtc
) {
3136 DRM_DEBUG("invalid crtc %d\n", crtc
);
3141 case AMDGPU_IRQ_STATE_DISABLE
:
3142 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3143 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3144 VBLANK_INTERRUPT_MASK
, 0);
3145 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3147 case AMDGPU_IRQ_STATE_ENABLE
:
3148 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3149 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3150 VBLANK_INTERRUPT_MASK
, 1);
3151 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3158 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device
*adev
,
3160 enum amdgpu_interrupt_state state
)
3162 u32 lb_interrupt_mask
;
3164 if (crtc
>= adev
->mode_info
.num_crtc
) {
3165 DRM_DEBUG("invalid crtc %d\n", crtc
);
3170 case AMDGPU_IRQ_STATE_DISABLE
:
3171 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3172 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3173 VLINE_INTERRUPT_MASK
, 0);
3174 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3176 case AMDGPU_IRQ_STATE_ENABLE
:
3177 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3178 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3179 VLINE_INTERRUPT_MASK
, 1);
3180 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3187 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device
*adev
,
3188 struct amdgpu_irq_src
*source
,
3190 enum amdgpu_interrupt_state state
)
3194 if (hpd
>= adev
->mode_info
.num_hpd
) {
3195 DRM_DEBUG("invalid hdp %d\n", hpd
);
3200 case AMDGPU_IRQ_STATE_DISABLE
:
3201 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
3202 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_EN
, 0);
3203 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
3205 case AMDGPU_IRQ_STATE_ENABLE
:
3206 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
3207 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_EN
, 1);
3208 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
3217 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device
*adev
,
3218 struct amdgpu_irq_src
*source
,
3220 enum amdgpu_interrupt_state state
)
3223 case AMDGPU_CRTC_IRQ_VBLANK1
:
3224 dce_v10_0_set_crtc_vblank_interrupt_state(adev
, 0, state
);
3226 case AMDGPU_CRTC_IRQ_VBLANK2
:
3227 dce_v10_0_set_crtc_vblank_interrupt_state(adev
, 1, state
);
3229 case AMDGPU_CRTC_IRQ_VBLANK3
:
3230 dce_v10_0_set_crtc_vblank_interrupt_state(adev
, 2, state
);
3232 case AMDGPU_CRTC_IRQ_VBLANK4
:
3233 dce_v10_0_set_crtc_vblank_interrupt_state(adev
, 3, state
);
3235 case AMDGPU_CRTC_IRQ_VBLANK5
:
3236 dce_v10_0_set_crtc_vblank_interrupt_state(adev
, 4, state
);
3238 case AMDGPU_CRTC_IRQ_VBLANK6
:
3239 dce_v10_0_set_crtc_vblank_interrupt_state(adev
, 5, state
);
3241 case AMDGPU_CRTC_IRQ_VLINE1
:
3242 dce_v10_0_set_crtc_vline_interrupt_state(adev
, 0, state
);
3244 case AMDGPU_CRTC_IRQ_VLINE2
:
3245 dce_v10_0_set_crtc_vline_interrupt_state(adev
, 1, state
);
3247 case AMDGPU_CRTC_IRQ_VLINE3
:
3248 dce_v10_0_set_crtc_vline_interrupt_state(adev
, 2, state
);
3250 case AMDGPU_CRTC_IRQ_VLINE4
:
3251 dce_v10_0_set_crtc_vline_interrupt_state(adev
, 3, state
);
3253 case AMDGPU_CRTC_IRQ_VLINE5
:
3254 dce_v10_0_set_crtc_vline_interrupt_state(adev
, 4, state
);
3256 case AMDGPU_CRTC_IRQ_VLINE6
:
3257 dce_v10_0_set_crtc_vline_interrupt_state(adev
, 5, state
);
3265 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device
*adev
,
3266 struct amdgpu_irq_src
*src
,
3268 enum amdgpu_interrupt_state state
)
3271 /* now deal with page flip IRQ */
3273 case AMDGPU_PAGEFLIP_IRQ_D1
:
3274 reg_block
= CRTC0_REGISTER_OFFSET
;
3276 case AMDGPU_PAGEFLIP_IRQ_D2
:
3277 reg_block
= CRTC1_REGISTER_OFFSET
;
3279 case AMDGPU_PAGEFLIP_IRQ_D3
:
3280 reg_block
= CRTC2_REGISTER_OFFSET
;
3282 case AMDGPU_PAGEFLIP_IRQ_D4
:
3283 reg_block
= CRTC3_REGISTER_OFFSET
;
3285 case AMDGPU_PAGEFLIP_IRQ_D5
:
3286 reg_block
= CRTC4_REGISTER_OFFSET
;
3288 case AMDGPU_PAGEFLIP_IRQ_D6
:
3289 reg_block
= CRTC5_REGISTER_OFFSET
;
3292 DRM_ERROR("invalid pageflip crtc %d\n", type
);
3296 reg
= RREG32(mmGRPH_INTERRUPT_CONTROL
+ reg_block
);
3297 if (state
== AMDGPU_IRQ_STATE_DISABLE
)
3298 WREG32(mmGRPH_INTERRUPT_CONTROL
+ reg_block
, reg
& ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
);
3300 WREG32(mmGRPH_INTERRUPT_CONTROL
+ reg_block
, reg
| GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
);
3305 static int dce_v10_0_pageflip_irq(struct amdgpu_device
*adev
,
3306 struct amdgpu_irq_src
*source
,
3307 struct amdgpu_iv_entry
*entry
)
3310 unsigned long flags
;
3312 struct amdgpu_crtc
*amdgpu_crtc
;
3313 struct amdgpu_flip_work
*works
;
3315 crtc_id
= (entry
->src_id
- 8) >> 1;
3316 amdgpu_crtc
= adev
->mode_info
.crtcs
[crtc_id
];
3318 /* ack the interrupt */
3320 case AMDGPU_PAGEFLIP_IRQ_D1
:
3321 reg_block
= CRTC0_REGISTER_OFFSET
;
3323 case AMDGPU_PAGEFLIP_IRQ_D2
:
3324 reg_block
= CRTC1_REGISTER_OFFSET
;
3326 case AMDGPU_PAGEFLIP_IRQ_D3
:
3327 reg_block
= CRTC2_REGISTER_OFFSET
;
3329 case AMDGPU_PAGEFLIP_IRQ_D4
:
3330 reg_block
= CRTC3_REGISTER_OFFSET
;
3332 case AMDGPU_PAGEFLIP_IRQ_D5
:
3333 reg_block
= CRTC4_REGISTER_OFFSET
;
3335 case AMDGPU_PAGEFLIP_IRQ_D6
:
3336 reg_block
= CRTC5_REGISTER_OFFSET
;
3339 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id
);
3343 if (RREG32(mmGRPH_INTERRUPT_STATUS
+ reg_block
) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
)
3344 WREG32(mmGRPH_INTERRUPT_STATUS
+ reg_block
, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
);
3346 /* IRQ could occur when in initial stage */
3347 if (amdgpu_crtc
== NULL
)
3350 spin_lock_irqsave(&adev
->ddev
->event_lock
, flags
);
3351 works
= amdgpu_crtc
->pflip_works
;
3352 if (amdgpu_crtc
->pflip_status
!= AMDGPU_FLIP_SUBMITTED
) {
3353 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3354 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3355 amdgpu_crtc
->pflip_status
,
3356 AMDGPU_FLIP_SUBMITTED
);
3357 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
3361 /* page flip completed. clean up */
3362 amdgpu_crtc
->pflip_status
= AMDGPU_FLIP_NONE
;
3363 amdgpu_crtc
->pflip_works
= NULL
;
3365 /* wakeup usersapce */
3367 drm_send_vblank_event(adev
->ddev
, crtc_id
, works
->event
);
3369 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
3371 drm_vblank_put(adev
->ddev
, amdgpu_crtc
->crtc_id
);
3372 amdgpu_irq_put(adev
, &adev
->pageflip_irq
, crtc_id
);
3373 queue_work(amdgpu_crtc
->pflip_queue
, &works
->unpin_work
);
3378 static void dce_v10_0_hpd_int_ack(struct amdgpu_device
*adev
,
3383 if (hpd
>= adev
->mode_info
.num_hpd
) {
3384 DRM_DEBUG("invalid hdp %d\n", hpd
);
3388 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
3389 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_ACK
, 1);
3390 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
3393 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device
*adev
,
3398 if (crtc
>= adev
->mode_info
.num_crtc
) {
3399 DRM_DEBUG("invalid crtc %d\n", crtc
);
3403 tmp
= RREG32(mmLB_VBLANK_STATUS
+ crtc_offsets
[crtc
]);
3404 tmp
= REG_SET_FIELD(tmp
, LB_VBLANK_STATUS
, VBLANK_ACK
, 1);
3405 WREG32(mmLB_VBLANK_STATUS
+ crtc_offsets
[crtc
], tmp
);
3408 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device
*adev
,
3413 if (crtc
>= adev
->mode_info
.num_crtc
) {
3414 DRM_DEBUG("invalid crtc %d\n", crtc
);
3418 tmp
= RREG32(mmLB_VLINE_STATUS
+ crtc_offsets
[crtc
]);
3419 tmp
= REG_SET_FIELD(tmp
, LB_VLINE_STATUS
, VLINE_ACK
, 1);
3420 WREG32(mmLB_VLINE_STATUS
+ crtc_offsets
[crtc
], tmp
);
3423 static int dce_v10_0_crtc_irq(struct amdgpu_device
*adev
,
3424 struct amdgpu_irq_src
*source
,
3425 struct amdgpu_iv_entry
*entry
)
3427 unsigned crtc
= entry
->src_id
- 1;
3428 uint32_t disp_int
= RREG32(interrupt_status_offsets
[crtc
].reg
);
3429 unsigned irq_type
= amdgpu_crtc_idx_to_irq_type(adev
, crtc
);
3431 switch (entry
->src_data
) {
3432 case 0: /* vblank */
3433 if (disp_int
& interrupt_status_offsets
[crtc
].vblank
)
3434 dce_v10_0_crtc_vblank_int_ack(adev
, crtc
);
3436 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3438 if (amdgpu_irq_enabled(adev
, source
, irq_type
)) {
3439 drm_handle_vblank(adev
->ddev
, crtc
);
3441 DRM_DEBUG("IH: D%d vblank\n", crtc
+ 1);
3445 if (disp_int
& interrupt_status_offsets
[crtc
].vline
)
3446 dce_v10_0_crtc_vline_int_ack(adev
, crtc
);
3448 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3450 DRM_DEBUG("IH: D%d vline\n", crtc
+ 1);
3454 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry
->src_id
, entry
->src_data
);
3461 static int dce_v10_0_hpd_irq(struct amdgpu_device
*adev
,
3462 struct amdgpu_irq_src
*source
,
3463 struct amdgpu_iv_entry
*entry
)
3465 uint32_t disp_int
, mask
;
3468 if (entry
->src_data
>= adev
->mode_info
.num_hpd
) {
3469 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry
->src_id
, entry
->src_data
);
3473 hpd
= entry
->src_data
;
3474 disp_int
= RREG32(interrupt_status_offsets
[hpd
].reg
);
3475 mask
= interrupt_status_offsets
[hpd
].hpd
;
3477 if (disp_int
& mask
) {
3478 dce_v10_0_hpd_int_ack(adev
, hpd
);
3479 schedule_work(&adev
->hotplug_work
);
3480 DRM_DEBUG("IH: HPD%d\n", hpd
+ 1);
3486 static int dce_v10_0_set_clockgating_state(void *handle
,
3487 enum amd_clockgating_state state
)
3492 static int dce_v10_0_set_powergating_state(void *handle
,
3493 enum amd_powergating_state state
)
3498 const struct amd_ip_funcs dce_v10_0_ip_funcs
= {
3499 .early_init
= dce_v10_0_early_init
,
3501 .sw_init
= dce_v10_0_sw_init
,
3502 .sw_fini
= dce_v10_0_sw_fini
,
3503 .hw_init
= dce_v10_0_hw_init
,
3504 .hw_fini
= dce_v10_0_hw_fini
,
3505 .suspend
= dce_v10_0_suspend
,
3506 .resume
= dce_v10_0_resume
,
3507 .is_idle
= dce_v10_0_is_idle
,
3508 .wait_for_idle
= dce_v10_0_wait_for_idle
,
3509 .soft_reset
= dce_v10_0_soft_reset
,
3510 .print_status
= dce_v10_0_print_status
,
3511 .set_clockgating_state
= dce_v10_0_set_clockgating_state
,
3512 .set_powergating_state
= dce_v10_0_set_powergating_state
,
3516 dce_v10_0_encoder_mode_set(struct drm_encoder
*encoder
,
3517 struct drm_display_mode
*mode
,
3518 struct drm_display_mode
*adjusted_mode
)
3520 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3522 amdgpu_encoder
->pixel_clock
= adjusted_mode
->clock
;
3524 /* need to call this here rather than in prepare() since we need some crtc info */
3525 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
3527 /* set scaler clears this on some chips */
3528 dce_v10_0_set_interleave(encoder
->crtc
, mode
);
3530 if (amdgpu_atombios_encoder_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
) {
3531 dce_v10_0_afmt_enable(encoder
, true);
3532 dce_v10_0_afmt_setmode(encoder
, adjusted_mode
);
3536 static void dce_v10_0_encoder_prepare(struct drm_encoder
*encoder
)
3538 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
3539 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3540 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
3542 if ((amdgpu_encoder
->active_device
&
3543 (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
3544 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) !=
3545 ENCODER_OBJECT_ID_NONE
)) {
3546 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
3548 dig
->dig_encoder
= dce_v10_0_pick_dig_encoder(encoder
);
3549 if (amdgpu_encoder
->active_device
& ATOM_DEVICE_DFP_SUPPORT
)
3550 dig
->afmt
= adev
->mode_info
.afmt
[dig
->dig_encoder
];
3554 amdgpu_atombios_scratch_regs_lock(adev
, true);
3557 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
3559 /* select the clock/data port if it uses a router */
3560 if (amdgpu_connector
->router
.cd_valid
)
3561 amdgpu_i2c_router_select_cd_port(amdgpu_connector
);
3563 /* turn eDP panel on for mode set */
3564 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3565 amdgpu_atombios_encoder_set_edp_panel_power(connector
,
3566 ATOM_TRANSMITTER_ACTION_POWER_ON
);
3569 /* this is needed for the pll/ss setup to work correctly in some cases */
3570 amdgpu_atombios_encoder_set_crtc_source(encoder
);
3571 /* set up the FMT blocks */
3572 dce_v10_0_program_fmt(encoder
);
3575 static void dce_v10_0_encoder_commit(struct drm_encoder
*encoder
)
3577 struct drm_device
*dev
= encoder
->dev
;
3578 struct amdgpu_device
*adev
= dev
->dev_private
;
3580 /* need to call this here as we need the crtc set up */
3581 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_ON
);
3582 amdgpu_atombios_scratch_regs_lock(adev
, false);
3585 static void dce_v10_0_encoder_disable(struct drm_encoder
*encoder
)
3587 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3588 struct amdgpu_encoder_atom_dig
*dig
;
3590 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
3592 if (amdgpu_atombios_encoder_is_digital(encoder
)) {
3593 if (amdgpu_atombios_encoder_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
)
3594 dce_v10_0_afmt_enable(encoder
, false);
3595 dig
= amdgpu_encoder
->enc_priv
;
3596 dig
->dig_encoder
= -1;
3598 amdgpu_encoder
->active_device
= 0;
3601 /* these are handled by the primary encoders */
3602 static void dce_v10_0_ext_prepare(struct drm_encoder
*encoder
)
3607 static void dce_v10_0_ext_commit(struct drm_encoder
*encoder
)
3613 dce_v10_0_ext_mode_set(struct drm_encoder
*encoder
,
3614 struct drm_display_mode
*mode
,
3615 struct drm_display_mode
*adjusted_mode
)
3620 static void dce_v10_0_ext_disable(struct drm_encoder
*encoder
)
3626 dce_v10_0_ext_dpms(struct drm_encoder
*encoder
, int mode
)
3631 static bool dce_v10_0_ext_mode_fixup(struct drm_encoder
*encoder
,
3632 const struct drm_display_mode
*mode
,
3633 struct drm_display_mode
*adjusted_mode
)
3638 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs
= {
3639 .dpms
= dce_v10_0_ext_dpms
,
3640 .mode_fixup
= dce_v10_0_ext_mode_fixup
,
3641 .prepare
= dce_v10_0_ext_prepare
,
3642 .mode_set
= dce_v10_0_ext_mode_set
,
3643 .commit
= dce_v10_0_ext_commit
,
3644 .disable
= dce_v10_0_ext_disable
,
3645 /* no detect for TMDS/LVDS yet */
3648 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs
= {
3649 .dpms
= amdgpu_atombios_encoder_dpms
,
3650 .mode_fixup
= amdgpu_atombios_encoder_mode_fixup
,
3651 .prepare
= dce_v10_0_encoder_prepare
,
3652 .mode_set
= dce_v10_0_encoder_mode_set
,
3653 .commit
= dce_v10_0_encoder_commit
,
3654 .disable
= dce_v10_0_encoder_disable
,
3655 .detect
= amdgpu_atombios_encoder_dig_detect
,
3658 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs
= {
3659 .dpms
= amdgpu_atombios_encoder_dpms
,
3660 .mode_fixup
= amdgpu_atombios_encoder_mode_fixup
,
3661 .prepare
= dce_v10_0_encoder_prepare
,
3662 .mode_set
= dce_v10_0_encoder_mode_set
,
3663 .commit
= dce_v10_0_encoder_commit
,
3664 .detect
= amdgpu_atombios_encoder_dac_detect
,
3667 static void dce_v10_0_encoder_destroy(struct drm_encoder
*encoder
)
3669 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3670 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
3671 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder
);
3672 kfree(amdgpu_encoder
->enc_priv
);
3673 drm_encoder_cleanup(encoder
);
3674 kfree(amdgpu_encoder
);
3677 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs
= {
3678 .destroy
= dce_v10_0_encoder_destroy
,
3681 static void dce_v10_0_encoder_add(struct amdgpu_device
*adev
,
3682 uint32_t encoder_enum
,
3683 uint32_t supported_device
,
3686 struct drm_device
*dev
= adev
->ddev
;
3687 struct drm_encoder
*encoder
;
3688 struct amdgpu_encoder
*amdgpu_encoder
;
3690 /* see if we already added it */
3691 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3692 amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3693 if (amdgpu_encoder
->encoder_enum
== encoder_enum
) {
3694 amdgpu_encoder
->devices
|= supported_device
;
3701 amdgpu_encoder
= kzalloc(sizeof(struct amdgpu_encoder
), GFP_KERNEL
);
3702 if (!amdgpu_encoder
)
3705 encoder
= &amdgpu_encoder
->base
;
3706 switch (adev
->mode_info
.num_crtc
) {
3708 encoder
->possible_crtcs
= 0x1;
3712 encoder
->possible_crtcs
= 0x3;
3715 encoder
->possible_crtcs
= 0xf;
3718 encoder
->possible_crtcs
= 0x3f;
3722 amdgpu_encoder
->enc_priv
= NULL
;
3724 amdgpu_encoder
->encoder_enum
= encoder_enum
;
3725 amdgpu_encoder
->encoder_id
= (encoder_enum
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
3726 amdgpu_encoder
->devices
= supported_device
;
3727 amdgpu_encoder
->rmx_type
= RMX_OFF
;
3728 amdgpu_encoder
->underscan_type
= UNDERSCAN_OFF
;
3729 amdgpu_encoder
->is_ext_encoder
= false;
3730 amdgpu_encoder
->caps
= caps
;
3732 switch (amdgpu_encoder
->encoder_id
) {
3733 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
3734 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
3735 drm_encoder_init(dev
, encoder
, &dce_v10_0_encoder_funcs
,
3736 DRM_MODE_ENCODER_DAC
);
3737 drm_encoder_helper_add(encoder
, &dce_v10_0_dac_helper_funcs
);
3739 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
3740 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
3741 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
3742 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
3743 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
3744 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
3745 amdgpu_encoder
->rmx_type
= RMX_FULL
;
3746 drm_encoder_init(dev
, encoder
, &dce_v10_0_encoder_funcs
,
3747 DRM_MODE_ENCODER_LVDS
);
3748 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder
);
3749 } else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
3750 drm_encoder_init(dev
, encoder
, &dce_v10_0_encoder_funcs
,
3751 DRM_MODE_ENCODER_DAC
);
3752 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder
);
3754 drm_encoder_init(dev
, encoder
, &dce_v10_0_encoder_funcs
,
3755 DRM_MODE_ENCODER_TMDS
);
3756 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder
);
3758 drm_encoder_helper_add(encoder
, &dce_v10_0_dig_helper_funcs
);
3760 case ENCODER_OBJECT_ID_SI170B
:
3761 case ENCODER_OBJECT_ID_CH7303
:
3762 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA
:
3763 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB
:
3764 case ENCODER_OBJECT_ID_TITFP513
:
3765 case ENCODER_OBJECT_ID_VT1623
:
3766 case ENCODER_OBJECT_ID_HDMI_SI1930
:
3767 case ENCODER_OBJECT_ID_TRAVIS
:
3768 case ENCODER_OBJECT_ID_NUTMEG
:
3769 /* these are handled by the primary encoders */
3770 amdgpu_encoder
->is_ext_encoder
= true;
3771 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
3772 drm_encoder_init(dev
, encoder
, &dce_v10_0_encoder_funcs
,
3773 DRM_MODE_ENCODER_LVDS
);
3774 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
))
3775 drm_encoder_init(dev
, encoder
, &dce_v10_0_encoder_funcs
,
3776 DRM_MODE_ENCODER_DAC
);
3778 drm_encoder_init(dev
, encoder
, &dce_v10_0_encoder_funcs
,
3779 DRM_MODE_ENCODER_TMDS
);
3780 drm_encoder_helper_add(encoder
, &dce_v10_0_ext_helper_funcs
);
3785 static const struct amdgpu_display_funcs dce_v10_0_display_funcs
= {
3786 .set_vga_render_state
= &dce_v10_0_set_vga_render_state
,
3787 .bandwidth_update
= &dce_v10_0_bandwidth_update
,
3788 .vblank_get_counter
= &dce_v10_0_vblank_get_counter
,
3789 .vblank_wait
= &dce_v10_0_vblank_wait
,
3790 .is_display_hung
= &dce_v10_0_is_display_hung
,
3791 .backlight_set_level
= &amdgpu_atombios_encoder_set_backlight_level
,
3792 .backlight_get_level
= &amdgpu_atombios_encoder_get_backlight_level
,
3793 .hpd_sense
= &dce_v10_0_hpd_sense
,
3794 .hpd_set_polarity
= &dce_v10_0_hpd_set_polarity
,
3795 .hpd_get_gpio_reg
= &dce_v10_0_hpd_get_gpio_reg
,
3796 .page_flip
= &dce_v10_0_page_flip
,
3797 .page_flip_get_scanoutpos
= &dce_v10_0_crtc_get_scanoutpos
,
3798 .add_encoder
= &dce_v10_0_encoder_add
,
3799 .add_connector
= &amdgpu_connector_add
,
3800 .stop_mc_access
= &dce_v10_0_stop_mc_access
,
3801 .resume_mc_access
= &dce_v10_0_resume_mc_access
,
3804 static void dce_v10_0_set_display_funcs(struct amdgpu_device
*adev
)
3806 if (adev
->mode_info
.funcs
== NULL
)
3807 adev
->mode_info
.funcs
= &dce_v10_0_display_funcs
;
3810 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs
= {
3811 .set
= dce_v10_0_set_crtc_irq_state
,
3812 .process
= dce_v10_0_crtc_irq
,
3815 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs
= {
3816 .set
= dce_v10_0_set_pageflip_irq_state
,
3817 .process
= dce_v10_0_pageflip_irq
,
3820 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs
= {
3821 .set
= dce_v10_0_set_hpd_irq_state
,
3822 .process
= dce_v10_0_hpd_irq
,
3825 static void dce_v10_0_set_irq_funcs(struct amdgpu_device
*adev
)
3827 adev
->crtc_irq
.num_types
= AMDGPU_CRTC_IRQ_LAST
;
3828 adev
->crtc_irq
.funcs
= &dce_v10_0_crtc_irq_funcs
;
3830 adev
->pageflip_irq
.num_types
= AMDGPU_PAGEFLIP_IRQ_LAST
;
3831 adev
->pageflip_irq
.funcs
= &dce_v10_0_pageflip_irq_funcs
;
3833 adev
->hpd_irq
.num_types
= AMDGPU_HPD_LAST
;
3834 adev
->hpd_irq
.funcs
= &dce_v10_0_hpd_irq_funcs
;