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Merge tag 'iio-for-4.13b' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23...
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / amd / amdgpu / dce_v10_0.c
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "drmP.h"
24 #include "amdgpu.h"
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
27 #include "vid.h"
28 #include "atom.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
34 #include "dce_v10_0.h"
35
36 #include "dce/dce_10_0_d.h"
37 #include "dce/dce_10_0_sh_mask.h"
38 #include "dce/dce_10_0_enum.h"
39 #include "oss/oss_3_0_d.h"
40 #include "oss/oss_3_0_sh_mask.h"
41 #include "gmc/gmc_8_1_d.h"
42 #include "gmc/gmc_8_1_sh_mask.h"
43
44 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
45 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
46
47 static const u32 crtc_offsets[] =
48 {
49 CRTC0_REGISTER_OFFSET,
50 CRTC1_REGISTER_OFFSET,
51 CRTC2_REGISTER_OFFSET,
52 CRTC3_REGISTER_OFFSET,
53 CRTC4_REGISTER_OFFSET,
54 CRTC5_REGISTER_OFFSET,
55 CRTC6_REGISTER_OFFSET
56 };
57
58 static const u32 hpd_offsets[] =
59 {
60 HPD0_REGISTER_OFFSET,
61 HPD1_REGISTER_OFFSET,
62 HPD2_REGISTER_OFFSET,
63 HPD3_REGISTER_OFFSET,
64 HPD4_REGISTER_OFFSET,
65 HPD5_REGISTER_OFFSET
66 };
67
68 static const uint32_t dig_offsets[] = {
69 DIG0_REGISTER_OFFSET,
70 DIG1_REGISTER_OFFSET,
71 DIG2_REGISTER_OFFSET,
72 DIG3_REGISTER_OFFSET,
73 DIG4_REGISTER_OFFSET,
74 DIG5_REGISTER_OFFSET,
75 DIG6_REGISTER_OFFSET
76 };
77
78 static const struct {
79 uint32_t reg;
80 uint32_t vblank;
81 uint32_t vline;
82 uint32_t hpd;
83
84 } interrupt_status_offsets[] = { {
85 .reg = mmDISP_INTERRUPT_STATUS,
86 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
87 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
88 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
89 }, {
90 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
91 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
92 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
93 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
94 }, {
95 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
96 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
97 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
98 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
99 }, {
100 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
101 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
102 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
103 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
104 }, {
105 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
106 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
107 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
108 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
109 }, {
110 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
111 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
112 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
113 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
114 } };
115
116 static const u32 golden_settings_tonga_a11[] =
117 {
118 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
119 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
120 mmFBC_MISC, 0x1f311fff, 0x12300000,
121 mmHDMI_CONTROL, 0x31000111, 0x00000011,
122 };
123
124 static const u32 tonga_mgcg_cgcg_init[] =
125 {
126 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
127 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
128 };
129
130 static const u32 golden_settings_fiji_a10[] =
131 {
132 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
133 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
134 mmFBC_MISC, 0x1f311fff, 0x12300000,
135 mmHDMI_CONTROL, 0x31000111, 0x00000011,
136 };
137
138 static const u32 fiji_mgcg_cgcg_init[] =
139 {
140 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
141 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
142 };
143
144 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
145 {
146 switch (adev->asic_type) {
147 case CHIP_FIJI:
148 amdgpu_program_register_sequence(adev,
149 fiji_mgcg_cgcg_init,
150 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
151 amdgpu_program_register_sequence(adev,
152 golden_settings_fiji_a10,
153 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
154 break;
155 case CHIP_TONGA:
156 amdgpu_program_register_sequence(adev,
157 tonga_mgcg_cgcg_init,
158 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
159 amdgpu_program_register_sequence(adev,
160 golden_settings_tonga_a11,
161 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
162 break;
163 default:
164 break;
165 }
166 }
167
168 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
169 u32 block_offset, u32 reg)
170 {
171 unsigned long flags;
172 u32 r;
173
174 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
175 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
176 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
177 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
178
179 return r;
180 }
181
182 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
183 u32 block_offset, u32 reg, u32 v)
184 {
185 unsigned long flags;
186
187 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
188 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
189 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
190 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
191 }
192
193 static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
194 {
195 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
196 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
197 return true;
198 else
199 return false;
200 }
201
202 static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
203 {
204 u32 pos1, pos2;
205
206 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
207 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
208
209 if (pos1 != pos2)
210 return true;
211 else
212 return false;
213 }
214
215 /**
216 * dce_v10_0_vblank_wait - vblank wait asic callback.
217 *
218 * @adev: amdgpu_device pointer
219 * @crtc: crtc to wait for vblank on
220 *
221 * Wait for vblank on the requested crtc (evergreen+).
222 */
223 static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc)
224 {
225 unsigned i = 100;
226
227 if (crtc >= adev->mode_info.num_crtc)
228 return;
229
230 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
231 return;
232
233 /* depending on when we hit vblank, we may be close to active; if so,
234 * wait for another frame.
235 */
236 while (dce_v10_0_is_in_vblank(adev, crtc)) {
237 if (i++ == 100) {
238 i = 0;
239 if (!dce_v10_0_is_counter_moving(adev, crtc))
240 break;
241 }
242 }
243
244 while (!dce_v10_0_is_in_vblank(adev, crtc)) {
245 if (i++ == 100) {
246 i = 0;
247 if (!dce_v10_0_is_counter_moving(adev, crtc))
248 break;
249 }
250 }
251 }
252
253 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
254 {
255 if (crtc >= adev->mode_info.num_crtc)
256 return 0;
257 else
258 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
259 }
260
261 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
262 {
263 unsigned i;
264
265 /* Enable pflip interrupts */
266 for (i = 0; i < adev->mode_info.num_crtc; i++)
267 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
268 }
269
270 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
271 {
272 unsigned i;
273
274 /* Disable pflip interrupts */
275 for (i = 0; i < adev->mode_info.num_crtc; i++)
276 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
277 }
278
279 /**
280 * dce_v10_0_page_flip - pageflip callback.
281 *
282 * @adev: amdgpu_device pointer
283 * @crtc_id: crtc to cleanup pageflip on
284 * @crtc_base: new address of the crtc (GPU MC address)
285 *
286 * Triggers the actual pageflip by updating the primary
287 * surface base address.
288 */
289 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
290 int crtc_id, u64 crtc_base, bool async)
291 {
292 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
293 u32 tmp;
294
295 /* flip at hsync for async, default is vsync */
296 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
297 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
298 GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
299 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
300 /* update the primary scanout address */
301 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
302 upper_32_bits(crtc_base));
303 /* writing to the low address triggers the update */
304 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
305 lower_32_bits(crtc_base));
306 /* post the write */
307 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
308 }
309
310 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
311 u32 *vbl, u32 *position)
312 {
313 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
314 return -EINVAL;
315
316 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
317 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
318
319 return 0;
320 }
321
322 /**
323 * dce_v10_0_hpd_sense - hpd sense callback.
324 *
325 * @adev: amdgpu_device pointer
326 * @hpd: hpd (hotplug detect) pin
327 *
328 * Checks if a digital monitor is connected (evergreen+).
329 * Returns true if connected, false if not connected.
330 */
331 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
332 enum amdgpu_hpd_id hpd)
333 {
334 bool connected = false;
335
336 if (hpd >= adev->mode_info.num_hpd)
337 return connected;
338
339 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
340 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
341 connected = true;
342
343 return connected;
344 }
345
346 /**
347 * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
348 *
349 * @adev: amdgpu_device pointer
350 * @hpd: hpd (hotplug detect) pin
351 *
352 * Set the polarity of the hpd pin (evergreen+).
353 */
354 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
355 enum amdgpu_hpd_id hpd)
356 {
357 u32 tmp;
358 bool connected = dce_v10_0_hpd_sense(adev, hpd);
359
360 if (hpd >= adev->mode_info.num_hpd)
361 return;
362
363 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
364 if (connected)
365 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
366 else
367 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
368 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
369 }
370
371 /**
372 * dce_v10_0_hpd_init - hpd setup callback.
373 *
374 * @adev: amdgpu_device pointer
375 *
376 * Setup the hpd pins used by the card (evergreen+).
377 * Enable the pin, set the polarity, and enable the hpd interrupts.
378 */
379 static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
380 {
381 struct drm_device *dev = adev->ddev;
382 struct drm_connector *connector;
383 u32 tmp;
384
385 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
386 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
387
388 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
389 continue;
390
391 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
392 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
393 /* don't try to enable hpd on eDP or LVDS avoid breaking the
394 * aux dp channel on imac and help (but not completely fix)
395 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
396 * also avoid interrupt storms during dpms.
397 */
398 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
399 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
400 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
401 continue;
402 }
403
404 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
405 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
406 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
407
408 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
409 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
410 DC_HPD_CONNECT_INT_DELAY,
411 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
412 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
413 DC_HPD_DISCONNECT_INT_DELAY,
414 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
415 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
416
417 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
418 amdgpu_irq_get(adev, &adev->hpd_irq,
419 amdgpu_connector->hpd.hpd);
420 }
421 }
422
423 /**
424 * dce_v10_0_hpd_fini - hpd tear down callback.
425 *
426 * @adev: amdgpu_device pointer
427 *
428 * Tear down the hpd pins used by the card (evergreen+).
429 * Disable the hpd interrupts.
430 */
431 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
432 {
433 struct drm_device *dev = adev->ddev;
434 struct drm_connector *connector;
435 u32 tmp;
436
437 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
438 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
439
440 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
441 continue;
442
443 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
444 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
445 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
446
447 amdgpu_irq_put(adev, &adev->hpd_irq,
448 amdgpu_connector->hpd.hpd);
449 }
450 }
451
452 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
453 {
454 return mmDC_GPIO_HPD_A;
455 }
456
457 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
458 {
459 u32 crtc_hung = 0;
460 u32 crtc_status[6];
461 u32 i, j, tmp;
462
463 for (i = 0; i < adev->mode_info.num_crtc; i++) {
464 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
465 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
466 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
467 crtc_hung |= (1 << i);
468 }
469 }
470
471 for (j = 0; j < 10; j++) {
472 for (i = 0; i < adev->mode_info.num_crtc; i++) {
473 if (crtc_hung & (1 << i)) {
474 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
475 if (tmp != crtc_status[i])
476 crtc_hung &= ~(1 << i);
477 }
478 }
479 if (crtc_hung == 0)
480 return false;
481 udelay(100);
482 }
483
484 return true;
485 }
486
487 static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
488 struct amdgpu_mode_mc_save *save)
489 {
490 u32 crtc_enabled, tmp;
491 int i;
492
493 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
494 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
495
496 /* disable VGA render */
497 tmp = RREG32(mmVGA_RENDER_CONTROL);
498 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
499 WREG32(mmVGA_RENDER_CONTROL, tmp);
500
501 /* blank the display controllers */
502 for (i = 0; i < adev->mode_info.num_crtc; i++) {
503 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
504 CRTC_CONTROL, CRTC_MASTER_EN);
505 if (crtc_enabled) {
506 #if 0
507 u32 frame_count;
508 int j;
509
510 save->crtc_enabled[i] = true;
511 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
512 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
513 amdgpu_display_vblank_wait(adev, i);
514 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
515 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
516 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
517 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
518 }
519 /* wait for the next frame */
520 frame_count = amdgpu_display_vblank_get_counter(adev, i);
521 for (j = 0; j < adev->usec_timeout; j++) {
522 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
523 break;
524 udelay(1);
525 }
526 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
527 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
528 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
529 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
530 }
531 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
532 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
533 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
534 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
535 }
536 #else
537 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
538 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
539 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
540 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
541 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
542 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
543 save->crtc_enabled[i] = false;
544 /* ***** */
545 #endif
546 } else {
547 save->crtc_enabled[i] = false;
548 }
549 }
550 }
551
552 static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
553 struct amdgpu_mode_mc_save *save)
554 {
555 u32 tmp, frame_count;
556 int i, j;
557
558 /* update crtc base addresses */
559 for (i = 0; i < adev->mode_info.num_crtc; i++) {
560 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
561 upper_32_bits(adev->mc.vram_start));
562 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
563 upper_32_bits(adev->mc.vram_start));
564 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
565 (u32)adev->mc.vram_start);
566 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
567 (u32)adev->mc.vram_start);
568
569 if (save->crtc_enabled[i]) {
570 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
571 if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 0) {
572 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 0);
573 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
574 }
575 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
576 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
577 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
578 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
579 }
580 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
581 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
582 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
583 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
584 }
585 for (j = 0; j < adev->usec_timeout; j++) {
586 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
587 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
588 break;
589 udelay(1);
590 }
591 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
592 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
593 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
594 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
595 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
596 /* wait for the next frame */
597 frame_count = amdgpu_display_vblank_get_counter(adev, i);
598 for (j = 0; j < adev->usec_timeout; j++) {
599 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
600 break;
601 udelay(1);
602 }
603 }
604 }
605
606 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
607 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
608
609 /* Unlock vga access */
610 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
611 mdelay(1);
612 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
613 }
614
615 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
616 bool render)
617 {
618 u32 tmp;
619
620 /* Lockout access through VGA aperture*/
621 tmp = RREG32(mmVGA_HDP_CONTROL);
622 if (render)
623 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
624 else
625 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
626 WREG32(mmVGA_HDP_CONTROL, tmp);
627
628 /* disable VGA render */
629 tmp = RREG32(mmVGA_RENDER_CONTROL);
630 if (render)
631 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
632 else
633 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
634 WREG32(mmVGA_RENDER_CONTROL, tmp);
635 }
636
637 static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
638 {
639 int num_crtc = 0;
640
641 switch (adev->asic_type) {
642 case CHIP_FIJI:
643 case CHIP_TONGA:
644 num_crtc = 6;
645 break;
646 default:
647 num_crtc = 0;
648 }
649 return num_crtc;
650 }
651
652 void dce_v10_0_disable_dce(struct amdgpu_device *adev)
653 {
654 /*Disable VGA render and enabled crtc, if has DCE engine*/
655 if (amdgpu_atombios_has_dce_engine_info(adev)) {
656 u32 tmp;
657 int crtc_enabled, i;
658
659 dce_v10_0_set_vga_render_state(adev, false);
660
661 /*Disable crtc*/
662 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
663 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
664 CRTC_CONTROL, CRTC_MASTER_EN);
665 if (crtc_enabled) {
666 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
667 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
668 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
669 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
670 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
671 }
672 }
673 }
674 }
675
676 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
677 {
678 struct drm_device *dev = encoder->dev;
679 struct amdgpu_device *adev = dev->dev_private;
680 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
681 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
682 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
683 int bpc = 0;
684 u32 tmp = 0;
685 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
686
687 if (connector) {
688 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
689 bpc = amdgpu_connector_get_monitor_bpc(connector);
690 dither = amdgpu_connector->dither;
691 }
692
693 /* LVDS/eDP FMT is set up by atom */
694 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
695 return;
696
697 /* not needed for analog */
698 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
699 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
700 return;
701
702 if (bpc == 0)
703 return;
704
705 switch (bpc) {
706 case 6:
707 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
708 /* XXX sort out optimal dither settings */
709 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
710 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
711 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
712 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
713 } else {
714 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
715 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
716 }
717 break;
718 case 8:
719 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
720 /* XXX sort out optimal dither settings */
721 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
722 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
723 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
724 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
725 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
726 } else {
727 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
728 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
729 }
730 break;
731 case 10:
732 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
733 /* XXX sort out optimal dither settings */
734 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
735 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
736 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
737 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
738 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
739 } else {
740 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
741 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
742 }
743 break;
744 default:
745 /* not needed */
746 break;
747 }
748
749 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
750 }
751
752
753 /* display watermark setup */
754 /**
755 * dce_v10_0_line_buffer_adjust - Set up the line buffer
756 *
757 * @adev: amdgpu_device pointer
758 * @amdgpu_crtc: the selected display controller
759 * @mode: the current display mode on the selected display
760 * controller
761 *
762 * Setup up the line buffer allocation for
763 * the selected display controller (CIK).
764 * Returns the line buffer size in pixels.
765 */
766 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
767 struct amdgpu_crtc *amdgpu_crtc,
768 struct drm_display_mode *mode)
769 {
770 u32 tmp, buffer_alloc, i, mem_cfg;
771 u32 pipe_offset = amdgpu_crtc->crtc_id;
772 /*
773 * Line Buffer Setup
774 * There are 6 line buffers, one for each display controllers.
775 * There are 3 partitions per LB. Select the number of partitions
776 * to enable based on the display width. For display widths larger
777 * than 4096, you need use to use 2 display controllers and combine
778 * them using the stereo blender.
779 */
780 if (amdgpu_crtc->base.enabled && mode) {
781 if (mode->crtc_hdisplay < 1920) {
782 mem_cfg = 1;
783 buffer_alloc = 2;
784 } else if (mode->crtc_hdisplay < 2560) {
785 mem_cfg = 2;
786 buffer_alloc = 2;
787 } else if (mode->crtc_hdisplay < 4096) {
788 mem_cfg = 0;
789 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
790 } else {
791 DRM_DEBUG_KMS("Mode too big for LB!\n");
792 mem_cfg = 0;
793 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
794 }
795 } else {
796 mem_cfg = 1;
797 buffer_alloc = 0;
798 }
799
800 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
801 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
802 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
803
804 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
805 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
806 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
807
808 for (i = 0; i < adev->usec_timeout; i++) {
809 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
810 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
811 break;
812 udelay(1);
813 }
814
815 if (amdgpu_crtc->base.enabled && mode) {
816 switch (mem_cfg) {
817 case 0:
818 default:
819 return 4096 * 2;
820 case 1:
821 return 1920 * 2;
822 case 2:
823 return 2560 * 2;
824 }
825 }
826
827 /* controller not enabled, so no lb used */
828 return 0;
829 }
830
831 /**
832 * cik_get_number_of_dram_channels - get the number of dram channels
833 *
834 * @adev: amdgpu_device pointer
835 *
836 * Look up the number of video ram channels (CIK).
837 * Used for display watermark bandwidth calculations
838 * Returns the number of dram channels
839 */
840 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
841 {
842 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
843
844 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
845 case 0:
846 default:
847 return 1;
848 case 1:
849 return 2;
850 case 2:
851 return 4;
852 case 3:
853 return 8;
854 case 4:
855 return 3;
856 case 5:
857 return 6;
858 case 6:
859 return 10;
860 case 7:
861 return 12;
862 case 8:
863 return 16;
864 }
865 }
866
867 struct dce10_wm_params {
868 u32 dram_channels; /* number of dram channels */
869 u32 yclk; /* bandwidth per dram data pin in kHz */
870 u32 sclk; /* engine clock in kHz */
871 u32 disp_clk; /* display clock in kHz */
872 u32 src_width; /* viewport width */
873 u32 active_time; /* active display time in ns */
874 u32 blank_time; /* blank time in ns */
875 bool interlaced; /* mode is interlaced */
876 fixed20_12 vsc; /* vertical scale ratio */
877 u32 num_heads; /* number of active crtcs */
878 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
879 u32 lb_size; /* line buffer allocated to pipe */
880 u32 vtaps; /* vertical scaler taps */
881 };
882
883 /**
884 * dce_v10_0_dram_bandwidth - get the dram bandwidth
885 *
886 * @wm: watermark calculation data
887 *
888 * Calculate the raw dram bandwidth (CIK).
889 * Used for display watermark bandwidth calculations
890 * Returns the dram bandwidth in MBytes/s
891 */
892 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
893 {
894 /* Calculate raw DRAM Bandwidth */
895 fixed20_12 dram_efficiency; /* 0.7 */
896 fixed20_12 yclk, dram_channels, bandwidth;
897 fixed20_12 a;
898
899 a.full = dfixed_const(1000);
900 yclk.full = dfixed_const(wm->yclk);
901 yclk.full = dfixed_div(yclk, a);
902 dram_channels.full = dfixed_const(wm->dram_channels * 4);
903 a.full = dfixed_const(10);
904 dram_efficiency.full = dfixed_const(7);
905 dram_efficiency.full = dfixed_div(dram_efficiency, a);
906 bandwidth.full = dfixed_mul(dram_channels, yclk);
907 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
908
909 return dfixed_trunc(bandwidth);
910 }
911
912 /**
913 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
914 *
915 * @wm: watermark calculation data
916 *
917 * Calculate the dram bandwidth used for display (CIK).
918 * Used for display watermark bandwidth calculations
919 * Returns the dram bandwidth for display in MBytes/s
920 */
921 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
922 {
923 /* Calculate DRAM Bandwidth and the part allocated to display. */
924 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
925 fixed20_12 yclk, dram_channels, bandwidth;
926 fixed20_12 a;
927
928 a.full = dfixed_const(1000);
929 yclk.full = dfixed_const(wm->yclk);
930 yclk.full = dfixed_div(yclk, a);
931 dram_channels.full = dfixed_const(wm->dram_channels * 4);
932 a.full = dfixed_const(10);
933 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
934 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
935 bandwidth.full = dfixed_mul(dram_channels, yclk);
936 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
937
938 return dfixed_trunc(bandwidth);
939 }
940
941 /**
942 * dce_v10_0_data_return_bandwidth - get the data return bandwidth
943 *
944 * @wm: watermark calculation data
945 *
946 * Calculate the data return bandwidth used for display (CIK).
947 * Used for display watermark bandwidth calculations
948 * Returns the data return bandwidth in MBytes/s
949 */
950 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
951 {
952 /* Calculate the display Data return Bandwidth */
953 fixed20_12 return_efficiency; /* 0.8 */
954 fixed20_12 sclk, bandwidth;
955 fixed20_12 a;
956
957 a.full = dfixed_const(1000);
958 sclk.full = dfixed_const(wm->sclk);
959 sclk.full = dfixed_div(sclk, a);
960 a.full = dfixed_const(10);
961 return_efficiency.full = dfixed_const(8);
962 return_efficiency.full = dfixed_div(return_efficiency, a);
963 a.full = dfixed_const(32);
964 bandwidth.full = dfixed_mul(a, sclk);
965 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
966
967 return dfixed_trunc(bandwidth);
968 }
969
970 /**
971 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
972 *
973 * @wm: watermark calculation data
974 *
975 * Calculate the dmif bandwidth used for display (CIK).
976 * Used for display watermark bandwidth calculations
977 * Returns the dmif bandwidth in MBytes/s
978 */
979 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
980 {
981 /* Calculate the DMIF Request Bandwidth */
982 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
983 fixed20_12 disp_clk, bandwidth;
984 fixed20_12 a, b;
985
986 a.full = dfixed_const(1000);
987 disp_clk.full = dfixed_const(wm->disp_clk);
988 disp_clk.full = dfixed_div(disp_clk, a);
989 a.full = dfixed_const(32);
990 b.full = dfixed_mul(a, disp_clk);
991
992 a.full = dfixed_const(10);
993 disp_clk_request_efficiency.full = dfixed_const(8);
994 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
995
996 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
997
998 return dfixed_trunc(bandwidth);
999 }
1000
1001 /**
1002 * dce_v10_0_available_bandwidth - get the min available bandwidth
1003 *
1004 * @wm: watermark calculation data
1005 *
1006 * Calculate the min available bandwidth used for display (CIK).
1007 * Used for display watermark bandwidth calculations
1008 * Returns the min available bandwidth in MBytes/s
1009 */
1010 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
1011 {
1012 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1013 u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
1014 u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
1015 u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
1016
1017 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1018 }
1019
1020 /**
1021 * dce_v10_0_average_bandwidth - get the average available bandwidth
1022 *
1023 * @wm: watermark calculation data
1024 *
1025 * Calculate the average available bandwidth used for display (CIK).
1026 * Used for display watermark bandwidth calculations
1027 * Returns the average available bandwidth in MBytes/s
1028 */
1029 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
1030 {
1031 /* Calculate the display mode Average Bandwidth
1032 * DisplayMode should contain the source and destination dimensions,
1033 * timing, etc.
1034 */
1035 fixed20_12 bpp;
1036 fixed20_12 line_time;
1037 fixed20_12 src_width;
1038 fixed20_12 bandwidth;
1039 fixed20_12 a;
1040
1041 a.full = dfixed_const(1000);
1042 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1043 line_time.full = dfixed_div(line_time, a);
1044 bpp.full = dfixed_const(wm->bytes_per_pixel);
1045 src_width.full = dfixed_const(wm->src_width);
1046 bandwidth.full = dfixed_mul(src_width, bpp);
1047 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1048 bandwidth.full = dfixed_div(bandwidth, line_time);
1049
1050 return dfixed_trunc(bandwidth);
1051 }
1052
1053 /**
1054 * dce_v10_0_latency_watermark - get the latency watermark
1055 *
1056 * @wm: watermark calculation data
1057 *
1058 * Calculate the latency watermark (CIK).
1059 * Used for display watermark bandwidth calculations
1060 * Returns the latency watermark in ns
1061 */
1062 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
1063 {
1064 /* First calculate the latency in ns */
1065 u32 mc_latency = 2000; /* 2000 ns. */
1066 u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
1067 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1068 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1069 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1070 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1071 (wm->num_heads * cursor_line_pair_return_time);
1072 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1073 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1074 u32 tmp, dmif_size = 12288;
1075 fixed20_12 a, b, c;
1076
1077 if (wm->num_heads == 0)
1078 return 0;
1079
1080 a.full = dfixed_const(2);
1081 b.full = dfixed_const(1);
1082 if ((wm->vsc.full > a.full) ||
1083 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1084 (wm->vtaps >= 5) ||
1085 ((wm->vsc.full >= a.full) && wm->interlaced))
1086 max_src_lines_per_dst_line = 4;
1087 else
1088 max_src_lines_per_dst_line = 2;
1089
1090 a.full = dfixed_const(available_bandwidth);
1091 b.full = dfixed_const(wm->num_heads);
1092 a.full = dfixed_div(a, b);
1093 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
1094 tmp = min(dfixed_trunc(a), tmp);
1095
1096 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
1097
1098 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1099 b.full = dfixed_const(1000);
1100 c.full = dfixed_const(lb_fill_bw);
1101 b.full = dfixed_div(c, b);
1102 a.full = dfixed_div(a, b);
1103 line_fill_time = dfixed_trunc(a);
1104
1105 if (line_fill_time < wm->active_time)
1106 return latency;
1107 else
1108 return latency + (line_fill_time - wm->active_time);
1109
1110 }
1111
1112 /**
1113 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1114 * average and available dram bandwidth
1115 *
1116 * @wm: watermark calculation data
1117 *
1118 * Check if the display average bandwidth fits in the display
1119 * dram bandwidth (CIK).
1120 * Used for display watermark bandwidth calculations
1121 * Returns true if the display fits, false if not.
1122 */
1123 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1124 {
1125 if (dce_v10_0_average_bandwidth(wm) <=
1126 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1127 return true;
1128 else
1129 return false;
1130 }
1131
1132 /**
1133 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
1134 * average and available bandwidth
1135 *
1136 * @wm: watermark calculation data
1137 *
1138 * Check if the display average bandwidth fits in the display
1139 * available bandwidth (CIK).
1140 * Used for display watermark bandwidth calculations
1141 * Returns true if the display fits, false if not.
1142 */
1143 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1144 {
1145 if (dce_v10_0_average_bandwidth(wm) <=
1146 (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
1147 return true;
1148 else
1149 return false;
1150 }
1151
1152 /**
1153 * dce_v10_0_check_latency_hiding - check latency hiding
1154 *
1155 * @wm: watermark calculation data
1156 *
1157 * Check latency hiding (CIK).
1158 * Used for display watermark bandwidth calculations
1159 * Returns true if the display fits, false if not.
1160 */
1161 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
1162 {
1163 u32 lb_partitions = wm->lb_size / wm->src_width;
1164 u32 line_time = wm->active_time + wm->blank_time;
1165 u32 latency_tolerant_lines;
1166 u32 latency_hiding;
1167 fixed20_12 a;
1168
1169 a.full = dfixed_const(1);
1170 if (wm->vsc.full > a.full)
1171 latency_tolerant_lines = 1;
1172 else {
1173 if (lb_partitions <= (wm->vtaps + 1))
1174 latency_tolerant_lines = 1;
1175 else
1176 latency_tolerant_lines = 2;
1177 }
1178
1179 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1180
1181 if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1182 return true;
1183 else
1184 return false;
1185 }
1186
1187 /**
1188 * dce_v10_0_program_watermarks - program display watermarks
1189 *
1190 * @adev: amdgpu_device pointer
1191 * @amdgpu_crtc: the selected display controller
1192 * @lb_size: line buffer size
1193 * @num_heads: number of display controllers in use
1194 *
1195 * Calculate and program the display watermarks for the
1196 * selected display controller (CIK).
1197 */
1198 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1199 struct amdgpu_crtc *amdgpu_crtc,
1200 u32 lb_size, u32 num_heads)
1201 {
1202 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1203 struct dce10_wm_params wm_low, wm_high;
1204 u32 active_time;
1205 u32 line_time = 0;
1206 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1207 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1208
1209 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1210 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1211 (u32)mode->clock);
1212 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1213 (u32)mode->clock);
1214 line_time = min(line_time, (u32)65535);
1215
1216 /* watermark for high clocks */
1217 if (adev->pm.dpm_enabled) {
1218 wm_high.yclk =
1219 amdgpu_dpm_get_mclk(adev, false) * 10;
1220 wm_high.sclk =
1221 amdgpu_dpm_get_sclk(adev, false) * 10;
1222 } else {
1223 wm_high.yclk = adev->pm.current_mclk * 10;
1224 wm_high.sclk = adev->pm.current_sclk * 10;
1225 }
1226
1227 wm_high.disp_clk = mode->clock;
1228 wm_high.src_width = mode->crtc_hdisplay;
1229 wm_high.active_time = active_time;
1230 wm_high.blank_time = line_time - wm_high.active_time;
1231 wm_high.interlaced = false;
1232 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1233 wm_high.interlaced = true;
1234 wm_high.vsc = amdgpu_crtc->vsc;
1235 wm_high.vtaps = 1;
1236 if (amdgpu_crtc->rmx_type != RMX_OFF)
1237 wm_high.vtaps = 2;
1238 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1239 wm_high.lb_size = lb_size;
1240 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1241 wm_high.num_heads = num_heads;
1242
1243 /* set for high clocks */
1244 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1245
1246 /* possibly force display priority to high */
1247 /* should really do this at mode validation time... */
1248 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1249 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1250 !dce_v10_0_check_latency_hiding(&wm_high) ||
1251 (adev->mode_info.disp_priority == 2)) {
1252 DRM_DEBUG_KMS("force priority to high\n");
1253 }
1254
1255 /* watermark for low clocks */
1256 if (adev->pm.dpm_enabled) {
1257 wm_low.yclk =
1258 amdgpu_dpm_get_mclk(adev, true) * 10;
1259 wm_low.sclk =
1260 amdgpu_dpm_get_sclk(adev, true) * 10;
1261 } else {
1262 wm_low.yclk = adev->pm.current_mclk * 10;
1263 wm_low.sclk = adev->pm.current_sclk * 10;
1264 }
1265
1266 wm_low.disp_clk = mode->clock;
1267 wm_low.src_width = mode->crtc_hdisplay;
1268 wm_low.active_time = active_time;
1269 wm_low.blank_time = line_time - wm_low.active_time;
1270 wm_low.interlaced = false;
1271 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1272 wm_low.interlaced = true;
1273 wm_low.vsc = amdgpu_crtc->vsc;
1274 wm_low.vtaps = 1;
1275 if (amdgpu_crtc->rmx_type != RMX_OFF)
1276 wm_low.vtaps = 2;
1277 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1278 wm_low.lb_size = lb_size;
1279 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1280 wm_low.num_heads = num_heads;
1281
1282 /* set for low clocks */
1283 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1284
1285 /* possibly force display priority to high */
1286 /* should really do this at mode validation time... */
1287 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1288 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1289 !dce_v10_0_check_latency_hiding(&wm_low) ||
1290 (adev->mode_info.disp_priority == 2)) {
1291 DRM_DEBUG_KMS("force priority to high\n");
1292 }
1293 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1294 }
1295
1296 /* select wm A */
1297 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1298 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1299 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1300 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1301 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1302 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1303 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1304 /* select wm B */
1305 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1306 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1307 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1308 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1309 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1310 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1311 /* restore original selection */
1312 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1313
1314 /* save values for DPM */
1315 amdgpu_crtc->line_time = line_time;
1316 amdgpu_crtc->wm_high = latency_watermark_a;
1317 amdgpu_crtc->wm_low = latency_watermark_b;
1318 /* Save number of lines the linebuffer leads before the scanout */
1319 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1320 }
1321
1322 /**
1323 * dce_v10_0_bandwidth_update - program display watermarks
1324 *
1325 * @adev: amdgpu_device pointer
1326 *
1327 * Calculate and program the display watermarks and line
1328 * buffer allocation (CIK).
1329 */
1330 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1331 {
1332 struct drm_display_mode *mode = NULL;
1333 u32 num_heads = 0, lb_size;
1334 int i;
1335
1336 amdgpu_update_display_priority(adev);
1337
1338 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1339 if (adev->mode_info.crtcs[i]->base.enabled)
1340 num_heads++;
1341 }
1342 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1343 mode = &adev->mode_info.crtcs[i]->base.mode;
1344 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1345 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1346 lb_size, num_heads);
1347 }
1348 }
1349
1350 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1351 {
1352 int i;
1353 u32 offset, tmp;
1354
1355 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1356 offset = adev->mode_info.audio.pin[i].offset;
1357 tmp = RREG32_AUDIO_ENDPT(offset,
1358 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1359 if (((tmp &
1360 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1361 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1362 adev->mode_info.audio.pin[i].connected = false;
1363 else
1364 adev->mode_info.audio.pin[i].connected = true;
1365 }
1366 }
1367
1368 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1369 {
1370 int i;
1371
1372 dce_v10_0_audio_get_connected_pins(adev);
1373
1374 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1375 if (adev->mode_info.audio.pin[i].connected)
1376 return &adev->mode_info.audio.pin[i];
1377 }
1378 DRM_ERROR("No connected audio pins found!\n");
1379 return NULL;
1380 }
1381
1382 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1383 {
1384 struct amdgpu_device *adev = encoder->dev->dev_private;
1385 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1386 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1387 u32 tmp;
1388
1389 if (!dig || !dig->afmt || !dig->afmt->pin)
1390 return;
1391
1392 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1393 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1394 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1395 }
1396
1397 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1398 struct drm_display_mode *mode)
1399 {
1400 struct amdgpu_device *adev = encoder->dev->dev_private;
1401 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1402 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1403 struct drm_connector *connector;
1404 struct amdgpu_connector *amdgpu_connector = NULL;
1405 u32 tmp;
1406 int interlace = 0;
1407
1408 if (!dig || !dig->afmt || !dig->afmt->pin)
1409 return;
1410
1411 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1412 if (connector->encoder == encoder) {
1413 amdgpu_connector = to_amdgpu_connector(connector);
1414 break;
1415 }
1416 }
1417
1418 if (!amdgpu_connector) {
1419 DRM_ERROR("Couldn't find encoder's connector\n");
1420 return;
1421 }
1422
1423 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1424 interlace = 1;
1425 if (connector->latency_present[interlace]) {
1426 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1427 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1428 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1429 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1430 } else {
1431 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1432 VIDEO_LIPSYNC, 0);
1433 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1434 AUDIO_LIPSYNC, 0);
1435 }
1436 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1437 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1438 }
1439
1440 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1441 {
1442 struct amdgpu_device *adev = encoder->dev->dev_private;
1443 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1444 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1445 struct drm_connector *connector;
1446 struct amdgpu_connector *amdgpu_connector = NULL;
1447 u32 tmp;
1448 u8 *sadb = NULL;
1449 int sad_count;
1450
1451 if (!dig || !dig->afmt || !dig->afmt->pin)
1452 return;
1453
1454 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1455 if (connector->encoder == encoder) {
1456 amdgpu_connector = to_amdgpu_connector(connector);
1457 break;
1458 }
1459 }
1460
1461 if (!amdgpu_connector) {
1462 DRM_ERROR("Couldn't find encoder's connector\n");
1463 return;
1464 }
1465
1466 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1467 if (sad_count < 0) {
1468 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1469 sad_count = 0;
1470 }
1471
1472 /* program the speaker allocation */
1473 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1474 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1475 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1476 DP_CONNECTION, 0);
1477 /* set HDMI mode */
1478 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1479 HDMI_CONNECTION, 1);
1480 if (sad_count)
1481 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1482 SPEAKER_ALLOCATION, sadb[0]);
1483 else
1484 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1485 SPEAKER_ALLOCATION, 5); /* stereo */
1486 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1487 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1488
1489 kfree(sadb);
1490 }
1491
1492 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1493 {
1494 struct amdgpu_device *adev = encoder->dev->dev_private;
1495 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1496 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1497 struct drm_connector *connector;
1498 struct amdgpu_connector *amdgpu_connector = NULL;
1499 struct cea_sad *sads;
1500 int i, sad_count;
1501
1502 static const u16 eld_reg_to_type[][2] = {
1503 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1504 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1505 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1506 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1507 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1508 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1509 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1510 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1511 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1512 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1513 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1514 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1515 };
1516
1517 if (!dig || !dig->afmt || !dig->afmt->pin)
1518 return;
1519
1520 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1521 if (connector->encoder == encoder) {
1522 amdgpu_connector = to_amdgpu_connector(connector);
1523 break;
1524 }
1525 }
1526
1527 if (!amdgpu_connector) {
1528 DRM_ERROR("Couldn't find encoder's connector\n");
1529 return;
1530 }
1531
1532 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1533 if (sad_count <= 0) {
1534 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1535 return;
1536 }
1537 BUG_ON(!sads);
1538
1539 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1540 u32 tmp = 0;
1541 u8 stereo_freqs = 0;
1542 int max_channels = -1;
1543 int j;
1544
1545 for (j = 0; j < sad_count; j++) {
1546 struct cea_sad *sad = &sads[j];
1547
1548 if (sad->format == eld_reg_to_type[i][1]) {
1549 if (sad->channels > max_channels) {
1550 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1551 MAX_CHANNELS, sad->channels);
1552 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1553 DESCRIPTOR_BYTE_2, sad->byte2);
1554 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1555 SUPPORTED_FREQUENCIES, sad->freq);
1556 max_channels = sad->channels;
1557 }
1558
1559 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1560 stereo_freqs |= sad->freq;
1561 else
1562 break;
1563 }
1564 }
1565
1566 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1567 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1568 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1569 }
1570
1571 kfree(sads);
1572 }
1573
1574 static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1575 struct amdgpu_audio_pin *pin,
1576 bool enable)
1577 {
1578 if (!pin)
1579 return;
1580
1581 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1582 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1583 }
1584
1585 static const u32 pin_offsets[] =
1586 {
1587 AUD0_REGISTER_OFFSET,
1588 AUD1_REGISTER_OFFSET,
1589 AUD2_REGISTER_OFFSET,
1590 AUD3_REGISTER_OFFSET,
1591 AUD4_REGISTER_OFFSET,
1592 AUD5_REGISTER_OFFSET,
1593 AUD6_REGISTER_OFFSET,
1594 };
1595
1596 static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1597 {
1598 int i;
1599
1600 if (!amdgpu_audio)
1601 return 0;
1602
1603 adev->mode_info.audio.enabled = true;
1604
1605 adev->mode_info.audio.num_pins = 7;
1606
1607 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1608 adev->mode_info.audio.pin[i].channels = -1;
1609 adev->mode_info.audio.pin[i].rate = -1;
1610 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1611 adev->mode_info.audio.pin[i].status_bits = 0;
1612 adev->mode_info.audio.pin[i].category_code = 0;
1613 adev->mode_info.audio.pin[i].connected = false;
1614 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1615 adev->mode_info.audio.pin[i].id = i;
1616 /* disable audio. it will be set up later */
1617 /* XXX remove once we switch to ip funcs */
1618 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1619 }
1620
1621 return 0;
1622 }
1623
1624 static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1625 {
1626 int i;
1627
1628 if (!amdgpu_audio)
1629 return;
1630
1631 if (!adev->mode_info.audio.enabled)
1632 return;
1633
1634 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1635 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1636
1637 adev->mode_info.audio.enabled = false;
1638 }
1639
1640 /*
1641 * update the N and CTS parameters for a given pixel clock rate
1642 */
1643 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1644 {
1645 struct drm_device *dev = encoder->dev;
1646 struct amdgpu_device *adev = dev->dev_private;
1647 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1648 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1649 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1650 u32 tmp;
1651
1652 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1653 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1654 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1655 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1656 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1657 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1658
1659 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1660 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1661 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1662 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1663 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1664 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1665
1666 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1667 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1668 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1669 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1670 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1671 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1672
1673 }
1674
1675 /*
1676 * build a HDMI Video Info Frame
1677 */
1678 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1679 void *buffer, size_t size)
1680 {
1681 struct drm_device *dev = encoder->dev;
1682 struct amdgpu_device *adev = dev->dev_private;
1683 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1684 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1685 uint8_t *frame = buffer + 3;
1686 uint8_t *header = buffer;
1687
1688 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1689 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1690 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1691 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1692 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1693 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1694 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1695 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1696 }
1697
1698 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1699 {
1700 struct drm_device *dev = encoder->dev;
1701 struct amdgpu_device *adev = dev->dev_private;
1702 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1703 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1704 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1705 u32 dto_phase = 24 * 1000;
1706 u32 dto_modulo = clock;
1707 u32 tmp;
1708
1709 if (!dig || !dig->afmt)
1710 return;
1711
1712 /* XXX two dtos; generally use dto0 for hdmi */
1713 /* Express [24MHz / target pixel clock] as an exact rational
1714 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1715 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1716 */
1717 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1718 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1719 amdgpu_crtc->crtc_id);
1720 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1721 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1722 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1723 }
1724
1725 /*
1726 * update the info frames with the data from the current display mode
1727 */
1728 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1729 struct drm_display_mode *mode)
1730 {
1731 struct drm_device *dev = encoder->dev;
1732 struct amdgpu_device *adev = dev->dev_private;
1733 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1734 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1735 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1736 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1737 struct hdmi_avi_infoframe frame;
1738 ssize_t err;
1739 u32 tmp;
1740 int bpc = 8;
1741
1742 if (!dig || !dig->afmt)
1743 return;
1744
1745 /* Silent, r600_hdmi_enable will raise WARN for us */
1746 if (!dig->afmt->enabled)
1747 return;
1748
1749 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1750 if (encoder->crtc) {
1751 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1752 bpc = amdgpu_crtc->bpc;
1753 }
1754
1755 /* disable audio prior to setting up hw */
1756 dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1757 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1758
1759 dce_v10_0_audio_set_dto(encoder, mode->clock);
1760
1761 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1762 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1763 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1764
1765 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1766
1767 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1768 switch (bpc) {
1769 case 0:
1770 case 6:
1771 case 8:
1772 case 16:
1773 default:
1774 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1775 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1776 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1777 connector->name, bpc);
1778 break;
1779 case 10:
1780 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1781 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1782 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1783 connector->name);
1784 break;
1785 case 12:
1786 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1787 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1788 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1789 connector->name);
1790 break;
1791 }
1792 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1793
1794 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1795 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1796 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1797 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1798 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1799
1800 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1801 /* enable audio info frames (frames won't be set until audio is enabled) */
1802 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1803 /* required for audio info values to be updated */
1804 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1805 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1806
1807 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1808 /* required for audio info values to be updated */
1809 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1810 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1811
1812 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1813 /* anything other than 0 */
1814 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1815 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1816
1817 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1818
1819 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1820 /* set the default audio delay */
1821 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1822 /* should be suffient for all audio modes and small enough for all hblanks */
1823 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1824 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1825
1826 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1827 /* allow 60958 channel status fields to be updated */
1828 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1829 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1830
1831 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1832 if (bpc > 8)
1833 /* clear SW CTS value */
1834 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1835 else
1836 /* select SW CTS value */
1837 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1838 /* allow hw to sent ACR packets when required */
1839 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1840 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1841
1842 dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1843
1844 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1845 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1846 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1847
1848 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1849 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1850 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1851
1852 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1853 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1854 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1855 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1856 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1857 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1858 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1859 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1860
1861 dce_v10_0_audio_write_speaker_allocation(encoder);
1862
1863 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1864 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1865
1866 dce_v10_0_afmt_audio_select_pin(encoder);
1867 dce_v10_0_audio_write_sad_regs(encoder);
1868 dce_v10_0_audio_write_latency_fields(encoder, mode);
1869
1870 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1871 if (err < 0) {
1872 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1873 return;
1874 }
1875
1876 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1877 if (err < 0) {
1878 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1879 return;
1880 }
1881
1882 dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1883
1884 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1885 /* enable AVI info frames */
1886 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1887 /* required for audio info values to be updated */
1888 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1889 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1890
1891 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1892 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1893 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1894
1895 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1896 /* send audio packets */
1897 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1898 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1899
1900 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1901 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1902 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1903 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1904
1905 /* enable audio after to setting up hw */
1906 dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1907 }
1908
1909 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1910 {
1911 struct drm_device *dev = encoder->dev;
1912 struct amdgpu_device *adev = dev->dev_private;
1913 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1914 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1915
1916 if (!dig || !dig->afmt)
1917 return;
1918
1919 /* Silent, r600_hdmi_enable will raise WARN for us */
1920 if (enable && dig->afmt->enabled)
1921 return;
1922 if (!enable && !dig->afmt->enabled)
1923 return;
1924
1925 if (!enable && dig->afmt->pin) {
1926 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1927 dig->afmt->pin = NULL;
1928 }
1929
1930 dig->afmt->enabled = enable;
1931
1932 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1933 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1934 }
1935
1936 static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
1937 {
1938 int i;
1939
1940 for (i = 0; i < adev->mode_info.num_dig; i++)
1941 adev->mode_info.afmt[i] = NULL;
1942
1943 /* DCE10 has audio blocks tied to DIG encoders */
1944 for (i = 0; i < adev->mode_info.num_dig; i++) {
1945 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1946 if (adev->mode_info.afmt[i]) {
1947 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1948 adev->mode_info.afmt[i]->id = i;
1949 } else {
1950 int j;
1951 for (j = 0; j < i; j++) {
1952 kfree(adev->mode_info.afmt[j]);
1953 adev->mode_info.afmt[j] = NULL;
1954 }
1955 return -ENOMEM;
1956 }
1957 }
1958 return 0;
1959 }
1960
1961 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1962 {
1963 int i;
1964
1965 for (i = 0; i < adev->mode_info.num_dig; i++) {
1966 kfree(adev->mode_info.afmt[i]);
1967 adev->mode_info.afmt[i] = NULL;
1968 }
1969 }
1970
1971 static const u32 vga_control_regs[6] =
1972 {
1973 mmD1VGA_CONTROL,
1974 mmD2VGA_CONTROL,
1975 mmD3VGA_CONTROL,
1976 mmD4VGA_CONTROL,
1977 mmD5VGA_CONTROL,
1978 mmD6VGA_CONTROL,
1979 };
1980
1981 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
1982 {
1983 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1984 struct drm_device *dev = crtc->dev;
1985 struct amdgpu_device *adev = dev->dev_private;
1986 u32 vga_control;
1987
1988 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1989 if (enable)
1990 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1991 else
1992 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1993 }
1994
1995 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
1996 {
1997 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1998 struct drm_device *dev = crtc->dev;
1999 struct amdgpu_device *adev = dev->dev_private;
2000
2001 if (enable)
2002 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2003 else
2004 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2005 }
2006
2007 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
2008 struct drm_framebuffer *fb,
2009 int x, int y, int atomic)
2010 {
2011 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2012 struct drm_device *dev = crtc->dev;
2013 struct amdgpu_device *adev = dev->dev_private;
2014 struct amdgpu_framebuffer *amdgpu_fb;
2015 struct drm_framebuffer *target_fb;
2016 struct drm_gem_object *obj;
2017 struct amdgpu_bo *abo;
2018 uint64_t fb_location, tiling_flags;
2019 uint32_t fb_format, fb_pitch_pixels;
2020 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2021 u32 pipe_config;
2022 u32 tmp, viewport_w, viewport_h;
2023 int r;
2024 bool bypass_lut = false;
2025 struct drm_format_name_buf format_name;
2026
2027 /* no fb bound */
2028 if (!atomic && !crtc->primary->fb) {
2029 DRM_DEBUG_KMS("No FB bound\n");
2030 return 0;
2031 }
2032
2033 if (atomic) {
2034 amdgpu_fb = to_amdgpu_framebuffer(fb);
2035 target_fb = fb;
2036 } else {
2037 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2038 target_fb = crtc->primary->fb;
2039 }
2040
2041 /* If atomic, assume fb object is pinned & idle & fenced and
2042 * just update base pointers
2043 */
2044 obj = amdgpu_fb->obj;
2045 abo = gem_to_amdgpu_bo(obj);
2046 r = amdgpu_bo_reserve(abo, false);
2047 if (unlikely(r != 0))
2048 return r;
2049
2050 if (atomic) {
2051 fb_location = amdgpu_bo_gpu_offset(abo);
2052 } else {
2053 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2054 if (unlikely(r != 0)) {
2055 amdgpu_bo_unreserve(abo);
2056 return -EINVAL;
2057 }
2058 }
2059
2060 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
2061 amdgpu_bo_unreserve(abo);
2062
2063 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2064
2065 switch (target_fb->format->format) {
2066 case DRM_FORMAT_C8:
2067 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2068 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2069 break;
2070 case DRM_FORMAT_XRGB4444:
2071 case DRM_FORMAT_ARGB4444:
2072 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2073 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2074 #ifdef __BIG_ENDIAN
2075 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2076 ENDIAN_8IN16);
2077 #endif
2078 break;
2079 case DRM_FORMAT_XRGB1555:
2080 case DRM_FORMAT_ARGB1555:
2081 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2082 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2083 #ifdef __BIG_ENDIAN
2084 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2085 ENDIAN_8IN16);
2086 #endif
2087 break;
2088 case DRM_FORMAT_BGRX5551:
2089 case DRM_FORMAT_BGRA5551:
2090 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2091 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2092 #ifdef __BIG_ENDIAN
2093 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2094 ENDIAN_8IN16);
2095 #endif
2096 break;
2097 case DRM_FORMAT_RGB565:
2098 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2099 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2100 #ifdef __BIG_ENDIAN
2101 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2102 ENDIAN_8IN16);
2103 #endif
2104 break;
2105 case DRM_FORMAT_XRGB8888:
2106 case DRM_FORMAT_ARGB8888:
2107 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2108 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2109 #ifdef __BIG_ENDIAN
2110 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2111 ENDIAN_8IN32);
2112 #endif
2113 break;
2114 case DRM_FORMAT_XRGB2101010:
2115 case DRM_FORMAT_ARGB2101010:
2116 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2117 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2118 #ifdef __BIG_ENDIAN
2119 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2120 ENDIAN_8IN32);
2121 #endif
2122 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2123 bypass_lut = true;
2124 break;
2125 case DRM_FORMAT_BGRX1010102:
2126 case DRM_FORMAT_BGRA1010102:
2127 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2128 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2129 #ifdef __BIG_ENDIAN
2130 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2131 ENDIAN_8IN32);
2132 #endif
2133 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2134 bypass_lut = true;
2135 break;
2136 default:
2137 DRM_ERROR("Unsupported screen format %s\n",
2138 drm_get_format_name(target_fb->format->format, &format_name));
2139 return -EINVAL;
2140 }
2141
2142 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2143 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2144
2145 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2146 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2147 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2148 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2149 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2150
2151 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2152 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2153 ARRAY_2D_TILED_THIN1);
2154 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2155 tile_split);
2156 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2157 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2158 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2159 mtaspect);
2160 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2161 ADDR_SURF_MICRO_TILING_DISPLAY);
2162 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2163 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2164 ARRAY_1D_TILED_THIN1);
2165 }
2166
2167 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2168 pipe_config);
2169
2170 dce_v10_0_vga_enable(crtc, false);
2171
2172 /* Make sure surface address is updated at vertical blank rather than
2173 * horizontal blank
2174 */
2175 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2176 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2177 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2178 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2179
2180 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2181 upper_32_bits(fb_location));
2182 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2183 upper_32_bits(fb_location));
2184 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2185 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2186 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2187 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2188 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2189 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2190
2191 /*
2192 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2193 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2194 * retain the full precision throughout the pipeline.
2195 */
2196 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2197 if (bypass_lut)
2198 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2199 else
2200 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2201 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2202
2203 if (bypass_lut)
2204 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2205
2206 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2207 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2208 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2209 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2210 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2211 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2212
2213 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2214 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2215
2216 dce_v10_0_grph_enable(crtc, true);
2217
2218 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2219 target_fb->height);
2220
2221 x &= ~3;
2222 y &= ~1;
2223 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2224 (x << 16) | y);
2225 viewport_w = crtc->mode.hdisplay;
2226 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2227 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2228 (viewport_w << 16) | viewport_h);
2229
2230 /* set pageflip to happen anywhere in vblank interval */
2231 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2232
2233 if (!atomic && fb && fb != crtc->primary->fb) {
2234 amdgpu_fb = to_amdgpu_framebuffer(fb);
2235 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2236 r = amdgpu_bo_reserve(abo, true);
2237 if (unlikely(r != 0))
2238 return r;
2239 amdgpu_bo_unpin(abo);
2240 amdgpu_bo_unreserve(abo);
2241 }
2242
2243 /* Bytes per pixel may have changed */
2244 dce_v10_0_bandwidth_update(adev);
2245
2246 return 0;
2247 }
2248
2249 static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2250 struct drm_display_mode *mode)
2251 {
2252 struct drm_device *dev = crtc->dev;
2253 struct amdgpu_device *adev = dev->dev_private;
2254 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2255 u32 tmp;
2256
2257 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2258 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2259 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2260 else
2261 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2262 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2263 }
2264
2265 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2266 {
2267 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2268 struct drm_device *dev = crtc->dev;
2269 struct amdgpu_device *adev = dev->dev_private;
2270 int i;
2271 u32 tmp;
2272
2273 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2274
2275 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2276 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2277 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2278 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2279
2280 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2281 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2282 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2283
2284 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2285 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2286 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2287
2288 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2289 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2290 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2291 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2292
2293 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2294
2295 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2296 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2297 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2298
2299 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2300 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2301 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2302
2303 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2304 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2305
2306 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2307 for (i = 0; i < 256; i++) {
2308 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2309 (amdgpu_crtc->lut_r[i] << 20) |
2310 (amdgpu_crtc->lut_g[i] << 10) |
2311 (amdgpu_crtc->lut_b[i] << 0));
2312 }
2313
2314 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2315 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2316 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2317 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2318 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2319
2320 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2321 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2322 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2323 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2324
2325 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2326 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2327 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2328 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2329
2330 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2331 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2332 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2333 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2334
2335 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2336 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2337 /* XXX this only needs to be programmed once per crtc at startup,
2338 * not sure where the best place for it is
2339 */
2340 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2341 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2342 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2343 }
2344
2345 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2346 {
2347 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2348 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2349
2350 switch (amdgpu_encoder->encoder_id) {
2351 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2352 if (dig->linkb)
2353 return 1;
2354 else
2355 return 0;
2356 break;
2357 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2358 if (dig->linkb)
2359 return 3;
2360 else
2361 return 2;
2362 break;
2363 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2364 if (dig->linkb)
2365 return 5;
2366 else
2367 return 4;
2368 break;
2369 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2370 return 6;
2371 break;
2372 default:
2373 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2374 return 0;
2375 }
2376 }
2377
2378 /**
2379 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2380 *
2381 * @crtc: drm crtc
2382 *
2383 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2384 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2385 * monitors a dedicated PPLL must be used. If a particular board has
2386 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2387 * as there is no need to program the PLL itself. If we are not able to
2388 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2389 * avoid messing up an existing monitor.
2390 *
2391 * Asic specific PLL information
2392 *
2393 * DCE 10.x
2394 * Tonga
2395 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2396 * CI
2397 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2398 *
2399 */
2400 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2401 {
2402 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2403 struct drm_device *dev = crtc->dev;
2404 struct amdgpu_device *adev = dev->dev_private;
2405 u32 pll_in_use;
2406 int pll;
2407
2408 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2409 if (adev->clock.dp_extclk)
2410 /* skip PPLL programming if using ext clock */
2411 return ATOM_PPLL_INVALID;
2412 else {
2413 /* use the same PPLL for all DP monitors */
2414 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2415 if (pll != ATOM_PPLL_INVALID)
2416 return pll;
2417 }
2418 } else {
2419 /* use the same PPLL for all monitors with the same clock */
2420 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2421 if (pll != ATOM_PPLL_INVALID)
2422 return pll;
2423 }
2424
2425 /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2426 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2427 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2428 return ATOM_PPLL2;
2429 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2430 return ATOM_PPLL1;
2431 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2432 return ATOM_PPLL0;
2433 DRM_ERROR("unable to allocate a PPLL\n");
2434 return ATOM_PPLL_INVALID;
2435 }
2436
2437 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2438 {
2439 struct amdgpu_device *adev = crtc->dev->dev_private;
2440 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2441 uint32_t cur_lock;
2442
2443 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2444 if (lock)
2445 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2446 else
2447 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2448 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2449 }
2450
2451 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2452 {
2453 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2454 struct amdgpu_device *adev = crtc->dev->dev_private;
2455 u32 tmp;
2456
2457 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2458 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2459 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2460 }
2461
2462 static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2463 {
2464 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2465 struct amdgpu_device *adev = crtc->dev->dev_private;
2466 u32 tmp;
2467
2468 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2469 upper_32_bits(amdgpu_crtc->cursor_addr));
2470 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2471 lower_32_bits(amdgpu_crtc->cursor_addr));
2472
2473 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2474 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2475 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2476 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2477 }
2478
2479 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2480 int x, int y)
2481 {
2482 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2483 struct amdgpu_device *adev = crtc->dev->dev_private;
2484 int xorigin = 0, yorigin = 0;
2485
2486 amdgpu_crtc->cursor_x = x;
2487 amdgpu_crtc->cursor_y = y;
2488
2489 /* avivo cursor are offset into the total surface */
2490 x += crtc->x;
2491 y += crtc->y;
2492 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2493
2494 if (x < 0) {
2495 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2496 x = 0;
2497 }
2498 if (y < 0) {
2499 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2500 y = 0;
2501 }
2502
2503 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2504 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2505 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2506 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2507
2508 return 0;
2509 }
2510
2511 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2512 int x, int y)
2513 {
2514 int ret;
2515
2516 dce_v10_0_lock_cursor(crtc, true);
2517 ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2518 dce_v10_0_lock_cursor(crtc, false);
2519
2520 return ret;
2521 }
2522
2523 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2524 struct drm_file *file_priv,
2525 uint32_t handle,
2526 uint32_t width,
2527 uint32_t height,
2528 int32_t hot_x,
2529 int32_t hot_y)
2530 {
2531 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2532 struct drm_gem_object *obj;
2533 struct amdgpu_bo *aobj;
2534 int ret;
2535
2536 if (!handle) {
2537 /* turn off cursor */
2538 dce_v10_0_hide_cursor(crtc);
2539 obj = NULL;
2540 goto unpin;
2541 }
2542
2543 if ((width > amdgpu_crtc->max_cursor_width) ||
2544 (height > amdgpu_crtc->max_cursor_height)) {
2545 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2546 return -EINVAL;
2547 }
2548
2549 obj = drm_gem_object_lookup(file_priv, handle);
2550 if (!obj) {
2551 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2552 return -ENOENT;
2553 }
2554
2555 aobj = gem_to_amdgpu_bo(obj);
2556 ret = amdgpu_bo_reserve(aobj, false);
2557 if (ret != 0) {
2558 drm_gem_object_unreference_unlocked(obj);
2559 return ret;
2560 }
2561
2562 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2563 amdgpu_bo_unreserve(aobj);
2564 if (ret) {
2565 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2566 drm_gem_object_unreference_unlocked(obj);
2567 return ret;
2568 }
2569
2570 dce_v10_0_lock_cursor(crtc, true);
2571
2572 if (width != amdgpu_crtc->cursor_width ||
2573 height != amdgpu_crtc->cursor_height ||
2574 hot_x != amdgpu_crtc->cursor_hot_x ||
2575 hot_y != amdgpu_crtc->cursor_hot_y) {
2576 int x, y;
2577
2578 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2579 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2580
2581 dce_v10_0_cursor_move_locked(crtc, x, y);
2582
2583 amdgpu_crtc->cursor_width = width;
2584 amdgpu_crtc->cursor_height = height;
2585 amdgpu_crtc->cursor_hot_x = hot_x;
2586 amdgpu_crtc->cursor_hot_y = hot_y;
2587 }
2588
2589 dce_v10_0_show_cursor(crtc);
2590 dce_v10_0_lock_cursor(crtc, false);
2591
2592 unpin:
2593 if (amdgpu_crtc->cursor_bo) {
2594 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2595 ret = amdgpu_bo_reserve(aobj, true);
2596 if (likely(ret == 0)) {
2597 amdgpu_bo_unpin(aobj);
2598 amdgpu_bo_unreserve(aobj);
2599 }
2600 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2601 }
2602
2603 amdgpu_crtc->cursor_bo = obj;
2604 return 0;
2605 }
2606
2607 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2608 {
2609 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2610
2611 if (amdgpu_crtc->cursor_bo) {
2612 dce_v10_0_lock_cursor(crtc, true);
2613
2614 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2615 amdgpu_crtc->cursor_y);
2616
2617 dce_v10_0_show_cursor(crtc);
2618
2619 dce_v10_0_lock_cursor(crtc, false);
2620 }
2621 }
2622
2623 static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2624 u16 *blue, uint32_t size,
2625 struct drm_modeset_acquire_ctx *ctx)
2626 {
2627 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2628 int i;
2629
2630 /* userspace palettes are always correct as is */
2631 for (i = 0; i < size; i++) {
2632 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2633 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2634 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2635 }
2636 dce_v10_0_crtc_load_lut(crtc);
2637
2638 return 0;
2639 }
2640
2641 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2642 {
2643 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2644
2645 drm_crtc_cleanup(crtc);
2646 kfree(amdgpu_crtc);
2647 }
2648
2649 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2650 .cursor_set2 = dce_v10_0_crtc_cursor_set2,
2651 .cursor_move = dce_v10_0_crtc_cursor_move,
2652 .gamma_set = dce_v10_0_crtc_gamma_set,
2653 .set_config = amdgpu_crtc_set_config,
2654 .destroy = dce_v10_0_crtc_destroy,
2655 .page_flip_target = amdgpu_crtc_page_flip_target,
2656 };
2657
2658 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2659 {
2660 struct drm_device *dev = crtc->dev;
2661 struct amdgpu_device *adev = dev->dev_private;
2662 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2663 unsigned type;
2664
2665 switch (mode) {
2666 case DRM_MODE_DPMS_ON:
2667 amdgpu_crtc->enabled = true;
2668 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2669 dce_v10_0_vga_enable(crtc, true);
2670 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2671 dce_v10_0_vga_enable(crtc, false);
2672 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2673 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2674 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2675 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2676 drm_crtc_vblank_on(crtc);
2677 dce_v10_0_crtc_load_lut(crtc);
2678 break;
2679 case DRM_MODE_DPMS_STANDBY:
2680 case DRM_MODE_DPMS_SUSPEND:
2681 case DRM_MODE_DPMS_OFF:
2682 drm_crtc_vblank_off(crtc);
2683 if (amdgpu_crtc->enabled) {
2684 dce_v10_0_vga_enable(crtc, true);
2685 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2686 dce_v10_0_vga_enable(crtc, false);
2687 }
2688 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2689 amdgpu_crtc->enabled = false;
2690 break;
2691 }
2692 /* adjust pm to dpms */
2693 amdgpu_pm_compute_clocks(adev);
2694 }
2695
2696 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2697 {
2698 /* disable crtc pair power gating before programming */
2699 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2700 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2701 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2702 }
2703
2704 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2705 {
2706 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2707 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2708 }
2709
2710 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2711 {
2712 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2713 struct drm_device *dev = crtc->dev;
2714 struct amdgpu_device *adev = dev->dev_private;
2715 struct amdgpu_atom_ss ss;
2716 int i;
2717
2718 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2719 if (crtc->primary->fb) {
2720 int r;
2721 struct amdgpu_framebuffer *amdgpu_fb;
2722 struct amdgpu_bo *abo;
2723
2724 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2725 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2726 r = amdgpu_bo_reserve(abo, true);
2727 if (unlikely(r))
2728 DRM_ERROR("failed to reserve abo before unpin\n");
2729 else {
2730 amdgpu_bo_unpin(abo);
2731 amdgpu_bo_unreserve(abo);
2732 }
2733 }
2734 /* disable the GRPH */
2735 dce_v10_0_grph_enable(crtc, false);
2736
2737 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2738
2739 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2740 if (adev->mode_info.crtcs[i] &&
2741 adev->mode_info.crtcs[i]->enabled &&
2742 i != amdgpu_crtc->crtc_id &&
2743 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2744 /* one other crtc is using this pll don't turn
2745 * off the pll
2746 */
2747 goto done;
2748 }
2749 }
2750
2751 switch (amdgpu_crtc->pll_id) {
2752 case ATOM_PPLL0:
2753 case ATOM_PPLL1:
2754 case ATOM_PPLL2:
2755 /* disable the ppll */
2756 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2757 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2758 break;
2759 default:
2760 break;
2761 }
2762 done:
2763 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2764 amdgpu_crtc->adjusted_clock = 0;
2765 amdgpu_crtc->encoder = NULL;
2766 amdgpu_crtc->connector = NULL;
2767 }
2768
2769 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2770 struct drm_display_mode *mode,
2771 struct drm_display_mode *adjusted_mode,
2772 int x, int y, struct drm_framebuffer *old_fb)
2773 {
2774 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2775
2776 if (!amdgpu_crtc->adjusted_clock)
2777 return -EINVAL;
2778
2779 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2780 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2781 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2782 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2783 amdgpu_atombios_crtc_scaler_setup(crtc);
2784 dce_v10_0_cursor_reset(crtc);
2785 /* update the hw version fpr dpm */
2786 amdgpu_crtc->hw_mode = *adjusted_mode;
2787
2788 return 0;
2789 }
2790
2791 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2792 const struct drm_display_mode *mode,
2793 struct drm_display_mode *adjusted_mode)
2794 {
2795 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2796 struct drm_device *dev = crtc->dev;
2797 struct drm_encoder *encoder;
2798
2799 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2800 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2801 if (encoder->crtc == crtc) {
2802 amdgpu_crtc->encoder = encoder;
2803 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2804 break;
2805 }
2806 }
2807 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2808 amdgpu_crtc->encoder = NULL;
2809 amdgpu_crtc->connector = NULL;
2810 return false;
2811 }
2812 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2813 return false;
2814 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2815 return false;
2816 /* pick pll */
2817 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2818 /* if we can't get a PPLL for a non-DP encoder, fail */
2819 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2820 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2821 return false;
2822
2823 return true;
2824 }
2825
2826 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2827 struct drm_framebuffer *old_fb)
2828 {
2829 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2830 }
2831
2832 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2833 struct drm_framebuffer *fb,
2834 int x, int y, enum mode_set_atomic state)
2835 {
2836 return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2837 }
2838
2839 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2840 .dpms = dce_v10_0_crtc_dpms,
2841 .mode_fixup = dce_v10_0_crtc_mode_fixup,
2842 .mode_set = dce_v10_0_crtc_mode_set,
2843 .mode_set_base = dce_v10_0_crtc_set_base,
2844 .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2845 .prepare = dce_v10_0_crtc_prepare,
2846 .commit = dce_v10_0_crtc_commit,
2847 .load_lut = dce_v10_0_crtc_load_lut,
2848 .disable = dce_v10_0_crtc_disable,
2849 };
2850
2851 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2852 {
2853 struct amdgpu_crtc *amdgpu_crtc;
2854 int i;
2855
2856 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2857 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2858 if (amdgpu_crtc == NULL)
2859 return -ENOMEM;
2860
2861 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2862
2863 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2864 amdgpu_crtc->crtc_id = index;
2865 adev->mode_info.crtcs[index] = amdgpu_crtc;
2866
2867 amdgpu_crtc->max_cursor_width = 128;
2868 amdgpu_crtc->max_cursor_height = 128;
2869 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2870 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2871
2872 for (i = 0; i < 256; i++) {
2873 amdgpu_crtc->lut_r[i] = i << 2;
2874 amdgpu_crtc->lut_g[i] = i << 2;
2875 amdgpu_crtc->lut_b[i] = i << 2;
2876 }
2877
2878 switch (amdgpu_crtc->crtc_id) {
2879 case 0:
2880 default:
2881 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2882 break;
2883 case 1:
2884 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2885 break;
2886 case 2:
2887 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2888 break;
2889 case 3:
2890 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2891 break;
2892 case 4:
2893 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2894 break;
2895 case 5:
2896 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2897 break;
2898 }
2899
2900 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2901 amdgpu_crtc->adjusted_clock = 0;
2902 amdgpu_crtc->encoder = NULL;
2903 amdgpu_crtc->connector = NULL;
2904 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2905
2906 return 0;
2907 }
2908
2909 static int dce_v10_0_early_init(void *handle)
2910 {
2911 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2912
2913 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2914 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2915
2916 dce_v10_0_set_display_funcs(adev);
2917 dce_v10_0_set_irq_funcs(adev);
2918
2919 adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
2920
2921 switch (adev->asic_type) {
2922 case CHIP_FIJI:
2923 case CHIP_TONGA:
2924 adev->mode_info.num_hpd = 6;
2925 adev->mode_info.num_dig = 7;
2926 break;
2927 default:
2928 /* FIXME: not supported yet */
2929 return -EINVAL;
2930 }
2931
2932 return 0;
2933 }
2934
2935 static int dce_v10_0_sw_init(void *handle)
2936 {
2937 int r, i;
2938 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2939
2940 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2941 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2942 if (r)
2943 return r;
2944 }
2945
2946 for (i = 8; i < 20; i += 2) {
2947 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2948 if (r)
2949 return r;
2950 }
2951
2952 /* HPD hotplug */
2953 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2954 if (r)
2955 return r;
2956
2957 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2958
2959 adev->ddev->mode_config.async_page_flip = true;
2960
2961 adev->ddev->mode_config.max_width = 16384;
2962 adev->ddev->mode_config.max_height = 16384;
2963
2964 adev->ddev->mode_config.preferred_depth = 24;
2965 adev->ddev->mode_config.prefer_shadow = 1;
2966
2967 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2968
2969 r = amdgpu_modeset_create_props(adev);
2970 if (r)
2971 return r;
2972
2973 adev->ddev->mode_config.max_width = 16384;
2974 adev->ddev->mode_config.max_height = 16384;
2975
2976 /* allocate crtcs */
2977 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2978 r = dce_v10_0_crtc_init(adev, i);
2979 if (r)
2980 return r;
2981 }
2982
2983 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2984 amdgpu_print_display_setup(adev->ddev);
2985 else
2986 return -EINVAL;
2987
2988 /* setup afmt */
2989 r = dce_v10_0_afmt_init(adev);
2990 if (r)
2991 return r;
2992
2993 r = dce_v10_0_audio_init(adev);
2994 if (r)
2995 return r;
2996
2997 drm_kms_helper_poll_init(adev->ddev);
2998
2999 adev->mode_info.mode_config_initialized = true;
3000 return 0;
3001 }
3002
3003 static int dce_v10_0_sw_fini(void *handle)
3004 {
3005 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3006
3007 kfree(adev->mode_info.bios_hardcoded_edid);
3008
3009 drm_kms_helper_poll_fini(adev->ddev);
3010
3011 dce_v10_0_audio_fini(adev);
3012
3013 dce_v10_0_afmt_fini(adev);
3014
3015 drm_mode_config_cleanup(adev->ddev);
3016 adev->mode_info.mode_config_initialized = false;
3017
3018 return 0;
3019 }
3020
3021 static int dce_v10_0_hw_init(void *handle)
3022 {
3023 int i;
3024 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3025
3026 dce_v10_0_init_golden_registers(adev);
3027
3028 /* init dig PHYs, disp eng pll */
3029 amdgpu_atombios_encoder_init_dig(adev);
3030 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3031
3032 /* initialize hpd */
3033 dce_v10_0_hpd_init(adev);
3034
3035 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3036 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3037 }
3038
3039 dce_v10_0_pageflip_interrupt_init(adev);
3040
3041 return 0;
3042 }
3043
3044 static int dce_v10_0_hw_fini(void *handle)
3045 {
3046 int i;
3047 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3048
3049 dce_v10_0_hpd_fini(adev);
3050
3051 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3052 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3053 }
3054
3055 dce_v10_0_pageflip_interrupt_fini(adev);
3056
3057 return 0;
3058 }
3059
3060 static int dce_v10_0_suspend(void *handle)
3061 {
3062 return dce_v10_0_hw_fini(handle);
3063 }
3064
3065 static int dce_v10_0_resume(void *handle)
3066 {
3067 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3068 int ret;
3069
3070 ret = dce_v10_0_hw_init(handle);
3071
3072 /* turn on the BL */
3073 if (adev->mode_info.bl_encoder) {
3074 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3075 adev->mode_info.bl_encoder);
3076 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3077 bl_level);
3078 }
3079
3080 return ret;
3081 }
3082
3083 static bool dce_v10_0_is_idle(void *handle)
3084 {
3085 return true;
3086 }
3087
3088 static int dce_v10_0_wait_for_idle(void *handle)
3089 {
3090 return 0;
3091 }
3092
3093 static bool dce_v10_0_check_soft_reset(void *handle)
3094 {
3095 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3096
3097 return dce_v10_0_is_display_hung(adev);
3098 }
3099
3100 static int dce_v10_0_soft_reset(void *handle)
3101 {
3102 u32 srbm_soft_reset = 0, tmp;
3103 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3104
3105 if (dce_v10_0_is_display_hung(adev))
3106 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3107
3108 if (srbm_soft_reset) {
3109 tmp = RREG32(mmSRBM_SOFT_RESET);
3110 tmp |= srbm_soft_reset;
3111 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3112 WREG32(mmSRBM_SOFT_RESET, tmp);
3113 tmp = RREG32(mmSRBM_SOFT_RESET);
3114
3115 udelay(50);
3116
3117 tmp &= ~srbm_soft_reset;
3118 WREG32(mmSRBM_SOFT_RESET, tmp);
3119 tmp = RREG32(mmSRBM_SOFT_RESET);
3120
3121 /* Wait a little for things to settle down */
3122 udelay(50);
3123 }
3124 return 0;
3125 }
3126
3127 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3128 int crtc,
3129 enum amdgpu_interrupt_state state)
3130 {
3131 u32 lb_interrupt_mask;
3132
3133 if (crtc >= adev->mode_info.num_crtc) {
3134 DRM_DEBUG("invalid crtc %d\n", crtc);
3135 return;
3136 }
3137
3138 switch (state) {
3139 case AMDGPU_IRQ_STATE_DISABLE:
3140 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3141 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3142 VBLANK_INTERRUPT_MASK, 0);
3143 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3144 break;
3145 case AMDGPU_IRQ_STATE_ENABLE:
3146 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3147 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3148 VBLANK_INTERRUPT_MASK, 1);
3149 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3150 break;
3151 default:
3152 break;
3153 }
3154 }
3155
3156 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3157 int crtc,
3158 enum amdgpu_interrupt_state state)
3159 {
3160 u32 lb_interrupt_mask;
3161
3162 if (crtc >= adev->mode_info.num_crtc) {
3163 DRM_DEBUG("invalid crtc %d\n", crtc);
3164 return;
3165 }
3166
3167 switch (state) {
3168 case AMDGPU_IRQ_STATE_DISABLE:
3169 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3170 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3171 VLINE_INTERRUPT_MASK, 0);
3172 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3173 break;
3174 case AMDGPU_IRQ_STATE_ENABLE:
3175 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3176 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3177 VLINE_INTERRUPT_MASK, 1);
3178 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3179 break;
3180 default:
3181 break;
3182 }
3183 }
3184
3185 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3186 struct amdgpu_irq_src *source,
3187 unsigned hpd,
3188 enum amdgpu_interrupt_state state)
3189 {
3190 u32 tmp;
3191
3192 if (hpd >= adev->mode_info.num_hpd) {
3193 DRM_DEBUG("invalid hdp %d\n", hpd);
3194 return 0;
3195 }
3196
3197 switch (state) {
3198 case AMDGPU_IRQ_STATE_DISABLE:
3199 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3200 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3201 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3202 break;
3203 case AMDGPU_IRQ_STATE_ENABLE:
3204 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3205 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3206 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3207 break;
3208 default:
3209 break;
3210 }
3211
3212 return 0;
3213 }
3214
3215 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3216 struct amdgpu_irq_src *source,
3217 unsigned type,
3218 enum amdgpu_interrupt_state state)
3219 {
3220 switch (type) {
3221 case AMDGPU_CRTC_IRQ_VBLANK1:
3222 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3223 break;
3224 case AMDGPU_CRTC_IRQ_VBLANK2:
3225 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3226 break;
3227 case AMDGPU_CRTC_IRQ_VBLANK3:
3228 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3229 break;
3230 case AMDGPU_CRTC_IRQ_VBLANK4:
3231 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3232 break;
3233 case AMDGPU_CRTC_IRQ_VBLANK5:
3234 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3235 break;
3236 case AMDGPU_CRTC_IRQ_VBLANK6:
3237 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3238 break;
3239 case AMDGPU_CRTC_IRQ_VLINE1:
3240 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3241 break;
3242 case AMDGPU_CRTC_IRQ_VLINE2:
3243 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3244 break;
3245 case AMDGPU_CRTC_IRQ_VLINE3:
3246 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3247 break;
3248 case AMDGPU_CRTC_IRQ_VLINE4:
3249 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3250 break;
3251 case AMDGPU_CRTC_IRQ_VLINE5:
3252 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3253 break;
3254 case AMDGPU_CRTC_IRQ_VLINE6:
3255 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3256 break;
3257 default:
3258 break;
3259 }
3260 return 0;
3261 }
3262
3263 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3264 struct amdgpu_irq_src *src,
3265 unsigned type,
3266 enum amdgpu_interrupt_state state)
3267 {
3268 u32 reg;
3269
3270 if (type >= adev->mode_info.num_crtc) {
3271 DRM_ERROR("invalid pageflip crtc %d\n", type);
3272 return -EINVAL;
3273 }
3274
3275 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3276 if (state == AMDGPU_IRQ_STATE_DISABLE)
3277 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3278 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3279 else
3280 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3281 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3282
3283 return 0;
3284 }
3285
3286 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3287 struct amdgpu_irq_src *source,
3288 struct amdgpu_iv_entry *entry)
3289 {
3290 unsigned long flags;
3291 unsigned crtc_id;
3292 struct amdgpu_crtc *amdgpu_crtc;
3293 struct amdgpu_flip_work *works;
3294
3295 crtc_id = (entry->src_id - 8) >> 1;
3296 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3297
3298 if (crtc_id >= adev->mode_info.num_crtc) {
3299 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3300 return -EINVAL;
3301 }
3302
3303 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3304 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3305 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3306 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3307
3308 /* IRQ could occur when in initial stage */
3309 if (amdgpu_crtc == NULL)
3310 return 0;
3311
3312 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3313 works = amdgpu_crtc->pflip_works;
3314 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3315 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3316 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3317 amdgpu_crtc->pflip_status,
3318 AMDGPU_FLIP_SUBMITTED);
3319 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3320 return 0;
3321 }
3322
3323 /* page flip completed. clean up */
3324 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3325 amdgpu_crtc->pflip_works = NULL;
3326
3327 /* wakeup usersapce */
3328 if (works->event)
3329 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3330
3331 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3332
3333 drm_crtc_vblank_put(&amdgpu_crtc->base);
3334 schedule_work(&works->unpin_work);
3335
3336 return 0;
3337 }
3338
3339 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3340 int hpd)
3341 {
3342 u32 tmp;
3343
3344 if (hpd >= adev->mode_info.num_hpd) {
3345 DRM_DEBUG("invalid hdp %d\n", hpd);
3346 return;
3347 }
3348
3349 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3350 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3351 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3352 }
3353
3354 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3355 int crtc)
3356 {
3357 u32 tmp;
3358
3359 if (crtc >= adev->mode_info.num_crtc) {
3360 DRM_DEBUG("invalid crtc %d\n", crtc);
3361 return;
3362 }
3363
3364 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3365 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3366 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3367 }
3368
3369 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3370 int crtc)
3371 {
3372 u32 tmp;
3373
3374 if (crtc >= adev->mode_info.num_crtc) {
3375 DRM_DEBUG("invalid crtc %d\n", crtc);
3376 return;
3377 }
3378
3379 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3380 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3381 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3382 }
3383
3384 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3385 struct amdgpu_irq_src *source,
3386 struct amdgpu_iv_entry *entry)
3387 {
3388 unsigned crtc = entry->src_id - 1;
3389 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3390 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3391
3392 switch (entry->src_data[0]) {
3393 case 0: /* vblank */
3394 if (disp_int & interrupt_status_offsets[crtc].vblank)
3395 dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3396 else
3397 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3398
3399 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3400 drm_handle_vblank(adev->ddev, crtc);
3401 }
3402 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3403
3404 break;
3405 case 1: /* vline */
3406 if (disp_int & interrupt_status_offsets[crtc].vline)
3407 dce_v10_0_crtc_vline_int_ack(adev, crtc);
3408 else
3409 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3410
3411 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3412
3413 break;
3414 default:
3415 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3416 break;
3417 }
3418
3419 return 0;
3420 }
3421
3422 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3423 struct amdgpu_irq_src *source,
3424 struct amdgpu_iv_entry *entry)
3425 {
3426 uint32_t disp_int, mask;
3427 unsigned hpd;
3428
3429 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3430 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3431 return 0;
3432 }
3433
3434 hpd = entry->src_data[0];
3435 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3436 mask = interrupt_status_offsets[hpd].hpd;
3437
3438 if (disp_int & mask) {
3439 dce_v10_0_hpd_int_ack(adev, hpd);
3440 schedule_work(&adev->hotplug_work);
3441 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3442 }
3443
3444 return 0;
3445 }
3446
3447 static int dce_v10_0_set_clockgating_state(void *handle,
3448 enum amd_clockgating_state state)
3449 {
3450 return 0;
3451 }
3452
3453 static int dce_v10_0_set_powergating_state(void *handle,
3454 enum amd_powergating_state state)
3455 {
3456 return 0;
3457 }
3458
3459 static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3460 .name = "dce_v10_0",
3461 .early_init = dce_v10_0_early_init,
3462 .late_init = NULL,
3463 .sw_init = dce_v10_0_sw_init,
3464 .sw_fini = dce_v10_0_sw_fini,
3465 .hw_init = dce_v10_0_hw_init,
3466 .hw_fini = dce_v10_0_hw_fini,
3467 .suspend = dce_v10_0_suspend,
3468 .resume = dce_v10_0_resume,
3469 .is_idle = dce_v10_0_is_idle,
3470 .wait_for_idle = dce_v10_0_wait_for_idle,
3471 .check_soft_reset = dce_v10_0_check_soft_reset,
3472 .soft_reset = dce_v10_0_soft_reset,
3473 .set_clockgating_state = dce_v10_0_set_clockgating_state,
3474 .set_powergating_state = dce_v10_0_set_powergating_state,
3475 };
3476
3477 static void
3478 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3479 struct drm_display_mode *mode,
3480 struct drm_display_mode *adjusted_mode)
3481 {
3482 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3483
3484 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3485
3486 /* need to call this here rather than in prepare() since we need some crtc info */
3487 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3488
3489 /* set scaler clears this on some chips */
3490 dce_v10_0_set_interleave(encoder->crtc, mode);
3491
3492 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3493 dce_v10_0_afmt_enable(encoder, true);
3494 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3495 }
3496 }
3497
3498 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3499 {
3500 struct amdgpu_device *adev = encoder->dev->dev_private;
3501 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3502 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3503
3504 if ((amdgpu_encoder->active_device &
3505 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3506 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3507 ENCODER_OBJECT_ID_NONE)) {
3508 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3509 if (dig) {
3510 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3511 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3512 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3513 }
3514 }
3515
3516 amdgpu_atombios_scratch_regs_lock(adev, true);
3517
3518 if (connector) {
3519 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3520
3521 /* select the clock/data port if it uses a router */
3522 if (amdgpu_connector->router.cd_valid)
3523 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3524
3525 /* turn eDP panel on for mode set */
3526 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3527 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3528 ATOM_TRANSMITTER_ACTION_POWER_ON);
3529 }
3530
3531 /* this is needed for the pll/ss setup to work correctly in some cases */
3532 amdgpu_atombios_encoder_set_crtc_source(encoder);
3533 /* set up the FMT blocks */
3534 dce_v10_0_program_fmt(encoder);
3535 }
3536
3537 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3538 {
3539 struct drm_device *dev = encoder->dev;
3540 struct amdgpu_device *adev = dev->dev_private;
3541
3542 /* need to call this here as we need the crtc set up */
3543 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3544 amdgpu_atombios_scratch_regs_lock(adev, false);
3545 }
3546
3547 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3548 {
3549 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3550 struct amdgpu_encoder_atom_dig *dig;
3551
3552 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3553
3554 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3555 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3556 dce_v10_0_afmt_enable(encoder, false);
3557 dig = amdgpu_encoder->enc_priv;
3558 dig->dig_encoder = -1;
3559 }
3560 amdgpu_encoder->active_device = 0;
3561 }
3562
3563 /* these are handled by the primary encoders */
3564 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3565 {
3566
3567 }
3568
3569 static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3570 {
3571
3572 }
3573
3574 static void
3575 dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3576 struct drm_display_mode *mode,
3577 struct drm_display_mode *adjusted_mode)
3578 {
3579
3580 }
3581
3582 static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3583 {
3584
3585 }
3586
3587 static void
3588 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3589 {
3590
3591 }
3592
3593 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3594 .dpms = dce_v10_0_ext_dpms,
3595 .prepare = dce_v10_0_ext_prepare,
3596 .mode_set = dce_v10_0_ext_mode_set,
3597 .commit = dce_v10_0_ext_commit,
3598 .disable = dce_v10_0_ext_disable,
3599 /* no detect for TMDS/LVDS yet */
3600 };
3601
3602 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3603 .dpms = amdgpu_atombios_encoder_dpms,
3604 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3605 .prepare = dce_v10_0_encoder_prepare,
3606 .mode_set = dce_v10_0_encoder_mode_set,
3607 .commit = dce_v10_0_encoder_commit,
3608 .disable = dce_v10_0_encoder_disable,
3609 .detect = amdgpu_atombios_encoder_dig_detect,
3610 };
3611
3612 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3613 .dpms = amdgpu_atombios_encoder_dpms,
3614 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3615 .prepare = dce_v10_0_encoder_prepare,
3616 .mode_set = dce_v10_0_encoder_mode_set,
3617 .commit = dce_v10_0_encoder_commit,
3618 .detect = amdgpu_atombios_encoder_dac_detect,
3619 };
3620
3621 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3622 {
3623 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3624 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3625 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3626 kfree(amdgpu_encoder->enc_priv);
3627 drm_encoder_cleanup(encoder);
3628 kfree(amdgpu_encoder);
3629 }
3630
3631 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3632 .destroy = dce_v10_0_encoder_destroy,
3633 };
3634
3635 static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3636 uint32_t encoder_enum,
3637 uint32_t supported_device,
3638 u16 caps)
3639 {
3640 struct drm_device *dev = adev->ddev;
3641 struct drm_encoder *encoder;
3642 struct amdgpu_encoder *amdgpu_encoder;
3643
3644 /* see if we already added it */
3645 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3646 amdgpu_encoder = to_amdgpu_encoder(encoder);
3647 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3648 amdgpu_encoder->devices |= supported_device;
3649 return;
3650 }
3651
3652 }
3653
3654 /* add a new one */
3655 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3656 if (!amdgpu_encoder)
3657 return;
3658
3659 encoder = &amdgpu_encoder->base;
3660 switch (adev->mode_info.num_crtc) {
3661 case 1:
3662 encoder->possible_crtcs = 0x1;
3663 break;
3664 case 2:
3665 default:
3666 encoder->possible_crtcs = 0x3;
3667 break;
3668 case 4:
3669 encoder->possible_crtcs = 0xf;
3670 break;
3671 case 6:
3672 encoder->possible_crtcs = 0x3f;
3673 break;
3674 }
3675
3676 amdgpu_encoder->enc_priv = NULL;
3677
3678 amdgpu_encoder->encoder_enum = encoder_enum;
3679 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3680 amdgpu_encoder->devices = supported_device;
3681 amdgpu_encoder->rmx_type = RMX_OFF;
3682 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3683 amdgpu_encoder->is_ext_encoder = false;
3684 amdgpu_encoder->caps = caps;
3685
3686 switch (amdgpu_encoder->encoder_id) {
3687 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3688 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3689 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3690 DRM_MODE_ENCODER_DAC, NULL);
3691 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3692 break;
3693 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3694 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3695 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3696 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3697 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3698 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3699 amdgpu_encoder->rmx_type = RMX_FULL;
3700 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3701 DRM_MODE_ENCODER_LVDS, NULL);
3702 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3703 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3704 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3705 DRM_MODE_ENCODER_DAC, NULL);
3706 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3707 } else {
3708 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3709 DRM_MODE_ENCODER_TMDS, NULL);
3710 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3711 }
3712 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3713 break;
3714 case ENCODER_OBJECT_ID_SI170B:
3715 case ENCODER_OBJECT_ID_CH7303:
3716 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3717 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3718 case ENCODER_OBJECT_ID_TITFP513:
3719 case ENCODER_OBJECT_ID_VT1623:
3720 case ENCODER_OBJECT_ID_HDMI_SI1930:
3721 case ENCODER_OBJECT_ID_TRAVIS:
3722 case ENCODER_OBJECT_ID_NUTMEG:
3723 /* these are handled by the primary encoders */
3724 amdgpu_encoder->is_ext_encoder = true;
3725 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3726 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3727 DRM_MODE_ENCODER_LVDS, NULL);
3728 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3729 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3730 DRM_MODE_ENCODER_DAC, NULL);
3731 else
3732 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3733 DRM_MODE_ENCODER_TMDS, NULL);
3734 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3735 break;
3736 }
3737 }
3738
3739 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3740 .set_vga_render_state = &dce_v10_0_set_vga_render_state,
3741 .bandwidth_update = &dce_v10_0_bandwidth_update,
3742 .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3743 .vblank_wait = &dce_v10_0_vblank_wait,
3744 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3745 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3746 .hpd_sense = &dce_v10_0_hpd_sense,
3747 .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3748 .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3749 .page_flip = &dce_v10_0_page_flip,
3750 .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3751 .add_encoder = &dce_v10_0_encoder_add,
3752 .add_connector = &amdgpu_connector_add,
3753 .stop_mc_access = &dce_v10_0_stop_mc_access,
3754 .resume_mc_access = &dce_v10_0_resume_mc_access,
3755 };
3756
3757 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3758 {
3759 if (adev->mode_info.funcs == NULL)
3760 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3761 }
3762
3763 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3764 .set = dce_v10_0_set_crtc_irq_state,
3765 .process = dce_v10_0_crtc_irq,
3766 };
3767
3768 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3769 .set = dce_v10_0_set_pageflip_irq_state,
3770 .process = dce_v10_0_pageflip_irq,
3771 };
3772
3773 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3774 .set = dce_v10_0_set_hpd_irq_state,
3775 .process = dce_v10_0_hpd_irq,
3776 };
3777
3778 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3779 {
3780 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3781 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3782
3783 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3784 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3785
3786 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3787 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3788 }
3789
3790 const struct amdgpu_ip_block_version dce_v10_0_ip_block =
3791 {
3792 .type = AMD_IP_BLOCK_TYPE_DCE,
3793 .major = 10,
3794 .minor = 0,
3795 .rev = 0,
3796 .funcs = &dce_v10_0_ip_funcs,
3797 };
3798
3799 const struct amdgpu_ip_block_version dce_v10_1_ip_block =
3800 {
3801 .type = AMD_IP_BLOCK_TYPE_DCE,
3802 .major = 10,
3803 .minor = 1,
3804 .rev = 0,
3805 .funcs = &dce_v10_0_ip_funcs,
3806 };
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