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[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / amd / amdgpu / dce_v11_0.c
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <drm/drmP.h>
24 #include "amdgpu.h"
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
27 #include "vid.h"
28 #include "atom.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
34 #include "dce_v11_0.h"
35
36 #include "dce/dce_11_0_d.h"
37 #include "dce/dce_11_0_sh_mask.h"
38 #include "dce/dce_11_0_enum.h"
39 #include "oss/oss_3_0_d.h"
40 #include "oss/oss_3_0_sh_mask.h"
41 #include "gmc/gmc_8_1_d.h"
42 #include "gmc/gmc_8_1_sh_mask.h"
43
44 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
45 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
46
47 static const u32 crtc_offsets[] =
48 {
49 CRTC0_REGISTER_OFFSET,
50 CRTC1_REGISTER_OFFSET,
51 CRTC2_REGISTER_OFFSET,
52 CRTC3_REGISTER_OFFSET,
53 CRTC4_REGISTER_OFFSET,
54 CRTC5_REGISTER_OFFSET,
55 CRTC6_REGISTER_OFFSET
56 };
57
58 static const u32 hpd_offsets[] =
59 {
60 HPD0_REGISTER_OFFSET,
61 HPD1_REGISTER_OFFSET,
62 HPD2_REGISTER_OFFSET,
63 HPD3_REGISTER_OFFSET,
64 HPD4_REGISTER_OFFSET,
65 HPD5_REGISTER_OFFSET
66 };
67
68 static const uint32_t dig_offsets[] = {
69 DIG0_REGISTER_OFFSET,
70 DIG1_REGISTER_OFFSET,
71 DIG2_REGISTER_OFFSET,
72 DIG3_REGISTER_OFFSET,
73 DIG4_REGISTER_OFFSET,
74 DIG5_REGISTER_OFFSET,
75 DIG6_REGISTER_OFFSET,
76 DIG7_REGISTER_OFFSET,
77 DIG8_REGISTER_OFFSET
78 };
79
80 static const struct {
81 uint32_t reg;
82 uint32_t vblank;
83 uint32_t vline;
84 uint32_t hpd;
85
86 } interrupt_status_offsets[] = { {
87 .reg = mmDISP_INTERRUPT_STATUS,
88 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
89 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
90 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
91 }, {
92 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
93 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
94 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
95 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
96 }, {
97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
99 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
101 }, {
102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
104 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
106 }, {
107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
109 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
111 }, {
112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
114 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
116 } };
117
118 static const u32 cz_golden_settings_a11[] =
119 {
120 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
121 mmFBC_MISC, 0x1f311fff, 0x14300000,
122 };
123
124 static const u32 cz_mgcg_cgcg_init[] =
125 {
126 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
127 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
128 };
129
130 static const u32 stoney_golden_settings_a11[] =
131 {
132 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
133 mmFBC_MISC, 0x1f311fff, 0x14302000,
134 };
135
136 static const u32 polaris11_golden_settings_a11[] =
137 {
138 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
139 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
140 mmFBC_DEBUG1, 0xffffffff, 0x00000008,
141 mmFBC_MISC, 0x9f313fff, 0x14302008,
142 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
143 };
144
145 static const u32 polaris10_golden_settings_a11[] =
146 {
147 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
148 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
149 mmFBC_MISC, 0x9f313fff, 0x14302008,
150 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
151 };
152
153 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
154 {
155 switch (adev->asic_type) {
156 case CHIP_CARRIZO:
157 amdgpu_device_program_register_sequence(adev,
158 cz_mgcg_cgcg_init,
159 ARRAY_SIZE(cz_mgcg_cgcg_init));
160 amdgpu_device_program_register_sequence(adev,
161 cz_golden_settings_a11,
162 ARRAY_SIZE(cz_golden_settings_a11));
163 break;
164 case CHIP_STONEY:
165 amdgpu_device_program_register_sequence(adev,
166 stoney_golden_settings_a11,
167 ARRAY_SIZE(stoney_golden_settings_a11));
168 break;
169 case CHIP_POLARIS11:
170 case CHIP_POLARIS12:
171 amdgpu_device_program_register_sequence(adev,
172 polaris11_golden_settings_a11,
173 ARRAY_SIZE(polaris11_golden_settings_a11));
174 break;
175 case CHIP_POLARIS10:
176 amdgpu_device_program_register_sequence(adev,
177 polaris10_golden_settings_a11,
178 ARRAY_SIZE(polaris10_golden_settings_a11));
179 break;
180 default:
181 break;
182 }
183 }
184
185 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
186 u32 block_offset, u32 reg)
187 {
188 unsigned long flags;
189 u32 r;
190
191 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
192 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
193 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
194 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
195
196 return r;
197 }
198
199 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
200 u32 block_offset, u32 reg, u32 v)
201 {
202 unsigned long flags;
203
204 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
205 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
206 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
207 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
208 }
209
210 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
211 {
212 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
213 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
214 return true;
215 else
216 return false;
217 }
218
219 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
220 {
221 u32 pos1, pos2;
222
223 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
224 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
225
226 if (pos1 != pos2)
227 return true;
228 else
229 return false;
230 }
231
232 /**
233 * dce_v11_0_vblank_wait - vblank wait asic callback.
234 *
235 * @adev: amdgpu_device pointer
236 * @crtc: crtc to wait for vblank on
237 *
238 * Wait for vblank on the requested crtc (evergreen+).
239 */
240 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
241 {
242 unsigned i = 100;
243
244 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
245 return;
246
247 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
248 return;
249
250 /* depending on when we hit vblank, we may be close to active; if so,
251 * wait for another frame.
252 */
253 while (dce_v11_0_is_in_vblank(adev, crtc)) {
254 if (i++ == 100) {
255 i = 0;
256 if (!dce_v11_0_is_counter_moving(adev, crtc))
257 break;
258 }
259 }
260
261 while (!dce_v11_0_is_in_vblank(adev, crtc)) {
262 if (i++ == 100) {
263 i = 0;
264 if (!dce_v11_0_is_counter_moving(adev, crtc))
265 break;
266 }
267 }
268 }
269
270 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
271 {
272 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
273 return 0;
274 else
275 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
276 }
277
278 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
279 {
280 unsigned i;
281
282 /* Enable pflip interrupts */
283 for (i = 0; i < adev->mode_info.num_crtc; i++)
284 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
285 }
286
287 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
288 {
289 unsigned i;
290
291 /* Disable pflip interrupts */
292 for (i = 0; i < adev->mode_info.num_crtc; i++)
293 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
294 }
295
296 /**
297 * dce_v11_0_page_flip - pageflip callback.
298 *
299 * @adev: amdgpu_device pointer
300 * @crtc_id: crtc to cleanup pageflip on
301 * @crtc_base: new address of the crtc (GPU MC address)
302 *
303 * Triggers the actual pageflip by updating the primary
304 * surface base address.
305 */
306 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
307 int crtc_id, u64 crtc_base, bool async)
308 {
309 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
310 u32 tmp;
311
312 /* flip immediate for async, default is vsync */
313 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
314 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
315 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
316 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
317 /* update the scanout addresses */
318 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
319 upper_32_bits(crtc_base));
320 /* writing to the low address triggers the update */
321 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
322 lower_32_bits(crtc_base));
323 /* post the write */
324 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
325 }
326
327 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
328 u32 *vbl, u32 *position)
329 {
330 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
331 return -EINVAL;
332
333 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
334 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
335
336 return 0;
337 }
338
339 /**
340 * dce_v11_0_hpd_sense - hpd sense callback.
341 *
342 * @adev: amdgpu_device pointer
343 * @hpd: hpd (hotplug detect) pin
344 *
345 * Checks if a digital monitor is connected (evergreen+).
346 * Returns true if connected, false if not connected.
347 */
348 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
349 enum amdgpu_hpd_id hpd)
350 {
351 bool connected = false;
352
353 if (hpd >= adev->mode_info.num_hpd)
354 return connected;
355
356 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
357 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
358 connected = true;
359
360 return connected;
361 }
362
363 /**
364 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
365 *
366 * @adev: amdgpu_device pointer
367 * @hpd: hpd (hotplug detect) pin
368 *
369 * Set the polarity of the hpd pin (evergreen+).
370 */
371 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
372 enum amdgpu_hpd_id hpd)
373 {
374 u32 tmp;
375 bool connected = dce_v11_0_hpd_sense(adev, hpd);
376
377 if (hpd >= adev->mode_info.num_hpd)
378 return;
379
380 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
381 if (connected)
382 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
383 else
384 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
385 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
386 }
387
388 /**
389 * dce_v11_0_hpd_init - hpd setup callback.
390 *
391 * @adev: amdgpu_device pointer
392 *
393 * Setup the hpd pins used by the card (evergreen+).
394 * Enable the pin, set the polarity, and enable the hpd interrupts.
395 */
396 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
397 {
398 struct drm_device *dev = adev->ddev;
399 struct drm_connector *connector;
400 u32 tmp;
401
402 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
403 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
404
405 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
406 continue;
407
408 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
409 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
410 /* don't try to enable hpd on eDP or LVDS avoid breaking the
411 * aux dp channel on imac and help (but not completely fix)
412 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
413 * also avoid interrupt storms during dpms.
414 */
415 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
416 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
417 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
418 continue;
419 }
420
421 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
422 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
423 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
424
425 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
426 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
427 DC_HPD_CONNECT_INT_DELAY,
428 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
429 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
430 DC_HPD_DISCONNECT_INT_DELAY,
431 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
432 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
433
434 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
435 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
436 }
437 }
438
439 /**
440 * dce_v11_0_hpd_fini - hpd tear down callback.
441 *
442 * @adev: amdgpu_device pointer
443 *
444 * Tear down the hpd pins used by the card (evergreen+).
445 * Disable the hpd interrupts.
446 */
447 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
448 {
449 struct drm_device *dev = adev->ddev;
450 struct drm_connector *connector;
451 u32 tmp;
452
453 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
454 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
455
456 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
457 continue;
458
459 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
460 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
461 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
462
463 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
464 }
465 }
466
467 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
468 {
469 return mmDC_GPIO_HPD_A;
470 }
471
472 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
473 {
474 u32 crtc_hung = 0;
475 u32 crtc_status[6];
476 u32 i, j, tmp;
477
478 for (i = 0; i < adev->mode_info.num_crtc; i++) {
479 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
480 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
481 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
482 crtc_hung |= (1 << i);
483 }
484 }
485
486 for (j = 0; j < 10; j++) {
487 for (i = 0; i < adev->mode_info.num_crtc; i++) {
488 if (crtc_hung & (1 << i)) {
489 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
490 if (tmp != crtc_status[i])
491 crtc_hung &= ~(1 << i);
492 }
493 }
494 if (crtc_hung == 0)
495 return false;
496 udelay(100);
497 }
498
499 return true;
500 }
501
502 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
503 bool render)
504 {
505 u32 tmp;
506
507 /* Lockout access through VGA aperture*/
508 tmp = RREG32(mmVGA_HDP_CONTROL);
509 if (render)
510 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
511 else
512 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
513 WREG32(mmVGA_HDP_CONTROL, tmp);
514
515 /* disable VGA render */
516 tmp = RREG32(mmVGA_RENDER_CONTROL);
517 if (render)
518 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
519 else
520 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
521 WREG32(mmVGA_RENDER_CONTROL, tmp);
522 }
523
524 static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
525 {
526 int num_crtc = 0;
527
528 switch (adev->asic_type) {
529 case CHIP_CARRIZO:
530 num_crtc = 3;
531 break;
532 case CHIP_STONEY:
533 num_crtc = 2;
534 break;
535 case CHIP_POLARIS10:
536 num_crtc = 6;
537 break;
538 case CHIP_POLARIS11:
539 case CHIP_POLARIS12:
540 num_crtc = 5;
541 break;
542 default:
543 num_crtc = 0;
544 }
545 return num_crtc;
546 }
547
548 void dce_v11_0_disable_dce(struct amdgpu_device *adev)
549 {
550 /*Disable VGA render and enabled crtc, if has DCE engine*/
551 if (amdgpu_atombios_has_dce_engine_info(adev)) {
552 u32 tmp;
553 int crtc_enabled, i;
554
555 dce_v11_0_set_vga_render_state(adev, false);
556
557 /*Disable crtc*/
558 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
559 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
560 CRTC_CONTROL, CRTC_MASTER_EN);
561 if (crtc_enabled) {
562 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
563 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
564 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
565 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
566 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
567 }
568 }
569 }
570 }
571
572 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
573 {
574 struct drm_device *dev = encoder->dev;
575 struct amdgpu_device *adev = dev->dev_private;
576 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
577 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
578 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
579 int bpc = 0;
580 u32 tmp = 0;
581 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
582
583 if (connector) {
584 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
585 bpc = amdgpu_connector_get_monitor_bpc(connector);
586 dither = amdgpu_connector->dither;
587 }
588
589 /* LVDS/eDP FMT is set up by atom */
590 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
591 return;
592
593 /* not needed for analog */
594 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
595 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
596 return;
597
598 if (bpc == 0)
599 return;
600
601 switch (bpc) {
602 case 6:
603 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
604 /* XXX sort out optimal dither settings */
605 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
606 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
607 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
608 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
609 } else {
610 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
611 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
612 }
613 break;
614 case 8:
615 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
616 /* XXX sort out optimal dither settings */
617 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
618 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
619 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
620 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
621 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
622 } else {
623 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
624 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
625 }
626 break;
627 case 10:
628 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
629 /* XXX sort out optimal dither settings */
630 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
631 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
632 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
633 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
634 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
635 } else {
636 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
637 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
638 }
639 break;
640 default:
641 /* not needed */
642 break;
643 }
644
645 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
646 }
647
648
649 /* display watermark setup */
650 /**
651 * dce_v11_0_line_buffer_adjust - Set up the line buffer
652 *
653 * @adev: amdgpu_device pointer
654 * @amdgpu_crtc: the selected display controller
655 * @mode: the current display mode on the selected display
656 * controller
657 *
658 * Setup up the line buffer allocation for
659 * the selected display controller (CIK).
660 * Returns the line buffer size in pixels.
661 */
662 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
663 struct amdgpu_crtc *amdgpu_crtc,
664 struct drm_display_mode *mode)
665 {
666 u32 tmp, buffer_alloc, i, mem_cfg;
667 u32 pipe_offset = amdgpu_crtc->crtc_id;
668 /*
669 * Line Buffer Setup
670 * There are 6 line buffers, one for each display controllers.
671 * There are 3 partitions per LB. Select the number of partitions
672 * to enable based on the display width. For display widths larger
673 * than 4096, you need use to use 2 display controllers and combine
674 * them using the stereo blender.
675 */
676 if (amdgpu_crtc->base.enabled && mode) {
677 if (mode->crtc_hdisplay < 1920) {
678 mem_cfg = 1;
679 buffer_alloc = 2;
680 } else if (mode->crtc_hdisplay < 2560) {
681 mem_cfg = 2;
682 buffer_alloc = 2;
683 } else if (mode->crtc_hdisplay < 4096) {
684 mem_cfg = 0;
685 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
686 } else {
687 DRM_DEBUG_KMS("Mode too big for LB!\n");
688 mem_cfg = 0;
689 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
690 }
691 } else {
692 mem_cfg = 1;
693 buffer_alloc = 0;
694 }
695
696 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
697 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
698 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
699
700 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
701 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
702 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
703
704 for (i = 0; i < adev->usec_timeout; i++) {
705 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
706 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
707 break;
708 udelay(1);
709 }
710
711 if (amdgpu_crtc->base.enabled && mode) {
712 switch (mem_cfg) {
713 case 0:
714 default:
715 return 4096 * 2;
716 case 1:
717 return 1920 * 2;
718 case 2:
719 return 2560 * 2;
720 }
721 }
722
723 /* controller not enabled, so no lb used */
724 return 0;
725 }
726
727 /**
728 * cik_get_number_of_dram_channels - get the number of dram channels
729 *
730 * @adev: amdgpu_device pointer
731 *
732 * Look up the number of video ram channels (CIK).
733 * Used for display watermark bandwidth calculations
734 * Returns the number of dram channels
735 */
736 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
737 {
738 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
739
740 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
741 case 0:
742 default:
743 return 1;
744 case 1:
745 return 2;
746 case 2:
747 return 4;
748 case 3:
749 return 8;
750 case 4:
751 return 3;
752 case 5:
753 return 6;
754 case 6:
755 return 10;
756 case 7:
757 return 12;
758 case 8:
759 return 16;
760 }
761 }
762
763 struct dce10_wm_params {
764 u32 dram_channels; /* number of dram channels */
765 u32 yclk; /* bandwidth per dram data pin in kHz */
766 u32 sclk; /* engine clock in kHz */
767 u32 disp_clk; /* display clock in kHz */
768 u32 src_width; /* viewport width */
769 u32 active_time; /* active display time in ns */
770 u32 blank_time; /* blank time in ns */
771 bool interlaced; /* mode is interlaced */
772 fixed20_12 vsc; /* vertical scale ratio */
773 u32 num_heads; /* number of active crtcs */
774 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
775 u32 lb_size; /* line buffer allocated to pipe */
776 u32 vtaps; /* vertical scaler taps */
777 };
778
779 /**
780 * dce_v11_0_dram_bandwidth - get the dram bandwidth
781 *
782 * @wm: watermark calculation data
783 *
784 * Calculate the raw dram bandwidth (CIK).
785 * Used for display watermark bandwidth calculations
786 * Returns the dram bandwidth in MBytes/s
787 */
788 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
789 {
790 /* Calculate raw DRAM Bandwidth */
791 fixed20_12 dram_efficiency; /* 0.7 */
792 fixed20_12 yclk, dram_channels, bandwidth;
793 fixed20_12 a;
794
795 a.full = dfixed_const(1000);
796 yclk.full = dfixed_const(wm->yclk);
797 yclk.full = dfixed_div(yclk, a);
798 dram_channels.full = dfixed_const(wm->dram_channels * 4);
799 a.full = dfixed_const(10);
800 dram_efficiency.full = dfixed_const(7);
801 dram_efficiency.full = dfixed_div(dram_efficiency, a);
802 bandwidth.full = dfixed_mul(dram_channels, yclk);
803 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
804
805 return dfixed_trunc(bandwidth);
806 }
807
808 /**
809 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
810 *
811 * @wm: watermark calculation data
812 *
813 * Calculate the dram bandwidth used for display (CIK).
814 * Used for display watermark bandwidth calculations
815 * Returns the dram bandwidth for display in MBytes/s
816 */
817 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
818 {
819 /* Calculate DRAM Bandwidth and the part allocated to display. */
820 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
821 fixed20_12 yclk, dram_channels, bandwidth;
822 fixed20_12 a;
823
824 a.full = dfixed_const(1000);
825 yclk.full = dfixed_const(wm->yclk);
826 yclk.full = dfixed_div(yclk, a);
827 dram_channels.full = dfixed_const(wm->dram_channels * 4);
828 a.full = dfixed_const(10);
829 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
830 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
831 bandwidth.full = dfixed_mul(dram_channels, yclk);
832 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
833
834 return dfixed_trunc(bandwidth);
835 }
836
837 /**
838 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
839 *
840 * @wm: watermark calculation data
841 *
842 * Calculate the data return bandwidth used for display (CIK).
843 * Used for display watermark bandwidth calculations
844 * Returns the data return bandwidth in MBytes/s
845 */
846 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
847 {
848 /* Calculate the display Data return Bandwidth */
849 fixed20_12 return_efficiency; /* 0.8 */
850 fixed20_12 sclk, bandwidth;
851 fixed20_12 a;
852
853 a.full = dfixed_const(1000);
854 sclk.full = dfixed_const(wm->sclk);
855 sclk.full = dfixed_div(sclk, a);
856 a.full = dfixed_const(10);
857 return_efficiency.full = dfixed_const(8);
858 return_efficiency.full = dfixed_div(return_efficiency, a);
859 a.full = dfixed_const(32);
860 bandwidth.full = dfixed_mul(a, sclk);
861 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
862
863 return dfixed_trunc(bandwidth);
864 }
865
866 /**
867 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
868 *
869 * @wm: watermark calculation data
870 *
871 * Calculate the dmif bandwidth used for display (CIK).
872 * Used for display watermark bandwidth calculations
873 * Returns the dmif bandwidth in MBytes/s
874 */
875 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
876 {
877 /* Calculate the DMIF Request Bandwidth */
878 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
879 fixed20_12 disp_clk, bandwidth;
880 fixed20_12 a, b;
881
882 a.full = dfixed_const(1000);
883 disp_clk.full = dfixed_const(wm->disp_clk);
884 disp_clk.full = dfixed_div(disp_clk, a);
885 a.full = dfixed_const(32);
886 b.full = dfixed_mul(a, disp_clk);
887
888 a.full = dfixed_const(10);
889 disp_clk_request_efficiency.full = dfixed_const(8);
890 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
891
892 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
893
894 return dfixed_trunc(bandwidth);
895 }
896
897 /**
898 * dce_v11_0_available_bandwidth - get the min available bandwidth
899 *
900 * @wm: watermark calculation data
901 *
902 * Calculate the min available bandwidth used for display (CIK).
903 * Used for display watermark bandwidth calculations
904 * Returns the min available bandwidth in MBytes/s
905 */
906 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
907 {
908 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
909 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
910 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
911 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
912
913 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
914 }
915
916 /**
917 * dce_v11_0_average_bandwidth - get the average available bandwidth
918 *
919 * @wm: watermark calculation data
920 *
921 * Calculate the average available bandwidth used for display (CIK).
922 * Used for display watermark bandwidth calculations
923 * Returns the average available bandwidth in MBytes/s
924 */
925 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
926 {
927 /* Calculate the display mode Average Bandwidth
928 * DisplayMode should contain the source and destination dimensions,
929 * timing, etc.
930 */
931 fixed20_12 bpp;
932 fixed20_12 line_time;
933 fixed20_12 src_width;
934 fixed20_12 bandwidth;
935 fixed20_12 a;
936
937 a.full = dfixed_const(1000);
938 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
939 line_time.full = dfixed_div(line_time, a);
940 bpp.full = dfixed_const(wm->bytes_per_pixel);
941 src_width.full = dfixed_const(wm->src_width);
942 bandwidth.full = dfixed_mul(src_width, bpp);
943 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
944 bandwidth.full = dfixed_div(bandwidth, line_time);
945
946 return dfixed_trunc(bandwidth);
947 }
948
949 /**
950 * dce_v11_0_latency_watermark - get the latency watermark
951 *
952 * @wm: watermark calculation data
953 *
954 * Calculate the latency watermark (CIK).
955 * Used for display watermark bandwidth calculations
956 * Returns the latency watermark in ns
957 */
958 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
959 {
960 /* First calculate the latency in ns */
961 u32 mc_latency = 2000; /* 2000 ns. */
962 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
963 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
964 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
965 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
966 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
967 (wm->num_heads * cursor_line_pair_return_time);
968 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
969 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
970 u32 tmp, dmif_size = 12288;
971 fixed20_12 a, b, c;
972
973 if (wm->num_heads == 0)
974 return 0;
975
976 a.full = dfixed_const(2);
977 b.full = dfixed_const(1);
978 if ((wm->vsc.full > a.full) ||
979 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
980 (wm->vtaps >= 5) ||
981 ((wm->vsc.full >= a.full) && wm->interlaced))
982 max_src_lines_per_dst_line = 4;
983 else
984 max_src_lines_per_dst_line = 2;
985
986 a.full = dfixed_const(available_bandwidth);
987 b.full = dfixed_const(wm->num_heads);
988 a.full = dfixed_div(a, b);
989 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
990 tmp = min(dfixed_trunc(a), tmp);
991
992 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
993
994 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
995 b.full = dfixed_const(1000);
996 c.full = dfixed_const(lb_fill_bw);
997 b.full = dfixed_div(c, b);
998 a.full = dfixed_div(a, b);
999 line_fill_time = dfixed_trunc(a);
1000
1001 if (line_fill_time < wm->active_time)
1002 return latency;
1003 else
1004 return latency + (line_fill_time - wm->active_time);
1005
1006 }
1007
1008 /**
1009 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1010 * average and available dram bandwidth
1011 *
1012 * @wm: watermark calculation data
1013 *
1014 * Check if the display average bandwidth fits in the display
1015 * dram bandwidth (CIK).
1016 * Used for display watermark bandwidth calculations
1017 * Returns true if the display fits, false if not.
1018 */
1019 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1020 {
1021 if (dce_v11_0_average_bandwidth(wm) <=
1022 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1023 return true;
1024 else
1025 return false;
1026 }
1027
1028 /**
1029 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1030 * average and available bandwidth
1031 *
1032 * @wm: watermark calculation data
1033 *
1034 * Check if the display average bandwidth fits in the display
1035 * available bandwidth (CIK).
1036 * Used for display watermark bandwidth calculations
1037 * Returns true if the display fits, false if not.
1038 */
1039 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1040 {
1041 if (dce_v11_0_average_bandwidth(wm) <=
1042 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1043 return true;
1044 else
1045 return false;
1046 }
1047
1048 /**
1049 * dce_v11_0_check_latency_hiding - check latency hiding
1050 *
1051 * @wm: watermark calculation data
1052 *
1053 * Check latency hiding (CIK).
1054 * Used for display watermark bandwidth calculations
1055 * Returns true if the display fits, false if not.
1056 */
1057 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1058 {
1059 u32 lb_partitions = wm->lb_size / wm->src_width;
1060 u32 line_time = wm->active_time + wm->blank_time;
1061 u32 latency_tolerant_lines;
1062 u32 latency_hiding;
1063 fixed20_12 a;
1064
1065 a.full = dfixed_const(1);
1066 if (wm->vsc.full > a.full)
1067 latency_tolerant_lines = 1;
1068 else {
1069 if (lb_partitions <= (wm->vtaps + 1))
1070 latency_tolerant_lines = 1;
1071 else
1072 latency_tolerant_lines = 2;
1073 }
1074
1075 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1076
1077 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1078 return true;
1079 else
1080 return false;
1081 }
1082
1083 /**
1084 * dce_v11_0_program_watermarks - program display watermarks
1085 *
1086 * @adev: amdgpu_device pointer
1087 * @amdgpu_crtc: the selected display controller
1088 * @lb_size: line buffer size
1089 * @num_heads: number of display controllers in use
1090 *
1091 * Calculate and program the display watermarks for the
1092 * selected display controller (CIK).
1093 */
1094 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1095 struct amdgpu_crtc *amdgpu_crtc,
1096 u32 lb_size, u32 num_heads)
1097 {
1098 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1099 struct dce10_wm_params wm_low, wm_high;
1100 u32 active_time;
1101 u32 line_time = 0;
1102 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1103 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1104
1105 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1106 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1107 (u32)mode->clock);
1108 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1109 (u32)mode->clock);
1110 line_time = min(line_time, (u32)65535);
1111
1112 /* watermark for high clocks */
1113 if (adev->pm.dpm_enabled) {
1114 wm_high.yclk =
1115 amdgpu_dpm_get_mclk(adev, false) * 10;
1116 wm_high.sclk =
1117 amdgpu_dpm_get_sclk(adev, false) * 10;
1118 } else {
1119 wm_high.yclk = adev->pm.current_mclk * 10;
1120 wm_high.sclk = adev->pm.current_sclk * 10;
1121 }
1122
1123 wm_high.disp_clk = mode->clock;
1124 wm_high.src_width = mode->crtc_hdisplay;
1125 wm_high.active_time = active_time;
1126 wm_high.blank_time = line_time - wm_high.active_time;
1127 wm_high.interlaced = false;
1128 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1129 wm_high.interlaced = true;
1130 wm_high.vsc = amdgpu_crtc->vsc;
1131 wm_high.vtaps = 1;
1132 if (amdgpu_crtc->rmx_type != RMX_OFF)
1133 wm_high.vtaps = 2;
1134 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1135 wm_high.lb_size = lb_size;
1136 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1137 wm_high.num_heads = num_heads;
1138
1139 /* set for high clocks */
1140 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1141
1142 /* possibly force display priority to high */
1143 /* should really do this at mode validation time... */
1144 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1145 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1146 !dce_v11_0_check_latency_hiding(&wm_high) ||
1147 (adev->mode_info.disp_priority == 2)) {
1148 DRM_DEBUG_KMS("force priority to high\n");
1149 }
1150
1151 /* watermark for low clocks */
1152 if (adev->pm.dpm_enabled) {
1153 wm_low.yclk =
1154 amdgpu_dpm_get_mclk(adev, true) * 10;
1155 wm_low.sclk =
1156 amdgpu_dpm_get_sclk(adev, true) * 10;
1157 } else {
1158 wm_low.yclk = adev->pm.current_mclk * 10;
1159 wm_low.sclk = adev->pm.current_sclk * 10;
1160 }
1161
1162 wm_low.disp_clk = mode->clock;
1163 wm_low.src_width = mode->crtc_hdisplay;
1164 wm_low.active_time = active_time;
1165 wm_low.blank_time = line_time - wm_low.active_time;
1166 wm_low.interlaced = false;
1167 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1168 wm_low.interlaced = true;
1169 wm_low.vsc = amdgpu_crtc->vsc;
1170 wm_low.vtaps = 1;
1171 if (amdgpu_crtc->rmx_type != RMX_OFF)
1172 wm_low.vtaps = 2;
1173 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1174 wm_low.lb_size = lb_size;
1175 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1176 wm_low.num_heads = num_heads;
1177
1178 /* set for low clocks */
1179 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1180
1181 /* possibly force display priority to high */
1182 /* should really do this at mode validation time... */
1183 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1184 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1185 !dce_v11_0_check_latency_hiding(&wm_low) ||
1186 (adev->mode_info.disp_priority == 2)) {
1187 DRM_DEBUG_KMS("force priority to high\n");
1188 }
1189 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1190 }
1191
1192 /* select wm A */
1193 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1194 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1195 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1196 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1197 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1198 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1199 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1200 /* select wm B */
1201 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1202 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1203 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1204 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1205 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1206 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1207 /* restore original selection */
1208 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1209
1210 /* save values for DPM */
1211 amdgpu_crtc->line_time = line_time;
1212 amdgpu_crtc->wm_high = latency_watermark_a;
1213 amdgpu_crtc->wm_low = latency_watermark_b;
1214 /* Save number of lines the linebuffer leads before the scanout */
1215 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1216 }
1217
1218 /**
1219 * dce_v11_0_bandwidth_update - program display watermarks
1220 *
1221 * @adev: amdgpu_device pointer
1222 *
1223 * Calculate and program the display watermarks and line
1224 * buffer allocation (CIK).
1225 */
1226 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1227 {
1228 struct drm_display_mode *mode = NULL;
1229 u32 num_heads = 0, lb_size;
1230 int i;
1231
1232 amdgpu_update_display_priority(adev);
1233
1234 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1235 if (adev->mode_info.crtcs[i]->base.enabled)
1236 num_heads++;
1237 }
1238 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1239 mode = &adev->mode_info.crtcs[i]->base.mode;
1240 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1241 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1242 lb_size, num_heads);
1243 }
1244 }
1245
1246 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1247 {
1248 int i;
1249 u32 offset, tmp;
1250
1251 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1252 offset = adev->mode_info.audio.pin[i].offset;
1253 tmp = RREG32_AUDIO_ENDPT(offset,
1254 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1255 if (((tmp &
1256 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1257 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1258 adev->mode_info.audio.pin[i].connected = false;
1259 else
1260 adev->mode_info.audio.pin[i].connected = true;
1261 }
1262 }
1263
1264 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1265 {
1266 int i;
1267
1268 dce_v11_0_audio_get_connected_pins(adev);
1269
1270 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1271 if (adev->mode_info.audio.pin[i].connected)
1272 return &adev->mode_info.audio.pin[i];
1273 }
1274 DRM_ERROR("No connected audio pins found!\n");
1275 return NULL;
1276 }
1277
1278 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1279 {
1280 struct amdgpu_device *adev = encoder->dev->dev_private;
1281 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1282 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1283 u32 tmp;
1284
1285 if (!dig || !dig->afmt || !dig->afmt->pin)
1286 return;
1287
1288 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1289 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1290 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1291 }
1292
1293 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1294 struct drm_display_mode *mode)
1295 {
1296 struct amdgpu_device *adev = encoder->dev->dev_private;
1297 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1298 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1299 struct drm_connector *connector;
1300 struct amdgpu_connector *amdgpu_connector = NULL;
1301 u32 tmp;
1302 int interlace = 0;
1303
1304 if (!dig || !dig->afmt || !dig->afmt->pin)
1305 return;
1306
1307 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1308 if (connector->encoder == encoder) {
1309 amdgpu_connector = to_amdgpu_connector(connector);
1310 break;
1311 }
1312 }
1313
1314 if (!amdgpu_connector) {
1315 DRM_ERROR("Couldn't find encoder's connector\n");
1316 return;
1317 }
1318
1319 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1320 interlace = 1;
1321 if (connector->latency_present[interlace]) {
1322 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1323 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1324 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1325 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1326 } else {
1327 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1328 VIDEO_LIPSYNC, 0);
1329 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1330 AUDIO_LIPSYNC, 0);
1331 }
1332 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1333 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1334 }
1335
1336 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1337 {
1338 struct amdgpu_device *adev = encoder->dev->dev_private;
1339 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1340 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1341 struct drm_connector *connector;
1342 struct amdgpu_connector *amdgpu_connector = NULL;
1343 u32 tmp;
1344 u8 *sadb = NULL;
1345 int sad_count;
1346
1347 if (!dig || !dig->afmt || !dig->afmt->pin)
1348 return;
1349
1350 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1351 if (connector->encoder == encoder) {
1352 amdgpu_connector = to_amdgpu_connector(connector);
1353 break;
1354 }
1355 }
1356
1357 if (!amdgpu_connector) {
1358 DRM_ERROR("Couldn't find encoder's connector\n");
1359 return;
1360 }
1361
1362 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1363 if (sad_count < 0) {
1364 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1365 sad_count = 0;
1366 }
1367
1368 /* program the speaker allocation */
1369 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1370 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1371 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1372 DP_CONNECTION, 0);
1373 /* set HDMI mode */
1374 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1375 HDMI_CONNECTION, 1);
1376 if (sad_count)
1377 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1378 SPEAKER_ALLOCATION, sadb[0]);
1379 else
1380 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1381 SPEAKER_ALLOCATION, 5); /* stereo */
1382 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1383 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1384
1385 kfree(sadb);
1386 }
1387
1388 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1389 {
1390 struct amdgpu_device *adev = encoder->dev->dev_private;
1391 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1392 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1393 struct drm_connector *connector;
1394 struct amdgpu_connector *amdgpu_connector = NULL;
1395 struct cea_sad *sads;
1396 int i, sad_count;
1397
1398 static const u16 eld_reg_to_type[][2] = {
1399 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1400 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1401 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1402 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1403 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1404 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1405 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1406 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1407 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1408 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1409 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1410 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1411 };
1412
1413 if (!dig || !dig->afmt || !dig->afmt->pin)
1414 return;
1415
1416 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1417 if (connector->encoder == encoder) {
1418 amdgpu_connector = to_amdgpu_connector(connector);
1419 break;
1420 }
1421 }
1422
1423 if (!amdgpu_connector) {
1424 DRM_ERROR("Couldn't find encoder's connector\n");
1425 return;
1426 }
1427
1428 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1429 if (sad_count <= 0) {
1430 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1431 return;
1432 }
1433 BUG_ON(!sads);
1434
1435 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1436 u32 tmp = 0;
1437 u8 stereo_freqs = 0;
1438 int max_channels = -1;
1439 int j;
1440
1441 for (j = 0; j < sad_count; j++) {
1442 struct cea_sad *sad = &sads[j];
1443
1444 if (sad->format == eld_reg_to_type[i][1]) {
1445 if (sad->channels > max_channels) {
1446 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1447 MAX_CHANNELS, sad->channels);
1448 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1449 DESCRIPTOR_BYTE_2, sad->byte2);
1450 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1451 SUPPORTED_FREQUENCIES, sad->freq);
1452 max_channels = sad->channels;
1453 }
1454
1455 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1456 stereo_freqs |= sad->freq;
1457 else
1458 break;
1459 }
1460 }
1461
1462 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1463 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1464 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1465 }
1466
1467 kfree(sads);
1468 }
1469
1470 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1471 struct amdgpu_audio_pin *pin,
1472 bool enable)
1473 {
1474 if (!pin)
1475 return;
1476
1477 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1478 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1479 }
1480
1481 static const u32 pin_offsets[] =
1482 {
1483 AUD0_REGISTER_OFFSET,
1484 AUD1_REGISTER_OFFSET,
1485 AUD2_REGISTER_OFFSET,
1486 AUD3_REGISTER_OFFSET,
1487 AUD4_REGISTER_OFFSET,
1488 AUD5_REGISTER_OFFSET,
1489 AUD6_REGISTER_OFFSET,
1490 AUD7_REGISTER_OFFSET,
1491 };
1492
1493 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1494 {
1495 int i;
1496
1497 if (!amdgpu_audio)
1498 return 0;
1499
1500 adev->mode_info.audio.enabled = true;
1501
1502 switch (adev->asic_type) {
1503 case CHIP_CARRIZO:
1504 case CHIP_STONEY:
1505 adev->mode_info.audio.num_pins = 7;
1506 break;
1507 case CHIP_POLARIS10:
1508 adev->mode_info.audio.num_pins = 8;
1509 break;
1510 case CHIP_POLARIS11:
1511 case CHIP_POLARIS12:
1512 adev->mode_info.audio.num_pins = 6;
1513 break;
1514 default:
1515 return -EINVAL;
1516 }
1517
1518 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1519 adev->mode_info.audio.pin[i].channels = -1;
1520 adev->mode_info.audio.pin[i].rate = -1;
1521 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1522 adev->mode_info.audio.pin[i].status_bits = 0;
1523 adev->mode_info.audio.pin[i].category_code = 0;
1524 adev->mode_info.audio.pin[i].connected = false;
1525 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1526 adev->mode_info.audio.pin[i].id = i;
1527 /* disable audio. it will be set up later */
1528 /* XXX remove once we switch to ip funcs */
1529 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1530 }
1531
1532 return 0;
1533 }
1534
1535 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1536 {
1537 int i;
1538
1539 if (!amdgpu_audio)
1540 return;
1541
1542 if (!adev->mode_info.audio.enabled)
1543 return;
1544
1545 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1546 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1547
1548 adev->mode_info.audio.enabled = false;
1549 }
1550
1551 /*
1552 * update the N and CTS parameters for a given pixel clock rate
1553 */
1554 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1555 {
1556 struct drm_device *dev = encoder->dev;
1557 struct amdgpu_device *adev = dev->dev_private;
1558 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1559 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1560 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1561 u32 tmp;
1562
1563 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1564 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1565 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1566 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1567 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1568 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1569
1570 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1571 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1572 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1573 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1574 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1575 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1576
1577 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1578 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1579 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1580 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1581 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1582 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1583
1584 }
1585
1586 /*
1587 * build a HDMI Video Info Frame
1588 */
1589 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1590 void *buffer, size_t size)
1591 {
1592 struct drm_device *dev = encoder->dev;
1593 struct amdgpu_device *adev = dev->dev_private;
1594 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1595 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1596 uint8_t *frame = buffer + 3;
1597 uint8_t *header = buffer;
1598
1599 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1600 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1601 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1602 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1603 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1604 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1605 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1606 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1607 }
1608
1609 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1610 {
1611 struct drm_device *dev = encoder->dev;
1612 struct amdgpu_device *adev = dev->dev_private;
1613 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1614 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1615 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1616 u32 dto_phase = 24 * 1000;
1617 u32 dto_modulo = clock;
1618 u32 tmp;
1619
1620 if (!dig || !dig->afmt)
1621 return;
1622
1623 /* XXX two dtos; generally use dto0 for hdmi */
1624 /* Express [24MHz / target pixel clock] as an exact rational
1625 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1626 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1627 */
1628 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1629 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1630 amdgpu_crtc->crtc_id);
1631 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1632 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1633 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1634 }
1635
1636 /*
1637 * update the info frames with the data from the current display mode
1638 */
1639 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1640 struct drm_display_mode *mode)
1641 {
1642 struct drm_device *dev = encoder->dev;
1643 struct amdgpu_device *adev = dev->dev_private;
1644 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1645 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1646 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1647 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1648 struct hdmi_avi_infoframe frame;
1649 ssize_t err;
1650 u32 tmp;
1651 int bpc = 8;
1652
1653 if (!dig || !dig->afmt)
1654 return;
1655
1656 /* Silent, r600_hdmi_enable will raise WARN for us */
1657 if (!dig->afmt->enabled)
1658 return;
1659
1660 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1661 if (encoder->crtc) {
1662 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1663 bpc = amdgpu_crtc->bpc;
1664 }
1665
1666 /* disable audio prior to setting up hw */
1667 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1668 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1669
1670 dce_v11_0_audio_set_dto(encoder, mode->clock);
1671
1672 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1673 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1674 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1675
1676 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1677
1678 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1679 switch (bpc) {
1680 case 0:
1681 case 6:
1682 case 8:
1683 case 16:
1684 default:
1685 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1686 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1687 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1688 connector->name, bpc);
1689 break;
1690 case 10:
1691 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1692 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1693 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1694 connector->name);
1695 break;
1696 case 12:
1697 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1698 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1699 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1700 connector->name);
1701 break;
1702 }
1703 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1704
1705 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1706 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1707 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1708 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1709 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1710
1711 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1712 /* enable audio info frames (frames won't be set until audio is enabled) */
1713 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1714 /* required for audio info values to be updated */
1715 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1716 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1717
1718 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1719 /* required for audio info values to be updated */
1720 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1721 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1722
1723 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1724 /* anything other than 0 */
1725 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1726 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1727
1728 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1729
1730 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1731 /* set the default audio delay */
1732 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1733 /* should be suffient for all audio modes and small enough for all hblanks */
1734 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1735 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1736
1737 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1738 /* allow 60958 channel status fields to be updated */
1739 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1740 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1741
1742 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1743 if (bpc > 8)
1744 /* clear SW CTS value */
1745 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1746 else
1747 /* select SW CTS value */
1748 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1749 /* allow hw to sent ACR packets when required */
1750 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1751 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1752
1753 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1754
1755 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1756 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1757 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1758
1759 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1760 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1761 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1762
1763 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1764 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1765 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1766 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1767 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1768 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1769 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1770 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1771
1772 dce_v11_0_audio_write_speaker_allocation(encoder);
1773
1774 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1775 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1776
1777 dce_v11_0_afmt_audio_select_pin(encoder);
1778 dce_v11_0_audio_write_sad_regs(encoder);
1779 dce_v11_0_audio_write_latency_fields(encoder, mode);
1780
1781 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1782 if (err < 0) {
1783 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1784 return;
1785 }
1786
1787 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1788 if (err < 0) {
1789 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1790 return;
1791 }
1792
1793 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1794
1795 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1796 /* enable AVI info frames */
1797 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1798 /* required for audio info values to be updated */
1799 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1800 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1801
1802 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1803 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1804 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1805
1806 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1807 /* send audio packets */
1808 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1809 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1810
1811 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1812 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1813 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1814 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1815
1816 /* enable audio after to setting up hw */
1817 dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1818 }
1819
1820 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1821 {
1822 struct drm_device *dev = encoder->dev;
1823 struct amdgpu_device *adev = dev->dev_private;
1824 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1825 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1826
1827 if (!dig || !dig->afmt)
1828 return;
1829
1830 /* Silent, r600_hdmi_enable will raise WARN for us */
1831 if (enable && dig->afmt->enabled)
1832 return;
1833 if (!enable && !dig->afmt->enabled)
1834 return;
1835
1836 if (!enable && dig->afmt->pin) {
1837 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1838 dig->afmt->pin = NULL;
1839 }
1840
1841 dig->afmt->enabled = enable;
1842
1843 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1844 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1845 }
1846
1847 static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1848 {
1849 int i;
1850
1851 for (i = 0; i < adev->mode_info.num_dig; i++)
1852 adev->mode_info.afmt[i] = NULL;
1853
1854 /* DCE11 has audio blocks tied to DIG encoders */
1855 for (i = 0; i < adev->mode_info.num_dig; i++) {
1856 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1857 if (adev->mode_info.afmt[i]) {
1858 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1859 adev->mode_info.afmt[i]->id = i;
1860 } else {
1861 int j;
1862 for (j = 0; j < i; j++) {
1863 kfree(adev->mode_info.afmt[j]);
1864 adev->mode_info.afmt[j] = NULL;
1865 }
1866 return -ENOMEM;
1867 }
1868 }
1869 return 0;
1870 }
1871
1872 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1873 {
1874 int i;
1875
1876 for (i = 0; i < adev->mode_info.num_dig; i++) {
1877 kfree(adev->mode_info.afmt[i]);
1878 adev->mode_info.afmt[i] = NULL;
1879 }
1880 }
1881
1882 static const u32 vga_control_regs[6] =
1883 {
1884 mmD1VGA_CONTROL,
1885 mmD2VGA_CONTROL,
1886 mmD3VGA_CONTROL,
1887 mmD4VGA_CONTROL,
1888 mmD5VGA_CONTROL,
1889 mmD6VGA_CONTROL,
1890 };
1891
1892 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1893 {
1894 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1895 struct drm_device *dev = crtc->dev;
1896 struct amdgpu_device *adev = dev->dev_private;
1897 u32 vga_control;
1898
1899 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1900 if (enable)
1901 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1902 else
1903 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1904 }
1905
1906 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
1907 {
1908 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1909 struct drm_device *dev = crtc->dev;
1910 struct amdgpu_device *adev = dev->dev_private;
1911
1912 if (enable)
1913 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1914 else
1915 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1916 }
1917
1918 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
1919 struct drm_framebuffer *fb,
1920 int x, int y, int atomic)
1921 {
1922 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1923 struct drm_device *dev = crtc->dev;
1924 struct amdgpu_device *adev = dev->dev_private;
1925 struct amdgpu_framebuffer *amdgpu_fb;
1926 struct drm_framebuffer *target_fb;
1927 struct drm_gem_object *obj;
1928 struct amdgpu_bo *abo;
1929 uint64_t fb_location, tiling_flags;
1930 uint32_t fb_format, fb_pitch_pixels;
1931 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1932 u32 pipe_config;
1933 u32 tmp, viewport_w, viewport_h;
1934 int r;
1935 bool bypass_lut = false;
1936 struct drm_format_name_buf format_name;
1937
1938 /* no fb bound */
1939 if (!atomic && !crtc->primary->fb) {
1940 DRM_DEBUG_KMS("No FB bound\n");
1941 return 0;
1942 }
1943
1944 if (atomic) {
1945 amdgpu_fb = to_amdgpu_framebuffer(fb);
1946 target_fb = fb;
1947 } else {
1948 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1949 target_fb = crtc->primary->fb;
1950 }
1951
1952 /* If atomic, assume fb object is pinned & idle & fenced and
1953 * just update base pointers
1954 */
1955 obj = amdgpu_fb->obj;
1956 abo = gem_to_amdgpu_bo(obj);
1957 r = amdgpu_bo_reserve(abo, false);
1958 if (unlikely(r != 0))
1959 return r;
1960
1961 if (atomic) {
1962 fb_location = amdgpu_bo_gpu_offset(abo);
1963 } else {
1964 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
1965 if (unlikely(r != 0)) {
1966 amdgpu_bo_unreserve(abo);
1967 return -EINVAL;
1968 }
1969 }
1970
1971 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1972 amdgpu_bo_unreserve(abo);
1973
1974 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1975
1976 switch (target_fb->format->format) {
1977 case DRM_FORMAT_C8:
1978 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1979 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1980 break;
1981 case DRM_FORMAT_XRGB4444:
1982 case DRM_FORMAT_ARGB4444:
1983 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1984 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1985 #ifdef __BIG_ENDIAN
1986 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1987 ENDIAN_8IN16);
1988 #endif
1989 break;
1990 case DRM_FORMAT_XRGB1555:
1991 case DRM_FORMAT_ARGB1555:
1992 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1993 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1994 #ifdef __BIG_ENDIAN
1995 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1996 ENDIAN_8IN16);
1997 #endif
1998 break;
1999 case DRM_FORMAT_BGRX5551:
2000 case DRM_FORMAT_BGRA5551:
2001 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2002 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2003 #ifdef __BIG_ENDIAN
2004 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2005 ENDIAN_8IN16);
2006 #endif
2007 break;
2008 case DRM_FORMAT_RGB565:
2009 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2010 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2011 #ifdef __BIG_ENDIAN
2012 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2013 ENDIAN_8IN16);
2014 #endif
2015 break;
2016 case DRM_FORMAT_XRGB8888:
2017 case DRM_FORMAT_ARGB8888:
2018 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2019 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2020 #ifdef __BIG_ENDIAN
2021 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2022 ENDIAN_8IN32);
2023 #endif
2024 break;
2025 case DRM_FORMAT_XRGB2101010:
2026 case DRM_FORMAT_ARGB2101010:
2027 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2028 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2029 #ifdef __BIG_ENDIAN
2030 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2031 ENDIAN_8IN32);
2032 #endif
2033 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2034 bypass_lut = true;
2035 break;
2036 case DRM_FORMAT_BGRX1010102:
2037 case DRM_FORMAT_BGRA1010102:
2038 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2039 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2040 #ifdef __BIG_ENDIAN
2041 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2042 ENDIAN_8IN32);
2043 #endif
2044 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2045 bypass_lut = true;
2046 break;
2047 default:
2048 DRM_ERROR("Unsupported screen format %s\n",
2049 drm_get_format_name(target_fb->format->format, &format_name));
2050 return -EINVAL;
2051 }
2052
2053 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2054 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2055
2056 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2057 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2058 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2059 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2060 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2061
2062 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2063 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2064 ARRAY_2D_TILED_THIN1);
2065 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2066 tile_split);
2067 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2068 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2069 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2070 mtaspect);
2071 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2072 ADDR_SURF_MICRO_TILING_DISPLAY);
2073 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2074 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2075 ARRAY_1D_TILED_THIN1);
2076 }
2077
2078 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2079 pipe_config);
2080
2081 dce_v11_0_vga_enable(crtc, false);
2082
2083 /* Make sure surface address is updated at vertical blank rather than
2084 * horizontal blank
2085 */
2086 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2087 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2088 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2089 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2090
2091 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2092 upper_32_bits(fb_location));
2093 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2094 upper_32_bits(fb_location));
2095 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2096 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2097 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2098 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2099 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2100 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2101
2102 /*
2103 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2104 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2105 * retain the full precision throughout the pipeline.
2106 */
2107 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2108 if (bypass_lut)
2109 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2110 else
2111 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2112 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2113
2114 if (bypass_lut)
2115 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2116
2117 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2118 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2119 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2120 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2121 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2122 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2123
2124 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2125 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2126
2127 dce_v11_0_grph_enable(crtc, true);
2128
2129 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2130 target_fb->height);
2131
2132 x &= ~3;
2133 y &= ~1;
2134 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2135 (x << 16) | y);
2136 viewport_w = crtc->mode.hdisplay;
2137 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2138 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2139 (viewport_w << 16) | viewport_h);
2140
2141 /* set pageflip to happen anywhere in vblank interval */
2142 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2143
2144 if (!atomic && fb && fb != crtc->primary->fb) {
2145 amdgpu_fb = to_amdgpu_framebuffer(fb);
2146 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2147 r = amdgpu_bo_reserve(abo, true);
2148 if (unlikely(r != 0))
2149 return r;
2150 amdgpu_bo_unpin(abo);
2151 amdgpu_bo_unreserve(abo);
2152 }
2153
2154 /* Bytes per pixel may have changed */
2155 dce_v11_0_bandwidth_update(adev);
2156
2157 return 0;
2158 }
2159
2160 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2161 struct drm_display_mode *mode)
2162 {
2163 struct drm_device *dev = crtc->dev;
2164 struct amdgpu_device *adev = dev->dev_private;
2165 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2166 u32 tmp;
2167
2168 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2169 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2170 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2171 else
2172 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2173 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2174 }
2175
2176 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2177 {
2178 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2179 struct drm_device *dev = crtc->dev;
2180 struct amdgpu_device *adev = dev->dev_private;
2181 u16 *r, *g, *b;
2182 int i;
2183 u32 tmp;
2184
2185 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2186
2187 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2188 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2189 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2190
2191 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2192 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2193 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2194
2195 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2196 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2197 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2198
2199 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2200
2201 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2202 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2203 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2204
2205 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2206 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2207 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2208
2209 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2210 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2211
2212 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2213 r = crtc->gamma_store;
2214 g = r + crtc->gamma_size;
2215 b = g + crtc->gamma_size;
2216 for (i = 0; i < 256; i++) {
2217 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2218 ((*r++ & 0xffc0) << 14) |
2219 ((*g++ & 0xffc0) << 4) |
2220 (*b++ >> 6));
2221 }
2222
2223 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2224 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2225 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2226 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2227 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2228
2229 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2230 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2231 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2232
2233 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2234 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2235 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2236
2237 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2238 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2239 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2240
2241 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2242 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2243 /* XXX this only needs to be programmed once per crtc at startup,
2244 * not sure where the best place for it is
2245 */
2246 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2247 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2248 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2249 }
2250
2251 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2252 {
2253 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2254 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2255
2256 switch (amdgpu_encoder->encoder_id) {
2257 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2258 if (dig->linkb)
2259 return 1;
2260 else
2261 return 0;
2262 break;
2263 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2264 if (dig->linkb)
2265 return 3;
2266 else
2267 return 2;
2268 break;
2269 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2270 if (dig->linkb)
2271 return 5;
2272 else
2273 return 4;
2274 break;
2275 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2276 return 6;
2277 break;
2278 default:
2279 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2280 return 0;
2281 }
2282 }
2283
2284 /**
2285 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2286 *
2287 * @crtc: drm crtc
2288 *
2289 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2290 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2291 * monitors a dedicated PPLL must be used. If a particular board has
2292 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2293 * as there is no need to program the PLL itself. If we are not able to
2294 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2295 * avoid messing up an existing monitor.
2296 *
2297 * Asic specific PLL information
2298 *
2299 * DCE 10.x
2300 * Tonga
2301 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2302 * CI
2303 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2304 *
2305 */
2306 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2307 {
2308 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2309 struct drm_device *dev = crtc->dev;
2310 struct amdgpu_device *adev = dev->dev_private;
2311 u32 pll_in_use;
2312 int pll;
2313
2314 if ((adev->asic_type == CHIP_POLARIS10) ||
2315 (adev->asic_type == CHIP_POLARIS11) ||
2316 (adev->asic_type == CHIP_POLARIS12)) {
2317 struct amdgpu_encoder *amdgpu_encoder =
2318 to_amdgpu_encoder(amdgpu_crtc->encoder);
2319 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2320
2321 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2322 return ATOM_DP_DTO;
2323
2324 switch (amdgpu_encoder->encoder_id) {
2325 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2326 if (dig->linkb)
2327 return ATOM_COMBOPHY_PLL1;
2328 else
2329 return ATOM_COMBOPHY_PLL0;
2330 break;
2331 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2332 if (dig->linkb)
2333 return ATOM_COMBOPHY_PLL3;
2334 else
2335 return ATOM_COMBOPHY_PLL2;
2336 break;
2337 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2338 if (dig->linkb)
2339 return ATOM_COMBOPHY_PLL5;
2340 else
2341 return ATOM_COMBOPHY_PLL4;
2342 break;
2343 default:
2344 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2345 return ATOM_PPLL_INVALID;
2346 }
2347 }
2348
2349 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2350 if (adev->clock.dp_extclk)
2351 /* skip PPLL programming if using ext clock */
2352 return ATOM_PPLL_INVALID;
2353 else {
2354 /* use the same PPLL for all DP monitors */
2355 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2356 if (pll != ATOM_PPLL_INVALID)
2357 return pll;
2358 }
2359 } else {
2360 /* use the same PPLL for all monitors with the same clock */
2361 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2362 if (pll != ATOM_PPLL_INVALID)
2363 return pll;
2364 }
2365
2366 /* XXX need to determine what plls are available on each DCE11 part */
2367 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2368 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2369 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2370 return ATOM_PPLL1;
2371 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2372 return ATOM_PPLL0;
2373 DRM_ERROR("unable to allocate a PPLL\n");
2374 return ATOM_PPLL_INVALID;
2375 } else {
2376 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2377 return ATOM_PPLL2;
2378 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2379 return ATOM_PPLL1;
2380 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2381 return ATOM_PPLL0;
2382 DRM_ERROR("unable to allocate a PPLL\n");
2383 return ATOM_PPLL_INVALID;
2384 }
2385 return ATOM_PPLL_INVALID;
2386 }
2387
2388 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2389 {
2390 struct amdgpu_device *adev = crtc->dev->dev_private;
2391 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2392 uint32_t cur_lock;
2393
2394 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2395 if (lock)
2396 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2397 else
2398 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2399 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2400 }
2401
2402 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2403 {
2404 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2405 struct amdgpu_device *adev = crtc->dev->dev_private;
2406 u32 tmp;
2407
2408 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2409 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2410 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2411 }
2412
2413 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2414 {
2415 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2416 struct amdgpu_device *adev = crtc->dev->dev_private;
2417 u32 tmp;
2418
2419 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2420 upper_32_bits(amdgpu_crtc->cursor_addr));
2421 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2422 lower_32_bits(amdgpu_crtc->cursor_addr));
2423
2424 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2425 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2426 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2427 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2428 }
2429
2430 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2431 int x, int y)
2432 {
2433 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2434 struct amdgpu_device *adev = crtc->dev->dev_private;
2435 int xorigin = 0, yorigin = 0;
2436
2437 amdgpu_crtc->cursor_x = x;
2438 amdgpu_crtc->cursor_y = y;
2439
2440 /* avivo cursor are offset into the total surface */
2441 x += crtc->x;
2442 y += crtc->y;
2443 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2444
2445 if (x < 0) {
2446 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2447 x = 0;
2448 }
2449 if (y < 0) {
2450 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2451 y = 0;
2452 }
2453
2454 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2455 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2456 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2457 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2458
2459 return 0;
2460 }
2461
2462 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2463 int x, int y)
2464 {
2465 int ret;
2466
2467 dce_v11_0_lock_cursor(crtc, true);
2468 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2469 dce_v11_0_lock_cursor(crtc, false);
2470
2471 return ret;
2472 }
2473
2474 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2475 struct drm_file *file_priv,
2476 uint32_t handle,
2477 uint32_t width,
2478 uint32_t height,
2479 int32_t hot_x,
2480 int32_t hot_y)
2481 {
2482 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2483 struct drm_gem_object *obj;
2484 struct amdgpu_bo *aobj;
2485 int ret;
2486
2487 if (!handle) {
2488 /* turn off cursor */
2489 dce_v11_0_hide_cursor(crtc);
2490 obj = NULL;
2491 goto unpin;
2492 }
2493
2494 if ((width > amdgpu_crtc->max_cursor_width) ||
2495 (height > amdgpu_crtc->max_cursor_height)) {
2496 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2497 return -EINVAL;
2498 }
2499
2500 obj = drm_gem_object_lookup(file_priv, handle);
2501 if (!obj) {
2502 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2503 return -ENOENT;
2504 }
2505
2506 aobj = gem_to_amdgpu_bo(obj);
2507 ret = amdgpu_bo_reserve(aobj, false);
2508 if (ret != 0) {
2509 drm_gem_object_put_unlocked(obj);
2510 return ret;
2511 }
2512
2513 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2514 amdgpu_bo_unreserve(aobj);
2515 if (ret) {
2516 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2517 drm_gem_object_put_unlocked(obj);
2518 return ret;
2519 }
2520
2521 dce_v11_0_lock_cursor(crtc, true);
2522
2523 if (width != amdgpu_crtc->cursor_width ||
2524 height != amdgpu_crtc->cursor_height ||
2525 hot_x != amdgpu_crtc->cursor_hot_x ||
2526 hot_y != amdgpu_crtc->cursor_hot_y) {
2527 int x, y;
2528
2529 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2530 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2531
2532 dce_v11_0_cursor_move_locked(crtc, x, y);
2533
2534 amdgpu_crtc->cursor_width = width;
2535 amdgpu_crtc->cursor_height = height;
2536 amdgpu_crtc->cursor_hot_x = hot_x;
2537 amdgpu_crtc->cursor_hot_y = hot_y;
2538 }
2539
2540 dce_v11_0_show_cursor(crtc);
2541 dce_v11_0_lock_cursor(crtc, false);
2542
2543 unpin:
2544 if (amdgpu_crtc->cursor_bo) {
2545 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2546 ret = amdgpu_bo_reserve(aobj, true);
2547 if (likely(ret == 0)) {
2548 amdgpu_bo_unpin(aobj);
2549 amdgpu_bo_unreserve(aobj);
2550 }
2551 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2552 }
2553
2554 amdgpu_crtc->cursor_bo = obj;
2555 return 0;
2556 }
2557
2558 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2559 {
2560 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2561
2562 if (amdgpu_crtc->cursor_bo) {
2563 dce_v11_0_lock_cursor(crtc, true);
2564
2565 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2566 amdgpu_crtc->cursor_y);
2567
2568 dce_v11_0_show_cursor(crtc);
2569
2570 dce_v11_0_lock_cursor(crtc, false);
2571 }
2572 }
2573
2574 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2575 u16 *blue, uint32_t size,
2576 struct drm_modeset_acquire_ctx *ctx)
2577 {
2578 dce_v11_0_crtc_load_lut(crtc);
2579
2580 return 0;
2581 }
2582
2583 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2584 {
2585 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2586
2587 drm_crtc_cleanup(crtc);
2588 kfree(amdgpu_crtc);
2589 }
2590
2591 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2592 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2593 .cursor_move = dce_v11_0_crtc_cursor_move,
2594 .gamma_set = dce_v11_0_crtc_gamma_set,
2595 .set_config = amdgpu_crtc_set_config,
2596 .destroy = dce_v11_0_crtc_destroy,
2597 .page_flip_target = amdgpu_crtc_page_flip_target,
2598 };
2599
2600 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2601 {
2602 struct drm_device *dev = crtc->dev;
2603 struct amdgpu_device *adev = dev->dev_private;
2604 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2605 unsigned type;
2606
2607 switch (mode) {
2608 case DRM_MODE_DPMS_ON:
2609 amdgpu_crtc->enabled = true;
2610 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2611 dce_v11_0_vga_enable(crtc, true);
2612 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2613 dce_v11_0_vga_enable(crtc, false);
2614 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2615 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2616 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2617 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2618 drm_crtc_vblank_on(crtc);
2619 dce_v11_0_crtc_load_lut(crtc);
2620 break;
2621 case DRM_MODE_DPMS_STANDBY:
2622 case DRM_MODE_DPMS_SUSPEND:
2623 case DRM_MODE_DPMS_OFF:
2624 drm_crtc_vblank_off(crtc);
2625 if (amdgpu_crtc->enabled) {
2626 dce_v11_0_vga_enable(crtc, true);
2627 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2628 dce_v11_0_vga_enable(crtc, false);
2629 }
2630 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2631 amdgpu_crtc->enabled = false;
2632 break;
2633 }
2634 /* adjust pm to dpms */
2635 amdgpu_pm_compute_clocks(adev);
2636 }
2637
2638 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2639 {
2640 /* disable crtc pair power gating before programming */
2641 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2642 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2643 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2644 }
2645
2646 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2647 {
2648 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2649 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2650 }
2651
2652 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2653 {
2654 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2655 struct drm_device *dev = crtc->dev;
2656 struct amdgpu_device *adev = dev->dev_private;
2657 struct amdgpu_atom_ss ss;
2658 int i;
2659
2660 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2661 if (crtc->primary->fb) {
2662 int r;
2663 struct amdgpu_framebuffer *amdgpu_fb;
2664 struct amdgpu_bo *abo;
2665
2666 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2667 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2668 r = amdgpu_bo_reserve(abo, true);
2669 if (unlikely(r))
2670 DRM_ERROR("failed to reserve abo before unpin\n");
2671 else {
2672 amdgpu_bo_unpin(abo);
2673 amdgpu_bo_unreserve(abo);
2674 }
2675 }
2676 /* disable the GRPH */
2677 dce_v11_0_grph_enable(crtc, false);
2678
2679 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2680
2681 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2682 if (adev->mode_info.crtcs[i] &&
2683 adev->mode_info.crtcs[i]->enabled &&
2684 i != amdgpu_crtc->crtc_id &&
2685 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2686 /* one other crtc is using this pll don't turn
2687 * off the pll
2688 */
2689 goto done;
2690 }
2691 }
2692
2693 switch (amdgpu_crtc->pll_id) {
2694 case ATOM_PPLL0:
2695 case ATOM_PPLL1:
2696 case ATOM_PPLL2:
2697 /* disable the ppll */
2698 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2699 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2700 break;
2701 case ATOM_COMBOPHY_PLL0:
2702 case ATOM_COMBOPHY_PLL1:
2703 case ATOM_COMBOPHY_PLL2:
2704 case ATOM_COMBOPHY_PLL3:
2705 case ATOM_COMBOPHY_PLL4:
2706 case ATOM_COMBOPHY_PLL5:
2707 /* disable the ppll */
2708 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2709 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2710 break;
2711 default:
2712 break;
2713 }
2714 done:
2715 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2716 amdgpu_crtc->adjusted_clock = 0;
2717 amdgpu_crtc->encoder = NULL;
2718 amdgpu_crtc->connector = NULL;
2719 }
2720
2721 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2722 struct drm_display_mode *mode,
2723 struct drm_display_mode *adjusted_mode,
2724 int x, int y, struct drm_framebuffer *old_fb)
2725 {
2726 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2727 struct drm_device *dev = crtc->dev;
2728 struct amdgpu_device *adev = dev->dev_private;
2729
2730 if (!amdgpu_crtc->adjusted_clock)
2731 return -EINVAL;
2732
2733 if ((adev->asic_type == CHIP_POLARIS10) ||
2734 (adev->asic_type == CHIP_POLARIS11) ||
2735 (adev->asic_type == CHIP_POLARIS12)) {
2736 struct amdgpu_encoder *amdgpu_encoder =
2737 to_amdgpu_encoder(amdgpu_crtc->encoder);
2738 int encoder_mode =
2739 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2740
2741 /* SetPixelClock calculates the plls and ss values now */
2742 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2743 amdgpu_crtc->pll_id,
2744 encoder_mode, amdgpu_encoder->encoder_id,
2745 adjusted_mode->clock, 0, 0, 0, 0,
2746 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2747 } else {
2748 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2749 }
2750 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2751 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2752 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2753 amdgpu_atombios_crtc_scaler_setup(crtc);
2754 dce_v11_0_cursor_reset(crtc);
2755 /* update the hw version fpr dpm */
2756 amdgpu_crtc->hw_mode = *adjusted_mode;
2757
2758 return 0;
2759 }
2760
2761 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2762 const struct drm_display_mode *mode,
2763 struct drm_display_mode *adjusted_mode)
2764 {
2765 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2766 struct drm_device *dev = crtc->dev;
2767 struct drm_encoder *encoder;
2768
2769 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2770 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2771 if (encoder->crtc == crtc) {
2772 amdgpu_crtc->encoder = encoder;
2773 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2774 break;
2775 }
2776 }
2777 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2778 amdgpu_crtc->encoder = NULL;
2779 amdgpu_crtc->connector = NULL;
2780 return false;
2781 }
2782 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2783 return false;
2784 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2785 return false;
2786 /* pick pll */
2787 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2788 /* if we can't get a PPLL for a non-DP encoder, fail */
2789 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2790 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2791 return false;
2792
2793 return true;
2794 }
2795
2796 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2797 struct drm_framebuffer *old_fb)
2798 {
2799 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2800 }
2801
2802 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2803 struct drm_framebuffer *fb,
2804 int x, int y, enum mode_set_atomic state)
2805 {
2806 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2807 }
2808
2809 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2810 .dpms = dce_v11_0_crtc_dpms,
2811 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2812 .mode_set = dce_v11_0_crtc_mode_set,
2813 .mode_set_base = dce_v11_0_crtc_set_base,
2814 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2815 .prepare = dce_v11_0_crtc_prepare,
2816 .commit = dce_v11_0_crtc_commit,
2817 .disable = dce_v11_0_crtc_disable,
2818 };
2819
2820 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2821 {
2822 struct amdgpu_crtc *amdgpu_crtc;
2823
2824 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2825 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2826 if (amdgpu_crtc == NULL)
2827 return -ENOMEM;
2828
2829 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2830
2831 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2832 amdgpu_crtc->crtc_id = index;
2833 adev->mode_info.crtcs[index] = amdgpu_crtc;
2834
2835 amdgpu_crtc->max_cursor_width = 128;
2836 amdgpu_crtc->max_cursor_height = 128;
2837 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2838 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2839
2840 switch (amdgpu_crtc->crtc_id) {
2841 case 0:
2842 default:
2843 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2844 break;
2845 case 1:
2846 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2847 break;
2848 case 2:
2849 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2850 break;
2851 case 3:
2852 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2853 break;
2854 case 4:
2855 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2856 break;
2857 case 5:
2858 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2859 break;
2860 }
2861
2862 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2863 amdgpu_crtc->adjusted_clock = 0;
2864 amdgpu_crtc->encoder = NULL;
2865 amdgpu_crtc->connector = NULL;
2866 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2867
2868 return 0;
2869 }
2870
2871 static int dce_v11_0_early_init(void *handle)
2872 {
2873 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2874
2875 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2876 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2877
2878 dce_v11_0_set_display_funcs(adev);
2879
2880 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
2881
2882 switch (adev->asic_type) {
2883 case CHIP_CARRIZO:
2884 adev->mode_info.num_hpd = 6;
2885 adev->mode_info.num_dig = 9;
2886 break;
2887 case CHIP_STONEY:
2888 adev->mode_info.num_hpd = 6;
2889 adev->mode_info.num_dig = 9;
2890 break;
2891 case CHIP_POLARIS10:
2892 adev->mode_info.num_hpd = 6;
2893 adev->mode_info.num_dig = 6;
2894 break;
2895 case CHIP_POLARIS11:
2896 case CHIP_POLARIS12:
2897 adev->mode_info.num_hpd = 5;
2898 adev->mode_info.num_dig = 5;
2899 break;
2900 default:
2901 /* FIXME: not supported yet */
2902 return -EINVAL;
2903 }
2904
2905 dce_v11_0_set_irq_funcs(adev);
2906
2907 return 0;
2908 }
2909
2910 static int dce_v11_0_sw_init(void *handle)
2911 {
2912 int r, i;
2913 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2914
2915 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2916 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2917 if (r)
2918 return r;
2919 }
2920
2921 for (i = 8; i < 20; i += 2) {
2922 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2923 if (r)
2924 return r;
2925 }
2926
2927 /* HPD hotplug */
2928 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2929 if (r)
2930 return r;
2931
2932 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2933
2934 adev->ddev->mode_config.async_page_flip = true;
2935
2936 adev->ddev->mode_config.max_width = 16384;
2937 adev->ddev->mode_config.max_height = 16384;
2938
2939 adev->ddev->mode_config.preferred_depth = 24;
2940 adev->ddev->mode_config.prefer_shadow = 1;
2941
2942 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2943
2944 r = amdgpu_modeset_create_props(adev);
2945 if (r)
2946 return r;
2947
2948 adev->ddev->mode_config.max_width = 16384;
2949 adev->ddev->mode_config.max_height = 16384;
2950
2951
2952 /* allocate crtcs */
2953 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2954 r = dce_v11_0_crtc_init(adev, i);
2955 if (r)
2956 return r;
2957 }
2958
2959 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2960 amdgpu_print_display_setup(adev->ddev);
2961 else
2962 return -EINVAL;
2963
2964 /* setup afmt */
2965 r = dce_v11_0_afmt_init(adev);
2966 if (r)
2967 return r;
2968
2969 r = dce_v11_0_audio_init(adev);
2970 if (r)
2971 return r;
2972
2973 drm_kms_helper_poll_init(adev->ddev);
2974
2975 adev->mode_info.mode_config_initialized = true;
2976 return 0;
2977 }
2978
2979 static int dce_v11_0_sw_fini(void *handle)
2980 {
2981 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2982
2983 kfree(adev->mode_info.bios_hardcoded_edid);
2984
2985 drm_kms_helper_poll_fini(adev->ddev);
2986
2987 dce_v11_0_audio_fini(adev);
2988
2989 dce_v11_0_afmt_fini(adev);
2990
2991 drm_mode_config_cleanup(adev->ddev);
2992 adev->mode_info.mode_config_initialized = false;
2993
2994 return 0;
2995 }
2996
2997 static int dce_v11_0_hw_init(void *handle)
2998 {
2999 int i;
3000 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3001
3002 dce_v11_0_init_golden_registers(adev);
3003
3004 /* disable vga render */
3005 dce_v11_0_set_vga_render_state(adev, false);
3006 /* init dig PHYs, disp eng pll */
3007 amdgpu_atombios_crtc_powergate_init(adev);
3008 amdgpu_atombios_encoder_init_dig(adev);
3009 if ((adev->asic_type == CHIP_POLARIS10) ||
3010 (adev->asic_type == CHIP_POLARIS11) ||
3011 (adev->asic_type == CHIP_POLARIS12)) {
3012 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
3013 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
3014 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
3015 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
3016 } else {
3017 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3018 }
3019
3020 /* initialize hpd */
3021 dce_v11_0_hpd_init(adev);
3022
3023 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3024 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3025 }
3026
3027 dce_v11_0_pageflip_interrupt_init(adev);
3028
3029 return 0;
3030 }
3031
3032 static int dce_v11_0_hw_fini(void *handle)
3033 {
3034 int i;
3035 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3036
3037 dce_v11_0_hpd_fini(adev);
3038
3039 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3040 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3041 }
3042
3043 dce_v11_0_pageflip_interrupt_fini(adev);
3044
3045 return 0;
3046 }
3047
3048 static int dce_v11_0_suspend(void *handle)
3049 {
3050 return dce_v11_0_hw_fini(handle);
3051 }
3052
3053 static int dce_v11_0_resume(void *handle)
3054 {
3055 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3056 int ret;
3057
3058 ret = dce_v11_0_hw_init(handle);
3059
3060 /* turn on the BL */
3061 if (adev->mode_info.bl_encoder) {
3062 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3063 adev->mode_info.bl_encoder);
3064 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3065 bl_level);
3066 }
3067
3068 return ret;
3069 }
3070
3071 static bool dce_v11_0_is_idle(void *handle)
3072 {
3073 return true;
3074 }
3075
3076 static int dce_v11_0_wait_for_idle(void *handle)
3077 {
3078 return 0;
3079 }
3080
3081 static int dce_v11_0_soft_reset(void *handle)
3082 {
3083 u32 srbm_soft_reset = 0, tmp;
3084 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3085
3086 if (dce_v11_0_is_display_hung(adev))
3087 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3088
3089 if (srbm_soft_reset) {
3090 tmp = RREG32(mmSRBM_SOFT_RESET);
3091 tmp |= srbm_soft_reset;
3092 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3093 WREG32(mmSRBM_SOFT_RESET, tmp);
3094 tmp = RREG32(mmSRBM_SOFT_RESET);
3095
3096 udelay(50);
3097
3098 tmp &= ~srbm_soft_reset;
3099 WREG32(mmSRBM_SOFT_RESET, tmp);
3100 tmp = RREG32(mmSRBM_SOFT_RESET);
3101
3102 /* Wait a little for things to settle down */
3103 udelay(50);
3104 }
3105 return 0;
3106 }
3107
3108 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3109 int crtc,
3110 enum amdgpu_interrupt_state state)
3111 {
3112 u32 lb_interrupt_mask;
3113
3114 if (crtc >= adev->mode_info.num_crtc) {
3115 DRM_DEBUG("invalid crtc %d\n", crtc);
3116 return;
3117 }
3118
3119 switch (state) {
3120 case AMDGPU_IRQ_STATE_DISABLE:
3121 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3122 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3123 VBLANK_INTERRUPT_MASK, 0);
3124 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3125 break;
3126 case AMDGPU_IRQ_STATE_ENABLE:
3127 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3128 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3129 VBLANK_INTERRUPT_MASK, 1);
3130 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3131 break;
3132 default:
3133 break;
3134 }
3135 }
3136
3137 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3138 int crtc,
3139 enum amdgpu_interrupt_state state)
3140 {
3141 u32 lb_interrupt_mask;
3142
3143 if (crtc >= adev->mode_info.num_crtc) {
3144 DRM_DEBUG("invalid crtc %d\n", crtc);
3145 return;
3146 }
3147
3148 switch (state) {
3149 case AMDGPU_IRQ_STATE_DISABLE:
3150 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3151 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3152 VLINE_INTERRUPT_MASK, 0);
3153 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3154 break;
3155 case AMDGPU_IRQ_STATE_ENABLE:
3156 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3157 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3158 VLINE_INTERRUPT_MASK, 1);
3159 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3160 break;
3161 default:
3162 break;
3163 }
3164 }
3165
3166 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3167 struct amdgpu_irq_src *source,
3168 unsigned hpd,
3169 enum amdgpu_interrupt_state state)
3170 {
3171 u32 tmp;
3172
3173 if (hpd >= adev->mode_info.num_hpd) {
3174 DRM_DEBUG("invalid hdp %d\n", hpd);
3175 return 0;
3176 }
3177
3178 switch (state) {
3179 case AMDGPU_IRQ_STATE_DISABLE:
3180 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3181 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3182 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3183 break;
3184 case AMDGPU_IRQ_STATE_ENABLE:
3185 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3186 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3187 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3188 break;
3189 default:
3190 break;
3191 }
3192
3193 return 0;
3194 }
3195
3196 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3197 struct amdgpu_irq_src *source,
3198 unsigned type,
3199 enum amdgpu_interrupt_state state)
3200 {
3201 switch (type) {
3202 case AMDGPU_CRTC_IRQ_VBLANK1:
3203 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3204 break;
3205 case AMDGPU_CRTC_IRQ_VBLANK2:
3206 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3207 break;
3208 case AMDGPU_CRTC_IRQ_VBLANK3:
3209 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3210 break;
3211 case AMDGPU_CRTC_IRQ_VBLANK4:
3212 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3213 break;
3214 case AMDGPU_CRTC_IRQ_VBLANK5:
3215 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3216 break;
3217 case AMDGPU_CRTC_IRQ_VBLANK6:
3218 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3219 break;
3220 case AMDGPU_CRTC_IRQ_VLINE1:
3221 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3222 break;
3223 case AMDGPU_CRTC_IRQ_VLINE2:
3224 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3225 break;
3226 case AMDGPU_CRTC_IRQ_VLINE3:
3227 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3228 break;
3229 case AMDGPU_CRTC_IRQ_VLINE4:
3230 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3231 break;
3232 case AMDGPU_CRTC_IRQ_VLINE5:
3233 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3234 break;
3235 case AMDGPU_CRTC_IRQ_VLINE6:
3236 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3237 break;
3238 default:
3239 break;
3240 }
3241 return 0;
3242 }
3243
3244 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3245 struct amdgpu_irq_src *src,
3246 unsigned type,
3247 enum amdgpu_interrupt_state state)
3248 {
3249 u32 reg;
3250
3251 if (type >= adev->mode_info.num_crtc) {
3252 DRM_ERROR("invalid pageflip crtc %d\n", type);
3253 return -EINVAL;
3254 }
3255
3256 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3257 if (state == AMDGPU_IRQ_STATE_DISABLE)
3258 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3259 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3260 else
3261 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3262 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3263
3264 return 0;
3265 }
3266
3267 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3268 struct amdgpu_irq_src *source,
3269 struct amdgpu_iv_entry *entry)
3270 {
3271 unsigned long flags;
3272 unsigned crtc_id;
3273 struct amdgpu_crtc *amdgpu_crtc;
3274 struct amdgpu_flip_work *works;
3275
3276 crtc_id = (entry->src_id - 8) >> 1;
3277 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3278
3279 if (crtc_id >= adev->mode_info.num_crtc) {
3280 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3281 return -EINVAL;
3282 }
3283
3284 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3285 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3286 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3287 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3288
3289 /* IRQ could occur when in initial stage */
3290 if(amdgpu_crtc == NULL)
3291 return 0;
3292
3293 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3294 works = amdgpu_crtc->pflip_works;
3295 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3296 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3297 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3298 amdgpu_crtc->pflip_status,
3299 AMDGPU_FLIP_SUBMITTED);
3300 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3301 return 0;
3302 }
3303
3304 /* page flip completed. clean up */
3305 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3306 amdgpu_crtc->pflip_works = NULL;
3307
3308 /* wakeup usersapce */
3309 if(works->event)
3310 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3311
3312 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3313
3314 drm_crtc_vblank_put(&amdgpu_crtc->base);
3315 schedule_work(&works->unpin_work);
3316
3317 return 0;
3318 }
3319
3320 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3321 int hpd)
3322 {
3323 u32 tmp;
3324
3325 if (hpd >= adev->mode_info.num_hpd) {
3326 DRM_DEBUG("invalid hdp %d\n", hpd);
3327 return;
3328 }
3329
3330 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3331 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3332 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3333 }
3334
3335 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3336 int crtc)
3337 {
3338 u32 tmp;
3339
3340 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3341 DRM_DEBUG("invalid crtc %d\n", crtc);
3342 return;
3343 }
3344
3345 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3346 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3347 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3348 }
3349
3350 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3351 int crtc)
3352 {
3353 u32 tmp;
3354
3355 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3356 DRM_DEBUG("invalid crtc %d\n", crtc);
3357 return;
3358 }
3359
3360 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3361 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3362 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3363 }
3364
3365 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3366 struct amdgpu_irq_src *source,
3367 struct amdgpu_iv_entry *entry)
3368 {
3369 unsigned crtc = entry->src_id - 1;
3370 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3371 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3372
3373 switch (entry->src_data[0]) {
3374 case 0: /* vblank */
3375 if (disp_int & interrupt_status_offsets[crtc].vblank)
3376 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3377 else
3378 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3379
3380 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3381 drm_handle_vblank(adev->ddev, crtc);
3382 }
3383 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3384
3385 break;
3386 case 1: /* vline */
3387 if (disp_int & interrupt_status_offsets[crtc].vline)
3388 dce_v11_0_crtc_vline_int_ack(adev, crtc);
3389 else
3390 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3391
3392 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3393
3394 break;
3395 default:
3396 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3397 break;
3398 }
3399
3400 return 0;
3401 }
3402
3403 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3404 struct amdgpu_irq_src *source,
3405 struct amdgpu_iv_entry *entry)
3406 {
3407 uint32_t disp_int, mask;
3408 unsigned hpd;
3409
3410 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3411 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3412 return 0;
3413 }
3414
3415 hpd = entry->src_data[0];
3416 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3417 mask = interrupt_status_offsets[hpd].hpd;
3418
3419 if (disp_int & mask) {
3420 dce_v11_0_hpd_int_ack(adev, hpd);
3421 schedule_work(&adev->hotplug_work);
3422 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3423 }
3424
3425 return 0;
3426 }
3427
3428 static int dce_v11_0_set_clockgating_state(void *handle,
3429 enum amd_clockgating_state state)
3430 {
3431 return 0;
3432 }
3433
3434 static int dce_v11_0_set_powergating_state(void *handle,
3435 enum amd_powergating_state state)
3436 {
3437 return 0;
3438 }
3439
3440 static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3441 .name = "dce_v11_0",
3442 .early_init = dce_v11_0_early_init,
3443 .late_init = NULL,
3444 .sw_init = dce_v11_0_sw_init,
3445 .sw_fini = dce_v11_0_sw_fini,
3446 .hw_init = dce_v11_0_hw_init,
3447 .hw_fini = dce_v11_0_hw_fini,
3448 .suspend = dce_v11_0_suspend,
3449 .resume = dce_v11_0_resume,
3450 .is_idle = dce_v11_0_is_idle,
3451 .wait_for_idle = dce_v11_0_wait_for_idle,
3452 .soft_reset = dce_v11_0_soft_reset,
3453 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3454 .set_powergating_state = dce_v11_0_set_powergating_state,
3455 };
3456
3457 static void
3458 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3459 struct drm_display_mode *mode,
3460 struct drm_display_mode *adjusted_mode)
3461 {
3462 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3463
3464 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3465
3466 /* need to call this here rather than in prepare() since we need some crtc info */
3467 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3468
3469 /* set scaler clears this on some chips */
3470 dce_v11_0_set_interleave(encoder->crtc, mode);
3471
3472 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3473 dce_v11_0_afmt_enable(encoder, true);
3474 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3475 }
3476 }
3477
3478 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3479 {
3480 struct amdgpu_device *adev = encoder->dev->dev_private;
3481 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3482 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3483
3484 if ((amdgpu_encoder->active_device &
3485 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3486 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3487 ENCODER_OBJECT_ID_NONE)) {
3488 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3489 if (dig) {
3490 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3491 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3492 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3493 }
3494 }
3495
3496 amdgpu_atombios_scratch_regs_lock(adev, true);
3497
3498 if (connector) {
3499 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3500
3501 /* select the clock/data port if it uses a router */
3502 if (amdgpu_connector->router.cd_valid)
3503 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3504
3505 /* turn eDP panel on for mode set */
3506 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3507 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3508 ATOM_TRANSMITTER_ACTION_POWER_ON);
3509 }
3510
3511 /* this is needed for the pll/ss setup to work correctly in some cases */
3512 amdgpu_atombios_encoder_set_crtc_source(encoder);
3513 /* set up the FMT blocks */
3514 dce_v11_0_program_fmt(encoder);
3515 }
3516
3517 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3518 {
3519 struct drm_device *dev = encoder->dev;
3520 struct amdgpu_device *adev = dev->dev_private;
3521
3522 /* need to call this here as we need the crtc set up */
3523 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3524 amdgpu_atombios_scratch_regs_lock(adev, false);
3525 }
3526
3527 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3528 {
3529 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3530 struct amdgpu_encoder_atom_dig *dig;
3531
3532 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3533
3534 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3535 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3536 dce_v11_0_afmt_enable(encoder, false);
3537 dig = amdgpu_encoder->enc_priv;
3538 dig->dig_encoder = -1;
3539 }
3540 amdgpu_encoder->active_device = 0;
3541 }
3542
3543 /* these are handled by the primary encoders */
3544 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3545 {
3546
3547 }
3548
3549 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3550 {
3551
3552 }
3553
3554 static void
3555 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3556 struct drm_display_mode *mode,
3557 struct drm_display_mode *adjusted_mode)
3558 {
3559
3560 }
3561
3562 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3563 {
3564
3565 }
3566
3567 static void
3568 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3569 {
3570
3571 }
3572
3573 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3574 .dpms = dce_v11_0_ext_dpms,
3575 .prepare = dce_v11_0_ext_prepare,
3576 .mode_set = dce_v11_0_ext_mode_set,
3577 .commit = dce_v11_0_ext_commit,
3578 .disable = dce_v11_0_ext_disable,
3579 /* no detect for TMDS/LVDS yet */
3580 };
3581
3582 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3583 .dpms = amdgpu_atombios_encoder_dpms,
3584 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3585 .prepare = dce_v11_0_encoder_prepare,
3586 .mode_set = dce_v11_0_encoder_mode_set,
3587 .commit = dce_v11_0_encoder_commit,
3588 .disable = dce_v11_0_encoder_disable,
3589 .detect = amdgpu_atombios_encoder_dig_detect,
3590 };
3591
3592 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3593 .dpms = amdgpu_atombios_encoder_dpms,
3594 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3595 .prepare = dce_v11_0_encoder_prepare,
3596 .mode_set = dce_v11_0_encoder_mode_set,
3597 .commit = dce_v11_0_encoder_commit,
3598 .detect = amdgpu_atombios_encoder_dac_detect,
3599 };
3600
3601 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3602 {
3603 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3604 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3605 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3606 kfree(amdgpu_encoder->enc_priv);
3607 drm_encoder_cleanup(encoder);
3608 kfree(amdgpu_encoder);
3609 }
3610
3611 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3612 .destroy = dce_v11_0_encoder_destroy,
3613 };
3614
3615 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3616 uint32_t encoder_enum,
3617 uint32_t supported_device,
3618 u16 caps)
3619 {
3620 struct drm_device *dev = adev->ddev;
3621 struct drm_encoder *encoder;
3622 struct amdgpu_encoder *amdgpu_encoder;
3623
3624 /* see if we already added it */
3625 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3626 amdgpu_encoder = to_amdgpu_encoder(encoder);
3627 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3628 amdgpu_encoder->devices |= supported_device;
3629 return;
3630 }
3631
3632 }
3633
3634 /* add a new one */
3635 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3636 if (!amdgpu_encoder)
3637 return;
3638
3639 encoder = &amdgpu_encoder->base;
3640 switch (adev->mode_info.num_crtc) {
3641 case 1:
3642 encoder->possible_crtcs = 0x1;
3643 break;
3644 case 2:
3645 default:
3646 encoder->possible_crtcs = 0x3;
3647 break;
3648 case 3:
3649 encoder->possible_crtcs = 0x7;
3650 break;
3651 case 4:
3652 encoder->possible_crtcs = 0xf;
3653 break;
3654 case 5:
3655 encoder->possible_crtcs = 0x1f;
3656 break;
3657 case 6:
3658 encoder->possible_crtcs = 0x3f;
3659 break;
3660 }
3661
3662 amdgpu_encoder->enc_priv = NULL;
3663
3664 amdgpu_encoder->encoder_enum = encoder_enum;
3665 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3666 amdgpu_encoder->devices = supported_device;
3667 amdgpu_encoder->rmx_type = RMX_OFF;
3668 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3669 amdgpu_encoder->is_ext_encoder = false;
3670 amdgpu_encoder->caps = caps;
3671
3672 switch (amdgpu_encoder->encoder_id) {
3673 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3674 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3675 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3676 DRM_MODE_ENCODER_DAC, NULL);
3677 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3678 break;
3679 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3680 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3681 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3682 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3683 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3684 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3685 amdgpu_encoder->rmx_type = RMX_FULL;
3686 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3687 DRM_MODE_ENCODER_LVDS, NULL);
3688 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3689 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3690 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3691 DRM_MODE_ENCODER_DAC, NULL);
3692 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3693 } else {
3694 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3695 DRM_MODE_ENCODER_TMDS, NULL);
3696 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3697 }
3698 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3699 break;
3700 case ENCODER_OBJECT_ID_SI170B:
3701 case ENCODER_OBJECT_ID_CH7303:
3702 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3703 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3704 case ENCODER_OBJECT_ID_TITFP513:
3705 case ENCODER_OBJECT_ID_VT1623:
3706 case ENCODER_OBJECT_ID_HDMI_SI1930:
3707 case ENCODER_OBJECT_ID_TRAVIS:
3708 case ENCODER_OBJECT_ID_NUTMEG:
3709 /* these are handled by the primary encoders */
3710 amdgpu_encoder->is_ext_encoder = true;
3711 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3712 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3713 DRM_MODE_ENCODER_LVDS, NULL);
3714 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3715 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3716 DRM_MODE_ENCODER_DAC, NULL);
3717 else
3718 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3719 DRM_MODE_ENCODER_TMDS, NULL);
3720 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3721 break;
3722 }
3723 }
3724
3725 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3726 .bandwidth_update = &dce_v11_0_bandwidth_update,
3727 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3728 .vblank_wait = &dce_v11_0_vblank_wait,
3729 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3730 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3731 .hpd_sense = &dce_v11_0_hpd_sense,
3732 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3733 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3734 .page_flip = &dce_v11_0_page_flip,
3735 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3736 .add_encoder = &dce_v11_0_encoder_add,
3737 .add_connector = &amdgpu_connector_add,
3738 };
3739
3740 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3741 {
3742 if (adev->mode_info.funcs == NULL)
3743 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3744 }
3745
3746 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3747 .set = dce_v11_0_set_crtc_irq_state,
3748 .process = dce_v11_0_crtc_irq,
3749 };
3750
3751 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3752 .set = dce_v11_0_set_pageflip_irq_state,
3753 .process = dce_v11_0_pageflip_irq,
3754 };
3755
3756 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3757 .set = dce_v11_0_set_hpd_irq_state,
3758 .process = dce_v11_0_hpd_irq,
3759 };
3760
3761 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3762 {
3763 if (adev->mode_info.num_crtc > 0)
3764 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3765 else
3766 adev->crtc_irq.num_types = 0;
3767 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3768
3769 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3770 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3771
3772 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3773 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3774 }
3775
3776 const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3777 {
3778 .type = AMD_IP_BLOCK_TYPE_DCE,
3779 .major = 11,
3780 .minor = 0,
3781 .rev = 0,
3782 .funcs = &dce_v11_0_ip_funcs,
3783 };
3784
3785 const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3786 {
3787 .type = AMD_IP_BLOCK_TYPE_DCE,
3788 .major = 11,
3789 .minor = 2,
3790 .rev = 0,
3791 .funcs = &dce_v11_0_ip_funcs,
3792 };
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