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drm/amdgpu: add amdgpu_vm_entries_mask v2
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / dce_v11_0.c
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <drm/drmP.h>
24 #include "amdgpu.h"
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
27 #include "vid.h"
28 #include "atom.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
34 #include "amdgpu_display.h"
35 #include "dce_v11_0.h"
36
37 #include "dce/dce_11_0_d.h"
38 #include "dce/dce_11_0_sh_mask.h"
39 #include "dce/dce_11_0_enum.h"
40 #include "oss/oss_3_0_d.h"
41 #include "oss/oss_3_0_sh_mask.h"
42 #include "gmc/gmc_8_1_d.h"
43 #include "gmc/gmc_8_1_sh_mask.h"
44
45 #include "ivsrcid/ivsrcid_vislands30.h"
46
47 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
48 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
49
50 static const u32 crtc_offsets[] =
51 {
52 CRTC0_REGISTER_OFFSET,
53 CRTC1_REGISTER_OFFSET,
54 CRTC2_REGISTER_OFFSET,
55 CRTC3_REGISTER_OFFSET,
56 CRTC4_REGISTER_OFFSET,
57 CRTC5_REGISTER_OFFSET,
58 CRTC6_REGISTER_OFFSET
59 };
60
61 static const u32 hpd_offsets[] =
62 {
63 HPD0_REGISTER_OFFSET,
64 HPD1_REGISTER_OFFSET,
65 HPD2_REGISTER_OFFSET,
66 HPD3_REGISTER_OFFSET,
67 HPD4_REGISTER_OFFSET,
68 HPD5_REGISTER_OFFSET
69 };
70
71 static const uint32_t dig_offsets[] = {
72 DIG0_REGISTER_OFFSET,
73 DIG1_REGISTER_OFFSET,
74 DIG2_REGISTER_OFFSET,
75 DIG3_REGISTER_OFFSET,
76 DIG4_REGISTER_OFFSET,
77 DIG5_REGISTER_OFFSET,
78 DIG6_REGISTER_OFFSET,
79 DIG7_REGISTER_OFFSET,
80 DIG8_REGISTER_OFFSET
81 };
82
83 static const struct {
84 uint32_t reg;
85 uint32_t vblank;
86 uint32_t vline;
87 uint32_t hpd;
88
89 } interrupt_status_offsets[] = { {
90 .reg = mmDISP_INTERRUPT_STATUS,
91 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
92 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
93 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
94 }, {
95 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
96 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
97 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
98 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
99 }, {
100 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
101 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
102 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
103 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
104 }, {
105 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
106 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
107 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
108 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
109 }, {
110 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
111 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
112 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
113 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
114 }, {
115 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
116 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
117 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
118 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
119 } };
120
121 static const u32 cz_golden_settings_a11[] =
122 {
123 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
124 mmFBC_MISC, 0x1f311fff, 0x14300000,
125 };
126
127 static const u32 cz_mgcg_cgcg_init[] =
128 {
129 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
130 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
131 };
132
133 static const u32 stoney_golden_settings_a11[] =
134 {
135 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
136 mmFBC_MISC, 0x1f311fff, 0x14302000,
137 };
138
139 static const u32 polaris11_golden_settings_a11[] =
140 {
141 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
142 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
143 mmFBC_DEBUG1, 0xffffffff, 0x00000008,
144 mmFBC_MISC, 0x9f313fff, 0x14302008,
145 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
146 };
147
148 static const u32 polaris10_golden_settings_a11[] =
149 {
150 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
151 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
152 mmFBC_MISC, 0x9f313fff, 0x14302008,
153 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
154 };
155
156 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
157 {
158 switch (adev->asic_type) {
159 case CHIP_CARRIZO:
160 amdgpu_device_program_register_sequence(adev,
161 cz_mgcg_cgcg_init,
162 ARRAY_SIZE(cz_mgcg_cgcg_init));
163 amdgpu_device_program_register_sequence(adev,
164 cz_golden_settings_a11,
165 ARRAY_SIZE(cz_golden_settings_a11));
166 break;
167 case CHIP_STONEY:
168 amdgpu_device_program_register_sequence(adev,
169 stoney_golden_settings_a11,
170 ARRAY_SIZE(stoney_golden_settings_a11));
171 break;
172 case CHIP_POLARIS11:
173 case CHIP_POLARIS12:
174 amdgpu_device_program_register_sequence(adev,
175 polaris11_golden_settings_a11,
176 ARRAY_SIZE(polaris11_golden_settings_a11));
177 break;
178 case CHIP_POLARIS10:
179 case CHIP_VEGAM:
180 amdgpu_device_program_register_sequence(adev,
181 polaris10_golden_settings_a11,
182 ARRAY_SIZE(polaris10_golden_settings_a11));
183 break;
184 default:
185 break;
186 }
187 }
188
189 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
190 u32 block_offset, u32 reg)
191 {
192 unsigned long flags;
193 u32 r;
194
195 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
196 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
197 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
198 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
199
200 return r;
201 }
202
203 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
204 u32 block_offset, u32 reg, u32 v)
205 {
206 unsigned long flags;
207
208 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
209 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
210 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
211 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
212 }
213
214 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
215 {
216 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
217 return 0;
218 else
219 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
220 }
221
222 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
223 {
224 unsigned i;
225
226 /* Enable pflip interrupts */
227 for (i = 0; i < adev->mode_info.num_crtc; i++)
228 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
229 }
230
231 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
232 {
233 unsigned i;
234
235 /* Disable pflip interrupts */
236 for (i = 0; i < adev->mode_info.num_crtc; i++)
237 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
238 }
239
240 /**
241 * dce_v11_0_page_flip - pageflip callback.
242 *
243 * @adev: amdgpu_device pointer
244 * @crtc_id: crtc to cleanup pageflip on
245 * @crtc_base: new address of the crtc (GPU MC address)
246 *
247 * Triggers the actual pageflip by updating the primary
248 * surface base address.
249 */
250 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
251 int crtc_id, u64 crtc_base, bool async)
252 {
253 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
254 u32 tmp;
255
256 /* flip immediate for async, default is vsync */
257 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
258 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
259 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
260 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
261 /* update the scanout addresses */
262 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
263 upper_32_bits(crtc_base));
264 /* writing to the low address triggers the update */
265 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
266 lower_32_bits(crtc_base));
267 /* post the write */
268 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
269 }
270
271 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
272 u32 *vbl, u32 *position)
273 {
274 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
275 return -EINVAL;
276
277 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
278 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
279
280 return 0;
281 }
282
283 /**
284 * dce_v11_0_hpd_sense - hpd sense callback.
285 *
286 * @adev: amdgpu_device pointer
287 * @hpd: hpd (hotplug detect) pin
288 *
289 * Checks if a digital monitor is connected (evergreen+).
290 * Returns true if connected, false if not connected.
291 */
292 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
293 enum amdgpu_hpd_id hpd)
294 {
295 bool connected = false;
296
297 if (hpd >= adev->mode_info.num_hpd)
298 return connected;
299
300 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
301 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
302 connected = true;
303
304 return connected;
305 }
306
307 /**
308 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
309 *
310 * @adev: amdgpu_device pointer
311 * @hpd: hpd (hotplug detect) pin
312 *
313 * Set the polarity of the hpd pin (evergreen+).
314 */
315 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
316 enum amdgpu_hpd_id hpd)
317 {
318 u32 tmp;
319 bool connected = dce_v11_0_hpd_sense(adev, hpd);
320
321 if (hpd >= adev->mode_info.num_hpd)
322 return;
323
324 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
325 if (connected)
326 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
327 else
328 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
329 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
330 }
331
332 /**
333 * dce_v11_0_hpd_init - hpd setup callback.
334 *
335 * @adev: amdgpu_device pointer
336 *
337 * Setup the hpd pins used by the card (evergreen+).
338 * Enable the pin, set the polarity, and enable the hpd interrupts.
339 */
340 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
341 {
342 struct drm_device *dev = adev->ddev;
343 struct drm_connector *connector;
344 u32 tmp;
345
346 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
347 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
348
349 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
350 continue;
351
352 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
353 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
354 /* don't try to enable hpd on eDP or LVDS avoid breaking the
355 * aux dp channel on imac and help (but not completely fix)
356 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
357 * also avoid interrupt storms during dpms.
358 */
359 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
360 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
361 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
362 continue;
363 }
364
365 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
366 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
367 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
368
369 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
370 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
371 DC_HPD_CONNECT_INT_DELAY,
372 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
373 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
374 DC_HPD_DISCONNECT_INT_DELAY,
375 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
376 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
377
378 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
379 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
380 }
381 }
382
383 /**
384 * dce_v11_0_hpd_fini - hpd tear down callback.
385 *
386 * @adev: amdgpu_device pointer
387 *
388 * Tear down the hpd pins used by the card (evergreen+).
389 * Disable the hpd interrupts.
390 */
391 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
392 {
393 struct drm_device *dev = adev->ddev;
394 struct drm_connector *connector;
395 u32 tmp;
396
397 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
398 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
399
400 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
401 continue;
402
403 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
404 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
405 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
406
407 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
408 }
409 }
410
411 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
412 {
413 return mmDC_GPIO_HPD_A;
414 }
415
416 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
417 {
418 u32 crtc_hung = 0;
419 u32 crtc_status[6];
420 u32 i, j, tmp;
421
422 for (i = 0; i < adev->mode_info.num_crtc; i++) {
423 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
424 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
425 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
426 crtc_hung |= (1 << i);
427 }
428 }
429
430 for (j = 0; j < 10; j++) {
431 for (i = 0; i < adev->mode_info.num_crtc; i++) {
432 if (crtc_hung & (1 << i)) {
433 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
434 if (tmp != crtc_status[i])
435 crtc_hung &= ~(1 << i);
436 }
437 }
438 if (crtc_hung == 0)
439 return false;
440 udelay(100);
441 }
442
443 return true;
444 }
445
446 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
447 bool render)
448 {
449 u32 tmp;
450
451 /* Lockout access through VGA aperture*/
452 tmp = RREG32(mmVGA_HDP_CONTROL);
453 if (render)
454 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
455 else
456 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
457 WREG32(mmVGA_HDP_CONTROL, tmp);
458
459 /* disable VGA render */
460 tmp = RREG32(mmVGA_RENDER_CONTROL);
461 if (render)
462 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
463 else
464 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
465 WREG32(mmVGA_RENDER_CONTROL, tmp);
466 }
467
468 static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
469 {
470 int num_crtc = 0;
471
472 switch (adev->asic_type) {
473 case CHIP_CARRIZO:
474 num_crtc = 3;
475 break;
476 case CHIP_STONEY:
477 num_crtc = 2;
478 break;
479 case CHIP_POLARIS10:
480 case CHIP_VEGAM:
481 num_crtc = 6;
482 break;
483 case CHIP_POLARIS11:
484 case CHIP_POLARIS12:
485 num_crtc = 5;
486 break;
487 default:
488 num_crtc = 0;
489 }
490 return num_crtc;
491 }
492
493 void dce_v11_0_disable_dce(struct amdgpu_device *adev)
494 {
495 /*Disable VGA render and enabled crtc, if has DCE engine*/
496 if (amdgpu_atombios_has_dce_engine_info(adev)) {
497 u32 tmp;
498 int crtc_enabled, i;
499
500 dce_v11_0_set_vga_render_state(adev, false);
501
502 /*Disable crtc*/
503 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
504 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
505 CRTC_CONTROL, CRTC_MASTER_EN);
506 if (crtc_enabled) {
507 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
508 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
509 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
510 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
511 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
512 }
513 }
514 }
515 }
516
517 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
518 {
519 struct drm_device *dev = encoder->dev;
520 struct amdgpu_device *adev = dev->dev_private;
521 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
522 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
523 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
524 int bpc = 0;
525 u32 tmp = 0;
526 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
527
528 if (connector) {
529 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
530 bpc = amdgpu_connector_get_monitor_bpc(connector);
531 dither = amdgpu_connector->dither;
532 }
533
534 /* LVDS/eDP FMT is set up by atom */
535 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
536 return;
537
538 /* not needed for analog */
539 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
540 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
541 return;
542
543 if (bpc == 0)
544 return;
545
546 switch (bpc) {
547 case 6:
548 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
549 /* XXX sort out optimal dither settings */
550 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
551 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
552 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
553 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
554 } else {
555 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
556 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
557 }
558 break;
559 case 8:
560 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
561 /* XXX sort out optimal dither settings */
562 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
563 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
564 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
565 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
566 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
567 } else {
568 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
570 }
571 break;
572 case 10:
573 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
574 /* XXX sort out optimal dither settings */
575 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
576 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
577 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
578 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
579 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
580 } else {
581 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
582 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
583 }
584 break;
585 default:
586 /* not needed */
587 break;
588 }
589
590 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
591 }
592
593
594 /* display watermark setup */
595 /**
596 * dce_v11_0_line_buffer_adjust - Set up the line buffer
597 *
598 * @adev: amdgpu_device pointer
599 * @amdgpu_crtc: the selected display controller
600 * @mode: the current display mode on the selected display
601 * controller
602 *
603 * Setup up the line buffer allocation for
604 * the selected display controller (CIK).
605 * Returns the line buffer size in pixels.
606 */
607 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
608 struct amdgpu_crtc *amdgpu_crtc,
609 struct drm_display_mode *mode)
610 {
611 u32 tmp, buffer_alloc, i, mem_cfg;
612 u32 pipe_offset = amdgpu_crtc->crtc_id;
613 /*
614 * Line Buffer Setup
615 * There are 6 line buffers, one for each display controllers.
616 * There are 3 partitions per LB. Select the number of partitions
617 * to enable based on the display width. For display widths larger
618 * than 4096, you need use to use 2 display controllers and combine
619 * them using the stereo blender.
620 */
621 if (amdgpu_crtc->base.enabled && mode) {
622 if (mode->crtc_hdisplay < 1920) {
623 mem_cfg = 1;
624 buffer_alloc = 2;
625 } else if (mode->crtc_hdisplay < 2560) {
626 mem_cfg = 2;
627 buffer_alloc = 2;
628 } else if (mode->crtc_hdisplay < 4096) {
629 mem_cfg = 0;
630 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
631 } else {
632 DRM_DEBUG_KMS("Mode too big for LB!\n");
633 mem_cfg = 0;
634 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
635 }
636 } else {
637 mem_cfg = 1;
638 buffer_alloc = 0;
639 }
640
641 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
642 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
643 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
644
645 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
646 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
647 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
648
649 for (i = 0; i < adev->usec_timeout; i++) {
650 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
651 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
652 break;
653 udelay(1);
654 }
655
656 if (amdgpu_crtc->base.enabled && mode) {
657 switch (mem_cfg) {
658 case 0:
659 default:
660 return 4096 * 2;
661 case 1:
662 return 1920 * 2;
663 case 2:
664 return 2560 * 2;
665 }
666 }
667
668 /* controller not enabled, so no lb used */
669 return 0;
670 }
671
672 /**
673 * cik_get_number_of_dram_channels - get the number of dram channels
674 *
675 * @adev: amdgpu_device pointer
676 *
677 * Look up the number of video ram channels (CIK).
678 * Used for display watermark bandwidth calculations
679 * Returns the number of dram channels
680 */
681 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
682 {
683 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
684
685 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
686 case 0:
687 default:
688 return 1;
689 case 1:
690 return 2;
691 case 2:
692 return 4;
693 case 3:
694 return 8;
695 case 4:
696 return 3;
697 case 5:
698 return 6;
699 case 6:
700 return 10;
701 case 7:
702 return 12;
703 case 8:
704 return 16;
705 }
706 }
707
708 struct dce10_wm_params {
709 u32 dram_channels; /* number of dram channels */
710 u32 yclk; /* bandwidth per dram data pin in kHz */
711 u32 sclk; /* engine clock in kHz */
712 u32 disp_clk; /* display clock in kHz */
713 u32 src_width; /* viewport width */
714 u32 active_time; /* active display time in ns */
715 u32 blank_time; /* blank time in ns */
716 bool interlaced; /* mode is interlaced */
717 fixed20_12 vsc; /* vertical scale ratio */
718 u32 num_heads; /* number of active crtcs */
719 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
720 u32 lb_size; /* line buffer allocated to pipe */
721 u32 vtaps; /* vertical scaler taps */
722 };
723
724 /**
725 * dce_v11_0_dram_bandwidth - get the dram bandwidth
726 *
727 * @wm: watermark calculation data
728 *
729 * Calculate the raw dram bandwidth (CIK).
730 * Used for display watermark bandwidth calculations
731 * Returns the dram bandwidth in MBytes/s
732 */
733 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
734 {
735 /* Calculate raw DRAM Bandwidth */
736 fixed20_12 dram_efficiency; /* 0.7 */
737 fixed20_12 yclk, dram_channels, bandwidth;
738 fixed20_12 a;
739
740 a.full = dfixed_const(1000);
741 yclk.full = dfixed_const(wm->yclk);
742 yclk.full = dfixed_div(yclk, a);
743 dram_channels.full = dfixed_const(wm->dram_channels * 4);
744 a.full = dfixed_const(10);
745 dram_efficiency.full = dfixed_const(7);
746 dram_efficiency.full = dfixed_div(dram_efficiency, a);
747 bandwidth.full = dfixed_mul(dram_channels, yclk);
748 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
749
750 return dfixed_trunc(bandwidth);
751 }
752
753 /**
754 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
755 *
756 * @wm: watermark calculation data
757 *
758 * Calculate the dram bandwidth used for display (CIK).
759 * Used for display watermark bandwidth calculations
760 * Returns the dram bandwidth for display in MBytes/s
761 */
762 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
763 {
764 /* Calculate DRAM Bandwidth and the part allocated to display. */
765 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
766 fixed20_12 yclk, dram_channels, bandwidth;
767 fixed20_12 a;
768
769 a.full = dfixed_const(1000);
770 yclk.full = dfixed_const(wm->yclk);
771 yclk.full = dfixed_div(yclk, a);
772 dram_channels.full = dfixed_const(wm->dram_channels * 4);
773 a.full = dfixed_const(10);
774 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
775 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
776 bandwidth.full = dfixed_mul(dram_channels, yclk);
777 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
778
779 return dfixed_trunc(bandwidth);
780 }
781
782 /**
783 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
784 *
785 * @wm: watermark calculation data
786 *
787 * Calculate the data return bandwidth used for display (CIK).
788 * Used for display watermark bandwidth calculations
789 * Returns the data return bandwidth in MBytes/s
790 */
791 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
792 {
793 /* Calculate the display Data return Bandwidth */
794 fixed20_12 return_efficiency; /* 0.8 */
795 fixed20_12 sclk, bandwidth;
796 fixed20_12 a;
797
798 a.full = dfixed_const(1000);
799 sclk.full = dfixed_const(wm->sclk);
800 sclk.full = dfixed_div(sclk, a);
801 a.full = dfixed_const(10);
802 return_efficiency.full = dfixed_const(8);
803 return_efficiency.full = dfixed_div(return_efficiency, a);
804 a.full = dfixed_const(32);
805 bandwidth.full = dfixed_mul(a, sclk);
806 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
807
808 return dfixed_trunc(bandwidth);
809 }
810
811 /**
812 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
813 *
814 * @wm: watermark calculation data
815 *
816 * Calculate the dmif bandwidth used for display (CIK).
817 * Used for display watermark bandwidth calculations
818 * Returns the dmif bandwidth in MBytes/s
819 */
820 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
821 {
822 /* Calculate the DMIF Request Bandwidth */
823 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
824 fixed20_12 disp_clk, bandwidth;
825 fixed20_12 a, b;
826
827 a.full = dfixed_const(1000);
828 disp_clk.full = dfixed_const(wm->disp_clk);
829 disp_clk.full = dfixed_div(disp_clk, a);
830 a.full = dfixed_const(32);
831 b.full = dfixed_mul(a, disp_clk);
832
833 a.full = dfixed_const(10);
834 disp_clk_request_efficiency.full = dfixed_const(8);
835 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
836
837 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
838
839 return dfixed_trunc(bandwidth);
840 }
841
842 /**
843 * dce_v11_0_available_bandwidth - get the min available bandwidth
844 *
845 * @wm: watermark calculation data
846 *
847 * Calculate the min available bandwidth used for display (CIK).
848 * Used for display watermark bandwidth calculations
849 * Returns the min available bandwidth in MBytes/s
850 */
851 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
852 {
853 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
854 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
855 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
856 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
857
858 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
859 }
860
861 /**
862 * dce_v11_0_average_bandwidth - get the average available bandwidth
863 *
864 * @wm: watermark calculation data
865 *
866 * Calculate the average available bandwidth used for display (CIK).
867 * Used for display watermark bandwidth calculations
868 * Returns the average available bandwidth in MBytes/s
869 */
870 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
871 {
872 /* Calculate the display mode Average Bandwidth
873 * DisplayMode should contain the source and destination dimensions,
874 * timing, etc.
875 */
876 fixed20_12 bpp;
877 fixed20_12 line_time;
878 fixed20_12 src_width;
879 fixed20_12 bandwidth;
880 fixed20_12 a;
881
882 a.full = dfixed_const(1000);
883 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
884 line_time.full = dfixed_div(line_time, a);
885 bpp.full = dfixed_const(wm->bytes_per_pixel);
886 src_width.full = dfixed_const(wm->src_width);
887 bandwidth.full = dfixed_mul(src_width, bpp);
888 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
889 bandwidth.full = dfixed_div(bandwidth, line_time);
890
891 return dfixed_trunc(bandwidth);
892 }
893
894 /**
895 * dce_v11_0_latency_watermark - get the latency watermark
896 *
897 * @wm: watermark calculation data
898 *
899 * Calculate the latency watermark (CIK).
900 * Used for display watermark bandwidth calculations
901 * Returns the latency watermark in ns
902 */
903 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
904 {
905 /* First calculate the latency in ns */
906 u32 mc_latency = 2000; /* 2000 ns. */
907 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
908 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
909 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
910 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
911 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
912 (wm->num_heads * cursor_line_pair_return_time);
913 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
914 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
915 u32 tmp, dmif_size = 12288;
916 fixed20_12 a, b, c;
917
918 if (wm->num_heads == 0)
919 return 0;
920
921 a.full = dfixed_const(2);
922 b.full = dfixed_const(1);
923 if ((wm->vsc.full > a.full) ||
924 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
925 (wm->vtaps >= 5) ||
926 ((wm->vsc.full >= a.full) && wm->interlaced))
927 max_src_lines_per_dst_line = 4;
928 else
929 max_src_lines_per_dst_line = 2;
930
931 a.full = dfixed_const(available_bandwidth);
932 b.full = dfixed_const(wm->num_heads);
933 a.full = dfixed_div(a, b);
934 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
935 tmp = min(dfixed_trunc(a), tmp);
936
937 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
938
939 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
940 b.full = dfixed_const(1000);
941 c.full = dfixed_const(lb_fill_bw);
942 b.full = dfixed_div(c, b);
943 a.full = dfixed_div(a, b);
944 line_fill_time = dfixed_trunc(a);
945
946 if (line_fill_time < wm->active_time)
947 return latency;
948 else
949 return latency + (line_fill_time - wm->active_time);
950
951 }
952
953 /**
954 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
955 * average and available dram bandwidth
956 *
957 * @wm: watermark calculation data
958 *
959 * Check if the display average bandwidth fits in the display
960 * dram bandwidth (CIK).
961 * Used for display watermark bandwidth calculations
962 * Returns true if the display fits, false if not.
963 */
964 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
965 {
966 if (dce_v11_0_average_bandwidth(wm) <=
967 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
968 return true;
969 else
970 return false;
971 }
972
973 /**
974 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
975 * average and available bandwidth
976 *
977 * @wm: watermark calculation data
978 *
979 * Check if the display average bandwidth fits in the display
980 * available bandwidth (CIK).
981 * Used for display watermark bandwidth calculations
982 * Returns true if the display fits, false if not.
983 */
984 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
985 {
986 if (dce_v11_0_average_bandwidth(wm) <=
987 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
988 return true;
989 else
990 return false;
991 }
992
993 /**
994 * dce_v11_0_check_latency_hiding - check latency hiding
995 *
996 * @wm: watermark calculation data
997 *
998 * Check latency hiding (CIK).
999 * Used for display watermark bandwidth calculations
1000 * Returns true if the display fits, false if not.
1001 */
1002 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1003 {
1004 u32 lb_partitions = wm->lb_size / wm->src_width;
1005 u32 line_time = wm->active_time + wm->blank_time;
1006 u32 latency_tolerant_lines;
1007 u32 latency_hiding;
1008 fixed20_12 a;
1009
1010 a.full = dfixed_const(1);
1011 if (wm->vsc.full > a.full)
1012 latency_tolerant_lines = 1;
1013 else {
1014 if (lb_partitions <= (wm->vtaps + 1))
1015 latency_tolerant_lines = 1;
1016 else
1017 latency_tolerant_lines = 2;
1018 }
1019
1020 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1021
1022 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1023 return true;
1024 else
1025 return false;
1026 }
1027
1028 /**
1029 * dce_v11_0_program_watermarks - program display watermarks
1030 *
1031 * @adev: amdgpu_device pointer
1032 * @amdgpu_crtc: the selected display controller
1033 * @lb_size: line buffer size
1034 * @num_heads: number of display controllers in use
1035 *
1036 * Calculate and program the display watermarks for the
1037 * selected display controller (CIK).
1038 */
1039 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1040 struct amdgpu_crtc *amdgpu_crtc,
1041 u32 lb_size, u32 num_heads)
1042 {
1043 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1044 struct dce10_wm_params wm_low, wm_high;
1045 u32 active_time;
1046 u32 line_time = 0;
1047 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1048 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1049
1050 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1051 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1052 (u32)mode->clock);
1053 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1054 (u32)mode->clock);
1055 line_time = min(line_time, (u32)65535);
1056
1057 /* watermark for high clocks */
1058 if (adev->pm.dpm_enabled) {
1059 wm_high.yclk =
1060 amdgpu_dpm_get_mclk(adev, false) * 10;
1061 wm_high.sclk =
1062 amdgpu_dpm_get_sclk(adev, false) * 10;
1063 } else {
1064 wm_high.yclk = adev->pm.current_mclk * 10;
1065 wm_high.sclk = adev->pm.current_sclk * 10;
1066 }
1067
1068 wm_high.disp_clk = mode->clock;
1069 wm_high.src_width = mode->crtc_hdisplay;
1070 wm_high.active_time = active_time;
1071 wm_high.blank_time = line_time - wm_high.active_time;
1072 wm_high.interlaced = false;
1073 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1074 wm_high.interlaced = true;
1075 wm_high.vsc = amdgpu_crtc->vsc;
1076 wm_high.vtaps = 1;
1077 if (amdgpu_crtc->rmx_type != RMX_OFF)
1078 wm_high.vtaps = 2;
1079 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1080 wm_high.lb_size = lb_size;
1081 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1082 wm_high.num_heads = num_heads;
1083
1084 /* set for high clocks */
1085 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1086
1087 /* possibly force display priority to high */
1088 /* should really do this at mode validation time... */
1089 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1090 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1091 !dce_v11_0_check_latency_hiding(&wm_high) ||
1092 (adev->mode_info.disp_priority == 2)) {
1093 DRM_DEBUG_KMS("force priority to high\n");
1094 }
1095
1096 /* watermark for low clocks */
1097 if (adev->pm.dpm_enabled) {
1098 wm_low.yclk =
1099 amdgpu_dpm_get_mclk(adev, true) * 10;
1100 wm_low.sclk =
1101 amdgpu_dpm_get_sclk(adev, true) * 10;
1102 } else {
1103 wm_low.yclk = adev->pm.current_mclk * 10;
1104 wm_low.sclk = adev->pm.current_sclk * 10;
1105 }
1106
1107 wm_low.disp_clk = mode->clock;
1108 wm_low.src_width = mode->crtc_hdisplay;
1109 wm_low.active_time = active_time;
1110 wm_low.blank_time = line_time - wm_low.active_time;
1111 wm_low.interlaced = false;
1112 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1113 wm_low.interlaced = true;
1114 wm_low.vsc = amdgpu_crtc->vsc;
1115 wm_low.vtaps = 1;
1116 if (amdgpu_crtc->rmx_type != RMX_OFF)
1117 wm_low.vtaps = 2;
1118 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1119 wm_low.lb_size = lb_size;
1120 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1121 wm_low.num_heads = num_heads;
1122
1123 /* set for low clocks */
1124 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1125
1126 /* possibly force display priority to high */
1127 /* should really do this at mode validation time... */
1128 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1129 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1130 !dce_v11_0_check_latency_hiding(&wm_low) ||
1131 (adev->mode_info.disp_priority == 2)) {
1132 DRM_DEBUG_KMS("force priority to high\n");
1133 }
1134 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1135 }
1136
1137 /* select wm A */
1138 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1139 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1140 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1141 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1142 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1143 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1144 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1145 /* select wm B */
1146 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1147 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1148 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1149 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1150 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1151 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1152 /* restore original selection */
1153 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1154
1155 /* save values for DPM */
1156 amdgpu_crtc->line_time = line_time;
1157 amdgpu_crtc->wm_high = latency_watermark_a;
1158 amdgpu_crtc->wm_low = latency_watermark_b;
1159 /* Save number of lines the linebuffer leads before the scanout */
1160 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1161 }
1162
1163 /**
1164 * dce_v11_0_bandwidth_update - program display watermarks
1165 *
1166 * @adev: amdgpu_device pointer
1167 *
1168 * Calculate and program the display watermarks and line
1169 * buffer allocation (CIK).
1170 */
1171 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1172 {
1173 struct drm_display_mode *mode = NULL;
1174 u32 num_heads = 0, lb_size;
1175 int i;
1176
1177 amdgpu_display_update_priority(adev);
1178
1179 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1180 if (adev->mode_info.crtcs[i]->base.enabled)
1181 num_heads++;
1182 }
1183 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1184 mode = &adev->mode_info.crtcs[i]->base.mode;
1185 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1186 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1187 lb_size, num_heads);
1188 }
1189 }
1190
1191 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1192 {
1193 int i;
1194 u32 offset, tmp;
1195
1196 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1197 offset = adev->mode_info.audio.pin[i].offset;
1198 tmp = RREG32_AUDIO_ENDPT(offset,
1199 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1200 if (((tmp &
1201 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1202 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1203 adev->mode_info.audio.pin[i].connected = false;
1204 else
1205 adev->mode_info.audio.pin[i].connected = true;
1206 }
1207 }
1208
1209 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1210 {
1211 int i;
1212
1213 dce_v11_0_audio_get_connected_pins(adev);
1214
1215 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1216 if (adev->mode_info.audio.pin[i].connected)
1217 return &adev->mode_info.audio.pin[i];
1218 }
1219 DRM_ERROR("No connected audio pins found!\n");
1220 return NULL;
1221 }
1222
1223 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1224 {
1225 struct amdgpu_device *adev = encoder->dev->dev_private;
1226 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1227 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1228 u32 tmp;
1229
1230 if (!dig || !dig->afmt || !dig->afmt->pin)
1231 return;
1232
1233 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1234 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1235 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1236 }
1237
1238 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1239 struct drm_display_mode *mode)
1240 {
1241 struct amdgpu_device *adev = encoder->dev->dev_private;
1242 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1243 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1244 struct drm_connector *connector;
1245 struct amdgpu_connector *amdgpu_connector = NULL;
1246 u32 tmp;
1247 int interlace = 0;
1248
1249 if (!dig || !dig->afmt || !dig->afmt->pin)
1250 return;
1251
1252 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1253 if (connector->encoder == encoder) {
1254 amdgpu_connector = to_amdgpu_connector(connector);
1255 break;
1256 }
1257 }
1258
1259 if (!amdgpu_connector) {
1260 DRM_ERROR("Couldn't find encoder's connector\n");
1261 return;
1262 }
1263
1264 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1265 interlace = 1;
1266 if (connector->latency_present[interlace]) {
1267 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1268 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1269 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1270 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1271 } else {
1272 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1273 VIDEO_LIPSYNC, 0);
1274 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1275 AUDIO_LIPSYNC, 0);
1276 }
1277 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1278 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1279 }
1280
1281 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1282 {
1283 struct amdgpu_device *adev = encoder->dev->dev_private;
1284 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1285 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1286 struct drm_connector *connector;
1287 struct amdgpu_connector *amdgpu_connector = NULL;
1288 u32 tmp;
1289 u8 *sadb = NULL;
1290 int sad_count;
1291
1292 if (!dig || !dig->afmt || !dig->afmt->pin)
1293 return;
1294
1295 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1296 if (connector->encoder == encoder) {
1297 amdgpu_connector = to_amdgpu_connector(connector);
1298 break;
1299 }
1300 }
1301
1302 if (!amdgpu_connector) {
1303 DRM_ERROR("Couldn't find encoder's connector\n");
1304 return;
1305 }
1306
1307 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1308 if (sad_count < 0) {
1309 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1310 sad_count = 0;
1311 }
1312
1313 /* program the speaker allocation */
1314 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1315 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1316 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1317 DP_CONNECTION, 0);
1318 /* set HDMI mode */
1319 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1320 HDMI_CONNECTION, 1);
1321 if (sad_count)
1322 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1323 SPEAKER_ALLOCATION, sadb[0]);
1324 else
1325 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1326 SPEAKER_ALLOCATION, 5); /* stereo */
1327 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1328 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1329
1330 kfree(sadb);
1331 }
1332
1333 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1334 {
1335 struct amdgpu_device *adev = encoder->dev->dev_private;
1336 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1337 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1338 struct drm_connector *connector;
1339 struct amdgpu_connector *amdgpu_connector = NULL;
1340 struct cea_sad *sads;
1341 int i, sad_count;
1342
1343 static const u16 eld_reg_to_type[][2] = {
1344 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1345 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1346 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1347 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1348 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1349 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1350 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1351 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1352 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1353 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1354 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1355 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1356 };
1357
1358 if (!dig || !dig->afmt || !dig->afmt->pin)
1359 return;
1360
1361 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1362 if (connector->encoder == encoder) {
1363 amdgpu_connector = to_amdgpu_connector(connector);
1364 break;
1365 }
1366 }
1367
1368 if (!amdgpu_connector) {
1369 DRM_ERROR("Couldn't find encoder's connector\n");
1370 return;
1371 }
1372
1373 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1374 if (sad_count <= 0) {
1375 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1376 return;
1377 }
1378 BUG_ON(!sads);
1379
1380 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1381 u32 tmp = 0;
1382 u8 stereo_freqs = 0;
1383 int max_channels = -1;
1384 int j;
1385
1386 for (j = 0; j < sad_count; j++) {
1387 struct cea_sad *sad = &sads[j];
1388
1389 if (sad->format == eld_reg_to_type[i][1]) {
1390 if (sad->channels > max_channels) {
1391 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1392 MAX_CHANNELS, sad->channels);
1393 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1394 DESCRIPTOR_BYTE_2, sad->byte2);
1395 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1396 SUPPORTED_FREQUENCIES, sad->freq);
1397 max_channels = sad->channels;
1398 }
1399
1400 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1401 stereo_freqs |= sad->freq;
1402 else
1403 break;
1404 }
1405 }
1406
1407 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1408 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1409 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1410 }
1411
1412 kfree(sads);
1413 }
1414
1415 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1416 struct amdgpu_audio_pin *pin,
1417 bool enable)
1418 {
1419 if (!pin)
1420 return;
1421
1422 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1423 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1424 }
1425
1426 static const u32 pin_offsets[] =
1427 {
1428 AUD0_REGISTER_OFFSET,
1429 AUD1_REGISTER_OFFSET,
1430 AUD2_REGISTER_OFFSET,
1431 AUD3_REGISTER_OFFSET,
1432 AUD4_REGISTER_OFFSET,
1433 AUD5_REGISTER_OFFSET,
1434 AUD6_REGISTER_OFFSET,
1435 AUD7_REGISTER_OFFSET,
1436 };
1437
1438 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1439 {
1440 int i;
1441
1442 if (!amdgpu_audio)
1443 return 0;
1444
1445 adev->mode_info.audio.enabled = true;
1446
1447 switch (adev->asic_type) {
1448 case CHIP_CARRIZO:
1449 case CHIP_STONEY:
1450 adev->mode_info.audio.num_pins = 7;
1451 break;
1452 case CHIP_POLARIS10:
1453 case CHIP_VEGAM:
1454 adev->mode_info.audio.num_pins = 8;
1455 break;
1456 case CHIP_POLARIS11:
1457 case CHIP_POLARIS12:
1458 adev->mode_info.audio.num_pins = 6;
1459 break;
1460 default:
1461 return -EINVAL;
1462 }
1463
1464 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1465 adev->mode_info.audio.pin[i].channels = -1;
1466 adev->mode_info.audio.pin[i].rate = -1;
1467 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1468 adev->mode_info.audio.pin[i].status_bits = 0;
1469 adev->mode_info.audio.pin[i].category_code = 0;
1470 adev->mode_info.audio.pin[i].connected = false;
1471 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1472 adev->mode_info.audio.pin[i].id = i;
1473 /* disable audio. it will be set up later */
1474 /* XXX remove once we switch to ip funcs */
1475 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1476 }
1477
1478 return 0;
1479 }
1480
1481 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1482 {
1483 int i;
1484
1485 if (!amdgpu_audio)
1486 return;
1487
1488 if (!adev->mode_info.audio.enabled)
1489 return;
1490
1491 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1492 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1493
1494 adev->mode_info.audio.enabled = false;
1495 }
1496
1497 /*
1498 * update the N and CTS parameters for a given pixel clock rate
1499 */
1500 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1501 {
1502 struct drm_device *dev = encoder->dev;
1503 struct amdgpu_device *adev = dev->dev_private;
1504 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1505 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1506 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1507 u32 tmp;
1508
1509 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1510 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1511 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1512 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1513 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1514 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1515
1516 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1517 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1518 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1519 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1520 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1521 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1522
1523 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1524 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1525 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1526 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1527 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1528 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1529
1530 }
1531
1532 /*
1533 * build a HDMI Video Info Frame
1534 */
1535 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1536 void *buffer, size_t size)
1537 {
1538 struct drm_device *dev = encoder->dev;
1539 struct amdgpu_device *adev = dev->dev_private;
1540 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1541 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1542 uint8_t *frame = buffer + 3;
1543 uint8_t *header = buffer;
1544
1545 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1546 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1547 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1548 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1549 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1550 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1551 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1552 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1553 }
1554
1555 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1556 {
1557 struct drm_device *dev = encoder->dev;
1558 struct amdgpu_device *adev = dev->dev_private;
1559 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1560 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1561 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1562 u32 dto_phase = 24 * 1000;
1563 u32 dto_modulo = clock;
1564 u32 tmp;
1565
1566 if (!dig || !dig->afmt)
1567 return;
1568
1569 /* XXX two dtos; generally use dto0 for hdmi */
1570 /* Express [24MHz / target pixel clock] as an exact rational
1571 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1572 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1573 */
1574 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1575 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1576 amdgpu_crtc->crtc_id);
1577 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1578 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1579 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1580 }
1581
1582 /*
1583 * update the info frames with the data from the current display mode
1584 */
1585 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1586 struct drm_display_mode *mode)
1587 {
1588 struct drm_device *dev = encoder->dev;
1589 struct amdgpu_device *adev = dev->dev_private;
1590 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1591 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1592 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1593 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1594 struct hdmi_avi_infoframe frame;
1595 ssize_t err;
1596 u32 tmp;
1597 int bpc = 8;
1598
1599 if (!dig || !dig->afmt)
1600 return;
1601
1602 /* Silent, r600_hdmi_enable will raise WARN for us */
1603 if (!dig->afmt->enabled)
1604 return;
1605
1606 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1607 if (encoder->crtc) {
1608 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1609 bpc = amdgpu_crtc->bpc;
1610 }
1611
1612 /* disable audio prior to setting up hw */
1613 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1614 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1615
1616 dce_v11_0_audio_set_dto(encoder, mode->clock);
1617
1618 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1619 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1620 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1621
1622 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1623
1624 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1625 switch (bpc) {
1626 case 0:
1627 case 6:
1628 case 8:
1629 case 16:
1630 default:
1631 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1632 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1633 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1634 connector->name, bpc);
1635 break;
1636 case 10:
1637 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1638 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1639 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1640 connector->name);
1641 break;
1642 case 12:
1643 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1644 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1645 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1646 connector->name);
1647 break;
1648 }
1649 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1650
1651 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1652 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1653 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1654 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1655 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1656
1657 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1658 /* enable audio info frames (frames won't be set until audio is enabled) */
1659 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1660 /* required for audio info values to be updated */
1661 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1662 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1663
1664 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1665 /* required for audio info values to be updated */
1666 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1667 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1668
1669 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1670 /* anything other than 0 */
1671 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1672 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1673
1674 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1675
1676 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1677 /* set the default audio delay */
1678 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1679 /* should be suffient for all audio modes and small enough for all hblanks */
1680 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1681 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1682
1683 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1684 /* allow 60958 channel status fields to be updated */
1685 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1686 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1687
1688 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1689 if (bpc > 8)
1690 /* clear SW CTS value */
1691 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1692 else
1693 /* select SW CTS value */
1694 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1695 /* allow hw to sent ACR packets when required */
1696 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1697 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1698
1699 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1700
1701 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1702 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1703 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1704
1705 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1706 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1707 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1708
1709 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1710 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1711 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1712 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1713 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1714 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1715 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1716 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1717
1718 dce_v11_0_audio_write_speaker_allocation(encoder);
1719
1720 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1721 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1722
1723 dce_v11_0_afmt_audio_select_pin(encoder);
1724 dce_v11_0_audio_write_sad_regs(encoder);
1725 dce_v11_0_audio_write_latency_fields(encoder, mode);
1726
1727 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1728 if (err < 0) {
1729 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1730 return;
1731 }
1732
1733 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1734 if (err < 0) {
1735 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1736 return;
1737 }
1738
1739 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1740
1741 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1742 /* enable AVI info frames */
1743 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1744 /* required for audio info values to be updated */
1745 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1746 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1747
1748 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1749 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1750 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1751
1752 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1753 /* send audio packets */
1754 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1755 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1756
1757 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1758 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1759 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1760 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1761
1762 /* enable audio after to setting up hw */
1763 dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1764 }
1765
1766 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1767 {
1768 struct drm_device *dev = encoder->dev;
1769 struct amdgpu_device *adev = dev->dev_private;
1770 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1771 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1772
1773 if (!dig || !dig->afmt)
1774 return;
1775
1776 /* Silent, r600_hdmi_enable will raise WARN for us */
1777 if (enable && dig->afmt->enabled)
1778 return;
1779 if (!enable && !dig->afmt->enabled)
1780 return;
1781
1782 if (!enable && dig->afmt->pin) {
1783 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1784 dig->afmt->pin = NULL;
1785 }
1786
1787 dig->afmt->enabled = enable;
1788
1789 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1790 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1791 }
1792
1793 static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1794 {
1795 int i;
1796
1797 for (i = 0; i < adev->mode_info.num_dig; i++)
1798 adev->mode_info.afmt[i] = NULL;
1799
1800 /* DCE11 has audio blocks tied to DIG encoders */
1801 for (i = 0; i < adev->mode_info.num_dig; i++) {
1802 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1803 if (adev->mode_info.afmt[i]) {
1804 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1805 adev->mode_info.afmt[i]->id = i;
1806 } else {
1807 int j;
1808 for (j = 0; j < i; j++) {
1809 kfree(adev->mode_info.afmt[j]);
1810 adev->mode_info.afmt[j] = NULL;
1811 }
1812 return -ENOMEM;
1813 }
1814 }
1815 return 0;
1816 }
1817
1818 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1819 {
1820 int i;
1821
1822 for (i = 0; i < adev->mode_info.num_dig; i++) {
1823 kfree(adev->mode_info.afmt[i]);
1824 adev->mode_info.afmt[i] = NULL;
1825 }
1826 }
1827
1828 static const u32 vga_control_regs[6] =
1829 {
1830 mmD1VGA_CONTROL,
1831 mmD2VGA_CONTROL,
1832 mmD3VGA_CONTROL,
1833 mmD4VGA_CONTROL,
1834 mmD5VGA_CONTROL,
1835 mmD6VGA_CONTROL,
1836 };
1837
1838 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1839 {
1840 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1841 struct drm_device *dev = crtc->dev;
1842 struct amdgpu_device *adev = dev->dev_private;
1843 u32 vga_control;
1844
1845 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1846 if (enable)
1847 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1848 else
1849 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1850 }
1851
1852 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
1853 {
1854 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1855 struct drm_device *dev = crtc->dev;
1856 struct amdgpu_device *adev = dev->dev_private;
1857
1858 if (enable)
1859 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1860 else
1861 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1862 }
1863
1864 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
1865 struct drm_framebuffer *fb,
1866 int x, int y, int atomic)
1867 {
1868 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1869 struct drm_device *dev = crtc->dev;
1870 struct amdgpu_device *adev = dev->dev_private;
1871 struct drm_framebuffer *target_fb;
1872 struct drm_gem_object *obj;
1873 struct amdgpu_bo *abo;
1874 uint64_t fb_location, tiling_flags;
1875 uint32_t fb_format, fb_pitch_pixels;
1876 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1877 u32 pipe_config;
1878 u32 tmp, viewport_w, viewport_h;
1879 int r;
1880 bool bypass_lut = false;
1881 struct drm_format_name_buf format_name;
1882
1883 /* no fb bound */
1884 if (!atomic && !crtc->primary->fb) {
1885 DRM_DEBUG_KMS("No FB bound\n");
1886 return 0;
1887 }
1888
1889 if (atomic)
1890 target_fb = fb;
1891 else
1892 target_fb = crtc->primary->fb;
1893
1894 /* If atomic, assume fb object is pinned & idle & fenced and
1895 * just update base pointers
1896 */
1897 obj = target_fb->obj[0];
1898 abo = gem_to_amdgpu_bo(obj);
1899 r = amdgpu_bo_reserve(abo, false);
1900 if (unlikely(r != 0))
1901 return r;
1902
1903 if (!atomic) {
1904 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1905 if (unlikely(r != 0)) {
1906 amdgpu_bo_unreserve(abo);
1907 return -EINVAL;
1908 }
1909 }
1910 fb_location = amdgpu_bo_gpu_offset(abo);
1911
1912 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1913 amdgpu_bo_unreserve(abo);
1914
1915 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1916
1917 switch (target_fb->format->format) {
1918 case DRM_FORMAT_C8:
1919 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1920 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1921 break;
1922 case DRM_FORMAT_XRGB4444:
1923 case DRM_FORMAT_ARGB4444:
1924 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1925 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1926 #ifdef __BIG_ENDIAN
1927 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1928 ENDIAN_8IN16);
1929 #endif
1930 break;
1931 case DRM_FORMAT_XRGB1555:
1932 case DRM_FORMAT_ARGB1555:
1933 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1934 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1935 #ifdef __BIG_ENDIAN
1936 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1937 ENDIAN_8IN16);
1938 #endif
1939 break;
1940 case DRM_FORMAT_BGRX5551:
1941 case DRM_FORMAT_BGRA5551:
1942 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1943 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1944 #ifdef __BIG_ENDIAN
1945 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1946 ENDIAN_8IN16);
1947 #endif
1948 break;
1949 case DRM_FORMAT_RGB565:
1950 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1951 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1952 #ifdef __BIG_ENDIAN
1953 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1954 ENDIAN_8IN16);
1955 #endif
1956 break;
1957 case DRM_FORMAT_XRGB8888:
1958 case DRM_FORMAT_ARGB8888:
1959 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1960 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1961 #ifdef __BIG_ENDIAN
1962 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1963 ENDIAN_8IN32);
1964 #endif
1965 break;
1966 case DRM_FORMAT_XRGB2101010:
1967 case DRM_FORMAT_ARGB2101010:
1968 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1969 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1970 #ifdef __BIG_ENDIAN
1971 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1972 ENDIAN_8IN32);
1973 #endif
1974 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1975 bypass_lut = true;
1976 break;
1977 case DRM_FORMAT_BGRX1010102:
1978 case DRM_FORMAT_BGRA1010102:
1979 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1980 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
1981 #ifdef __BIG_ENDIAN
1982 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1983 ENDIAN_8IN32);
1984 #endif
1985 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1986 bypass_lut = true;
1987 break;
1988 case DRM_FORMAT_XBGR8888:
1989 case DRM_FORMAT_ABGR8888:
1990 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1991 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1992 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
1993 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
1994 #ifdef __BIG_ENDIAN
1995 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1996 ENDIAN_8IN32);
1997 #endif
1998 break;
1999 default:
2000 DRM_ERROR("Unsupported screen format %s\n",
2001 drm_get_format_name(target_fb->format->format, &format_name));
2002 return -EINVAL;
2003 }
2004
2005 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2006 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2007
2008 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2009 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2010 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2011 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2012 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2013
2014 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2015 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2016 ARRAY_2D_TILED_THIN1);
2017 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2018 tile_split);
2019 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2020 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2021 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2022 mtaspect);
2023 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2024 ADDR_SURF_MICRO_TILING_DISPLAY);
2025 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2026 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2027 ARRAY_1D_TILED_THIN1);
2028 }
2029
2030 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2031 pipe_config);
2032
2033 dce_v11_0_vga_enable(crtc, false);
2034
2035 /* Make sure surface address is updated at vertical blank rather than
2036 * horizontal blank
2037 */
2038 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2039 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2040 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2041 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2042
2043 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2044 upper_32_bits(fb_location));
2045 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2046 upper_32_bits(fb_location));
2047 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2048 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2049 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2050 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2051 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2052 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2053
2054 /*
2055 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2056 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2057 * retain the full precision throughout the pipeline.
2058 */
2059 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2060 if (bypass_lut)
2061 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2062 else
2063 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2064 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2065
2066 if (bypass_lut)
2067 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2068
2069 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2070 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2071 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2072 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2073 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2074 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2075
2076 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2077 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2078
2079 dce_v11_0_grph_enable(crtc, true);
2080
2081 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2082 target_fb->height);
2083
2084 x &= ~3;
2085 y &= ~1;
2086 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2087 (x << 16) | y);
2088 viewport_w = crtc->mode.hdisplay;
2089 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2090 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2091 (viewport_w << 16) | viewport_h);
2092
2093 /* set pageflip to happen anywhere in vblank interval */
2094 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2095
2096 if (!atomic && fb && fb != crtc->primary->fb) {
2097 abo = gem_to_amdgpu_bo(fb->obj[0]);
2098 r = amdgpu_bo_reserve(abo, true);
2099 if (unlikely(r != 0))
2100 return r;
2101 amdgpu_bo_unpin(abo);
2102 amdgpu_bo_unreserve(abo);
2103 }
2104
2105 /* Bytes per pixel may have changed */
2106 dce_v11_0_bandwidth_update(adev);
2107
2108 return 0;
2109 }
2110
2111 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2112 struct drm_display_mode *mode)
2113 {
2114 struct drm_device *dev = crtc->dev;
2115 struct amdgpu_device *adev = dev->dev_private;
2116 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2117 u32 tmp;
2118
2119 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2120 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2121 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2122 else
2123 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2124 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2125 }
2126
2127 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2128 {
2129 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2130 struct drm_device *dev = crtc->dev;
2131 struct amdgpu_device *adev = dev->dev_private;
2132 u16 *r, *g, *b;
2133 int i;
2134 u32 tmp;
2135
2136 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2137
2138 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2139 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2140 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2141
2142 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2143 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2144 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2145
2146 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2147 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2148 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2149
2150 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2151
2152 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2153 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2154 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2155
2156 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2157 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2158 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2159
2160 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2161 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2162
2163 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2164 r = crtc->gamma_store;
2165 g = r + crtc->gamma_size;
2166 b = g + crtc->gamma_size;
2167 for (i = 0; i < 256; i++) {
2168 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2169 ((*r++ & 0xffc0) << 14) |
2170 ((*g++ & 0xffc0) << 4) |
2171 (*b++ >> 6));
2172 }
2173
2174 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2175 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2176 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2177 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2178 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2179
2180 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2181 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2182 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2183
2184 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2185 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2186 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2187
2188 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2189 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2190 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2191
2192 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2193 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2194 /* XXX this only needs to be programmed once per crtc at startup,
2195 * not sure where the best place for it is
2196 */
2197 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2198 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2199 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2200 }
2201
2202 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2203 {
2204 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2205 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2206
2207 switch (amdgpu_encoder->encoder_id) {
2208 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2209 if (dig->linkb)
2210 return 1;
2211 else
2212 return 0;
2213 break;
2214 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2215 if (dig->linkb)
2216 return 3;
2217 else
2218 return 2;
2219 break;
2220 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2221 if (dig->linkb)
2222 return 5;
2223 else
2224 return 4;
2225 break;
2226 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2227 return 6;
2228 break;
2229 default:
2230 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2231 return 0;
2232 }
2233 }
2234
2235 /**
2236 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2237 *
2238 * @crtc: drm crtc
2239 *
2240 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2241 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2242 * monitors a dedicated PPLL must be used. If a particular board has
2243 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2244 * as there is no need to program the PLL itself. If we are not able to
2245 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2246 * avoid messing up an existing monitor.
2247 *
2248 * Asic specific PLL information
2249 *
2250 * DCE 10.x
2251 * Tonga
2252 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2253 * CI
2254 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2255 *
2256 */
2257 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2258 {
2259 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2260 struct drm_device *dev = crtc->dev;
2261 struct amdgpu_device *adev = dev->dev_private;
2262 u32 pll_in_use;
2263 int pll;
2264
2265 if ((adev->asic_type == CHIP_POLARIS10) ||
2266 (adev->asic_type == CHIP_POLARIS11) ||
2267 (adev->asic_type == CHIP_POLARIS12) ||
2268 (adev->asic_type == CHIP_VEGAM)) {
2269 struct amdgpu_encoder *amdgpu_encoder =
2270 to_amdgpu_encoder(amdgpu_crtc->encoder);
2271 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2272
2273 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2274 return ATOM_DP_DTO;
2275
2276 switch (amdgpu_encoder->encoder_id) {
2277 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2278 if (dig->linkb)
2279 return ATOM_COMBOPHY_PLL1;
2280 else
2281 return ATOM_COMBOPHY_PLL0;
2282 break;
2283 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2284 if (dig->linkb)
2285 return ATOM_COMBOPHY_PLL3;
2286 else
2287 return ATOM_COMBOPHY_PLL2;
2288 break;
2289 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2290 if (dig->linkb)
2291 return ATOM_COMBOPHY_PLL5;
2292 else
2293 return ATOM_COMBOPHY_PLL4;
2294 break;
2295 default:
2296 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2297 return ATOM_PPLL_INVALID;
2298 }
2299 }
2300
2301 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2302 if (adev->clock.dp_extclk)
2303 /* skip PPLL programming if using ext clock */
2304 return ATOM_PPLL_INVALID;
2305 else {
2306 /* use the same PPLL for all DP monitors */
2307 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2308 if (pll != ATOM_PPLL_INVALID)
2309 return pll;
2310 }
2311 } else {
2312 /* use the same PPLL for all monitors with the same clock */
2313 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2314 if (pll != ATOM_PPLL_INVALID)
2315 return pll;
2316 }
2317
2318 /* XXX need to determine what plls are available on each DCE11 part */
2319 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2320 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2321 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2322 return ATOM_PPLL1;
2323 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2324 return ATOM_PPLL0;
2325 DRM_ERROR("unable to allocate a PPLL\n");
2326 return ATOM_PPLL_INVALID;
2327 } else {
2328 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2329 return ATOM_PPLL2;
2330 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2331 return ATOM_PPLL1;
2332 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2333 return ATOM_PPLL0;
2334 DRM_ERROR("unable to allocate a PPLL\n");
2335 return ATOM_PPLL_INVALID;
2336 }
2337 return ATOM_PPLL_INVALID;
2338 }
2339
2340 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2341 {
2342 struct amdgpu_device *adev = crtc->dev->dev_private;
2343 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2344 uint32_t cur_lock;
2345
2346 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2347 if (lock)
2348 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2349 else
2350 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2351 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2352 }
2353
2354 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2355 {
2356 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2357 struct amdgpu_device *adev = crtc->dev->dev_private;
2358 u32 tmp;
2359
2360 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2361 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2362 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2363 }
2364
2365 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2366 {
2367 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2368 struct amdgpu_device *adev = crtc->dev->dev_private;
2369 u32 tmp;
2370
2371 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2372 upper_32_bits(amdgpu_crtc->cursor_addr));
2373 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2374 lower_32_bits(amdgpu_crtc->cursor_addr));
2375
2376 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2377 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2378 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2379 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2380 }
2381
2382 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2383 int x, int y)
2384 {
2385 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2386 struct amdgpu_device *adev = crtc->dev->dev_private;
2387 int xorigin = 0, yorigin = 0;
2388
2389 amdgpu_crtc->cursor_x = x;
2390 amdgpu_crtc->cursor_y = y;
2391
2392 /* avivo cursor are offset into the total surface */
2393 x += crtc->x;
2394 y += crtc->y;
2395 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2396
2397 if (x < 0) {
2398 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2399 x = 0;
2400 }
2401 if (y < 0) {
2402 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2403 y = 0;
2404 }
2405
2406 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2407 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2408 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2409 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2410
2411 return 0;
2412 }
2413
2414 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2415 int x, int y)
2416 {
2417 int ret;
2418
2419 dce_v11_0_lock_cursor(crtc, true);
2420 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2421 dce_v11_0_lock_cursor(crtc, false);
2422
2423 return ret;
2424 }
2425
2426 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2427 struct drm_file *file_priv,
2428 uint32_t handle,
2429 uint32_t width,
2430 uint32_t height,
2431 int32_t hot_x,
2432 int32_t hot_y)
2433 {
2434 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2435 struct drm_gem_object *obj;
2436 struct amdgpu_bo *aobj;
2437 int ret;
2438
2439 if (!handle) {
2440 /* turn off cursor */
2441 dce_v11_0_hide_cursor(crtc);
2442 obj = NULL;
2443 goto unpin;
2444 }
2445
2446 if ((width > amdgpu_crtc->max_cursor_width) ||
2447 (height > amdgpu_crtc->max_cursor_height)) {
2448 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2449 return -EINVAL;
2450 }
2451
2452 obj = drm_gem_object_lookup(file_priv, handle);
2453 if (!obj) {
2454 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2455 return -ENOENT;
2456 }
2457
2458 aobj = gem_to_amdgpu_bo(obj);
2459 ret = amdgpu_bo_reserve(aobj, false);
2460 if (ret != 0) {
2461 drm_gem_object_put_unlocked(obj);
2462 return ret;
2463 }
2464
2465 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2466 amdgpu_bo_unreserve(aobj);
2467 if (ret) {
2468 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2469 drm_gem_object_put_unlocked(obj);
2470 return ret;
2471 }
2472 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2473
2474 dce_v11_0_lock_cursor(crtc, true);
2475
2476 if (width != amdgpu_crtc->cursor_width ||
2477 height != amdgpu_crtc->cursor_height ||
2478 hot_x != amdgpu_crtc->cursor_hot_x ||
2479 hot_y != amdgpu_crtc->cursor_hot_y) {
2480 int x, y;
2481
2482 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2483 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2484
2485 dce_v11_0_cursor_move_locked(crtc, x, y);
2486
2487 amdgpu_crtc->cursor_width = width;
2488 amdgpu_crtc->cursor_height = height;
2489 amdgpu_crtc->cursor_hot_x = hot_x;
2490 amdgpu_crtc->cursor_hot_y = hot_y;
2491 }
2492
2493 dce_v11_0_show_cursor(crtc);
2494 dce_v11_0_lock_cursor(crtc, false);
2495
2496 unpin:
2497 if (amdgpu_crtc->cursor_bo) {
2498 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2499 ret = amdgpu_bo_reserve(aobj, true);
2500 if (likely(ret == 0)) {
2501 amdgpu_bo_unpin(aobj);
2502 amdgpu_bo_unreserve(aobj);
2503 }
2504 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2505 }
2506
2507 amdgpu_crtc->cursor_bo = obj;
2508 return 0;
2509 }
2510
2511 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2512 {
2513 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2514
2515 if (amdgpu_crtc->cursor_bo) {
2516 dce_v11_0_lock_cursor(crtc, true);
2517
2518 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2519 amdgpu_crtc->cursor_y);
2520
2521 dce_v11_0_show_cursor(crtc);
2522
2523 dce_v11_0_lock_cursor(crtc, false);
2524 }
2525 }
2526
2527 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2528 u16 *blue, uint32_t size,
2529 struct drm_modeset_acquire_ctx *ctx)
2530 {
2531 dce_v11_0_crtc_load_lut(crtc);
2532
2533 return 0;
2534 }
2535
2536 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2537 {
2538 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2539
2540 drm_crtc_cleanup(crtc);
2541 kfree(amdgpu_crtc);
2542 }
2543
2544 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2545 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2546 .cursor_move = dce_v11_0_crtc_cursor_move,
2547 .gamma_set = dce_v11_0_crtc_gamma_set,
2548 .set_config = amdgpu_display_crtc_set_config,
2549 .destroy = dce_v11_0_crtc_destroy,
2550 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2551 };
2552
2553 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2554 {
2555 struct drm_device *dev = crtc->dev;
2556 struct amdgpu_device *adev = dev->dev_private;
2557 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2558 unsigned type;
2559
2560 switch (mode) {
2561 case DRM_MODE_DPMS_ON:
2562 amdgpu_crtc->enabled = true;
2563 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2564 dce_v11_0_vga_enable(crtc, true);
2565 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2566 dce_v11_0_vga_enable(crtc, false);
2567 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2568 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2569 amdgpu_crtc->crtc_id);
2570 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2571 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2572 drm_crtc_vblank_on(crtc);
2573 dce_v11_0_crtc_load_lut(crtc);
2574 break;
2575 case DRM_MODE_DPMS_STANDBY:
2576 case DRM_MODE_DPMS_SUSPEND:
2577 case DRM_MODE_DPMS_OFF:
2578 drm_crtc_vblank_off(crtc);
2579 if (amdgpu_crtc->enabled) {
2580 dce_v11_0_vga_enable(crtc, true);
2581 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2582 dce_v11_0_vga_enable(crtc, false);
2583 }
2584 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2585 amdgpu_crtc->enabled = false;
2586 break;
2587 }
2588 /* adjust pm to dpms */
2589 amdgpu_pm_compute_clocks(adev);
2590 }
2591
2592 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2593 {
2594 /* disable crtc pair power gating before programming */
2595 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2596 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2597 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2598 }
2599
2600 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2601 {
2602 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2603 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2604 }
2605
2606 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2607 {
2608 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2609 struct drm_device *dev = crtc->dev;
2610 struct amdgpu_device *adev = dev->dev_private;
2611 struct amdgpu_atom_ss ss;
2612 int i;
2613
2614 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2615 if (crtc->primary->fb) {
2616 int r;
2617 struct amdgpu_bo *abo;
2618
2619 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2620 r = amdgpu_bo_reserve(abo, true);
2621 if (unlikely(r))
2622 DRM_ERROR("failed to reserve abo before unpin\n");
2623 else {
2624 amdgpu_bo_unpin(abo);
2625 amdgpu_bo_unreserve(abo);
2626 }
2627 }
2628 /* disable the GRPH */
2629 dce_v11_0_grph_enable(crtc, false);
2630
2631 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2632
2633 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2634 if (adev->mode_info.crtcs[i] &&
2635 adev->mode_info.crtcs[i]->enabled &&
2636 i != amdgpu_crtc->crtc_id &&
2637 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2638 /* one other crtc is using this pll don't turn
2639 * off the pll
2640 */
2641 goto done;
2642 }
2643 }
2644
2645 switch (amdgpu_crtc->pll_id) {
2646 case ATOM_PPLL0:
2647 case ATOM_PPLL1:
2648 case ATOM_PPLL2:
2649 /* disable the ppll */
2650 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2651 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2652 break;
2653 case ATOM_COMBOPHY_PLL0:
2654 case ATOM_COMBOPHY_PLL1:
2655 case ATOM_COMBOPHY_PLL2:
2656 case ATOM_COMBOPHY_PLL3:
2657 case ATOM_COMBOPHY_PLL4:
2658 case ATOM_COMBOPHY_PLL5:
2659 /* disable the ppll */
2660 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2661 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2662 break;
2663 default:
2664 break;
2665 }
2666 done:
2667 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2668 amdgpu_crtc->adjusted_clock = 0;
2669 amdgpu_crtc->encoder = NULL;
2670 amdgpu_crtc->connector = NULL;
2671 }
2672
2673 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2674 struct drm_display_mode *mode,
2675 struct drm_display_mode *adjusted_mode,
2676 int x, int y, struct drm_framebuffer *old_fb)
2677 {
2678 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2679 struct drm_device *dev = crtc->dev;
2680 struct amdgpu_device *adev = dev->dev_private;
2681
2682 if (!amdgpu_crtc->adjusted_clock)
2683 return -EINVAL;
2684
2685 if ((adev->asic_type == CHIP_POLARIS10) ||
2686 (adev->asic_type == CHIP_POLARIS11) ||
2687 (adev->asic_type == CHIP_POLARIS12) ||
2688 (adev->asic_type == CHIP_VEGAM)) {
2689 struct amdgpu_encoder *amdgpu_encoder =
2690 to_amdgpu_encoder(amdgpu_crtc->encoder);
2691 int encoder_mode =
2692 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2693
2694 /* SetPixelClock calculates the plls and ss values now */
2695 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2696 amdgpu_crtc->pll_id,
2697 encoder_mode, amdgpu_encoder->encoder_id,
2698 adjusted_mode->clock, 0, 0, 0, 0,
2699 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2700 } else {
2701 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2702 }
2703 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2704 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2705 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2706 amdgpu_atombios_crtc_scaler_setup(crtc);
2707 dce_v11_0_cursor_reset(crtc);
2708 /* update the hw version fpr dpm */
2709 amdgpu_crtc->hw_mode = *adjusted_mode;
2710
2711 return 0;
2712 }
2713
2714 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2715 const struct drm_display_mode *mode,
2716 struct drm_display_mode *adjusted_mode)
2717 {
2718 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2719 struct drm_device *dev = crtc->dev;
2720 struct drm_encoder *encoder;
2721
2722 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2723 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2724 if (encoder->crtc == crtc) {
2725 amdgpu_crtc->encoder = encoder;
2726 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2727 break;
2728 }
2729 }
2730 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2731 amdgpu_crtc->encoder = NULL;
2732 amdgpu_crtc->connector = NULL;
2733 return false;
2734 }
2735 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2736 return false;
2737 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2738 return false;
2739 /* pick pll */
2740 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2741 /* if we can't get a PPLL for a non-DP encoder, fail */
2742 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2743 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2744 return false;
2745
2746 return true;
2747 }
2748
2749 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2750 struct drm_framebuffer *old_fb)
2751 {
2752 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2753 }
2754
2755 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2756 struct drm_framebuffer *fb,
2757 int x, int y, enum mode_set_atomic state)
2758 {
2759 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2760 }
2761
2762 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2763 .dpms = dce_v11_0_crtc_dpms,
2764 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2765 .mode_set = dce_v11_0_crtc_mode_set,
2766 .mode_set_base = dce_v11_0_crtc_set_base,
2767 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2768 .prepare = dce_v11_0_crtc_prepare,
2769 .commit = dce_v11_0_crtc_commit,
2770 .disable = dce_v11_0_crtc_disable,
2771 };
2772
2773 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2774 {
2775 struct amdgpu_crtc *amdgpu_crtc;
2776
2777 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2778 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2779 if (amdgpu_crtc == NULL)
2780 return -ENOMEM;
2781
2782 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2783
2784 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2785 amdgpu_crtc->crtc_id = index;
2786 adev->mode_info.crtcs[index] = amdgpu_crtc;
2787
2788 amdgpu_crtc->max_cursor_width = 128;
2789 amdgpu_crtc->max_cursor_height = 128;
2790 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2791 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2792
2793 switch (amdgpu_crtc->crtc_id) {
2794 case 0:
2795 default:
2796 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2797 break;
2798 case 1:
2799 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2800 break;
2801 case 2:
2802 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2803 break;
2804 case 3:
2805 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2806 break;
2807 case 4:
2808 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2809 break;
2810 case 5:
2811 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2812 break;
2813 }
2814
2815 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2816 amdgpu_crtc->adjusted_clock = 0;
2817 amdgpu_crtc->encoder = NULL;
2818 amdgpu_crtc->connector = NULL;
2819 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2820
2821 return 0;
2822 }
2823
2824 static int dce_v11_0_early_init(void *handle)
2825 {
2826 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2827
2828 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2829 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2830
2831 dce_v11_0_set_display_funcs(adev);
2832
2833 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
2834
2835 switch (adev->asic_type) {
2836 case CHIP_CARRIZO:
2837 adev->mode_info.num_hpd = 6;
2838 adev->mode_info.num_dig = 9;
2839 break;
2840 case CHIP_STONEY:
2841 adev->mode_info.num_hpd = 6;
2842 adev->mode_info.num_dig = 9;
2843 break;
2844 case CHIP_POLARIS10:
2845 case CHIP_VEGAM:
2846 adev->mode_info.num_hpd = 6;
2847 adev->mode_info.num_dig = 6;
2848 break;
2849 case CHIP_POLARIS11:
2850 case CHIP_POLARIS12:
2851 adev->mode_info.num_hpd = 5;
2852 adev->mode_info.num_dig = 5;
2853 break;
2854 default:
2855 /* FIXME: not supported yet */
2856 return -EINVAL;
2857 }
2858
2859 dce_v11_0_set_irq_funcs(adev);
2860
2861 return 0;
2862 }
2863
2864 static int dce_v11_0_sw_init(void *handle)
2865 {
2866 int r, i;
2867 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2868
2869 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2870 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2871 if (r)
2872 return r;
2873 }
2874
2875 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2876 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2877 if (r)
2878 return r;
2879 }
2880
2881 /* HPD hotplug */
2882 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2883 if (r)
2884 return r;
2885
2886 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2887
2888 adev->ddev->mode_config.async_page_flip = true;
2889
2890 adev->ddev->mode_config.max_width = 16384;
2891 adev->ddev->mode_config.max_height = 16384;
2892
2893 adev->ddev->mode_config.preferred_depth = 24;
2894 adev->ddev->mode_config.prefer_shadow = 1;
2895
2896 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2897
2898 r = amdgpu_display_modeset_create_props(adev);
2899 if (r)
2900 return r;
2901
2902 adev->ddev->mode_config.max_width = 16384;
2903 adev->ddev->mode_config.max_height = 16384;
2904
2905
2906 /* allocate crtcs */
2907 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2908 r = dce_v11_0_crtc_init(adev, i);
2909 if (r)
2910 return r;
2911 }
2912
2913 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2914 amdgpu_display_print_display_setup(adev->ddev);
2915 else
2916 return -EINVAL;
2917
2918 /* setup afmt */
2919 r = dce_v11_0_afmt_init(adev);
2920 if (r)
2921 return r;
2922
2923 r = dce_v11_0_audio_init(adev);
2924 if (r)
2925 return r;
2926
2927 drm_kms_helper_poll_init(adev->ddev);
2928
2929 adev->mode_info.mode_config_initialized = true;
2930 return 0;
2931 }
2932
2933 static int dce_v11_0_sw_fini(void *handle)
2934 {
2935 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2936
2937 kfree(adev->mode_info.bios_hardcoded_edid);
2938
2939 drm_kms_helper_poll_fini(adev->ddev);
2940
2941 dce_v11_0_audio_fini(adev);
2942
2943 dce_v11_0_afmt_fini(adev);
2944
2945 drm_mode_config_cleanup(adev->ddev);
2946 adev->mode_info.mode_config_initialized = false;
2947
2948 return 0;
2949 }
2950
2951 static int dce_v11_0_hw_init(void *handle)
2952 {
2953 int i;
2954 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2955
2956 dce_v11_0_init_golden_registers(adev);
2957
2958 /* disable vga render */
2959 dce_v11_0_set_vga_render_state(adev, false);
2960 /* init dig PHYs, disp eng pll */
2961 amdgpu_atombios_crtc_powergate_init(adev);
2962 amdgpu_atombios_encoder_init_dig(adev);
2963 if ((adev->asic_type == CHIP_POLARIS10) ||
2964 (adev->asic_type == CHIP_POLARIS11) ||
2965 (adev->asic_type == CHIP_POLARIS12) ||
2966 (adev->asic_type == CHIP_VEGAM)) {
2967 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
2968 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
2969 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
2970 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
2971 } else {
2972 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2973 }
2974
2975 /* initialize hpd */
2976 dce_v11_0_hpd_init(adev);
2977
2978 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2979 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2980 }
2981
2982 dce_v11_0_pageflip_interrupt_init(adev);
2983
2984 return 0;
2985 }
2986
2987 static int dce_v11_0_hw_fini(void *handle)
2988 {
2989 int i;
2990 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2991
2992 dce_v11_0_hpd_fini(adev);
2993
2994 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2995 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2996 }
2997
2998 dce_v11_0_pageflip_interrupt_fini(adev);
2999
3000 return 0;
3001 }
3002
3003 static int dce_v11_0_suspend(void *handle)
3004 {
3005 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3006
3007 adev->mode_info.bl_level =
3008 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
3009
3010 return dce_v11_0_hw_fini(handle);
3011 }
3012
3013 static int dce_v11_0_resume(void *handle)
3014 {
3015 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3016 int ret;
3017
3018 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
3019 adev->mode_info.bl_level);
3020
3021 ret = dce_v11_0_hw_init(handle);
3022
3023 /* turn on the BL */
3024 if (adev->mode_info.bl_encoder) {
3025 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3026 adev->mode_info.bl_encoder);
3027 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3028 bl_level);
3029 }
3030
3031 return ret;
3032 }
3033
3034 static bool dce_v11_0_is_idle(void *handle)
3035 {
3036 return true;
3037 }
3038
3039 static int dce_v11_0_wait_for_idle(void *handle)
3040 {
3041 return 0;
3042 }
3043
3044 static int dce_v11_0_soft_reset(void *handle)
3045 {
3046 u32 srbm_soft_reset = 0, tmp;
3047 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3048
3049 if (dce_v11_0_is_display_hung(adev))
3050 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3051
3052 if (srbm_soft_reset) {
3053 tmp = RREG32(mmSRBM_SOFT_RESET);
3054 tmp |= srbm_soft_reset;
3055 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3056 WREG32(mmSRBM_SOFT_RESET, tmp);
3057 tmp = RREG32(mmSRBM_SOFT_RESET);
3058
3059 udelay(50);
3060
3061 tmp &= ~srbm_soft_reset;
3062 WREG32(mmSRBM_SOFT_RESET, tmp);
3063 tmp = RREG32(mmSRBM_SOFT_RESET);
3064
3065 /* Wait a little for things to settle down */
3066 udelay(50);
3067 }
3068 return 0;
3069 }
3070
3071 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3072 int crtc,
3073 enum amdgpu_interrupt_state state)
3074 {
3075 u32 lb_interrupt_mask;
3076
3077 if (crtc >= adev->mode_info.num_crtc) {
3078 DRM_DEBUG("invalid crtc %d\n", crtc);
3079 return;
3080 }
3081
3082 switch (state) {
3083 case AMDGPU_IRQ_STATE_DISABLE:
3084 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3085 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3086 VBLANK_INTERRUPT_MASK, 0);
3087 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3088 break;
3089 case AMDGPU_IRQ_STATE_ENABLE:
3090 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3091 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3092 VBLANK_INTERRUPT_MASK, 1);
3093 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3094 break;
3095 default:
3096 break;
3097 }
3098 }
3099
3100 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3101 int crtc,
3102 enum amdgpu_interrupt_state state)
3103 {
3104 u32 lb_interrupt_mask;
3105
3106 if (crtc >= adev->mode_info.num_crtc) {
3107 DRM_DEBUG("invalid crtc %d\n", crtc);
3108 return;
3109 }
3110
3111 switch (state) {
3112 case AMDGPU_IRQ_STATE_DISABLE:
3113 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3114 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3115 VLINE_INTERRUPT_MASK, 0);
3116 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3117 break;
3118 case AMDGPU_IRQ_STATE_ENABLE:
3119 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3120 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3121 VLINE_INTERRUPT_MASK, 1);
3122 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3123 break;
3124 default:
3125 break;
3126 }
3127 }
3128
3129 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3130 struct amdgpu_irq_src *source,
3131 unsigned hpd,
3132 enum amdgpu_interrupt_state state)
3133 {
3134 u32 tmp;
3135
3136 if (hpd >= adev->mode_info.num_hpd) {
3137 DRM_DEBUG("invalid hdp %d\n", hpd);
3138 return 0;
3139 }
3140
3141 switch (state) {
3142 case AMDGPU_IRQ_STATE_DISABLE:
3143 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3144 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3145 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3146 break;
3147 case AMDGPU_IRQ_STATE_ENABLE:
3148 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3149 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3150 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3151 break;
3152 default:
3153 break;
3154 }
3155
3156 return 0;
3157 }
3158
3159 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3160 struct amdgpu_irq_src *source,
3161 unsigned type,
3162 enum amdgpu_interrupt_state state)
3163 {
3164 switch (type) {
3165 case AMDGPU_CRTC_IRQ_VBLANK1:
3166 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3167 break;
3168 case AMDGPU_CRTC_IRQ_VBLANK2:
3169 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3170 break;
3171 case AMDGPU_CRTC_IRQ_VBLANK3:
3172 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3173 break;
3174 case AMDGPU_CRTC_IRQ_VBLANK4:
3175 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3176 break;
3177 case AMDGPU_CRTC_IRQ_VBLANK5:
3178 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3179 break;
3180 case AMDGPU_CRTC_IRQ_VBLANK6:
3181 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3182 break;
3183 case AMDGPU_CRTC_IRQ_VLINE1:
3184 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3185 break;
3186 case AMDGPU_CRTC_IRQ_VLINE2:
3187 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3188 break;
3189 case AMDGPU_CRTC_IRQ_VLINE3:
3190 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3191 break;
3192 case AMDGPU_CRTC_IRQ_VLINE4:
3193 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3194 break;
3195 case AMDGPU_CRTC_IRQ_VLINE5:
3196 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3197 break;
3198 case AMDGPU_CRTC_IRQ_VLINE6:
3199 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3200 break;
3201 default:
3202 break;
3203 }
3204 return 0;
3205 }
3206
3207 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3208 struct amdgpu_irq_src *src,
3209 unsigned type,
3210 enum amdgpu_interrupt_state state)
3211 {
3212 u32 reg;
3213
3214 if (type >= adev->mode_info.num_crtc) {
3215 DRM_ERROR("invalid pageflip crtc %d\n", type);
3216 return -EINVAL;
3217 }
3218
3219 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3220 if (state == AMDGPU_IRQ_STATE_DISABLE)
3221 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3222 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3223 else
3224 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3225 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3226
3227 return 0;
3228 }
3229
3230 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3231 struct amdgpu_irq_src *source,
3232 struct amdgpu_iv_entry *entry)
3233 {
3234 unsigned long flags;
3235 unsigned crtc_id;
3236 struct amdgpu_crtc *amdgpu_crtc;
3237 struct amdgpu_flip_work *works;
3238
3239 crtc_id = (entry->src_id - 8) >> 1;
3240 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3241
3242 if (crtc_id >= adev->mode_info.num_crtc) {
3243 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3244 return -EINVAL;
3245 }
3246
3247 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3248 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3249 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3250 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3251
3252 /* IRQ could occur when in initial stage */
3253 if(amdgpu_crtc == NULL)
3254 return 0;
3255
3256 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3257 works = amdgpu_crtc->pflip_works;
3258 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3259 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3260 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3261 amdgpu_crtc->pflip_status,
3262 AMDGPU_FLIP_SUBMITTED);
3263 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3264 return 0;
3265 }
3266
3267 /* page flip completed. clean up */
3268 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3269 amdgpu_crtc->pflip_works = NULL;
3270
3271 /* wakeup usersapce */
3272 if(works->event)
3273 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3274
3275 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3276
3277 drm_crtc_vblank_put(&amdgpu_crtc->base);
3278 schedule_work(&works->unpin_work);
3279
3280 return 0;
3281 }
3282
3283 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3284 int hpd)
3285 {
3286 u32 tmp;
3287
3288 if (hpd >= adev->mode_info.num_hpd) {
3289 DRM_DEBUG("invalid hdp %d\n", hpd);
3290 return;
3291 }
3292
3293 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3294 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3295 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3296 }
3297
3298 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3299 int crtc)
3300 {
3301 u32 tmp;
3302
3303 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3304 DRM_DEBUG("invalid crtc %d\n", crtc);
3305 return;
3306 }
3307
3308 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3309 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3310 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3311 }
3312
3313 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3314 int crtc)
3315 {
3316 u32 tmp;
3317
3318 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3319 DRM_DEBUG("invalid crtc %d\n", crtc);
3320 return;
3321 }
3322
3323 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3324 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3325 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3326 }
3327
3328 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3329 struct amdgpu_irq_src *source,
3330 struct amdgpu_iv_entry *entry)
3331 {
3332 unsigned crtc = entry->src_id - 1;
3333 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3334 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3335 crtc);
3336
3337 switch (entry->src_data[0]) {
3338 case 0: /* vblank */
3339 if (disp_int & interrupt_status_offsets[crtc].vblank)
3340 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3341 else
3342 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3343
3344 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3345 drm_handle_vblank(adev->ddev, crtc);
3346 }
3347 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3348
3349 break;
3350 case 1: /* vline */
3351 if (disp_int & interrupt_status_offsets[crtc].vline)
3352 dce_v11_0_crtc_vline_int_ack(adev, crtc);
3353 else
3354 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3355
3356 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3357
3358 break;
3359 default:
3360 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3361 break;
3362 }
3363
3364 return 0;
3365 }
3366
3367 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3368 struct amdgpu_irq_src *source,
3369 struct amdgpu_iv_entry *entry)
3370 {
3371 uint32_t disp_int, mask;
3372 unsigned hpd;
3373
3374 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3375 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3376 return 0;
3377 }
3378
3379 hpd = entry->src_data[0];
3380 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3381 mask = interrupt_status_offsets[hpd].hpd;
3382
3383 if (disp_int & mask) {
3384 dce_v11_0_hpd_int_ack(adev, hpd);
3385 schedule_work(&adev->hotplug_work);
3386 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3387 }
3388
3389 return 0;
3390 }
3391
3392 static int dce_v11_0_set_clockgating_state(void *handle,
3393 enum amd_clockgating_state state)
3394 {
3395 return 0;
3396 }
3397
3398 static int dce_v11_0_set_powergating_state(void *handle,
3399 enum amd_powergating_state state)
3400 {
3401 return 0;
3402 }
3403
3404 static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3405 .name = "dce_v11_0",
3406 .early_init = dce_v11_0_early_init,
3407 .late_init = NULL,
3408 .sw_init = dce_v11_0_sw_init,
3409 .sw_fini = dce_v11_0_sw_fini,
3410 .hw_init = dce_v11_0_hw_init,
3411 .hw_fini = dce_v11_0_hw_fini,
3412 .suspend = dce_v11_0_suspend,
3413 .resume = dce_v11_0_resume,
3414 .is_idle = dce_v11_0_is_idle,
3415 .wait_for_idle = dce_v11_0_wait_for_idle,
3416 .soft_reset = dce_v11_0_soft_reset,
3417 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3418 .set_powergating_state = dce_v11_0_set_powergating_state,
3419 };
3420
3421 static void
3422 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3423 struct drm_display_mode *mode,
3424 struct drm_display_mode *adjusted_mode)
3425 {
3426 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3427
3428 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3429
3430 /* need to call this here rather than in prepare() since we need some crtc info */
3431 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3432
3433 /* set scaler clears this on some chips */
3434 dce_v11_0_set_interleave(encoder->crtc, mode);
3435
3436 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3437 dce_v11_0_afmt_enable(encoder, true);
3438 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3439 }
3440 }
3441
3442 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3443 {
3444 struct amdgpu_device *adev = encoder->dev->dev_private;
3445 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3446 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3447
3448 if ((amdgpu_encoder->active_device &
3449 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3450 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3451 ENCODER_OBJECT_ID_NONE)) {
3452 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3453 if (dig) {
3454 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3455 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3456 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3457 }
3458 }
3459
3460 amdgpu_atombios_scratch_regs_lock(adev, true);
3461
3462 if (connector) {
3463 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3464
3465 /* select the clock/data port if it uses a router */
3466 if (amdgpu_connector->router.cd_valid)
3467 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3468
3469 /* turn eDP panel on for mode set */
3470 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3471 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3472 ATOM_TRANSMITTER_ACTION_POWER_ON);
3473 }
3474
3475 /* this is needed for the pll/ss setup to work correctly in some cases */
3476 amdgpu_atombios_encoder_set_crtc_source(encoder);
3477 /* set up the FMT blocks */
3478 dce_v11_0_program_fmt(encoder);
3479 }
3480
3481 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3482 {
3483 struct drm_device *dev = encoder->dev;
3484 struct amdgpu_device *adev = dev->dev_private;
3485
3486 /* need to call this here as we need the crtc set up */
3487 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3488 amdgpu_atombios_scratch_regs_lock(adev, false);
3489 }
3490
3491 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3492 {
3493 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3494 struct amdgpu_encoder_atom_dig *dig;
3495
3496 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3497
3498 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3499 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3500 dce_v11_0_afmt_enable(encoder, false);
3501 dig = amdgpu_encoder->enc_priv;
3502 dig->dig_encoder = -1;
3503 }
3504 amdgpu_encoder->active_device = 0;
3505 }
3506
3507 /* these are handled by the primary encoders */
3508 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3509 {
3510
3511 }
3512
3513 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3514 {
3515
3516 }
3517
3518 static void
3519 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3520 struct drm_display_mode *mode,
3521 struct drm_display_mode *adjusted_mode)
3522 {
3523
3524 }
3525
3526 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3527 {
3528
3529 }
3530
3531 static void
3532 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3533 {
3534
3535 }
3536
3537 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3538 .dpms = dce_v11_0_ext_dpms,
3539 .prepare = dce_v11_0_ext_prepare,
3540 .mode_set = dce_v11_0_ext_mode_set,
3541 .commit = dce_v11_0_ext_commit,
3542 .disable = dce_v11_0_ext_disable,
3543 /* no detect for TMDS/LVDS yet */
3544 };
3545
3546 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3547 .dpms = amdgpu_atombios_encoder_dpms,
3548 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3549 .prepare = dce_v11_0_encoder_prepare,
3550 .mode_set = dce_v11_0_encoder_mode_set,
3551 .commit = dce_v11_0_encoder_commit,
3552 .disable = dce_v11_0_encoder_disable,
3553 .detect = amdgpu_atombios_encoder_dig_detect,
3554 };
3555
3556 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3557 .dpms = amdgpu_atombios_encoder_dpms,
3558 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3559 .prepare = dce_v11_0_encoder_prepare,
3560 .mode_set = dce_v11_0_encoder_mode_set,
3561 .commit = dce_v11_0_encoder_commit,
3562 .detect = amdgpu_atombios_encoder_dac_detect,
3563 };
3564
3565 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3566 {
3567 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3568 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3569 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3570 kfree(amdgpu_encoder->enc_priv);
3571 drm_encoder_cleanup(encoder);
3572 kfree(amdgpu_encoder);
3573 }
3574
3575 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3576 .destroy = dce_v11_0_encoder_destroy,
3577 };
3578
3579 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3580 uint32_t encoder_enum,
3581 uint32_t supported_device,
3582 u16 caps)
3583 {
3584 struct drm_device *dev = adev->ddev;
3585 struct drm_encoder *encoder;
3586 struct amdgpu_encoder *amdgpu_encoder;
3587
3588 /* see if we already added it */
3589 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3590 amdgpu_encoder = to_amdgpu_encoder(encoder);
3591 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3592 amdgpu_encoder->devices |= supported_device;
3593 return;
3594 }
3595
3596 }
3597
3598 /* add a new one */
3599 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3600 if (!amdgpu_encoder)
3601 return;
3602
3603 encoder = &amdgpu_encoder->base;
3604 switch (adev->mode_info.num_crtc) {
3605 case 1:
3606 encoder->possible_crtcs = 0x1;
3607 break;
3608 case 2:
3609 default:
3610 encoder->possible_crtcs = 0x3;
3611 break;
3612 case 3:
3613 encoder->possible_crtcs = 0x7;
3614 break;
3615 case 4:
3616 encoder->possible_crtcs = 0xf;
3617 break;
3618 case 5:
3619 encoder->possible_crtcs = 0x1f;
3620 break;
3621 case 6:
3622 encoder->possible_crtcs = 0x3f;
3623 break;
3624 }
3625
3626 amdgpu_encoder->enc_priv = NULL;
3627
3628 amdgpu_encoder->encoder_enum = encoder_enum;
3629 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3630 amdgpu_encoder->devices = supported_device;
3631 amdgpu_encoder->rmx_type = RMX_OFF;
3632 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3633 amdgpu_encoder->is_ext_encoder = false;
3634 amdgpu_encoder->caps = caps;
3635
3636 switch (amdgpu_encoder->encoder_id) {
3637 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3638 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3639 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3640 DRM_MODE_ENCODER_DAC, NULL);
3641 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3642 break;
3643 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3644 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3645 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3646 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3647 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3648 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3649 amdgpu_encoder->rmx_type = RMX_FULL;
3650 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3651 DRM_MODE_ENCODER_LVDS, NULL);
3652 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3653 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3654 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3655 DRM_MODE_ENCODER_DAC, NULL);
3656 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3657 } else {
3658 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3659 DRM_MODE_ENCODER_TMDS, NULL);
3660 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3661 }
3662 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3663 break;
3664 case ENCODER_OBJECT_ID_SI170B:
3665 case ENCODER_OBJECT_ID_CH7303:
3666 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3667 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3668 case ENCODER_OBJECT_ID_TITFP513:
3669 case ENCODER_OBJECT_ID_VT1623:
3670 case ENCODER_OBJECT_ID_HDMI_SI1930:
3671 case ENCODER_OBJECT_ID_TRAVIS:
3672 case ENCODER_OBJECT_ID_NUTMEG:
3673 /* these are handled by the primary encoders */
3674 amdgpu_encoder->is_ext_encoder = true;
3675 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3676 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3677 DRM_MODE_ENCODER_LVDS, NULL);
3678 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3679 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3680 DRM_MODE_ENCODER_DAC, NULL);
3681 else
3682 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3683 DRM_MODE_ENCODER_TMDS, NULL);
3684 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3685 break;
3686 }
3687 }
3688
3689 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3690 .bandwidth_update = &dce_v11_0_bandwidth_update,
3691 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3692 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3693 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3694 .hpd_sense = &dce_v11_0_hpd_sense,
3695 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3696 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3697 .page_flip = &dce_v11_0_page_flip,
3698 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3699 .add_encoder = &dce_v11_0_encoder_add,
3700 .add_connector = &amdgpu_connector_add,
3701 };
3702
3703 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3704 {
3705 if (adev->mode_info.funcs == NULL)
3706 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3707 }
3708
3709 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3710 .set = dce_v11_0_set_crtc_irq_state,
3711 .process = dce_v11_0_crtc_irq,
3712 };
3713
3714 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3715 .set = dce_v11_0_set_pageflip_irq_state,
3716 .process = dce_v11_0_pageflip_irq,
3717 };
3718
3719 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3720 .set = dce_v11_0_set_hpd_irq_state,
3721 .process = dce_v11_0_hpd_irq,
3722 };
3723
3724 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3725 {
3726 if (adev->mode_info.num_crtc > 0)
3727 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3728 else
3729 adev->crtc_irq.num_types = 0;
3730 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3731
3732 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3733 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3734
3735 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3736 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3737 }
3738
3739 const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3740 {
3741 .type = AMD_IP_BLOCK_TYPE_DCE,
3742 .major = 11,
3743 .minor = 0,
3744 .rev = 0,
3745 .funcs = &dce_v11_0_ip_funcs,
3746 };
3747
3748 const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3749 {
3750 .type = AMD_IP_BLOCK_TYPE_DCE,
3751 .major = 11,
3752 .minor = 2,
3753 .rev = 0,
3754 .funcs = &dce_v11_0_ip_funcs,
3755 };
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