2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
34 #include "amdgpu_display.h"
35 #include "dce_v11_0.h"
37 #include "dce/dce_11_0_d.h"
38 #include "dce/dce_11_0_sh_mask.h"
39 #include "dce/dce_11_0_enum.h"
40 #include "oss/oss_3_0_d.h"
41 #include "oss/oss_3_0_sh_mask.h"
42 #include "gmc/gmc_8_1_d.h"
43 #include "gmc/gmc_8_1_sh_mask.h"
45 #include "ivsrcid/ivsrcid_vislands30.h"
47 static void dce_v11_0_set_display_funcs(struct amdgpu_device
*adev
);
48 static void dce_v11_0_set_irq_funcs(struct amdgpu_device
*adev
);
50 static const u32 crtc_offsets
[] =
52 CRTC0_REGISTER_OFFSET
,
53 CRTC1_REGISTER_OFFSET
,
54 CRTC2_REGISTER_OFFSET
,
55 CRTC3_REGISTER_OFFSET
,
56 CRTC4_REGISTER_OFFSET
,
57 CRTC5_REGISTER_OFFSET
,
61 static const u32 hpd_offsets
[] =
71 static const uint32_t dig_offsets
[] = {
89 } interrupt_status_offsets
[] = { {
90 .reg
= mmDISP_INTERRUPT_STATUS
,
91 .vblank
= DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK
,
92 .vline
= DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK
,
93 .hpd
= DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
95 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE
,
96 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK
,
97 .vline
= DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK
,
98 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
100 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE2
,
101 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK
,
102 .vline
= DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK
,
103 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
105 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE3
,
106 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK
,
107 .vline
= DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK
,
108 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
110 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE4
,
111 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK
,
112 .vline
= DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK
,
113 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
115 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE5
,
116 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK
,
117 .vline
= DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK
,
118 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
121 static const u32 cz_golden_settings_a11
[] =
123 mmCRTC_DOUBLE_BUFFER_CONTROL
, 0x00010101, 0x00010000,
124 mmFBC_MISC
, 0x1f311fff, 0x14300000,
127 static const u32 cz_mgcg_cgcg_init
[] =
129 mmXDMA_CLOCK_GATING_CNTL
, 0xffffffff, 0x00000100,
130 mmXDMA_MEM_POWER_CNTL
, 0x00000101, 0x00000000,
133 static const u32 stoney_golden_settings_a11
[] =
135 mmCRTC_DOUBLE_BUFFER_CONTROL
, 0x00010101, 0x00010000,
136 mmFBC_MISC
, 0x1f311fff, 0x14302000,
139 static const u32 polaris11_golden_settings_a11
[] =
141 mmDCI_CLK_CNTL
, 0x00000080, 0x00000000,
142 mmFBC_DEBUG_COMP
, 0x000000f0, 0x00000070,
143 mmFBC_DEBUG1
, 0xffffffff, 0x00000008,
144 mmFBC_MISC
, 0x9f313fff, 0x14302008,
145 mmHDMI_CONTROL
, 0x313f031f, 0x00000011,
148 static const u32 polaris10_golden_settings_a11
[] =
150 mmDCI_CLK_CNTL
, 0x00000080, 0x00000000,
151 mmFBC_DEBUG_COMP
, 0x000000f0, 0x00000070,
152 mmFBC_MISC
, 0x9f313fff, 0x14302008,
153 mmHDMI_CONTROL
, 0x313f031f, 0x00000011,
156 static void dce_v11_0_init_golden_registers(struct amdgpu_device
*adev
)
158 switch (adev
->asic_type
) {
160 amdgpu_device_program_register_sequence(adev
,
162 ARRAY_SIZE(cz_mgcg_cgcg_init
));
163 amdgpu_device_program_register_sequence(adev
,
164 cz_golden_settings_a11
,
165 ARRAY_SIZE(cz_golden_settings_a11
));
168 amdgpu_device_program_register_sequence(adev
,
169 stoney_golden_settings_a11
,
170 ARRAY_SIZE(stoney_golden_settings_a11
));
174 amdgpu_device_program_register_sequence(adev
,
175 polaris11_golden_settings_a11
,
176 ARRAY_SIZE(polaris11_golden_settings_a11
));
180 amdgpu_device_program_register_sequence(adev
,
181 polaris10_golden_settings_a11
,
182 ARRAY_SIZE(polaris10_golden_settings_a11
));
189 static u32
dce_v11_0_audio_endpt_rreg(struct amdgpu_device
*adev
,
190 u32 block_offset
, u32 reg
)
195 spin_lock_irqsave(&adev
->audio_endpt_idx_lock
, flags
);
196 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
197 r
= RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA
+ block_offset
);
198 spin_unlock_irqrestore(&adev
->audio_endpt_idx_lock
, flags
);
203 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device
*adev
,
204 u32 block_offset
, u32 reg
, u32 v
)
208 spin_lock_irqsave(&adev
->audio_endpt_idx_lock
, flags
);
209 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
210 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA
+ block_offset
, v
);
211 spin_unlock_irqrestore(&adev
->audio_endpt_idx_lock
, flags
);
214 static u32
dce_v11_0_vblank_get_counter(struct amdgpu_device
*adev
, int crtc
)
216 if (crtc
< 0 || crtc
>= adev
->mode_info
.num_crtc
)
219 return RREG32(mmCRTC_STATUS_FRAME_COUNT
+ crtc_offsets
[crtc
]);
222 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device
*adev
)
226 /* Enable pflip interrupts */
227 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++)
228 amdgpu_irq_get(adev
, &adev
->pageflip_irq
, i
);
231 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device
*adev
)
235 /* Disable pflip interrupts */
236 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++)
237 amdgpu_irq_put(adev
, &adev
->pageflip_irq
, i
);
241 * dce_v11_0_page_flip - pageflip callback.
243 * @adev: amdgpu_device pointer
244 * @crtc_id: crtc to cleanup pageflip on
245 * @crtc_base: new address of the crtc (GPU MC address)
247 * Triggers the actual pageflip by updating the primary
248 * surface base address.
250 static void dce_v11_0_page_flip(struct amdgpu_device
*adev
,
251 int crtc_id
, u64 crtc_base
, bool async
)
253 struct amdgpu_crtc
*amdgpu_crtc
= adev
->mode_info
.crtcs
[crtc_id
];
256 /* flip immediate for async, default is vsync */
257 tmp
= RREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
);
258 tmp
= REG_SET_FIELD(tmp
, GRPH_FLIP_CONTROL
,
259 GRPH_SURFACE_UPDATE_IMMEDIATE_EN
, async
? 1 : 0);
260 WREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
261 /* update the scanout addresses */
262 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
263 upper_32_bits(crtc_base
));
264 /* writing to the low address triggers the update */
265 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
266 lower_32_bits(crtc_base
));
268 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
);
271 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device
*adev
, int crtc
,
272 u32
*vbl
, u32
*position
)
274 if ((crtc
< 0) || (crtc
>= adev
->mode_info
.num_crtc
))
277 *vbl
= RREG32(mmCRTC_V_BLANK_START_END
+ crtc_offsets
[crtc
]);
278 *position
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
284 * dce_v11_0_hpd_sense - hpd sense callback.
286 * @adev: amdgpu_device pointer
287 * @hpd: hpd (hotplug detect) pin
289 * Checks if a digital monitor is connected (evergreen+).
290 * Returns true if connected, false if not connected.
292 static bool dce_v11_0_hpd_sense(struct amdgpu_device
*adev
,
293 enum amdgpu_hpd_id hpd
)
295 bool connected
= false;
297 if (hpd
>= adev
->mode_info
.num_hpd
)
300 if (RREG32(mmDC_HPD_INT_STATUS
+ hpd_offsets
[hpd
]) &
301 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK
)
308 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
310 * @adev: amdgpu_device pointer
311 * @hpd: hpd (hotplug detect) pin
313 * Set the polarity of the hpd pin (evergreen+).
315 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device
*adev
,
316 enum amdgpu_hpd_id hpd
)
319 bool connected
= dce_v11_0_hpd_sense(adev
, hpd
);
321 if (hpd
>= adev
->mode_info
.num_hpd
)
324 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
326 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_POLARITY
, 0);
328 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_POLARITY
, 1);
329 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
333 * dce_v11_0_hpd_init - hpd setup callback.
335 * @adev: amdgpu_device pointer
337 * Setup the hpd pins used by the card (evergreen+).
338 * Enable the pin, set the polarity, and enable the hpd interrupts.
340 static void dce_v11_0_hpd_init(struct amdgpu_device
*adev
)
342 struct drm_device
*dev
= adev
->ddev
;
343 struct drm_connector
*connector
;
346 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
347 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
349 if (amdgpu_connector
->hpd
.hpd
>= adev
->mode_info
.num_hpd
)
352 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
||
353 connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
354 /* don't try to enable hpd on eDP or LVDS avoid breaking the
355 * aux dp channel on imac and help (but not completely fix)
356 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
357 * also avoid interrupt storms during dpms.
359 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[amdgpu_connector
->hpd
.hpd
]);
360 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_EN
, 0);
361 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[amdgpu_connector
->hpd
.hpd
], tmp
);
365 tmp
= RREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[amdgpu_connector
->hpd
.hpd
]);
366 tmp
= REG_SET_FIELD(tmp
, DC_HPD_CONTROL
, DC_HPD_EN
, 1);
367 WREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[amdgpu_connector
->hpd
.hpd
], tmp
);
369 tmp
= RREG32(mmDC_HPD_TOGGLE_FILT_CNTL
+ hpd_offsets
[amdgpu_connector
->hpd
.hpd
]);
370 tmp
= REG_SET_FIELD(tmp
, DC_HPD_TOGGLE_FILT_CNTL
,
371 DC_HPD_CONNECT_INT_DELAY
,
372 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS
);
373 tmp
= REG_SET_FIELD(tmp
, DC_HPD_TOGGLE_FILT_CNTL
,
374 DC_HPD_DISCONNECT_INT_DELAY
,
375 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS
);
376 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL
+ hpd_offsets
[amdgpu_connector
->hpd
.hpd
], tmp
);
378 dce_v11_0_hpd_set_polarity(adev
, amdgpu_connector
->hpd
.hpd
);
379 amdgpu_irq_get(adev
, &adev
->hpd_irq
, amdgpu_connector
->hpd
.hpd
);
384 * dce_v11_0_hpd_fini - hpd tear down callback.
386 * @adev: amdgpu_device pointer
388 * Tear down the hpd pins used by the card (evergreen+).
389 * Disable the hpd interrupts.
391 static void dce_v11_0_hpd_fini(struct amdgpu_device
*adev
)
393 struct drm_device
*dev
= adev
->ddev
;
394 struct drm_connector
*connector
;
397 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
398 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
400 if (amdgpu_connector
->hpd
.hpd
>= adev
->mode_info
.num_hpd
)
403 tmp
= RREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[amdgpu_connector
->hpd
.hpd
]);
404 tmp
= REG_SET_FIELD(tmp
, DC_HPD_CONTROL
, DC_HPD_EN
, 0);
405 WREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[amdgpu_connector
->hpd
.hpd
], tmp
);
407 amdgpu_irq_put(adev
, &adev
->hpd_irq
, amdgpu_connector
->hpd
.hpd
);
411 static u32
dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device
*adev
)
413 return mmDC_GPIO_HPD_A
;
416 static bool dce_v11_0_is_display_hung(struct amdgpu_device
*adev
)
422 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
423 tmp
= RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]);
424 if (REG_GET_FIELD(tmp
, CRTC_CONTROL
, CRTC_MASTER_EN
)) {
425 crtc_status
[i
] = RREG32(mmCRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
426 crtc_hung
|= (1 << i
);
430 for (j
= 0; j
< 10; j
++) {
431 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
432 if (crtc_hung
& (1 << i
)) {
433 tmp
= RREG32(mmCRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
434 if (tmp
!= crtc_status
[i
])
435 crtc_hung
&= ~(1 << i
);
446 static void dce_v11_0_set_vga_render_state(struct amdgpu_device
*adev
,
451 /* Lockout access through VGA aperture*/
452 tmp
= RREG32(mmVGA_HDP_CONTROL
);
454 tmp
= REG_SET_FIELD(tmp
, VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
, 0);
456 tmp
= REG_SET_FIELD(tmp
, VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
, 1);
457 WREG32(mmVGA_HDP_CONTROL
, tmp
);
459 /* disable VGA render */
460 tmp
= RREG32(mmVGA_RENDER_CONTROL
);
462 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 1);
464 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 0);
465 WREG32(mmVGA_RENDER_CONTROL
, tmp
);
468 static int dce_v11_0_get_num_crtc (struct amdgpu_device
*adev
)
472 switch (adev
->asic_type
) {
493 void dce_v11_0_disable_dce(struct amdgpu_device
*adev
)
495 /*Disable VGA render and enabled crtc, if has DCE engine*/
496 if (amdgpu_atombios_has_dce_engine_info(adev
)) {
500 dce_v11_0_set_vga_render_state(adev
, false);
503 for (i
= 0; i
< dce_v11_0_get_num_crtc(adev
); i
++) {
504 crtc_enabled
= REG_GET_FIELD(RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]),
505 CRTC_CONTROL
, CRTC_MASTER_EN
);
507 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
508 tmp
= RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]);
509 tmp
= REG_SET_FIELD(tmp
, CRTC_CONTROL
, CRTC_MASTER_EN
, 0);
510 WREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
], tmp
);
511 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
517 static void dce_v11_0_program_fmt(struct drm_encoder
*encoder
)
519 struct drm_device
*dev
= encoder
->dev
;
520 struct amdgpu_device
*adev
= dev
->dev_private
;
521 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
522 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
523 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
526 enum amdgpu_connector_dither dither
= AMDGPU_FMT_DITHER_DISABLE
;
529 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
530 bpc
= amdgpu_connector_get_monitor_bpc(connector
);
531 dither
= amdgpu_connector
->dither
;
534 /* LVDS/eDP FMT is set up by atom */
535 if (amdgpu_encoder
->devices
& ATOM_DEVICE_LCD_SUPPORT
)
538 /* not needed for analog */
539 if ((amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
) ||
540 (amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
))
548 if (dither
== AMDGPU_FMT_DITHER_ENABLE
) {
549 /* XXX sort out optimal dither settings */
550 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_FRAME_RANDOM_ENABLE
, 1);
551 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_HIGHPASS_RANDOM_ENABLE
, 1);
552 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_EN
, 1);
553 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_DEPTH
, 0);
555 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_EN
, 1);
556 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_DEPTH
, 0);
560 if (dither
== AMDGPU_FMT_DITHER_ENABLE
) {
561 /* XXX sort out optimal dither settings */
562 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_FRAME_RANDOM_ENABLE
, 1);
563 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_HIGHPASS_RANDOM_ENABLE
, 1);
564 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_RGB_RANDOM_ENABLE
, 1);
565 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_EN
, 1);
566 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_DEPTH
, 1);
568 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_EN
, 1);
569 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_DEPTH
, 1);
573 if (dither
== AMDGPU_FMT_DITHER_ENABLE
) {
574 /* XXX sort out optimal dither settings */
575 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_FRAME_RANDOM_ENABLE
, 1);
576 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_HIGHPASS_RANDOM_ENABLE
, 1);
577 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_RGB_RANDOM_ENABLE
, 1);
578 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_EN
, 1);
579 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_DEPTH
, 2);
581 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_EN
, 1);
582 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_DEPTH
, 2);
590 WREG32(mmFMT_BIT_DEPTH_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
594 /* display watermark setup */
596 * dce_v11_0_line_buffer_adjust - Set up the line buffer
598 * @adev: amdgpu_device pointer
599 * @amdgpu_crtc: the selected display controller
600 * @mode: the current display mode on the selected display
603 * Setup up the line buffer allocation for
604 * the selected display controller (CIK).
605 * Returns the line buffer size in pixels.
607 static u32
dce_v11_0_line_buffer_adjust(struct amdgpu_device
*adev
,
608 struct amdgpu_crtc
*amdgpu_crtc
,
609 struct drm_display_mode
*mode
)
611 u32 tmp
, buffer_alloc
, i
, mem_cfg
;
612 u32 pipe_offset
= amdgpu_crtc
->crtc_id
;
615 * There are 6 line buffers, one for each display controllers.
616 * There are 3 partitions per LB. Select the number of partitions
617 * to enable based on the display width. For display widths larger
618 * than 4096, you need use to use 2 display controllers and combine
619 * them using the stereo blender.
621 if (amdgpu_crtc
->base
.enabled
&& mode
) {
622 if (mode
->crtc_hdisplay
< 1920) {
625 } else if (mode
->crtc_hdisplay
< 2560) {
628 } else if (mode
->crtc_hdisplay
< 4096) {
630 buffer_alloc
= (adev
->flags
& AMD_IS_APU
) ? 2 : 4;
632 DRM_DEBUG_KMS("Mode too big for LB!\n");
634 buffer_alloc
= (adev
->flags
& AMD_IS_APU
) ? 2 : 4;
641 tmp
= RREG32(mmLB_MEMORY_CTRL
+ amdgpu_crtc
->crtc_offset
);
642 tmp
= REG_SET_FIELD(tmp
, LB_MEMORY_CTRL
, LB_MEMORY_CONFIG
, mem_cfg
);
643 WREG32(mmLB_MEMORY_CTRL
+ amdgpu_crtc
->crtc_offset
, tmp
);
645 tmp
= RREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
);
646 tmp
= REG_SET_FIELD(tmp
, PIPE0_DMIF_BUFFER_CONTROL
, DMIF_BUFFERS_ALLOCATED
, buffer_alloc
);
647 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
, tmp
);
649 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
650 tmp
= RREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
);
651 if (REG_GET_FIELD(tmp
, PIPE0_DMIF_BUFFER_CONTROL
, DMIF_BUFFERS_ALLOCATION_COMPLETED
))
656 if (amdgpu_crtc
->base
.enabled
&& mode
) {
668 /* controller not enabled, so no lb used */
673 * cik_get_number_of_dram_channels - get the number of dram channels
675 * @adev: amdgpu_device pointer
677 * Look up the number of video ram channels (CIK).
678 * Used for display watermark bandwidth calculations
679 * Returns the number of dram channels
681 static u32
cik_get_number_of_dram_channels(struct amdgpu_device
*adev
)
683 u32 tmp
= RREG32(mmMC_SHARED_CHMAP
);
685 switch (REG_GET_FIELD(tmp
, MC_SHARED_CHMAP
, NOOFCHAN
)) {
708 struct dce10_wm_params
{
709 u32 dram_channels
; /* number of dram channels */
710 u32 yclk
; /* bandwidth per dram data pin in kHz */
711 u32 sclk
; /* engine clock in kHz */
712 u32 disp_clk
; /* display clock in kHz */
713 u32 src_width
; /* viewport width */
714 u32 active_time
; /* active display time in ns */
715 u32 blank_time
; /* blank time in ns */
716 bool interlaced
; /* mode is interlaced */
717 fixed20_12 vsc
; /* vertical scale ratio */
718 u32 num_heads
; /* number of active crtcs */
719 u32 bytes_per_pixel
; /* bytes per pixel display + overlay */
720 u32 lb_size
; /* line buffer allocated to pipe */
721 u32 vtaps
; /* vertical scaler taps */
725 * dce_v11_0_dram_bandwidth - get the dram bandwidth
727 * @wm: watermark calculation data
729 * Calculate the raw dram bandwidth (CIK).
730 * Used for display watermark bandwidth calculations
731 * Returns the dram bandwidth in MBytes/s
733 static u32
dce_v11_0_dram_bandwidth(struct dce10_wm_params
*wm
)
735 /* Calculate raw DRAM Bandwidth */
736 fixed20_12 dram_efficiency
; /* 0.7 */
737 fixed20_12 yclk
, dram_channels
, bandwidth
;
740 a
.full
= dfixed_const(1000);
741 yclk
.full
= dfixed_const(wm
->yclk
);
742 yclk
.full
= dfixed_div(yclk
, a
);
743 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
744 a
.full
= dfixed_const(10);
745 dram_efficiency
.full
= dfixed_const(7);
746 dram_efficiency
.full
= dfixed_div(dram_efficiency
, a
);
747 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
748 bandwidth
.full
= dfixed_mul(bandwidth
, dram_efficiency
);
750 return dfixed_trunc(bandwidth
);
754 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
756 * @wm: watermark calculation data
758 * Calculate the dram bandwidth used for display (CIK).
759 * Used for display watermark bandwidth calculations
760 * Returns the dram bandwidth for display in MBytes/s
762 static u32
dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params
*wm
)
764 /* Calculate DRAM Bandwidth and the part allocated to display. */
765 fixed20_12 disp_dram_allocation
; /* 0.3 to 0.7 */
766 fixed20_12 yclk
, dram_channels
, bandwidth
;
769 a
.full
= dfixed_const(1000);
770 yclk
.full
= dfixed_const(wm
->yclk
);
771 yclk
.full
= dfixed_div(yclk
, a
);
772 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
773 a
.full
= dfixed_const(10);
774 disp_dram_allocation
.full
= dfixed_const(3); /* XXX worse case value 0.3 */
775 disp_dram_allocation
.full
= dfixed_div(disp_dram_allocation
, a
);
776 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
777 bandwidth
.full
= dfixed_mul(bandwidth
, disp_dram_allocation
);
779 return dfixed_trunc(bandwidth
);
783 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
785 * @wm: watermark calculation data
787 * Calculate the data return bandwidth used for display (CIK).
788 * Used for display watermark bandwidth calculations
789 * Returns the data return bandwidth in MBytes/s
791 static u32
dce_v11_0_data_return_bandwidth(struct dce10_wm_params
*wm
)
793 /* Calculate the display Data return Bandwidth */
794 fixed20_12 return_efficiency
; /* 0.8 */
795 fixed20_12 sclk
, bandwidth
;
798 a
.full
= dfixed_const(1000);
799 sclk
.full
= dfixed_const(wm
->sclk
);
800 sclk
.full
= dfixed_div(sclk
, a
);
801 a
.full
= dfixed_const(10);
802 return_efficiency
.full
= dfixed_const(8);
803 return_efficiency
.full
= dfixed_div(return_efficiency
, a
);
804 a
.full
= dfixed_const(32);
805 bandwidth
.full
= dfixed_mul(a
, sclk
);
806 bandwidth
.full
= dfixed_mul(bandwidth
, return_efficiency
);
808 return dfixed_trunc(bandwidth
);
812 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
814 * @wm: watermark calculation data
816 * Calculate the dmif bandwidth used for display (CIK).
817 * Used for display watermark bandwidth calculations
818 * Returns the dmif bandwidth in MBytes/s
820 static u32
dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params
*wm
)
822 /* Calculate the DMIF Request Bandwidth */
823 fixed20_12 disp_clk_request_efficiency
; /* 0.8 */
824 fixed20_12 disp_clk
, bandwidth
;
827 a
.full
= dfixed_const(1000);
828 disp_clk
.full
= dfixed_const(wm
->disp_clk
);
829 disp_clk
.full
= dfixed_div(disp_clk
, a
);
830 a
.full
= dfixed_const(32);
831 b
.full
= dfixed_mul(a
, disp_clk
);
833 a
.full
= dfixed_const(10);
834 disp_clk_request_efficiency
.full
= dfixed_const(8);
835 disp_clk_request_efficiency
.full
= dfixed_div(disp_clk_request_efficiency
, a
);
837 bandwidth
.full
= dfixed_mul(b
, disp_clk_request_efficiency
);
839 return dfixed_trunc(bandwidth
);
843 * dce_v11_0_available_bandwidth - get the min available bandwidth
845 * @wm: watermark calculation data
847 * Calculate the min available bandwidth used for display (CIK).
848 * Used for display watermark bandwidth calculations
849 * Returns the min available bandwidth in MBytes/s
851 static u32
dce_v11_0_available_bandwidth(struct dce10_wm_params
*wm
)
853 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
854 u32 dram_bandwidth
= dce_v11_0_dram_bandwidth(wm
);
855 u32 data_return_bandwidth
= dce_v11_0_data_return_bandwidth(wm
);
856 u32 dmif_req_bandwidth
= dce_v11_0_dmif_request_bandwidth(wm
);
858 return min(dram_bandwidth
, min(data_return_bandwidth
, dmif_req_bandwidth
));
862 * dce_v11_0_average_bandwidth - get the average available bandwidth
864 * @wm: watermark calculation data
866 * Calculate the average available bandwidth used for display (CIK).
867 * Used for display watermark bandwidth calculations
868 * Returns the average available bandwidth in MBytes/s
870 static u32
dce_v11_0_average_bandwidth(struct dce10_wm_params
*wm
)
872 /* Calculate the display mode Average Bandwidth
873 * DisplayMode should contain the source and destination dimensions,
877 fixed20_12 line_time
;
878 fixed20_12 src_width
;
879 fixed20_12 bandwidth
;
882 a
.full
= dfixed_const(1000);
883 line_time
.full
= dfixed_const(wm
->active_time
+ wm
->blank_time
);
884 line_time
.full
= dfixed_div(line_time
, a
);
885 bpp
.full
= dfixed_const(wm
->bytes_per_pixel
);
886 src_width
.full
= dfixed_const(wm
->src_width
);
887 bandwidth
.full
= dfixed_mul(src_width
, bpp
);
888 bandwidth
.full
= dfixed_mul(bandwidth
, wm
->vsc
);
889 bandwidth
.full
= dfixed_div(bandwidth
, line_time
);
891 return dfixed_trunc(bandwidth
);
895 * dce_v11_0_latency_watermark - get the latency watermark
897 * @wm: watermark calculation data
899 * Calculate the latency watermark (CIK).
900 * Used for display watermark bandwidth calculations
901 * Returns the latency watermark in ns
903 static u32
dce_v11_0_latency_watermark(struct dce10_wm_params
*wm
)
905 /* First calculate the latency in ns */
906 u32 mc_latency
= 2000; /* 2000 ns. */
907 u32 available_bandwidth
= dce_v11_0_available_bandwidth(wm
);
908 u32 worst_chunk_return_time
= (512 * 8 * 1000) / available_bandwidth
;
909 u32 cursor_line_pair_return_time
= (128 * 4 * 1000) / available_bandwidth
;
910 u32 dc_latency
= 40000000 / wm
->disp_clk
; /* dc pipe latency */
911 u32 other_heads_data_return_time
= ((wm
->num_heads
+ 1) * worst_chunk_return_time
) +
912 (wm
->num_heads
* cursor_line_pair_return_time
);
913 u32 latency
= mc_latency
+ other_heads_data_return_time
+ dc_latency
;
914 u32 max_src_lines_per_dst_line
, lb_fill_bw
, line_fill_time
;
915 u32 tmp
, dmif_size
= 12288;
918 if (wm
->num_heads
== 0)
921 a
.full
= dfixed_const(2);
922 b
.full
= dfixed_const(1);
923 if ((wm
->vsc
.full
> a
.full
) ||
924 ((wm
->vsc
.full
> b
.full
) && (wm
->vtaps
>= 3)) ||
926 ((wm
->vsc
.full
>= a
.full
) && wm
->interlaced
))
927 max_src_lines_per_dst_line
= 4;
929 max_src_lines_per_dst_line
= 2;
931 a
.full
= dfixed_const(available_bandwidth
);
932 b
.full
= dfixed_const(wm
->num_heads
);
933 a
.full
= dfixed_div(a
, b
);
934 tmp
= div_u64((u64
) dmif_size
* (u64
) wm
->disp_clk
, mc_latency
+ 512);
935 tmp
= min(dfixed_trunc(a
), tmp
);
937 lb_fill_bw
= min(tmp
, wm
->disp_clk
* wm
->bytes_per_pixel
/ 1000);
939 a
.full
= dfixed_const(max_src_lines_per_dst_line
* wm
->src_width
* wm
->bytes_per_pixel
);
940 b
.full
= dfixed_const(1000);
941 c
.full
= dfixed_const(lb_fill_bw
);
942 b
.full
= dfixed_div(c
, b
);
943 a
.full
= dfixed_div(a
, b
);
944 line_fill_time
= dfixed_trunc(a
);
946 if (line_fill_time
< wm
->active_time
)
949 return latency
+ (line_fill_time
- wm
->active_time
);
954 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
955 * average and available dram bandwidth
957 * @wm: watermark calculation data
959 * Check if the display average bandwidth fits in the display
960 * dram bandwidth (CIK).
961 * Used for display watermark bandwidth calculations
962 * Returns true if the display fits, false if not.
964 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params
*wm
)
966 if (dce_v11_0_average_bandwidth(wm
) <=
967 (dce_v11_0_dram_bandwidth_for_display(wm
) / wm
->num_heads
))
974 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
975 * average and available bandwidth
977 * @wm: watermark calculation data
979 * Check if the display average bandwidth fits in the display
980 * available bandwidth (CIK).
981 * Used for display watermark bandwidth calculations
982 * Returns true if the display fits, false if not.
984 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params
*wm
)
986 if (dce_v11_0_average_bandwidth(wm
) <=
987 (dce_v11_0_available_bandwidth(wm
) / wm
->num_heads
))
994 * dce_v11_0_check_latency_hiding - check latency hiding
996 * @wm: watermark calculation data
998 * Check latency hiding (CIK).
999 * Used for display watermark bandwidth calculations
1000 * Returns true if the display fits, false if not.
1002 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params
*wm
)
1004 u32 lb_partitions
= wm
->lb_size
/ wm
->src_width
;
1005 u32 line_time
= wm
->active_time
+ wm
->blank_time
;
1006 u32 latency_tolerant_lines
;
1010 a
.full
= dfixed_const(1);
1011 if (wm
->vsc
.full
> a
.full
)
1012 latency_tolerant_lines
= 1;
1014 if (lb_partitions
<= (wm
->vtaps
+ 1))
1015 latency_tolerant_lines
= 1;
1017 latency_tolerant_lines
= 2;
1020 latency_hiding
= (latency_tolerant_lines
* line_time
+ wm
->blank_time
);
1022 if (dce_v11_0_latency_watermark(wm
) <= latency_hiding
)
1029 * dce_v11_0_program_watermarks - program display watermarks
1031 * @adev: amdgpu_device pointer
1032 * @amdgpu_crtc: the selected display controller
1033 * @lb_size: line buffer size
1034 * @num_heads: number of display controllers in use
1036 * Calculate and program the display watermarks for the
1037 * selected display controller (CIK).
1039 static void dce_v11_0_program_watermarks(struct amdgpu_device
*adev
,
1040 struct amdgpu_crtc
*amdgpu_crtc
,
1041 u32 lb_size
, u32 num_heads
)
1043 struct drm_display_mode
*mode
= &amdgpu_crtc
->base
.mode
;
1044 struct dce10_wm_params wm_low
, wm_high
;
1047 u32 latency_watermark_a
= 0, latency_watermark_b
= 0;
1048 u32 tmp
, wm_mask
, lb_vblank_lead_lines
= 0;
1050 if (amdgpu_crtc
->base
.enabled
&& num_heads
&& mode
) {
1051 active_time
= (u32
) div_u64((u64
)mode
->crtc_hdisplay
* 1000000,
1053 line_time
= (u32
) div_u64((u64
)mode
->crtc_htotal
* 1000000,
1055 line_time
= min(line_time
, (u32
)65535);
1057 /* watermark for high clocks */
1058 if (adev
->pm
.dpm_enabled
) {
1060 amdgpu_dpm_get_mclk(adev
, false) * 10;
1062 amdgpu_dpm_get_sclk(adev
, false) * 10;
1064 wm_high
.yclk
= adev
->pm
.current_mclk
* 10;
1065 wm_high
.sclk
= adev
->pm
.current_sclk
* 10;
1068 wm_high
.disp_clk
= mode
->clock
;
1069 wm_high
.src_width
= mode
->crtc_hdisplay
;
1070 wm_high
.active_time
= active_time
;
1071 wm_high
.blank_time
= line_time
- wm_high
.active_time
;
1072 wm_high
.interlaced
= false;
1073 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1074 wm_high
.interlaced
= true;
1075 wm_high
.vsc
= amdgpu_crtc
->vsc
;
1077 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
)
1079 wm_high
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1080 wm_high
.lb_size
= lb_size
;
1081 wm_high
.dram_channels
= cik_get_number_of_dram_channels(adev
);
1082 wm_high
.num_heads
= num_heads
;
1084 /* set for high clocks */
1085 latency_watermark_a
= min(dce_v11_0_latency_watermark(&wm_high
), (u32
)65535);
1087 /* possibly force display priority to high */
1088 /* should really do this at mode validation time... */
1089 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high
) ||
1090 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high
) ||
1091 !dce_v11_0_check_latency_hiding(&wm_high
) ||
1092 (adev
->mode_info
.disp_priority
== 2)) {
1093 DRM_DEBUG_KMS("force priority to high\n");
1096 /* watermark for low clocks */
1097 if (adev
->pm
.dpm_enabled
) {
1099 amdgpu_dpm_get_mclk(adev
, true) * 10;
1101 amdgpu_dpm_get_sclk(adev
, true) * 10;
1103 wm_low
.yclk
= adev
->pm
.current_mclk
* 10;
1104 wm_low
.sclk
= adev
->pm
.current_sclk
* 10;
1107 wm_low
.disp_clk
= mode
->clock
;
1108 wm_low
.src_width
= mode
->crtc_hdisplay
;
1109 wm_low
.active_time
= active_time
;
1110 wm_low
.blank_time
= line_time
- wm_low
.active_time
;
1111 wm_low
.interlaced
= false;
1112 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1113 wm_low
.interlaced
= true;
1114 wm_low
.vsc
= amdgpu_crtc
->vsc
;
1116 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
)
1118 wm_low
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1119 wm_low
.lb_size
= lb_size
;
1120 wm_low
.dram_channels
= cik_get_number_of_dram_channels(adev
);
1121 wm_low
.num_heads
= num_heads
;
1123 /* set for low clocks */
1124 latency_watermark_b
= min(dce_v11_0_latency_watermark(&wm_low
), (u32
)65535);
1126 /* possibly force display priority to high */
1127 /* should really do this at mode validation time... */
1128 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low
) ||
1129 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low
) ||
1130 !dce_v11_0_check_latency_hiding(&wm_low
) ||
1131 (adev
->mode_info
.disp_priority
== 2)) {
1132 DRM_DEBUG_KMS("force priority to high\n");
1134 lb_vblank_lead_lines
= DIV_ROUND_UP(lb_size
, mode
->crtc_hdisplay
);
1138 wm_mask
= RREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1139 tmp
= REG_SET_FIELD(wm_mask
, DPG_WATERMARK_MASK_CONTROL
, URGENCY_WATERMARK_MASK
, 1);
1140 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1141 tmp
= RREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1142 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_LOW_WATERMARK
, latency_watermark_a
);
1143 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_HIGH_WATERMARK
, line_time
);
1144 WREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1146 tmp
= REG_SET_FIELD(wm_mask
, DPG_WATERMARK_MASK_CONTROL
, URGENCY_WATERMARK_MASK
, 2);
1147 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1148 tmp
= RREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1149 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_LOW_WATERMARK
, latency_watermark_b
);
1150 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_HIGH_WATERMARK
, line_time
);
1151 WREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1152 /* restore original selection */
1153 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, wm_mask
);
1155 /* save values for DPM */
1156 amdgpu_crtc
->line_time
= line_time
;
1157 amdgpu_crtc
->wm_high
= latency_watermark_a
;
1158 amdgpu_crtc
->wm_low
= latency_watermark_b
;
1159 /* Save number of lines the linebuffer leads before the scanout */
1160 amdgpu_crtc
->lb_vblank_lead_lines
= lb_vblank_lead_lines
;
1164 * dce_v11_0_bandwidth_update - program display watermarks
1166 * @adev: amdgpu_device pointer
1168 * Calculate and program the display watermarks and line
1169 * buffer allocation (CIK).
1171 static void dce_v11_0_bandwidth_update(struct amdgpu_device
*adev
)
1173 struct drm_display_mode
*mode
= NULL
;
1174 u32 num_heads
= 0, lb_size
;
1177 amdgpu_display_update_priority(adev
);
1179 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
1180 if (adev
->mode_info
.crtcs
[i
]->base
.enabled
)
1183 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
1184 mode
= &adev
->mode_info
.crtcs
[i
]->base
.mode
;
1185 lb_size
= dce_v11_0_line_buffer_adjust(adev
, adev
->mode_info
.crtcs
[i
], mode
);
1186 dce_v11_0_program_watermarks(adev
, adev
->mode_info
.crtcs
[i
],
1187 lb_size
, num_heads
);
1191 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device
*adev
)
1196 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1197 offset
= adev
->mode_info
.audio
.pin
[i
].offset
;
1198 tmp
= RREG32_AUDIO_ENDPT(offset
,
1199 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
);
1201 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
) >>
1202 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
) == 1)
1203 adev
->mode_info
.audio
.pin
[i
].connected
= false;
1205 adev
->mode_info
.audio
.pin
[i
].connected
= true;
1209 static struct amdgpu_audio_pin
*dce_v11_0_audio_get_pin(struct amdgpu_device
*adev
)
1213 dce_v11_0_audio_get_connected_pins(adev
);
1215 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1216 if (adev
->mode_info
.audio
.pin
[i
].connected
)
1217 return &adev
->mode_info
.audio
.pin
[i
];
1219 DRM_ERROR("No connected audio pins found!\n");
1223 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder
*encoder
)
1225 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1226 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1227 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1230 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1233 tmp
= RREG32(mmAFMT_AUDIO_SRC_CONTROL
+ dig
->afmt
->offset
);
1234 tmp
= REG_SET_FIELD(tmp
, AFMT_AUDIO_SRC_CONTROL
, AFMT_AUDIO_SRC_SELECT
, dig
->afmt
->pin
->id
);
1235 WREG32(mmAFMT_AUDIO_SRC_CONTROL
+ dig
->afmt
->offset
, tmp
);
1238 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder
*encoder
,
1239 struct drm_display_mode
*mode
)
1241 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1242 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1243 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1244 struct drm_connector
*connector
;
1245 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1249 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1252 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1253 if (connector
->encoder
== encoder
) {
1254 amdgpu_connector
= to_amdgpu_connector(connector
);
1259 if (!amdgpu_connector
) {
1260 DRM_ERROR("Couldn't find encoder's connector\n");
1264 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1266 if (connector
->latency_present
[interlace
]) {
1267 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1268 VIDEO_LIPSYNC
, connector
->video_latency
[interlace
]);
1269 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1270 AUDIO_LIPSYNC
, connector
->audio_latency
[interlace
]);
1272 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1274 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1277 WREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
,
1278 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
, tmp
);
1281 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder
*encoder
)
1283 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1284 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1285 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1286 struct drm_connector
*connector
;
1287 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1292 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1295 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1296 if (connector
->encoder
== encoder
) {
1297 amdgpu_connector
= to_amdgpu_connector(connector
);
1302 if (!amdgpu_connector
) {
1303 DRM_ERROR("Couldn't find encoder's connector\n");
1307 sad_count
= drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector
), &sadb
);
1308 if (sad_count
< 0) {
1309 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count
);
1313 /* program the speaker allocation */
1314 tmp
= RREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
,
1315 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
);
1316 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1319 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1320 HDMI_CONNECTION
, 1);
1322 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1323 SPEAKER_ALLOCATION
, sadb
[0]);
1325 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1326 SPEAKER_ALLOCATION
, 5); /* stereo */
1327 WREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
,
1328 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
, tmp
);
1333 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder
*encoder
)
1335 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1336 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1337 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1338 struct drm_connector
*connector
;
1339 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1340 struct cea_sad
*sads
;
1343 static const u16 eld_reg_to_type
[][2] = {
1344 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
, HDMI_AUDIO_CODING_TYPE_PCM
},
1345 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
, HDMI_AUDIO_CODING_TYPE_AC3
},
1346 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
, HDMI_AUDIO_CODING_TYPE_MPEG1
},
1347 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
, HDMI_AUDIO_CODING_TYPE_MP3
},
1348 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
, HDMI_AUDIO_CODING_TYPE_MPEG2
},
1349 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
, HDMI_AUDIO_CODING_TYPE_AAC_LC
},
1350 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
, HDMI_AUDIO_CODING_TYPE_DTS
},
1351 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
, HDMI_AUDIO_CODING_TYPE_ATRAC
},
1352 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
, HDMI_AUDIO_CODING_TYPE_EAC3
},
1353 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
, HDMI_AUDIO_CODING_TYPE_DTS_HD
},
1354 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
, HDMI_AUDIO_CODING_TYPE_MLP
},
1355 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
, HDMI_AUDIO_CODING_TYPE_WMA_PRO
},
1358 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1361 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1362 if (connector
->encoder
== encoder
) {
1363 amdgpu_connector
= to_amdgpu_connector(connector
);
1368 if (!amdgpu_connector
) {
1369 DRM_ERROR("Couldn't find encoder's connector\n");
1373 sad_count
= drm_edid_to_sad(amdgpu_connector_edid(connector
), &sads
);
1374 if (sad_count
<= 0) {
1375 DRM_ERROR("Couldn't read SADs: %d\n", sad_count
);
1380 for (i
= 0; i
< ARRAY_SIZE(eld_reg_to_type
); i
++) {
1382 u8 stereo_freqs
= 0;
1383 int max_channels
= -1;
1386 for (j
= 0; j
< sad_count
; j
++) {
1387 struct cea_sad
*sad
= &sads
[j
];
1389 if (sad
->format
== eld_reg_to_type
[i
][1]) {
1390 if (sad
->channels
> max_channels
) {
1391 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1392 MAX_CHANNELS
, sad
->channels
);
1393 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1394 DESCRIPTOR_BYTE_2
, sad
->byte2
);
1395 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1396 SUPPORTED_FREQUENCIES
, sad
->freq
);
1397 max_channels
= sad
->channels
;
1400 if (sad
->format
== HDMI_AUDIO_CODING_TYPE_PCM
)
1401 stereo_freqs
|= sad
->freq
;
1407 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1408 SUPPORTED_FREQUENCIES_STEREO
, stereo_freqs
);
1409 WREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
, eld_reg_to_type
[i
][0], tmp
);
1415 static void dce_v11_0_audio_enable(struct amdgpu_device
*adev
,
1416 struct amdgpu_audio_pin
*pin
,
1422 WREG32_AUDIO_ENDPT(pin
->offset
, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
,
1423 enable
? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
: 0);
1426 static const u32 pin_offsets
[] =
1428 AUD0_REGISTER_OFFSET
,
1429 AUD1_REGISTER_OFFSET
,
1430 AUD2_REGISTER_OFFSET
,
1431 AUD3_REGISTER_OFFSET
,
1432 AUD4_REGISTER_OFFSET
,
1433 AUD5_REGISTER_OFFSET
,
1434 AUD6_REGISTER_OFFSET
,
1435 AUD7_REGISTER_OFFSET
,
1438 static int dce_v11_0_audio_init(struct amdgpu_device
*adev
)
1445 adev
->mode_info
.audio
.enabled
= true;
1447 switch (adev
->asic_type
) {
1450 adev
->mode_info
.audio
.num_pins
= 7;
1452 case CHIP_POLARIS10
:
1454 adev
->mode_info
.audio
.num_pins
= 8;
1456 case CHIP_POLARIS11
:
1457 case CHIP_POLARIS12
:
1458 adev
->mode_info
.audio
.num_pins
= 6;
1464 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1465 adev
->mode_info
.audio
.pin
[i
].channels
= -1;
1466 adev
->mode_info
.audio
.pin
[i
].rate
= -1;
1467 adev
->mode_info
.audio
.pin
[i
].bits_per_sample
= -1;
1468 adev
->mode_info
.audio
.pin
[i
].status_bits
= 0;
1469 adev
->mode_info
.audio
.pin
[i
].category_code
= 0;
1470 adev
->mode_info
.audio
.pin
[i
].connected
= false;
1471 adev
->mode_info
.audio
.pin
[i
].offset
= pin_offsets
[i
];
1472 adev
->mode_info
.audio
.pin
[i
].id
= i
;
1473 /* disable audio. it will be set up later */
1474 /* XXX remove once we switch to ip funcs */
1475 dce_v11_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
1481 static void dce_v11_0_audio_fini(struct amdgpu_device
*adev
)
1488 if (!adev
->mode_info
.audio
.enabled
)
1491 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++)
1492 dce_v11_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
1494 adev
->mode_info
.audio
.enabled
= false;
1498 * update the N and CTS parameters for a given pixel clock rate
1500 static void dce_v11_0_afmt_update_ACR(struct drm_encoder
*encoder
, uint32_t clock
)
1502 struct drm_device
*dev
= encoder
->dev
;
1503 struct amdgpu_device
*adev
= dev
->dev_private
;
1504 struct amdgpu_afmt_acr acr
= amdgpu_afmt_acr(clock
);
1505 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1506 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1509 tmp
= RREG32(mmHDMI_ACR_32_0
+ dig
->afmt
->offset
);
1510 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_32_0
, HDMI_ACR_CTS_32
, acr
.cts_32khz
);
1511 WREG32(mmHDMI_ACR_32_0
+ dig
->afmt
->offset
, tmp
);
1512 tmp
= RREG32(mmHDMI_ACR_32_1
+ dig
->afmt
->offset
);
1513 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_32_1
, HDMI_ACR_N_32
, acr
.n_32khz
);
1514 WREG32(mmHDMI_ACR_32_1
+ dig
->afmt
->offset
, tmp
);
1516 tmp
= RREG32(mmHDMI_ACR_44_0
+ dig
->afmt
->offset
);
1517 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_44_0
, HDMI_ACR_CTS_44
, acr
.cts_44_1khz
);
1518 WREG32(mmHDMI_ACR_44_0
+ dig
->afmt
->offset
, tmp
);
1519 tmp
= RREG32(mmHDMI_ACR_44_1
+ dig
->afmt
->offset
);
1520 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_44_1
, HDMI_ACR_N_44
, acr
.n_44_1khz
);
1521 WREG32(mmHDMI_ACR_44_1
+ dig
->afmt
->offset
, tmp
);
1523 tmp
= RREG32(mmHDMI_ACR_48_0
+ dig
->afmt
->offset
);
1524 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_48_0
, HDMI_ACR_CTS_48
, acr
.cts_48khz
);
1525 WREG32(mmHDMI_ACR_48_0
+ dig
->afmt
->offset
, tmp
);
1526 tmp
= RREG32(mmHDMI_ACR_48_1
+ dig
->afmt
->offset
);
1527 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_48_1
, HDMI_ACR_N_48
, acr
.n_48khz
);
1528 WREG32(mmHDMI_ACR_48_1
+ dig
->afmt
->offset
, tmp
);
1533 * build a HDMI Video Info Frame
1535 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder
*encoder
,
1536 void *buffer
, size_t size
)
1538 struct drm_device
*dev
= encoder
->dev
;
1539 struct amdgpu_device
*adev
= dev
->dev_private
;
1540 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1541 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1542 uint8_t *frame
= buffer
+ 3;
1543 uint8_t *header
= buffer
;
1545 WREG32(mmAFMT_AVI_INFO0
+ dig
->afmt
->offset
,
1546 frame
[0x0] | (frame
[0x1] << 8) | (frame
[0x2] << 16) | (frame
[0x3] << 24));
1547 WREG32(mmAFMT_AVI_INFO1
+ dig
->afmt
->offset
,
1548 frame
[0x4] | (frame
[0x5] << 8) | (frame
[0x6] << 16) | (frame
[0x7] << 24));
1549 WREG32(mmAFMT_AVI_INFO2
+ dig
->afmt
->offset
,
1550 frame
[0x8] | (frame
[0x9] << 8) | (frame
[0xA] << 16) | (frame
[0xB] << 24));
1551 WREG32(mmAFMT_AVI_INFO3
+ dig
->afmt
->offset
,
1552 frame
[0xC] | (frame
[0xD] << 8) | (header
[1] << 24));
1555 static void dce_v11_0_audio_set_dto(struct drm_encoder
*encoder
, u32 clock
)
1557 struct drm_device
*dev
= encoder
->dev
;
1558 struct amdgpu_device
*adev
= dev
->dev_private
;
1559 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1560 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1561 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1562 u32 dto_phase
= 24 * 1000;
1563 u32 dto_modulo
= clock
;
1566 if (!dig
|| !dig
->afmt
)
1569 /* XXX two dtos; generally use dto0 for hdmi */
1570 /* Express [24MHz / target pixel clock] as an exact rational
1571 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1572 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1574 tmp
= RREG32(mmDCCG_AUDIO_DTO_SOURCE
);
1575 tmp
= REG_SET_FIELD(tmp
, DCCG_AUDIO_DTO_SOURCE
, DCCG_AUDIO_DTO0_SOURCE_SEL
,
1576 amdgpu_crtc
->crtc_id
);
1577 WREG32(mmDCCG_AUDIO_DTO_SOURCE
, tmp
);
1578 WREG32(mmDCCG_AUDIO_DTO0_PHASE
, dto_phase
);
1579 WREG32(mmDCCG_AUDIO_DTO0_MODULE
, dto_modulo
);
1583 * update the info frames with the data from the current display mode
1585 static void dce_v11_0_afmt_setmode(struct drm_encoder
*encoder
,
1586 struct drm_display_mode
*mode
)
1588 struct drm_device
*dev
= encoder
->dev
;
1589 struct amdgpu_device
*adev
= dev
->dev_private
;
1590 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1591 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1592 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
1593 u8 buffer
[HDMI_INFOFRAME_HEADER_SIZE
+ HDMI_AVI_INFOFRAME_SIZE
];
1594 struct hdmi_avi_infoframe frame
;
1599 if (!dig
|| !dig
->afmt
)
1602 /* Silent, r600_hdmi_enable will raise WARN for us */
1603 if (!dig
->afmt
->enabled
)
1606 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1607 if (encoder
->crtc
) {
1608 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1609 bpc
= amdgpu_crtc
->bpc
;
1612 /* disable audio prior to setting up hw */
1613 dig
->afmt
->pin
= dce_v11_0_audio_get_pin(adev
);
1614 dce_v11_0_audio_enable(adev
, dig
->afmt
->pin
, false);
1616 dce_v11_0_audio_set_dto(encoder
, mode
->clock
);
1618 tmp
= RREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
);
1619 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_NULL_SEND
, 1);
1620 WREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
); /* send null packets when required */
1622 WREG32(mmAFMT_AUDIO_CRC_CONTROL
+ dig
->afmt
->offset
, 0x1000);
1624 tmp
= RREG32(mmHDMI_CONTROL
+ dig
->afmt
->offset
);
1631 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_ENABLE
, 0);
1632 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 0);
1633 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1634 connector
->name
, bpc
);
1637 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_ENABLE
, 1);
1638 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 1);
1639 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1643 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_ENABLE
, 1);
1644 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 2);
1645 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1649 WREG32(mmHDMI_CONTROL
+ dig
->afmt
->offset
, tmp
);
1651 tmp
= RREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
);
1652 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_NULL_SEND
, 1); /* send null packets when required */
1653 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_GC_SEND
, 1); /* send general control packets */
1654 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_GC_CONT
, 1); /* send general control packets every frame */
1655 WREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1657 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
);
1658 /* enable audio info frames (frames won't be set until audio is enabled) */
1659 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AUDIO_INFO_SEND
, 1);
1660 /* required for audio info values to be updated */
1661 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AUDIO_INFO_CONT
, 1);
1662 WREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, tmp
);
1664 tmp
= RREG32(mmAFMT_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
);
1665 /* required for audio info values to be updated */
1666 tmp
= REG_SET_FIELD(tmp
, AFMT_INFOFRAME_CONTROL0
, AFMT_AUDIO_INFO_UPDATE
, 1);
1667 WREG32(mmAFMT_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, tmp
);
1669 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
);
1670 /* anything other than 0 */
1671 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL1
, HDMI_AUDIO_INFO_LINE
, 2);
1672 WREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
, tmp
);
1674 WREG32(mmHDMI_GC
+ dig
->afmt
->offset
, 0); /* unset HDMI_GC_AVMUTE */
1676 tmp
= RREG32(mmHDMI_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
);
1677 /* set the default audio delay */
1678 tmp
= REG_SET_FIELD(tmp
, HDMI_AUDIO_PACKET_CONTROL
, HDMI_AUDIO_DELAY_EN
, 1);
1679 /* should be suffient for all audio modes and small enough for all hblanks */
1680 tmp
= REG_SET_FIELD(tmp
, HDMI_AUDIO_PACKET_CONTROL
, HDMI_AUDIO_PACKETS_PER_LINE
, 3);
1681 WREG32(mmHDMI_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1683 tmp
= RREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
);
1684 /* allow 60958 channel status fields to be updated */
1685 tmp
= REG_SET_FIELD(tmp
, AFMT_AUDIO_PACKET_CONTROL
, AFMT_60958_CS_UPDATE
, 1);
1686 WREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1688 tmp
= RREG32(mmHDMI_ACR_PACKET_CONTROL
+ dig
->afmt
->offset
);
1690 /* clear SW CTS value */
1691 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_PACKET_CONTROL
, HDMI_ACR_SOURCE
, 0);
1693 /* select SW CTS value */
1694 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_PACKET_CONTROL
, HDMI_ACR_SOURCE
, 1);
1695 /* allow hw to sent ACR packets when required */
1696 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_PACKET_CONTROL
, HDMI_ACR_AUTO_SEND
, 1);
1697 WREG32(mmHDMI_ACR_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1699 dce_v11_0_afmt_update_ACR(encoder
, mode
->clock
);
1701 tmp
= RREG32(mmAFMT_60958_0
+ dig
->afmt
->offset
);
1702 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_0
, AFMT_60958_CS_CHANNEL_NUMBER_L
, 1);
1703 WREG32(mmAFMT_60958_0
+ dig
->afmt
->offset
, tmp
);
1705 tmp
= RREG32(mmAFMT_60958_1
+ dig
->afmt
->offset
);
1706 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_1
, AFMT_60958_CS_CHANNEL_NUMBER_R
, 2);
1707 WREG32(mmAFMT_60958_1
+ dig
->afmt
->offset
, tmp
);
1709 tmp
= RREG32(mmAFMT_60958_2
+ dig
->afmt
->offset
);
1710 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_2
, 3);
1711 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_3
, 4);
1712 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_4
, 5);
1713 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_5
, 6);
1714 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_6
, 7);
1715 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_7
, 8);
1716 WREG32(mmAFMT_60958_2
+ dig
->afmt
->offset
, tmp
);
1718 dce_v11_0_audio_write_speaker_allocation(encoder
);
1720 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2
+ dig
->afmt
->offset
,
1721 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT
));
1723 dce_v11_0_afmt_audio_select_pin(encoder
);
1724 dce_v11_0_audio_write_sad_regs(encoder
);
1725 dce_v11_0_audio_write_latency_fields(encoder
, mode
);
1727 err
= drm_hdmi_avi_infoframe_from_display_mode(&frame
, mode
, false);
1729 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err
);
1733 err
= hdmi_avi_infoframe_pack(&frame
, buffer
, sizeof(buffer
));
1735 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err
);
1739 dce_v11_0_afmt_update_avi_infoframe(encoder
, buffer
, sizeof(buffer
));
1741 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
);
1742 /* enable AVI info frames */
1743 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AVI_INFO_SEND
, 1);
1744 /* required for audio info values to be updated */
1745 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AVI_INFO_CONT
, 1);
1746 WREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, tmp
);
1748 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
);
1749 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL1
, HDMI_AVI_INFO_LINE
, 2);
1750 WREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
, tmp
);
1752 tmp
= RREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
);
1753 /* send audio packets */
1754 tmp
= REG_SET_FIELD(tmp
, AFMT_AUDIO_PACKET_CONTROL
, AFMT_AUDIO_SAMPLE_SEND
, 1);
1755 WREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1757 WREG32(mmAFMT_RAMP_CONTROL0
+ dig
->afmt
->offset
, 0x00FFFFFF);
1758 WREG32(mmAFMT_RAMP_CONTROL1
+ dig
->afmt
->offset
, 0x007FFFFF);
1759 WREG32(mmAFMT_RAMP_CONTROL2
+ dig
->afmt
->offset
, 0x00000001);
1760 WREG32(mmAFMT_RAMP_CONTROL3
+ dig
->afmt
->offset
, 0x00000001);
1762 /* enable audio after to setting up hw */
1763 dce_v11_0_audio_enable(adev
, dig
->afmt
->pin
, true);
1766 static void dce_v11_0_afmt_enable(struct drm_encoder
*encoder
, bool enable
)
1768 struct drm_device
*dev
= encoder
->dev
;
1769 struct amdgpu_device
*adev
= dev
->dev_private
;
1770 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1771 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1773 if (!dig
|| !dig
->afmt
)
1776 /* Silent, r600_hdmi_enable will raise WARN for us */
1777 if (enable
&& dig
->afmt
->enabled
)
1779 if (!enable
&& !dig
->afmt
->enabled
)
1782 if (!enable
&& dig
->afmt
->pin
) {
1783 dce_v11_0_audio_enable(adev
, dig
->afmt
->pin
, false);
1784 dig
->afmt
->pin
= NULL
;
1787 dig
->afmt
->enabled
= enable
;
1789 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1790 enable
? "En" : "Dis", dig
->afmt
->offset
, amdgpu_encoder
->encoder_id
);
1793 static int dce_v11_0_afmt_init(struct amdgpu_device
*adev
)
1797 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++)
1798 adev
->mode_info
.afmt
[i
] = NULL
;
1800 /* DCE11 has audio blocks tied to DIG encoders */
1801 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++) {
1802 adev
->mode_info
.afmt
[i
] = kzalloc(sizeof(struct amdgpu_afmt
), GFP_KERNEL
);
1803 if (adev
->mode_info
.afmt
[i
]) {
1804 adev
->mode_info
.afmt
[i
]->offset
= dig_offsets
[i
];
1805 adev
->mode_info
.afmt
[i
]->id
= i
;
1808 for (j
= 0; j
< i
; j
++) {
1809 kfree(adev
->mode_info
.afmt
[j
]);
1810 adev
->mode_info
.afmt
[j
] = NULL
;
1818 static void dce_v11_0_afmt_fini(struct amdgpu_device
*adev
)
1822 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++) {
1823 kfree(adev
->mode_info
.afmt
[i
]);
1824 adev
->mode_info
.afmt
[i
] = NULL
;
1828 static const u32 vga_control_regs
[6] =
1838 static void dce_v11_0_vga_enable(struct drm_crtc
*crtc
, bool enable
)
1840 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
1841 struct drm_device
*dev
= crtc
->dev
;
1842 struct amdgpu_device
*adev
= dev
->dev_private
;
1845 vga_control
= RREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
]) & ~1;
1847 WREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
], vga_control
| 1);
1849 WREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
], vga_control
);
1852 static void dce_v11_0_grph_enable(struct drm_crtc
*crtc
, bool enable
)
1854 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
1855 struct drm_device
*dev
= crtc
->dev
;
1856 struct amdgpu_device
*adev
= dev
->dev_private
;
1859 WREG32(mmGRPH_ENABLE
+ amdgpu_crtc
->crtc_offset
, 1);
1861 WREG32(mmGRPH_ENABLE
+ amdgpu_crtc
->crtc_offset
, 0);
1864 static int dce_v11_0_crtc_do_set_base(struct drm_crtc
*crtc
,
1865 struct drm_framebuffer
*fb
,
1866 int x
, int y
, int atomic
)
1868 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
1869 struct drm_device
*dev
= crtc
->dev
;
1870 struct amdgpu_device
*adev
= dev
->dev_private
;
1871 struct drm_framebuffer
*target_fb
;
1872 struct drm_gem_object
*obj
;
1873 struct amdgpu_bo
*abo
;
1874 uint64_t fb_location
, tiling_flags
;
1875 uint32_t fb_format
, fb_pitch_pixels
;
1876 u32 fb_swap
= REG_SET_FIELD(0, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
, ENDIAN_NONE
);
1878 u32 tmp
, viewport_w
, viewport_h
;
1880 bool bypass_lut
= false;
1881 struct drm_format_name_buf format_name
;
1884 if (!atomic
&& !crtc
->primary
->fb
) {
1885 DRM_DEBUG_KMS("No FB bound\n");
1892 target_fb
= crtc
->primary
->fb
;
1894 /* If atomic, assume fb object is pinned & idle & fenced and
1895 * just update base pointers
1897 obj
= target_fb
->obj
[0];
1898 abo
= gem_to_amdgpu_bo(obj
);
1899 r
= amdgpu_bo_reserve(abo
, false);
1900 if (unlikely(r
!= 0))
1904 r
= amdgpu_bo_pin(abo
, AMDGPU_GEM_DOMAIN_VRAM
);
1905 if (unlikely(r
!= 0)) {
1906 amdgpu_bo_unreserve(abo
);
1910 fb_location
= amdgpu_bo_gpu_offset(abo
);
1912 amdgpu_bo_get_tiling_flags(abo
, &tiling_flags
);
1913 amdgpu_bo_unreserve(abo
);
1915 pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
1917 switch (target_fb
->format
->format
) {
1919 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 0);
1920 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
1922 case DRM_FORMAT_XRGB4444
:
1923 case DRM_FORMAT_ARGB4444
:
1924 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
1925 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 2);
1927 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
1931 case DRM_FORMAT_XRGB1555
:
1932 case DRM_FORMAT_ARGB1555
:
1933 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
1934 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
1936 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
1940 case DRM_FORMAT_BGRX5551
:
1941 case DRM_FORMAT_BGRA5551
:
1942 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
1943 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 5);
1945 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
1949 case DRM_FORMAT_RGB565
:
1950 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
1951 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 1);
1953 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
1957 case DRM_FORMAT_XRGB8888
:
1958 case DRM_FORMAT_ARGB8888
:
1959 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
1960 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
1962 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
1966 case DRM_FORMAT_XRGB2101010
:
1967 case DRM_FORMAT_ARGB2101010
:
1968 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
1969 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 1);
1971 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
1974 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1977 case DRM_FORMAT_BGRX1010102
:
1978 case DRM_FORMAT_BGRA1010102
:
1979 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
1980 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 4);
1982 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
1985 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1988 case DRM_FORMAT_XBGR8888
:
1989 case DRM_FORMAT_ABGR8888
:
1990 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
1991 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
1992 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_RED_CROSSBAR
, 2);
1993 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_BLUE_CROSSBAR
, 2);
1995 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2000 DRM_ERROR("Unsupported screen format %s\n",
2001 drm_get_format_name(target_fb
->format
->format
, &format_name
));
2005 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == ARRAY_2D_TILED_THIN1
) {
2006 unsigned bankw
, bankh
, mtaspect
, tile_split
, num_banks
;
2008 bankw
= AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
2009 bankh
= AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
2010 mtaspect
= AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
2011 tile_split
= AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
);
2012 num_banks
= AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
2014 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_NUM_BANKS
, num_banks
);
2015 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_ARRAY_MODE
,
2016 ARRAY_2D_TILED_THIN1
);
2017 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_TILE_SPLIT
,
2019 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_BANK_WIDTH
, bankw
);
2020 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_BANK_HEIGHT
, bankh
);
2021 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_MACRO_TILE_ASPECT
,
2023 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_MICRO_TILE_MODE
,
2024 ADDR_SURF_MICRO_TILING_DISPLAY
);
2025 } else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == ARRAY_1D_TILED_THIN1
) {
2026 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_ARRAY_MODE
,
2027 ARRAY_1D_TILED_THIN1
);
2030 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_PIPE_CONFIG
,
2033 dce_v11_0_vga_enable(crtc
, false);
2035 /* Make sure surface address is updated at vertical blank rather than
2038 tmp
= RREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2039 tmp
= REG_SET_FIELD(tmp
, GRPH_FLIP_CONTROL
,
2040 GRPH_SURFACE_UPDATE_H_RETRACE_EN
, 0);
2041 WREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2043 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2044 upper_32_bits(fb_location
));
2045 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2046 upper_32_bits(fb_location
));
2047 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2048 (u32
)fb_location
& GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
);
2049 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2050 (u32
) fb_location
& GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
);
2051 WREG32(mmGRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
, fb_format
);
2052 WREG32(mmGRPH_SWAP_CNTL
+ amdgpu_crtc
->crtc_offset
, fb_swap
);
2055 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2056 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2057 * retain the full precision throughout the pipeline.
2059 tmp
= RREG32(mmGRPH_LUT_10BIT_BYPASS
+ amdgpu_crtc
->crtc_offset
);
2061 tmp
= REG_SET_FIELD(tmp
, GRPH_LUT_10BIT_BYPASS
, GRPH_LUT_10BIT_BYPASS_EN
, 1);
2063 tmp
= REG_SET_FIELD(tmp
, GRPH_LUT_10BIT_BYPASS
, GRPH_LUT_10BIT_BYPASS_EN
, 0);
2064 WREG32(mmGRPH_LUT_10BIT_BYPASS
+ amdgpu_crtc
->crtc_offset
, tmp
);
2067 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2069 WREG32(mmGRPH_SURFACE_OFFSET_X
+ amdgpu_crtc
->crtc_offset
, 0);
2070 WREG32(mmGRPH_SURFACE_OFFSET_Y
+ amdgpu_crtc
->crtc_offset
, 0);
2071 WREG32(mmGRPH_X_START
+ amdgpu_crtc
->crtc_offset
, 0);
2072 WREG32(mmGRPH_Y_START
+ amdgpu_crtc
->crtc_offset
, 0);
2073 WREG32(mmGRPH_X_END
+ amdgpu_crtc
->crtc_offset
, target_fb
->width
);
2074 WREG32(mmGRPH_Y_END
+ amdgpu_crtc
->crtc_offset
, target_fb
->height
);
2076 fb_pitch_pixels
= target_fb
->pitches
[0] / target_fb
->format
->cpp
[0];
2077 WREG32(mmGRPH_PITCH
+ amdgpu_crtc
->crtc_offset
, fb_pitch_pixels
);
2079 dce_v11_0_grph_enable(crtc
, true);
2081 WREG32(mmLB_DESKTOP_HEIGHT
+ amdgpu_crtc
->crtc_offset
,
2086 WREG32(mmVIEWPORT_START
+ amdgpu_crtc
->crtc_offset
,
2088 viewport_w
= crtc
->mode
.hdisplay
;
2089 viewport_h
= (crtc
->mode
.vdisplay
+ 1) & ~1;
2090 WREG32(mmVIEWPORT_SIZE
+ amdgpu_crtc
->crtc_offset
,
2091 (viewport_w
<< 16) | viewport_h
);
2093 /* set pageflip to happen anywhere in vblank interval */
2094 WREG32(mmCRTC_MASTER_UPDATE_MODE
+ amdgpu_crtc
->crtc_offset
, 0);
2096 if (!atomic
&& fb
&& fb
!= crtc
->primary
->fb
) {
2097 abo
= gem_to_amdgpu_bo(fb
->obj
[0]);
2098 r
= amdgpu_bo_reserve(abo
, true);
2099 if (unlikely(r
!= 0))
2101 amdgpu_bo_unpin(abo
);
2102 amdgpu_bo_unreserve(abo
);
2105 /* Bytes per pixel may have changed */
2106 dce_v11_0_bandwidth_update(adev
);
2111 static void dce_v11_0_set_interleave(struct drm_crtc
*crtc
,
2112 struct drm_display_mode
*mode
)
2114 struct drm_device
*dev
= crtc
->dev
;
2115 struct amdgpu_device
*adev
= dev
->dev_private
;
2116 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2119 tmp
= RREG32(mmLB_DATA_FORMAT
+ amdgpu_crtc
->crtc_offset
);
2120 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
2121 tmp
= REG_SET_FIELD(tmp
, LB_DATA_FORMAT
, INTERLEAVE_EN
, 1);
2123 tmp
= REG_SET_FIELD(tmp
, LB_DATA_FORMAT
, INTERLEAVE_EN
, 0);
2124 WREG32(mmLB_DATA_FORMAT
+ amdgpu_crtc
->crtc_offset
, tmp
);
2127 static void dce_v11_0_crtc_load_lut(struct drm_crtc
*crtc
)
2129 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2130 struct drm_device
*dev
= crtc
->dev
;
2131 struct amdgpu_device
*adev
= dev
->dev_private
;
2136 DRM_DEBUG_KMS("%d\n", amdgpu_crtc
->crtc_id
);
2138 tmp
= RREG32(mmINPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2139 tmp
= REG_SET_FIELD(tmp
, INPUT_CSC_CONTROL
, INPUT_CSC_GRPH_MODE
, 0);
2140 WREG32(mmINPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2142 tmp
= RREG32(mmPRESCALE_GRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2143 tmp
= REG_SET_FIELD(tmp
, PRESCALE_GRPH_CONTROL
, GRPH_PRESCALE_BYPASS
, 1);
2144 WREG32(mmPRESCALE_GRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2146 tmp
= RREG32(mmINPUT_GAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2147 tmp
= REG_SET_FIELD(tmp
, INPUT_GAMMA_CONTROL
, GRPH_INPUT_GAMMA_MODE
, 0);
2148 WREG32(mmINPUT_GAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2150 WREG32(mmDC_LUT_CONTROL
+ amdgpu_crtc
->crtc_offset
, 0);
2152 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE
+ amdgpu_crtc
->crtc_offset
, 0);
2153 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN
+ amdgpu_crtc
->crtc_offset
, 0);
2154 WREG32(mmDC_LUT_BLACK_OFFSET_RED
+ amdgpu_crtc
->crtc_offset
, 0);
2156 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2157 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2158 WREG32(mmDC_LUT_WHITE_OFFSET_RED
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2160 WREG32(mmDC_LUT_RW_MODE
+ amdgpu_crtc
->crtc_offset
, 0);
2161 WREG32(mmDC_LUT_WRITE_EN_MASK
+ amdgpu_crtc
->crtc_offset
, 0x00000007);
2163 WREG32(mmDC_LUT_RW_INDEX
+ amdgpu_crtc
->crtc_offset
, 0);
2164 r
= crtc
->gamma_store
;
2165 g
= r
+ crtc
->gamma_size
;
2166 b
= g
+ crtc
->gamma_size
;
2167 for (i
= 0; i
< 256; i
++) {
2168 WREG32(mmDC_LUT_30_COLOR
+ amdgpu_crtc
->crtc_offset
,
2169 ((*r
++ & 0xffc0) << 14) |
2170 ((*g
++ & 0xffc0) << 4) |
2174 tmp
= RREG32(mmDEGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2175 tmp
= REG_SET_FIELD(tmp
, DEGAMMA_CONTROL
, GRPH_DEGAMMA_MODE
, 0);
2176 tmp
= REG_SET_FIELD(tmp
, DEGAMMA_CONTROL
, CURSOR_DEGAMMA_MODE
, 0);
2177 tmp
= REG_SET_FIELD(tmp
, DEGAMMA_CONTROL
, CURSOR2_DEGAMMA_MODE
, 0);
2178 WREG32(mmDEGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2180 tmp
= RREG32(mmGAMUT_REMAP_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2181 tmp
= REG_SET_FIELD(tmp
, GAMUT_REMAP_CONTROL
, GRPH_GAMUT_REMAP_MODE
, 0);
2182 WREG32(mmGAMUT_REMAP_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2184 tmp
= RREG32(mmREGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2185 tmp
= REG_SET_FIELD(tmp
, REGAMMA_CONTROL
, GRPH_REGAMMA_MODE
, 0);
2186 WREG32(mmREGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2188 tmp
= RREG32(mmOUTPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2189 tmp
= REG_SET_FIELD(tmp
, OUTPUT_CSC_CONTROL
, OUTPUT_CSC_GRPH_MODE
, 0);
2190 WREG32(mmOUTPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2192 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2193 WREG32(mmDENORM_CONTROL
+ amdgpu_crtc
->crtc_offset
, 0);
2194 /* XXX this only needs to be programmed once per crtc at startup,
2195 * not sure where the best place for it is
2197 tmp
= RREG32(mmALPHA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2198 tmp
= REG_SET_FIELD(tmp
, ALPHA_CONTROL
, CURSOR_ALPHA_BLND_ENA
, 1);
2199 WREG32(mmALPHA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2202 static int dce_v11_0_pick_dig_encoder(struct drm_encoder
*encoder
)
2204 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
2205 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
2207 switch (amdgpu_encoder
->encoder_id
) {
2208 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2214 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2220 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2226 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2230 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder
->encoder_id
);
2236 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2240 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2241 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2242 * monitors a dedicated PPLL must be used. If a particular board has
2243 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2244 * as there is no need to program the PLL itself. If we are not able to
2245 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2246 * avoid messing up an existing monitor.
2248 * Asic specific PLL information
2252 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2254 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2257 static u32
dce_v11_0_pick_pll(struct drm_crtc
*crtc
)
2259 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2260 struct drm_device
*dev
= crtc
->dev
;
2261 struct amdgpu_device
*adev
= dev
->dev_private
;
2265 if ((adev
->asic_type
== CHIP_POLARIS10
) ||
2266 (adev
->asic_type
== CHIP_POLARIS11
) ||
2267 (adev
->asic_type
== CHIP_POLARIS12
) ||
2268 (adev
->asic_type
== CHIP_VEGAM
)) {
2269 struct amdgpu_encoder
*amdgpu_encoder
=
2270 to_amdgpu_encoder(amdgpu_crtc
->encoder
);
2271 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
2273 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
)))
2276 switch (amdgpu_encoder
->encoder_id
) {
2277 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2279 return ATOM_COMBOPHY_PLL1
;
2281 return ATOM_COMBOPHY_PLL0
;
2283 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2285 return ATOM_COMBOPHY_PLL3
;
2287 return ATOM_COMBOPHY_PLL2
;
2289 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2291 return ATOM_COMBOPHY_PLL5
;
2293 return ATOM_COMBOPHY_PLL4
;
2296 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder
->encoder_id
);
2297 return ATOM_PPLL_INVALID
;
2301 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
))) {
2302 if (adev
->clock
.dp_extclk
)
2303 /* skip PPLL programming if using ext clock */
2304 return ATOM_PPLL_INVALID
;
2306 /* use the same PPLL for all DP monitors */
2307 pll
= amdgpu_pll_get_shared_dp_ppll(crtc
);
2308 if (pll
!= ATOM_PPLL_INVALID
)
2312 /* use the same PPLL for all monitors with the same clock */
2313 pll
= amdgpu_pll_get_shared_nondp_ppll(crtc
);
2314 if (pll
!= ATOM_PPLL_INVALID
)
2318 /* XXX need to determine what plls are available on each DCE11 part */
2319 pll_in_use
= amdgpu_pll_get_use_mask(crtc
);
2320 if (adev
->asic_type
== CHIP_CARRIZO
|| adev
->asic_type
== CHIP_STONEY
) {
2321 if (!(pll_in_use
& (1 << ATOM_PPLL1
)))
2323 if (!(pll_in_use
& (1 << ATOM_PPLL0
)))
2325 DRM_ERROR("unable to allocate a PPLL\n");
2326 return ATOM_PPLL_INVALID
;
2328 if (!(pll_in_use
& (1 << ATOM_PPLL2
)))
2330 if (!(pll_in_use
& (1 << ATOM_PPLL1
)))
2332 if (!(pll_in_use
& (1 << ATOM_PPLL0
)))
2334 DRM_ERROR("unable to allocate a PPLL\n");
2335 return ATOM_PPLL_INVALID
;
2337 return ATOM_PPLL_INVALID
;
2340 static void dce_v11_0_lock_cursor(struct drm_crtc
*crtc
, bool lock
)
2342 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2343 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2346 cur_lock
= RREG32(mmCUR_UPDATE
+ amdgpu_crtc
->crtc_offset
);
2348 cur_lock
= REG_SET_FIELD(cur_lock
, CUR_UPDATE
, CURSOR_UPDATE_LOCK
, 1);
2350 cur_lock
= REG_SET_FIELD(cur_lock
, CUR_UPDATE
, CURSOR_UPDATE_LOCK
, 0);
2351 WREG32(mmCUR_UPDATE
+ amdgpu_crtc
->crtc_offset
, cur_lock
);
2354 static void dce_v11_0_hide_cursor(struct drm_crtc
*crtc
)
2356 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2357 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2360 tmp
= RREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2361 tmp
= REG_SET_FIELD(tmp
, CUR_CONTROL
, CURSOR_EN
, 0);
2362 WREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2365 static void dce_v11_0_show_cursor(struct drm_crtc
*crtc
)
2367 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2368 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2371 WREG32(mmCUR_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2372 upper_32_bits(amdgpu_crtc
->cursor_addr
));
2373 WREG32(mmCUR_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2374 lower_32_bits(amdgpu_crtc
->cursor_addr
));
2376 tmp
= RREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2377 tmp
= REG_SET_FIELD(tmp
, CUR_CONTROL
, CURSOR_EN
, 1);
2378 tmp
= REG_SET_FIELD(tmp
, CUR_CONTROL
, CURSOR_MODE
, 2);
2379 WREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2382 static int dce_v11_0_cursor_move_locked(struct drm_crtc
*crtc
,
2385 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2386 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2387 int xorigin
= 0, yorigin
= 0;
2389 amdgpu_crtc
->cursor_x
= x
;
2390 amdgpu_crtc
->cursor_y
= y
;
2392 /* avivo cursor are offset into the total surface */
2395 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x
, y
, crtc
->x
, crtc
->y
);
2398 xorigin
= min(-x
, amdgpu_crtc
->max_cursor_width
- 1);
2402 yorigin
= min(-y
, amdgpu_crtc
->max_cursor_height
- 1);
2406 WREG32(mmCUR_POSITION
+ amdgpu_crtc
->crtc_offset
, (x
<< 16) | y
);
2407 WREG32(mmCUR_HOT_SPOT
+ amdgpu_crtc
->crtc_offset
, (xorigin
<< 16) | yorigin
);
2408 WREG32(mmCUR_SIZE
+ amdgpu_crtc
->crtc_offset
,
2409 ((amdgpu_crtc
->cursor_width
- 1) << 16) | (amdgpu_crtc
->cursor_height
- 1));
2414 static int dce_v11_0_crtc_cursor_move(struct drm_crtc
*crtc
,
2419 dce_v11_0_lock_cursor(crtc
, true);
2420 ret
= dce_v11_0_cursor_move_locked(crtc
, x
, y
);
2421 dce_v11_0_lock_cursor(crtc
, false);
2426 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc
*crtc
,
2427 struct drm_file
*file_priv
,
2434 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2435 struct drm_gem_object
*obj
;
2436 struct amdgpu_bo
*aobj
;
2440 /* turn off cursor */
2441 dce_v11_0_hide_cursor(crtc
);
2446 if ((width
> amdgpu_crtc
->max_cursor_width
) ||
2447 (height
> amdgpu_crtc
->max_cursor_height
)) {
2448 DRM_ERROR("bad cursor width or height %d x %d\n", width
, height
);
2452 obj
= drm_gem_object_lookup(file_priv
, handle
);
2454 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle
, amdgpu_crtc
->crtc_id
);
2458 aobj
= gem_to_amdgpu_bo(obj
);
2459 ret
= amdgpu_bo_reserve(aobj
, false);
2461 drm_gem_object_put_unlocked(obj
);
2465 ret
= amdgpu_bo_pin(aobj
, AMDGPU_GEM_DOMAIN_VRAM
);
2466 amdgpu_bo_unreserve(aobj
);
2468 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret
);
2469 drm_gem_object_put_unlocked(obj
);
2472 amdgpu_crtc
->cursor_addr
= amdgpu_bo_gpu_offset(aobj
);
2474 dce_v11_0_lock_cursor(crtc
, true);
2476 if (width
!= amdgpu_crtc
->cursor_width
||
2477 height
!= amdgpu_crtc
->cursor_height
||
2478 hot_x
!= amdgpu_crtc
->cursor_hot_x
||
2479 hot_y
!= amdgpu_crtc
->cursor_hot_y
) {
2482 x
= amdgpu_crtc
->cursor_x
+ amdgpu_crtc
->cursor_hot_x
- hot_x
;
2483 y
= amdgpu_crtc
->cursor_y
+ amdgpu_crtc
->cursor_hot_y
- hot_y
;
2485 dce_v11_0_cursor_move_locked(crtc
, x
, y
);
2487 amdgpu_crtc
->cursor_width
= width
;
2488 amdgpu_crtc
->cursor_height
= height
;
2489 amdgpu_crtc
->cursor_hot_x
= hot_x
;
2490 amdgpu_crtc
->cursor_hot_y
= hot_y
;
2493 dce_v11_0_show_cursor(crtc
);
2494 dce_v11_0_lock_cursor(crtc
, false);
2497 if (amdgpu_crtc
->cursor_bo
) {
2498 struct amdgpu_bo
*aobj
= gem_to_amdgpu_bo(amdgpu_crtc
->cursor_bo
);
2499 ret
= amdgpu_bo_reserve(aobj
, true);
2500 if (likely(ret
== 0)) {
2501 amdgpu_bo_unpin(aobj
);
2502 amdgpu_bo_unreserve(aobj
);
2504 drm_gem_object_put_unlocked(amdgpu_crtc
->cursor_bo
);
2507 amdgpu_crtc
->cursor_bo
= obj
;
2511 static void dce_v11_0_cursor_reset(struct drm_crtc
*crtc
)
2513 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2515 if (amdgpu_crtc
->cursor_bo
) {
2516 dce_v11_0_lock_cursor(crtc
, true);
2518 dce_v11_0_cursor_move_locked(crtc
, amdgpu_crtc
->cursor_x
,
2519 amdgpu_crtc
->cursor_y
);
2521 dce_v11_0_show_cursor(crtc
);
2523 dce_v11_0_lock_cursor(crtc
, false);
2527 static int dce_v11_0_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
2528 u16
*blue
, uint32_t size
,
2529 struct drm_modeset_acquire_ctx
*ctx
)
2531 dce_v11_0_crtc_load_lut(crtc
);
2536 static void dce_v11_0_crtc_destroy(struct drm_crtc
*crtc
)
2538 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2540 drm_crtc_cleanup(crtc
);
2544 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs
= {
2545 .cursor_set2
= dce_v11_0_crtc_cursor_set2
,
2546 .cursor_move
= dce_v11_0_crtc_cursor_move
,
2547 .gamma_set
= dce_v11_0_crtc_gamma_set
,
2548 .set_config
= amdgpu_display_crtc_set_config
,
2549 .destroy
= dce_v11_0_crtc_destroy
,
2550 .page_flip_target
= amdgpu_display_crtc_page_flip_target
,
2553 static void dce_v11_0_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2555 struct drm_device
*dev
= crtc
->dev
;
2556 struct amdgpu_device
*adev
= dev
->dev_private
;
2557 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2561 case DRM_MODE_DPMS_ON
:
2562 amdgpu_crtc
->enabled
= true;
2563 amdgpu_atombios_crtc_enable(crtc
, ATOM_ENABLE
);
2564 dce_v11_0_vga_enable(crtc
, true);
2565 amdgpu_atombios_crtc_blank(crtc
, ATOM_DISABLE
);
2566 dce_v11_0_vga_enable(crtc
, false);
2567 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2568 type
= amdgpu_display_crtc_idx_to_irq_type(adev
,
2569 amdgpu_crtc
->crtc_id
);
2570 amdgpu_irq_update(adev
, &adev
->crtc_irq
, type
);
2571 amdgpu_irq_update(adev
, &adev
->pageflip_irq
, type
);
2572 drm_crtc_vblank_on(crtc
);
2573 dce_v11_0_crtc_load_lut(crtc
);
2575 case DRM_MODE_DPMS_STANDBY
:
2576 case DRM_MODE_DPMS_SUSPEND
:
2577 case DRM_MODE_DPMS_OFF
:
2578 drm_crtc_vblank_off(crtc
);
2579 if (amdgpu_crtc
->enabled
) {
2580 dce_v11_0_vga_enable(crtc
, true);
2581 amdgpu_atombios_crtc_blank(crtc
, ATOM_ENABLE
);
2582 dce_v11_0_vga_enable(crtc
, false);
2584 amdgpu_atombios_crtc_enable(crtc
, ATOM_DISABLE
);
2585 amdgpu_crtc
->enabled
= false;
2588 /* adjust pm to dpms */
2589 amdgpu_pm_compute_clocks(adev
);
2592 static void dce_v11_0_crtc_prepare(struct drm_crtc
*crtc
)
2594 /* disable crtc pair power gating before programming */
2595 amdgpu_atombios_crtc_powergate(crtc
, ATOM_DISABLE
);
2596 amdgpu_atombios_crtc_lock(crtc
, ATOM_ENABLE
);
2597 dce_v11_0_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
2600 static void dce_v11_0_crtc_commit(struct drm_crtc
*crtc
)
2602 dce_v11_0_crtc_dpms(crtc
, DRM_MODE_DPMS_ON
);
2603 amdgpu_atombios_crtc_lock(crtc
, ATOM_DISABLE
);
2606 static void dce_v11_0_crtc_disable(struct drm_crtc
*crtc
)
2608 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2609 struct drm_device
*dev
= crtc
->dev
;
2610 struct amdgpu_device
*adev
= dev
->dev_private
;
2611 struct amdgpu_atom_ss ss
;
2614 dce_v11_0_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
2615 if (crtc
->primary
->fb
) {
2617 struct amdgpu_bo
*abo
;
2619 abo
= gem_to_amdgpu_bo(crtc
->primary
->fb
->obj
[0]);
2620 r
= amdgpu_bo_reserve(abo
, true);
2622 DRM_ERROR("failed to reserve abo before unpin\n");
2624 amdgpu_bo_unpin(abo
);
2625 amdgpu_bo_unreserve(abo
);
2628 /* disable the GRPH */
2629 dce_v11_0_grph_enable(crtc
, false);
2631 amdgpu_atombios_crtc_powergate(crtc
, ATOM_ENABLE
);
2633 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2634 if (adev
->mode_info
.crtcs
[i
] &&
2635 adev
->mode_info
.crtcs
[i
]->enabled
&&
2636 i
!= amdgpu_crtc
->crtc_id
&&
2637 amdgpu_crtc
->pll_id
== adev
->mode_info
.crtcs
[i
]->pll_id
) {
2638 /* one other crtc is using this pll don't turn
2645 switch (amdgpu_crtc
->pll_id
) {
2649 /* disable the ppll */
2650 amdgpu_atombios_crtc_program_pll(crtc
, amdgpu_crtc
->crtc_id
, amdgpu_crtc
->pll_id
,
2651 0, 0, ATOM_DISABLE
, 0, 0, 0, 0, 0, false, &ss
);
2653 case ATOM_COMBOPHY_PLL0
:
2654 case ATOM_COMBOPHY_PLL1
:
2655 case ATOM_COMBOPHY_PLL2
:
2656 case ATOM_COMBOPHY_PLL3
:
2657 case ATOM_COMBOPHY_PLL4
:
2658 case ATOM_COMBOPHY_PLL5
:
2659 /* disable the ppll */
2660 amdgpu_atombios_crtc_program_pll(crtc
, ATOM_CRTC_INVALID
, amdgpu_crtc
->pll_id
,
2661 0, 0, ATOM_DISABLE
, 0, 0, 0, 0, 0, false, &ss
);
2667 amdgpu_crtc
->pll_id
= ATOM_PPLL_INVALID
;
2668 amdgpu_crtc
->adjusted_clock
= 0;
2669 amdgpu_crtc
->encoder
= NULL
;
2670 amdgpu_crtc
->connector
= NULL
;
2673 static int dce_v11_0_crtc_mode_set(struct drm_crtc
*crtc
,
2674 struct drm_display_mode
*mode
,
2675 struct drm_display_mode
*adjusted_mode
,
2676 int x
, int y
, struct drm_framebuffer
*old_fb
)
2678 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2679 struct drm_device
*dev
= crtc
->dev
;
2680 struct amdgpu_device
*adev
= dev
->dev_private
;
2682 if (!amdgpu_crtc
->adjusted_clock
)
2685 if ((adev
->asic_type
== CHIP_POLARIS10
) ||
2686 (adev
->asic_type
== CHIP_POLARIS11
) ||
2687 (adev
->asic_type
== CHIP_POLARIS12
) ||
2688 (adev
->asic_type
== CHIP_VEGAM
)) {
2689 struct amdgpu_encoder
*amdgpu_encoder
=
2690 to_amdgpu_encoder(amdgpu_crtc
->encoder
);
2692 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
);
2694 /* SetPixelClock calculates the plls and ss values now */
2695 amdgpu_atombios_crtc_program_pll(crtc
, amdgpu_crtc
->crtc_id
,
2696 amdgpu_crtc
->pll_id
,
2697 encoder_mode
, amdgpu_encoder
->encoder_id
,
2698 adjusted_mode
->clock
, 0, 0, 0, 0,
2699 amdgpu_crtc
->bpc
, amdgpu_crtc
->ss_enabled
, &amdgpu_crtc
->ss
);
2701 amdgpu_atombios_crtc_set_pll(crtc
, adjusted_mode
);
2703 amdgpu_atombios_crtc_set_dtd_timing(crtc
, adjusted_mode
);
2704 dce_v11_0_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
2705 amdgpu_atombios_crtc_overscan_setup(crtc
, mode
, adjusted_mode
);
2706 amdgpu_atombios_crtc_scaler_setup(crtc
);
2707 dce_v11_0_cursor_reset(crtc
);
2708 /* update the hw version fpr dpm */
2709 amdgpu_crtc
->hw_mode
= *adjusted_mode
;
2714 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc
*crtc
,
2715 const struct drm_display_mode
*mode
,
2716 struct drm_display_mode
*adjusted_mode
)
2718 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2719 struct drm_device
*dev
= crtc
->dev
;
2720 struct drm_encoder
*encoder
;
2722 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2723 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2724 if (encoder
->crtc
== crtc
) {
2725 amdgpu_crtc
->encoder
= encoder
;
2726 amdgpu_crtc
->connector
= amdgpu_get_connector_for_encoder(encoder
);
2730 if ((amdgpu_crtc
->encoder
== NULL
) || (amdgpu_crtc
->connector
== NULL
)) {
2731 amdgpu_crtc
->encoder
= NULL
;
2732 amdgpu_crtc
->connector
= NULL
;
2735 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc
, mode
, adjusted_mode
))
2737 if (amdgpu_atombios_crtc_prepare_pll(crtc
, adjusted_mode
))
2740 amdgpu_crtc
->pll_id
= dce_v11_0_pick_pll(crtc
);
2741 /* if we can't get a PPLL for a non-DP encoder, fail */
2742 if ((amdgpu_crtc
->pll_id
== ATOM_PPLL_INVALID
) &&
2743 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
)))
2749 static int dce_v11_0_crtc_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2750 struct drm_framebuffer
*old_fb
)
2752 return dce_v11_0_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
2755 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc
*crtc
,
2756 struct drm_framebuffer
*fb
,
2757 int x
, int y
, enum mode_set_atomic state
)
2759 return dce_v11_0_crtc_do_set_base(crtc
, fb
, x
, y
, 1);
2762 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs
= {
2763 .dpms
= dce_v11_0_crtc_dpms
,
2764 .mode_fixup
= dce_v11_0_crtc_mode_fixup
,
2765 .mode_set
= dce_v11_0_crtc_mode_set
,
2766 .mode_set_base
= dce_v11_0_crtc_set_base
,
2767 .mode_set_base_atomic
= dce_v11_0_crtc_set_base_atomic
,
2768 .prepare
= dce_v11_0_crtc_prepare
,
2769 .commit
= dce_v11_0_crtc_commit
,
2770 .disable
= dce_v11_0_crtc_disable
,
2773 static int dce_v11_0_crtc_init(struct amdgpu_device
*adev
, int index
)
2775 struct amdgpu_crtc
*amdgpu_crtc
;
2777 amdgpu_crtc
= kzalloc(sizeof(struct amdgpu_crtc
) +
2778 (AMDGPUFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
2779 if (amdgpu_crtc
== NULL
)
2782 drm_crtc_init(adev
->ddev
, &amdgpu_crtc
->base
, &dce_v11_0_crtc_funcs
);
2784 drm_mode_crtc_set_gamma_size(&amdgpu_crtc
->base
, 256);
2785 amdgpu_crtc
->crtc_id
= index
;
2786 adev
->mode_info
.crtcs
[index
] = amdgpu_crtc
;
2788 amdgpu_crtc
->max_cursor_width
= 128;
2789 amdgpu_crtc
->max_cursor_height
= 128;
2790 adev
->ddev
->mode_config
.cursor_width
= amdgpu_crtc
->max_cursor_width
;
2791 adev
->ddev
->mode_config
.cursor_height
= amdgpu_crtc
->max_cursor_height
;
2793 switch (amdgpu_crtc
->crtc_id
) {
2796 amdgpu_crtc
->crtc_offset
= CRTC0_REGISTER_OFFSET
;
2799 amdgpu_crtc
->crtc_offset
= CRTC1_REGISTER_OFFSET
;
2802 amdgpu_crtc
->crtc_offset
= CRTC2_REGISTER_OFFSET
;
2805 amdgpu_crtc
->crtc_offset
= CRTC3_REGISTER_OFFSET
;
2808 amdgpu_crtc
->crtc_offset
= CRTC4_REGISTER_OFFSET
;
2811 amdgpu_crtc
->crtc_offset
= CRTC5_REGISTER_OFFSET
;
2815 amdgpu_crtc
->pll_id
= ATOM_PPLL_INVALID
;
2816 amdgpu_crtc
->adjusted_clock
= 0;
2817 amdgpu_crtc
->encoder
= NULL
;
2818 amdgpu_crtc
->connector
= NULL
;
2819 drm_crtc_helper_add(&amdgpu_crtc
->base
, &dce_v11_0_crtc_helper_funcs
);
2824 static int dce_v11_0_early_init(void *handle
)
2826 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2828 adev
->audio_endpt_rreg
= &dce_v11_0_audio_endpt_rreg
;
2829 adev
->audio_endpt_wreg
= &dce_v11_0_audio_endpt_wreg
;
2831 dce_v11_0_set_display_funcs(adev
);
2833 adev
->mode_info
.num_crtc
= dce_v11_0_get_num_crtc(adev
);
2835 switch (adev
->asic_type
) {
2837 adev
->mode_info
.num_hpd
= 6;
2838 adev
->mode_info
.num_dig
= 9;
2841 adev
->mode_info
.num_hpd
= 6;
2842 adev
->mode_info
.num_dig
= 9;
2844 case CHIP_POLARIS10
:
2846 adev
->mode_info
.num_hpd
= 6;
2847 adev
->mode_info
.num_dig
= 6;
2849 case CHIP_POLARIS11
:
2850 case CHIP_POLARIS12
:
2851 adev
->mode_info
.num_hpd
= 5;
2852 adev
->mode_info
.num_dig
= 5;
2855 /* FIXME: not supported yet */
2859 dce_v11_0_set_irq_funcs(adev
);
2864 static int dce_v11_0_sw_init(void *handle
)
2867 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2869 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2870 r
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_LEGACY
, i
+ 1, &adev
->crtc_irq
);
2875 for (i
= VISLANDS30_IV_SRCID_D1_GRPH_PFLIP
; i
< 20; i
+= 2) {
2876 r
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_LEGACY
, i
, &adev
->pageflip_irq
);
2882 r
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_LEGACY
, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A
, &adev
->hpd_irq
);
2886 adev
->ddev
->mode_config
.funcs
= &amdgpu_mode_funcs
;
2888 adev
->ddev
->mode_config
.async_page_flip
= true;
2890 adev
->ddev
->mode_config
.max_width
= 16384;
2891 adev
->ddev
->mode_config
.max_height
= 16384;
2893 adev
->ddev
->mode_config
.preferred_depth
= 24;
2894 adev
->ddev
->mode_config
.prefer_shadow
= 1;
2896 adev
->ddev
->mode_config
.fb_base
= adev
->gmc
.aper_base
;
2898 r
= amdgpu_display_modeset_create_props(adev
);
2902 adev
->ddev
->mode_config
.max_width
= 16384;
2903 adev
->ddev
->mode_config
.max_height
= 16384;
2906 /* allocate crtcs */
2907 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2908 r
= dce_v11_0_crtc_init(adev
, i
);
2913 if (amdgpu_atombios_get_connector_info_from_object_table(adev
))
2914 amdgpu_display_print_display_setup(adev
->ddev
);
2919 r
= dce_v11_0_afmt_init(adev
);
2923 r
= dce_v11_0_audio_init(adev
);
2927 drm_kms_helper_poll_init(adev
->ddev
);
2929 adev
->mode_info
.mode_config_initialized
= true;
2933 static int dce_v11_0_sw_fini(void *handle
)
2935 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2937 kfree(adev
->mode_info
.bios_hardcoded_edid
);
2939 drm_kms_helper_poll_fini(adev
->ddev
);
2941 dce_v11_0_audio_fini(adev
);
2943 dce_v11_0_afmt_fini(adev
);
2945 drm_mode_config_cleanup(adev
->ddev
);
2946 adev
->mode_info
.mode_config_initialized
= false;
2951 static int dce_v11_0_hw_init(void *handle
)
2954 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2956 dce_v11_0_init_golden_registers(adev
);
2958 /* disable vga render */
2959 dce_v11_0_set_vga_render_state(adev
, false);
2960 /* init dig PHYs, disp eng pll */
2961 amdgpu_atombios_crtc_powergate_init(adev
);
2962 amdgpu_atombios_encoder_init_dig(adev
);
2963 if ((adev
->asic_type
== CHIP_POLARIS10
) ||
2964 (adev
->asic_type
== CHIP_POLARIS11
) ||
2965 (adev
->asic_type
== CHIP_POLARIS12
) ||
2966 (adev
->asic_type
== CHIP_VEGAM
)) {
2967 amdgpu_atombios_crtc_set_dce_clock(adev
, adev
->clock
.default_dispclk
,
2968 DCE_CLOCK_TYPE_DISPCLK
, ATOM_GCK_DFS
);
2969 amdgpu_atombios_crtc_set_dce_clock(adev
, 0,
2970 DCE_CLOCK_TYPE_DPREFCLK
, ATOM_GCK_DFS
);
2972 amdgpu_atombios_crtc_set_disp_eng_pll(adev
, adev
->clock
.default_dispclk
);
2975 /* initialize hpd */
2976 dce_v11_0_hpd_init(adev
);
2978 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
2979 dce_v11_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
2982 dce_v11_0_pageflip_interrupt_init(adev
);
2987 static int dce_v11_0_hw_fini(void *handle
)
2990 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2992 dce_v11_0_hpd_fini(adev
);
2994 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
2995 dce_v11_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
2998 dce_v11_0_pageflip_interrupt_fini(adev
);
3003 static int dce_v11_0_suspend(void *handle
)
3005 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3007 adev
->mode_info
.bl_level
=
3008 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev
);
3010 return dce_v11_0_hw_fini(handle
);
3013 static int dce_v11_0_resume(void *handle
)
3015 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3018 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev
,
3019 adev
->mode_info
.bl_level
);
3021 ret
= dce_v11_0_hw_init(handle
);
3023 /* turn on the BL */
3024 if (adev
->mode_info
.bl_encoder
) {
3025 u8 bl_level
= amdgpu_display_backlight_get_level(adev
,
3026 adev
->mode_info
.bl_encoder
);
3027 amdgpu_display_backlight_set_level(adev
, adev
->mode_info
.bl_encoder
,
3034 static bool dce_v11_0_is_idle(void *handle
)
3039 static int dce_v11_0_wait_for_idle(void *handle
)
3044 static int dce_v11_0_soft_reset(void *handle
)
3046 u32 srbm_soft_reset
= 0, tmp
;
3047 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3049 if (dce_v11_0_is_display_hung(adev
))
3050 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK
;
3052 if (srbm_soft_reset
) {
3053 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3054 tmp
|= srbm_soft_reset
;
3055 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
3056 WREG32(mmSRBM_SOFT_RESET
, tmp
);
3057 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3061 tmp
&= ~srbm_soft_reset
;
3062 WREG32(mmSRBM_SOFT_RESET
, tmp
);
3063 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3065 /* Wait a little for things to settle down */
3071 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device
*adev
,
3073 enum amdgpu_interrupt_state state
)
3075 u32 lb_interrupt_mask
;
3077 if (crtc
>= adev
->mode_info
.num_crtc
) {
3078 DRM_DEBUG("invalid crtc %d\n", crtc
);
3083 case AMDGPU_IRQ_STATE_DISABLE
:
3084 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3085 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3086 VBLANK_INTERRUPT_MASK
, 0);
3087 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3089 case AMDGPU_IRQ_STATE_ENABLE
:
3090 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3091 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3092 VBLANK_INTERRUPT_MASK
, 1);
3093 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3100 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device
*adev
,
3102 enum amdgpu_interrupt_state state
)
3104 u32 lb_interrupt_mask
;
3106 if (crtc
>= adev
->mode_info
.num_crtc
) {
3107 DRM_DEBUG("invalid crtc %d\n", crtc
);
3112 case AMDGPU_IRQ_STATE_DISABLE
:
3113 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3114 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3115 VLINE_INTERRUPT_MASK
, 0);
3116 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3118 case AMDGPU_IRQ_STATE_ENABLE
:
3119 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3120 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3121 VLINE_INTERRUPT_MASK
, 1);
3122 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3129 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device
*adev
,
3130 struct amdgpu_irq_src
*source
,
3132 enum amdgpu_interrupt_state state
)
3136 if (hpd
>= adev
->mode_info
.num_hpd
) {
3137 DRM_DEBUG("invalid hdp %d\n", hpd
);
3142 case AMDGPU_IRQ_STATE_DISABLE
:
3143 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
3144 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_EN
, 0);
3145 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
3147 case AMDGPU_IRQ_STATE_ENABLE
:
3148 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
3149 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_EN
, 1);
3150 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
3159 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device
*adev
,
3160 struct amdgpu_irq_src
*source
,
3162 enum amdgpu_interrupt_state state
)
3165 case AMDGPU_CRTC_IRQ_VBLANK1
:
3166 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 0, state
);
3168 case AMDGPU_CRTC_IRQ_VBLANK2
:
3169 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 1, state
);
3171 case AMDGPU_CRTC_IRQ_VBLANK3
:
3172 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 2, state
);
3174 case AMDGPU_CRTC_IRQ_VBLANK4
:
3175 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 3, state
);
3177 case AMDGPU_CRTC_IRQ_VBLANK5
:
3178 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 4, state
);
3180 case AMDGPU_CRTC_IRQ_VBLANK6
:
3181 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 5, state
);
3183 case AMDGPU_CRTC_IRQ_VLINE1
:
3184 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 0, state
);
3186 case AMDGPU_CRTC_IRQ_VLINE2
:
3187 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 1, state
);
3189 case AMDGPU_CRTC_IRQ_VLINE3
:
3190 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 2, state
);
3192 case AMDGPU_CRTC_IRQ_VLINE4
:
3193 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 3, state
);
3195 case AMDGPU_CRTC_IRQ_VLINE5
:
3196 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 4, state
);
3198 case AMDGPU_CRTC_IRQ_VLINE6
:
3199 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 5, state
);
3207 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device
*adev
,
3208 struct amdgpu_irq_src
*src
,
3210 enum amdgpu_interrupt_state state
)
3214 if (type
>= adev
->mode_info
.num_crtc
) {
3215 DRM_ERROR("invalid pageflip crtc %d\n", type
);
3219 reg
= RREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
]);
3220 if (state
== AMDGPU_IRQ_STATE_DISABLE
)
3221 WREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
],
3222 reg
& ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
);
3224 WREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
],
3225 reg
| GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
);
3230 static int dce_v11_0_pageflip_irq(struct amdgpu_device
*adev
,
3231 struct amdgpu_irq_src
*source
,
3232 struct amdgpu_iv_entry
*entry
)
3234 unsigned long flags
;
3236 struct amdgpu_crtc
*amdgpu_crtc
;
3237 struct amdgpu_flip_work
*works
;
3239 crtc_id
= (entry
->src_id
- 8) >> 1;
3240 amdgpu_crtc
= adev
->mode_info
.crtcs
[crtc_id
];
3242 if (crtc_id
>= adev
->mode_info
.num_crtc
) {
3243 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id
);
3247 if (RREG32(mmGRPH_INTERRUPT_STATUS
+ crtc_offsets
[crtc_id
]) &
3248 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
)
3249 WREG32(mmGRPH_INTERRUPT_STATUS
+ crtc_offsets
[crtc_id
],
3250 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
);
3252 /* IRQ could occur when in initial stage */
3253 if(amdgpu_crtc
== NULL
)
3256 spin_lock_irqsave(&adev
->ddev
->event_lock
, flags
);
3257 works
= amdgpu_crtc
->pflip_works
;
3258 if (amdgpu_crtc
->pflip_status
!= AMDGPU_FLIP_SUBMITTED
){
3259 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3260 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3261 amdgpu_crtc
->pflip_status
,
3262 AMDGPU_FLIP_SUBMITTED
);
3263 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
3267 /* page flip completed. clean up */
3268 amdgpu_crtc
->pflip_status
= AMDGPU_FLIP_NONE
;
3269 amdgpu_crtc
->pflip_works
= NULL
;
3271 /* wakeup usersapce */
3273 drm_crtc_send_vblank_event(&amdgpu_crtc
->base
, works
->event
);
3275 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
3277 drm_crtc_vblank_put(&amdgpu_crtc
->base
);
3278 schedule_work(&works
->unpin_work
);
3283 static void dce_v11_0_hpd_int_ack(struct amdgpu_device
*adev
,
3288 if (hpd
>= adev
->mode_info
.num_hpd
) {
3289 DRM_DEBUG("invalid hdp %d\n", hpd
);
3293 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
3294 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_ACK
, 1);
3295 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
3298 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device
*adev
,
3303 if (crtc
< 0 || crtc
>= adev
->mode_info
.num_crtc
) {
3304 DRM_DEBUG("invalid crtc %d\n", crtc
);
3308 tmp
= RREG32(mmLB_VBLANK_STATUS
+ crtc_offsets
[crtc
]);
3309 tmp
= REG_SET_FIELD(tmp
, LB_VBLANK_STATUS
, VBLANK_ACK
, 1);
3310 WREG32(mmLB_VBLANK_STATUS
+ crtc_offsets
[crtc
], tmp
);
3313 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device
*adev
,
3318 if (crtc
< 0 || crtc
>= adev
->mode_info
.num_crtc
) {
3319 DRM_DEBUG("invalid crtc %d\n", crtc
);
3323 tmp
= RREG32(mmLB_VLINE_STATUS
+ crtc_offsets
[crtc
]);
3324 tmp
= REG_SET_FIELD(tmp
, LB_VLINE_STATUS
, VLINE_ACK
, 1);
3325 WREG32(mmLB_VLINE_STATUS
+ crtc_offsets
[crtc
], tmp
);
3328 static int dce_v11_0_crtc_irq(struct amdgpu_device
*adev
,
3329 struct amdgpu_irq_src
*source
,
3330 struct amdgpu_iv_entry
*entry
)
3332 unsigned crtc
= entry
->src_id
- 1;
3333 uint32_t disp_int
= RREG32(interrupt_status_offsets
[crtc
].reg
);
3334 unsigned int irq_type
= amdgpu_display_crtc_idx_to_irq_type(adev
,
3337 switch (entry
->src_data
[0]) {
3338 case 0: /* vblank */
3339 if (disp_int
& interrupt_status_offsets
[crtc
].vblank
)
3340 dce_v11_0_crtc_vblank_int_ack(adev
, crtc
);
3342 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3344 if (amdgpu_irq_enabled(adev
, source
, irq_type
)) {
3345 drm_handle_vblank(adev
->ddev
, crtc
);
3347 DRM_DEBUG("IH: D%d vblank\n", crtc
+ 1);
3351 if (disp_int
& interrupt_status_offsets
[crtc
].vline
)
3352 dce_v11_0_crtc_vline_int_ack(adev
, crtc
);
3354 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3356 DRM_DEBUG("IH: D%d vline\n", crtc
+ 1);
3360 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry
->src_id
, entry
->src_data
[0]);
3367 static int dce_v11_0_hpd_irq(struct amdgpu_device
*adev
,
3368 struct amdgpu_irq_src
*source
,
3369 struct amdgpu_iv_entry
*entry
)
3371 uint32_t disp_int
, mask
;
3374 if (entry
->src_data
[0] >= adev
->mode_info
.num_hpd
) {
3375 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry
->src_id
, entry
->src_data
[0]);
3379 hpd
= entry
->src_data
[0];
3380 disp_int
= RREG32(interrupt_status_offsets
[hpd
].reg
);
3381 mask
= interrupt_status_offsets
[hpd
].hpd
;
3383 if (disp_int
& mask
) {
3384 dce_v11_0_hpd_int_ack(adev
, hpd
);
3385 schedule_work(&adev
->hotplug_work
);
3386 DRM_DEBUG("IH: HPD%d\n", hpd
+ 1);
3392 static int dce_v11_0_set_clockgating_state(void *handle
,
3393 enum amd_clockgating_state state
)
3398 static int dce_v11_0_set_powergating_state(void *handle
,
3399 enum amd_powergating_state state
)
3404 static const struct amd_ip_funcs dce_v11_0_ip_funcs
= {
3405 .name
= "dce_v11_0",
3406 .early_init
= dce_v11_0_early_init
,
3408 .sw_init
= dce_v11_0_sw_init
,
3409 .sw_fini
= dce_v11_0_sw_fini
,
3410 .hw_init
= dce_v11_0_hw_init
,
3411 .hw_fini
= dce_v11_0_hw_fini
,
3412 .suspend
= dce_v11_0_suspend
,
3413 .resume
= dce_v11_0_resume
,
3414 .is_idle
= dce_v11_0_is_idle
,
3415 .wait_for_idle
= dce_v11_0_wait_for_idle
,
3416 .soft_reset
= dce_v11_0_soft_reset
,
3417 .set_clockgating_state
= dce_v11_0_set_clockgating_state
,
3418 .set_powergating_state
= dce_v11_0_set_powergating_state
,
3422 dce_v11_0_encoder_mode_set(struct drm_encoder
*encoder
,
3423 struct drm_display_mode
*mode
,
3424 struct drm_display_mode
*adjusted_mode
)
3426 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3428 amdgpu_encoder
->pixel_clock
= adjusted_mode
->clock
;
3430 /* need to call this here rather than in prepare() since we need some crtc info */
3431 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
3433 /* set scaler clears this on some chips */
3434 dce_v11_0_set_interleave(encoder
->crtc
, mode
);
3436 if (amdgpu_atombios_encoder_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
) {
3437 dce_v11_0_afmt_enable(encoder
, true);
3438 dce_v11_0_afmt_setmode(encoder
, adjusted_mode
);
3442 static void dce_v11_0_encoder_prepare(struct drm_encoder
*encoder
)
3444 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
3445 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3446 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
3448 if ((amdgpu_encoder
->active_device
&
3449 (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
3450 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) !=
3451 ENCODER_OBJECT_ID_NONE
)) {
3452 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
3454 dig
->dig_encoder
= dce_v11_0_pick_dig_encoder(encoder
);
3455 if (amdgpu_encoder
->active_device
& ATOM_DEVICE_DFP_SUPPORT
)
3456 dig
->afmt
= adev
->mode_info
.afmt
[dig
->dig_encoder
];
3460 amdgpu_atombios_scratch_regs_lock(adev
, true);
3463 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
3465 /* select the clock/data port if it uses a router */
3466 if (amdgpu_connector
->router
.cd_valid
)
3467 amdgpu_i2c_router_select_cd_port(amdgpu_connector
);
3469 /* turn eDP panel on for mode set */
3470 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3471 amdgpu_atombios_encoder_set_edp_panel_power(connector
,
3472 ATOM_TRANSMITTER_ACTION_POWER_ON
);
3475 /* this is needed for the pll/ss setup to work correctly in some cases */
3476 amdgpu_atombios_encoder_set_crtc_source(encoder
);
3477 /* set up the FMT blocks */
3478 dce_v11_0_program_fmt(encoder
);
3481 static void dce_v11_0_encoder_commit(struct drm_encoder
*encoder
)
3483 struct drm_device
*dev
= encoder
->dev
;
3484 struct amdgpu_device
*adev
= dev
->dev_private
;
3486 /* need to call this here as we need the crtc set up */
3487 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_ON
);
3488 amdgpu_atombios_scratch_regs_lock(adev
, false);
3491 static void dce_v11_0_encoder_disable(struct drm_encoder
*encoder
)
3493 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3494 struct amdgpu_encoder_atom_dig
*dig
;
3496 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
3498 if (amdgpu_atombios_encoder_is_digital(encoder
)) {
3499 if (amdgpu_atombios_encoder_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
)
3500 dce_v11_0_afmt_enable(encoder
, false);
3501 dig
= amdgpu_encoder
->enc_priv
;
3502 dig
->dig_encoder
= -1;
3504 amdgpu_encoder
->active_device
= 0;
3507 /* these are handled by the primary encoders */
3508 static void dce_v11_0_ext_prepare(struct drm_encoder
*encoder
)
3513 static void dce_v11_0_ext_commit(struct drm_encoder
*encoder
)
3519 dce_v11_0_ext_mode_set(struct drm_encoder
*encoder
,
3520 struct drm_display_mode
*mode
,
3521 struct drm_display_mode
*adjusted_mode
)
3526 static void dce_v11_0_ext_disable(struct drm_encoder
*encoder
)
3532 dce_v11_0_ext_dpms(struct drm_encoder
*encoder
, int mode
)
3537 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs
= {
3538 .dpms
= dce_v11_0_ext_dpms
,
3539 .prepare
= dce_v11_0_ext_prepare
,
3540 .mode_set
= dce_v11_0_ext_mode_set
,
3541 .commit
= dce_v11_0_ext_commit
,
3542 .disable
= dce_v11_0_ext_disable
,
3543 /* no detect for TMDS/LVDS yet */
3546 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs
= {
3547 .dpms
= amdgpu_atombios_encoder_dpms
,
3548 .mode_fixup
= amdgpu_atombios_encoder_mode_fixup
,
3549 .prepare
= dce_v11_0_encoder_prepare
,
3550 .mode_set
= dce_v11_0_encoder_mode_set
,
3551 .commit
= dce_v11_0_encoder_commit
,
3552 .disable
= dce_v11_0_encoder_disable
,
3553 .detect
= amdgpu_atombios_encoder_dig_detect
,
3556 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs
= {
3557 .dpms
= amdgpu_atombios_encoder_dpms
,
3558 .mode_fixup
= amdgpu_atombios_encoder_mode_fixup
,
3559 .prepare
= dce_v11_0_encoder_prepare
,
3560 .mode_set
= dce_v11_0_encoder_mode_set
,
3561 .commit
= dce_v11_0_encoder_commit
,
3562 .detect
= amdgpu_atombios_encoder_dac_detect
,
3565 static void dce_v11_0_encoder_destroy(struct drm_encoder
*encoder
)
3567 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3568 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
3569 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder
);
3570 kfree(amdgpu_encoder
->enc_priv
);
3571 drm_encoder_cleanup(encoder
);
3572 kfree(amdgpu_encoder
);
3575 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs
= {
3576 .destroy
= dce_v11_0_encoder_destroy
,
3579 static void dce_v11_0_encoder_add(struct amdgpu_device
*adev
,
3580 uint32_t encoder_enum
,
3581 uint32_t supported_device
,
3584 struct drm_device
*dev
= adev
->ddev
;
3585 struct drm_encoder
*encoder
;
3586 struct amdgpu_encoder
*amdgpu_encoder
;
3588 /* see if we already added it */
3589 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3590 amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3591 if (amdgpu_encoder
->encoder_enum
== encoder_enum
) {
3592 amdgpu_encoder
->devices
|= supported_device
;
3599 amdgpu_encoder
= kzalloc(sizeof(struct amdgpu_encoder
), GFP_KERNEL
);
3600 if (!amdgpu_encoder
)
3603 encoder
= &amdgpu_encoder
->base
;
3604 switch (adev
->mode_info
.num_crtc
) {
3606 encoder
->possible_crtcs
= 0x1;
3610 encoder
->possible_crtcs
= 0x3;
3613 encoder
->possible_crtcs
= 0x7;
3616 encoder
->possible_crtcs
= 0xf;
3619 encoder
->possible_crtcs
= 0x1f;
3622 encoder
->possible_crtcs
= 0x3f;
3626 amdgpu_encoder
->enc_priv
= NULL
;
3628 amdgpu_encoder
->encoder_enum
= encoder_enum
;
3629 amdgpu_encoder
->encoder_id
= (encoder_enum
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
3630 amdgpu_encoder
->devices
= supported_device
;
3631 amdgpu_encoder
->rmx_type
= RMX_OFF
;
3632 amdgpu_encoder
->underscan_type
= UNDERSCAN_OFF
;
3633 amdgpu_encoder
->is_ext_encoder
= false;
3634 amdgpu_encoder
->caps
= caps
;
3636 switch (amdgpu_encoder
->encoder_id
) {
3637 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
3638 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
3639 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3640 DRM_MODE_ENCODER_DAC
, NULL
);
3641 drm_encoder_helper_add(encoder
, &dce_v11_0_dac_helper_funcs
);
3643 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
3644 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
3645 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
3646 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
3647 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
3648 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
3649 amdgpu_encoder
->rmx_type
= RMX_FULL
;
3650 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3651 DRM_MODE_ENCODER_LVDS
, NULL
);
3652 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder
);
3653 } else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
3654 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3655 DRM_MODE_ENCODER_DAC
, NULL
);
3656 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder
);
3658 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3659 DRM_MODE_ENCODER_TMDS
, NULL
);
3660 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder
);
3662 drm_encoder_helper_add(encoder
, &dce_v11_0_dig_helper_funcs
);
3664 case ENCODER_OBJECT_ID_SI170B
:
3665 case ENCODER_OBJECT_ID_CH7303
:
3666 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA
:
3667 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB
:
3668 case ENCODER_OBJECT_ID_TITFP513
:
3669 case ENCODER_OBJECT_ID_VT1623
:
3670 case ENCODER_OBJECT_ID_HDMI_SI1930
:
3671 case ENCODER_OBJECT_ID_TRAVIS
:
3672 case ENCODER_OBJECT_ID_NUTMEG
:
3673 /* these are handled by the primary encoders */
3674 amdgpu_encoder
->is_ext_encoder
= true;
3675 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
3676 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3677 DRM_MODE_ENCODER_LVDS
, NULL
);
3678 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
))
3679 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3680 DRM_MODE_ENCODER_DAC
, NULL
);
3682 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3683 DRM_MODE_ENCODER_TMDS
, NULL
);
3684 drm_encoder_helper_add(encoder
, &dce_v11_0_ext_helper_funcs
);
3689 static const struct amdgpu_display_funcs dce_v11_0_display_funcs
= {
3690 .bandwidth_update
= &dce_v11_0_bandwidth_update
,
3691 .vblank_get_counter
= &dce_v11_0_vblank_get_counter
,
3692 .backlight_set_level
= &amdgpu_atombios_encoder_set_backlight_level
,
3693 .backlight_get_level
= &amdgpu_atombios_encoder_get_backlight_level
,
3694 .hpd_sense
= &dce_v11_0_hpd_sense
,
3695 .hpd_set_polarity
= &dce_v11_0_hpd_set_polarity
,
3696 .hpd_get_gpio_reg
= &dce_v11_0_hpd_get_gpio_reg
,
3697 .page_flip
= &dce_v11_0_page_flip
,
3698 .page_flip_get_scanoutpos
= &dce_v11_0_crtc_get_scanoutpos
,
3699 .add_encoder
= &dce_v11_0_encoder_add
,
3700 .add_connector
= &amdgpu_connector_add
,
3703 static void dce_v11_0_set_display_funcs(struct amdgpu_device
*adev
)
3705 if (adev
->mode_info
.funcs
== NULL
)
3706 adev
->mode_info
.funcs
= &dce_v11_0_display_funcs
;
3709 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs
= {
3710 .set
= dce_v11_0_set_crtc_irq_state
,
3711 .process
= dce_v11_0_crtc_irq
,
3714 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs
= {
3715 .set
= dce_v11_0_set_pageflip_irq_state
,
3716 .process
= dce_v11_0_pageflip_irq
,
3719 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs
= {
3720 .set
= dce_v11_0_set_hpd_irq_state
,
3721 .process
= dce_v11_0_hpd_irq
,
3724 static void dce_v11_0_set_irq_funcs(struct amdgpu_device
*adev
)
3726 if (adev
->mode_info
.num_crtc
> 0)
3727 adev
->crtc_irq
.num_types
= AMDGPU_CRTC_IRQ_VLINE1
+ adev
->mode_info
.num_crtc
;
3729 adev
->crtc_irq
.num_types
= 0;
3730 adev
->crtc_irq
.funcs
= &dce_v11_0_crtc_irq_funcs
;
3732 adev
->pageflip_irq
.num_types
= adev
->mode_info
.num_crtc
;
3733 adev
->pageflip_irq
.funcs
= &dce_v11_0_pageflip_irq_funcs
;
3735 adev
->hpd_irq
.num_types
= adev
->mode_info
.num_hpd
;
3736 adev
->hpd_irq
.funcs
= &dce_v11_0_hpd_irq_funcs
;
3739 const struct amdgpu_ip_block_version dce_v11_0_ip_block
=
3741 .type
= AMD_IP_BLOCK_TYPE_DCE
,
3745 .funcs
= &dce_v11_0_ip_funcs
,
3748 const struct amdgpu_ip_block_version dce_v11_2_ip_block
=
3750 .type
= AMD_IP_BLOCK_TYPE_DCE
,
3754 .funcs
= &dce_v11_0_ip_funcs
,