]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:


af26ec0bc59d35b1c09b00cb7be2fb4c5ca5ede0
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / amdgpu / dce_v11_0.c
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "drmP.h"
24 #include "amdgpu.h"
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
27 #include "vid.h"
28 #include "atom.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
34
35 #include "dce/dce_11_0_d.h"
36 #include "dce/dce_11_0_sh_mask.h"
37 #include "dce/dce_11_0_enum.h"
38 #include "oss/oss_3_0_d.h"
39 #include "oss/oss_3_0_sh_mask.h"
40 #include "gmc/gmc_8_1_d.h"
41 #include "gmc/gmc_8_1_sh_mask.h"
42
43 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
45
46 static const u32 crtc_offsets[] =
47 {
48 CRTC0_REGISTER_OFFSET,
49 CRTC1_REGISTER_OFFSET,
50 CRTC2_REGISTER_OFFSET,
51 CRTC3_REGISTER_OFFSET,
52 CRTC4_REGISTER_OFFSET,
53 CRTC5_REGISTER_OFFSET,
54 CRTC6_REGISTER_OFFSET
55 };
56
57 static const u32 hpd_offsets[] =
58 {
59 HPD0_REGISTER_OFFSET,
60 HPD1_REGISTER_OFFSET,
61 HPD2_REGISTER_OFFSET,
62 HPD3_REGISTER_OFFSET,
63 HPD4_REGISTER_OFFSET,
64 HPD5_REGISTER_OFFSET
65 };
66
67 static const uint32_t dig_offsets[] = {
68 DIG0_REGISTER_OFFSET,
69 DIG1_REGISTER_OFFSET,
70 DIG2_REGISTER_OFFSET,
71 DIG3_REGISTER_OFFSET,
72 DIG4_REGISTER_OFFSET,
73 DIG5_REGISTER_OFFSET,
74 DIG6_REGISTER_OFFSET,
75 DIG7_REGISTER_OFFSET,
76 DIG8_REGISTER_OFFSET
77 };
78
79 static const struct {
80 uint32_t reg;
81 uint32_t vblank;
82 uint32_t vline;
83 uint32_t hpd;
84
85 } interrupt_status_offsets[] = { {
86 .reg = mmDISP_INTERRUPT_STATUS,
87 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
88 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
89 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
90 }, {
91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
95 }, {
96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
100 }, {
101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
105 }, {
106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
110 }, {
111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
115 } };
116
117 static const u32 cz_golden_settings_a11[] =
118 {
119 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
120 mmFBC_MISC, 0x1f311fff, 0x14300000,
121 };
122
123 static const u32 cz_mgcg_cgcg_init[] =
124 {
125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
127 };
128
129 static const u32 stoney_golden_settings_a11[] =
130 {
131 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
132 mmFBC_MISC, 0x1f311fff, 0x14302000,
133 };
134
135 static const u32 polaris11_golden_settings_a11[] =
136 {
137 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
138 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
139 mmFBC_DEBUG1, 0xffffffff, 0x00000008,
140 mmFBC_MISC, 0x9f313fff, 0x14302008,
141 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
142 };
143
144 static const u32 polaris10_golden_settings_a11[] =
145 {
146 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
147 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
148 mmFBC_MISC, 0x9f313fff, 0x14302008,
149 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
150 };
151
152 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
153 {
154 switch (adev->asic_type) {
155 case CHIP_CARRIZO:
156 amdgpu_program_register_sequence(adev,
157 cz_mgcg_cgcg_init,
158 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
159 amdgpu_program_register_sequence(adev,
160 cz_golden_settings_a11,
161 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
162 break;
163 case CHIP_STONEY:
164 amdgpu_program_register_sequence(adev,
165 stoney_golden_settings_a11,
166 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
167 break;
168 case CHIP_POLARIS11:
169 amdgpu_program_register_sequence(adev,
170 polaris11_golden_settings_a11,
171 (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
172 break;
173 case CHIP_POLARIS10:
174 amdgpu_program_register_sequence(adev,
175 polaris10_golden_settings_a11,
176 (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
177 break;
178 default:
179 break;
180 }
181 }
182
183 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
184 u32 block_offset, u32 reg)
185 {
186 unsigned long flags;
187 u32 r;
188
189 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
190 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
191 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
192 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
193
194 return r;
195 }
196
197 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
198 u32 block_offset, u32 reg, u32 v)
199 {
200 unsigned long flags;
201
202 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
203 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
204 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
205 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
206 }
207
208 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
209 {
210 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
211 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
212 return true;
213 else
214 return false;
215 }
216
217 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
218 {
219 u32 pos1, pos2;
220
221 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
222 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
223
224 if (pos1 != pos2)
225 return true;
226 else
227 return false;
228 }
229
230 /**
231 * dce_v11_0_vblank_wait - vblank wait asic callback.
232 *
233 * @adev: amdgpu_device pointer
234 * @crtc: crtc to wait for vblank on
235 *
236 * Wait for vblank on the requested crtc (evergreen+).
237 */
238 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
239 {
240 unsigned i = 100;
241
242 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
243 return;
244
245 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
246 return;
247
248 /* depending on when we hit vblank, we may be close to active; if so,
249 * wait for another frame.
250 */
251 while (dce_v11_0_is_in_vblank(adev, crtc)) {
252 if (i++ == 100) {
253 i = 0;
254 if (!dce_v11_0_is_counter_moving(adev, crtc))
255 break;
256 }
257 }
258
259 while (!dce_v11_0_is_in_vblank(adev, crtc)) {
260 if (i++ == 100) {
261 i = 0;
262 if (!dce_v11_0_is_counter_moving(adev, crtc))
263 break;
264 }
265 }
266 }
267
268 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
269 {
270 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
271 return 0;
272 else
273 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
274 }
275
276 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
277 {
278 unsigned i;
279
280 /* Enable pflip interrupts */
281 for (i = 0; i < adev->mode_info.num_crtc; i++)
282 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
283 }
284
285 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
286 {
287 unsigned i;
288
289 /* Disable pflip interrupts */
290 for (i = 0; i < adev->mode_info.num_crtc; i++)
291 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
292 }
293
294 /**
295 * dce_v11_0_page_flip - pageflip callback.
296 *
297 * @adev: amdgpu_device pointer
298 * @crtc_id: crtc to cleanup pageflip on
299 * @crtc_base: new address of the crtc (GPU MC address)
300 *
301 * Triggers the actual pageflip by updating the primary
302 * surface base address.
303 */
304 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
305 int crtc_id, u64 crtc_base, bool async)
306 {
307 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
308 u32 tmp;
309
310 /* flip at hsync for async, default is vsync */
311 /* use UPDATE_IMMEDIATE_EN instead for async? */
312 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
313 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
314 GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
315 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
316 /* update the scanout addresses */
317 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
318 upper_32_bits(crtc_base));
319 /* writing to the low address triggers the update */
320 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
321 lower_32_bits(crtc_base));
322 /* post the write */
323 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
324 }
325
326 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
327 u32 *vbl, u32 *position)
328 {
329 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
330 return -EINVAL;
331
332 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
333 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
334
335 return 0;
336 }
337
338 /**
339 * dce_v11_0_hpd_sense - hpd sense callback.
340 *
341 * @adev: amdgpu_device pointer
342 * @hpd: hpd (hotplug detect) pin
343 *
344 * Checks if a digital monitor is connected (evergreen+).
345 * Returns true if connected, false if not connected.
346 */
347 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
348 enum amdgpu_hpd_id hpd)
349 {
350 int idx;
351 bool connected = false;
352
353 switch (hpd) {
354 case AMDGPU_HPD_1:
355 idx = 0;
356 break;
357 case AMDGPU_HPD_2:
358 idx = 1;
359 break;
360 case AMDGPU_HPD_3:
361 idx = 2;
362 break;
363 case AMDGPU_HPD_4:
364 idx = 3;
365 break;
366 case AMDGPU_HPD_5:
367 idx = 4;
368 break;
369 case AMDGPU_HPD_6:
370 idx = 5;
371 break;
372 default:
373 return connected;
374 }
375
376 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
377 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
378 connected = true;
379
380 return connected;
381 }
382
383 /**
384 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
385 *
386 * @adev: amdgpu_device pointer
387 * @hpd: hpd (hotplug detect) pin
388 *
389 * Set the polarity of the hpd pin (evergreen+).
390 */
391 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
392 enum amdgpu_hpd_id hpd)
393 {
394 u32 tmp;
395 bool connected = dce_v11_0_hpd_sense(adev, hpd);
396 int idx;
397
398 switch (hpd) {
399 case AMDGPU_HPD_1:
400 idx = 0;
401 break;
402 case AMDGPU_HPD_2:
403 idx = 1;
404 break;
405 case AMDGPU_HPD_3:
406 idx = 2;
407 break;
408 case AMDGPU_HPD_4:
409 idx = 3;
410 break;
411 case AMDGPU_HPD_5:
412 idx = 4;
413 break;
414 case AMDGPU_HPD_6:
415 idx = 5;
416 break;
417 default:
418 return;
419 }
420
421 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
422 if (connected)
423 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
424 else
425 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
426 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
427 }
428
429 /**
430 * dce_v11_0_hpd_init - hpd setup callback.
431 *
432 * @adev: amdgpu_device pointer
433 *
434 * Setup the hpd pins used by the card (evergreen+).
435 * Enable the pin, set the polarity, and enable the hpd interrupts.
436 */
437 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
438 {
439 struct drm_device *dev = adev->ddev;
440 struct drm_connector *connector;
441 u32 tmp;
442 int idx;
443
444 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
445 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
446
447 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
448 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
449 /* don't try to enable hpd on eDP or LVDS avoid breaking the
450 * aux dp channel on imac and help (but not completely fix)
451 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
452 * also avoid interrupt storms during dpms.
453 */
454 continue;
455 }
456
457 switch (amdgpu_connector->hpd.hpd) {
458 case AMDGPU_HPD_1:
459 idx = 0;
460 break;
461 case AMDGPU_HPD_2:
462 idx = 1;
463 break;
464 case AMDGPU_HPD_3:
465 idx = 2;
466 break;
467 case AMDGPU_HPD_4:
468 idx = 3;
469 break;
470 case AMDGPU_HPD_5:
471 idx = 4;
472 break;
473 case AMDGPU_HPD_6:
474 idx = 5;
475 break;
476 default:
477 continue;
478 }
479
480 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
481 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
482 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
483
484 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
485 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
486 DC_HPD_CONNECT_INT_DELAY,
487 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
488 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
489 DC_HPD_DISCONNECT_INT_DELAY,
490 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
491 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
492
493 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
494 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
495 }
496 }
497
498 /**
499 * dce_v11_0_hpd_fini - hpd tear down callback.
500 *
501 * @adev: amdgpu_device pointer
502 *
503 * Tear down the hpd pins used by the card (evergreen+).
504 * Disable the hpd interrupts.
505 */
506 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
507 {
508 struct drm_device *dev = adev->ddev;
509 struct drm_connector *connector;
510 u32 tmp;
511 int idx;
512
513 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
514 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
515
516 switch (amdgpu_connector->hpd.hpd) {
517 case AMDGPU_HPD_1:
518 idx = 0;
519 break;
520 case AMDGPU_HPD_2:
521 idx = 1;
522 break;
523 case AMDGPU_HPD_3:
524 idx = 2;
525 break;
526 case AMDGPU_HPD_4:
527 idx = 3;
528 break;
529 case AMDGPU_HPD_5:
530 idx = 4;
531 break;
532 case AMDGPU_HPD_6:
533 idx = 5;
534 break;
535 default:
536 continue;
537 }
538
539 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
540 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
541 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
542
543 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
544 }
545 }
546
547 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
548 {
549 return mmDC_GPIO_HPD_A;
550 }
551
552 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
553 {
554 u32 crtc_hung = 0;
555 u32 crtc_status[6];
556 u32 i, j, tmp;
557
558 for (i = 0; i < adev->mode_info.num_crtc; i++) {
559 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
560 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
561 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
562 crtc_hung |= (1 << i);
563 }
564 }
565
566 for (j = 0; j < 10; j++) {
567 for (i = 0; i < adev->mode_info.num_crtc; i++) {
568 if (crtc_hung & (1 << i)) {
569 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
570 if (tmp != crtc_status[i])
571 crtc_hung &= ~(1 << i);
572 }
573 }
574 if (crtc_hung == 0)
575 return false;
576 udelay(100);
577 }
578
579 return true;
580 }
581
582 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
583 struct amdgpu_mode_mc_save *save)
584 {
585 u32 crtc_enabled, tmp;
586 int i;
587
588 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
589 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
590
591 /* disable VGA render */
592 tmp = RREG32(mmVGA_RENDER_CONTROL);
593 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
594 WREG32(mmVGA_RENDER_CONTROL, tmp);
595
596 /* blank the display controllers */
597 for (i = 0; i < adev->mode_info.num_crtc; i++) {
598 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
599 CRTC_CONTROL, CRTC_MASTER_EN);
600 if (crtc_enabled) {
601 #if 1
602 save->crtc_enabled[i] = true;
603 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
604 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
605 /*it is correct only for RGB ; black is 0*/
606 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
607 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
608 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
609 }
610 #else
611 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
612 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
613 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
614 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
615 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
616 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
617 save->crtc_enabled[i] = false;
618 /* ***** */
619 #endif
620 } else {
621 save->crtc_enabled[i] = false;
622 }
623 }
624 }
625
626 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
627 struct amdgpu_mode_mc_save *save)
628 {
629 u32 tmp;
630 int i;
631
632 /* update crtc base addresses */
633 for (i = 0; i < adev->mode_info.num_crtc; i++) {
634 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
635 upper_32_bits(adev->mc.vram_start));
636 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
637 (u32)adev->mc.vram_start);
638
639 if (save->crtc_enabled[i]) {
640 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
641 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
642 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
643 }
644 }
645
646 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
647 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
648
649 /* Unlock vga access */
650 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
651 mdelay(1);
652 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
653 }
654
655 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
656 bool render)
657 {
658 u32 tmp;
659
660 /* Lockout access through VGA aperture*/
661 tmp = RREG32(mmVGA_HDP_CONTROL);
662 if (render)
663 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
664 else
665 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
666 WREG32(mmVGA_HDP_CONTROL, tmp);
667
668 /* disable VGA render */
669 tmp = RREG32(mmVGA_RENDER_CONTROL);
670 if (render)
671 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
672 else
673 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
674 WREG32(mmVGA_RENDER_CONTROL, tmp);
675 }
676
677 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
678 {
679 struct drm_device *dev = encoder->dev;
680 struct amdgpu_device *adev = dev->dev_private;
681 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
682 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
683 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
684 int bpc = 0;
685 u32 tmp = 0;
686 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
687
688 if (connector) {
689 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
690 bpc = amdgpu_connector_get_monitor_bpc(connector);
691 dither = amdgpu_connector->dither;
692 }
693
694 /* LVDS/eDP FMT is set up by atom */
695 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
696 return;
697
698 /* not needed for analog */
699 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
700 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
701 return;
702
703 if (bpc == 0)
704 return;
705
706 switch (bpc) {
707 case 6:
708 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
709 /* XXX sort out optimal dither settings */
710 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
711 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
712 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
713 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
714 } else {
715 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
716 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
717 }
718 break;
719 case 8:
720 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
721 /* XXX sort out optimal dither settings */
722 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
723 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
724 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
725 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
726 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
727 } else {
728 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
729 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
730 }
731 break;
732 case 10:
733 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
734 /* XXX sort out optimal dither settings */
735 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
736 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
737 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
738 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
739 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
740 } else {
741 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
742 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
743 }
744 break;
745 default:
746 /* not needed */
747 break;
748 }
749
750 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
751 }
752
753
754 /* display watermark setup */
755 /**
756 * dce_v11_0_line_buffer_adjust - Set up the line buffer
757 *
758 * @adev: amdgpu_device pointer
759 * @amdgpu_crtc: the selected display controller
760 * @mode: the current display mode on the selected display
761 * controller
762 *
763 * Setup up the line buffer allocation for
764 * the selected display controller (CIK).
765 * Returns the line buffer size in pixels.
766 */
767 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
768 struct amdgpu_crtc *amdgpu_crtc,
769 struct drm_display_mode *mode)
770 {
771 u32 tmp, buffer_alloc, i, mem_cfg;
772 u32 pipe_offset = amdgpu_crtc->crtc_id;
773 /*
774 * Line Buffer Setup
775 * There are 6 line buffers, one for each display controllers.
776 * There are 3 partitions per LB. Select the number of partitions
777 * to enable based on the display width. For display widths larger
778 * than 4096, you need use to use 2 display controllers and combine
779 * them using the stereo blender.
780 */
781 if (amdgpu_crtc->base.enabled && mode) {
782 if (mode->crtc_hdisplay < 1920) {
783 mem_cfg = 1;
784 buffer_alloc = 2;
785 } else if (mode->crtc_hdisplay < 2560) {
786 mem_cfg = 2;
787 buffer_alloc = 2;
788 } else if (mode->crtc_hdisplay < 4096) {
789 mem_cfg = 0;
790 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
791 } else {
792 DRM_DEBUG_KMS("Mode too big for LB!\n");
793 mem_cfg = 0;
794 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
795 }
796 } else {
797 mem_cfg = 1;
798 buffer_alloc = 0;
799 }
800
801 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
802 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
803 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
804
805 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
806 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
807 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
808
809 for (i = 0; i < adev->usec_timeout; i++) {
810 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
811 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
812 break;
813 udelay(1);
814 }
815
816 if (amdgpu_crtc->base.enabled && mode) {
817 switch (mem_cfg) {
818 case 0:
819 default:
820 return 4096 * 2;
821 case 1:
822 return 1920 * 2;
823 case 2:
824 return 2560 * 2;
825 }
826 }
827
828 /* controller not enabled, so no lb used */
829 return 0;
830 }
831
832 /**
833 * cik_get_number_of_dram_channels - get the number of dram channels
834 *
835 * @adev: amdgpu_device pointer
836 *
837 * Look up the number of video ram channels (CIK).
838 * Used for display watermark bandwidth calculations
839 * Returns the number of dram channels
840 */
841 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
842 {
843 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
844
845 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
846 case 0:
847 default:
848 return 1;
849 case 1:
850 return 2;
851 case 2:
852 return 4;
853 case 3:
854 return 8;
855 case 4:
856 return 3;
857 case 5:
858 return 6;
859 case 6:
860 return 10;
861 case 7:
862 return 12;
863 case 8:
864 return 16;
865 }
866 }
867
868 struct dce10_wm_params {
869 u32 dram_channels; /* number of dram channels */
870 u32 yclk; /* bandwidth per dram data pin in kHz */
871 u32 sclk; /* engine clock in kHz */
872 u32 disp_clk; /* display clock in kHz */
873 u32 src_width; /* viewport width */
874 u32 active_time; /* active display time in ns */
875 u32 blank_time; /* blank time in ns */
876 bool interlaced; /* mode is interlaced */
877 fixed20_12 vsc; /* vertical scale ratio */
878 u32 num_heads; /* number of active crtcs */
879 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
880 u32 lb_size; /* line buffer allocated to pipe */
881 u32 vtaps; /* vertical scaler taps */
882 };
883
884 /**
885 * dce_v11_0_dram_bandwidth - get the dram bandwidth
886 *
887 * @wm: watermark calculation data
888 *
889 * Calculate the raw dram bandwidth (CIK).
890 * Used for display watermark bandwidth calculations
891 * Returns the dram bandwidth in MBytes/s
892 */
893 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
894 {
895 /* Calculate raw DRAM Bandwidth */
896 fixed20_12 dram_efficiency; /* 0.7 */
897 fixed20_12 yclk, dram_channels, bandwidth;
898 fixed20_12 a;
899
900 a.full = dfixed_const(1000);
901 yclk.full = dfixed_const(wm->yclk);
902 yclk.full = dfixed_div(yclk, a);
903 dram_channels.full = dfixed_const(wm->dram_channels * 4);
904 a.full = dfixed_const(10);
905 dram_efficiency.full = dfixed_const(7);
906 dram_efficiency.full = dfixed_div(dram_efficiency, a);
907 bandwidth.full = dfixed_mul(dram_channels, yclk);
908 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
909
910 return dfixed_trunc(bandwidth);
911 }
912
913 /**
914 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
915 *
916 * @wm: watermark calculation data
917 *
918 * Calculate the dram bandwidth used for display (CIK).
919 * Used for display watermark bandwidth calculations
920 * Returns the dram bandwidth for display in MBytes/s
921 */
922 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
923 {
924 /* Calculate DRAM Bandwidth and the part allocated to display. */
925 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
926 fixed20_12 yclk, dram_channels, bandwidth;
927 fixed20_12 a;
928
929 a.full = dfixed_const(1000);
930 yclk.full = dfixed_const(wm->yclk);
931 yclk.full = dfixed_div(yclk, a);
932 dram_channels.full = dfixed_const(wm->dram_channels * 4);
933 a.full = dfixed_const(10);
934 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
935 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
936 bandwidth.full = dfixed_mul(dram_channels, yclk);
937 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
938
939 return dfixed_trunc(bandwidth);
940 }
941
942 /**
943 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
944 *
945 * @wm: watermark calculation data
946 *
947 * Calculate the data return bandwidth used for display (CIK).
948 * Used for display watermark bandwidth calculations
949 * Returns the data return bandwidth in MBytes/s
950 */
951 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
952 {
953 /* Calculate the display Data return Bandwidth */
954 fixed20_12 return_efficiency; /* 0.8 */
955 fixed20_12 sclk, bandwidth;
956 fixed20_12 a;
957
958 a.full = dfixed_const(1000);
959 sclk.full = dfixed_const(wm->sclk);
960 sclk.full = dfixed_div(sclk, a);
961 a.full = dfixed_const(10);
962 return_efficiency.full = dfixed_const(8);
963 return_efficiency.full = dfixed_div(return_efficiency, a);
964 a.full = dfixed_const(32);
965 bandwidth.full = dfixed_mul(a, sclk);
966 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
967
968 return dfixed_trunc(bandwidth);
969 }
970
971 /**
972 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
973 *
974 * @wm: watermark calculation data
975 *
976 * Calculate the dmif bandwidth used for display (CIK).
977 * Used for display watermark bandwidth calculations
978 * Returns the dmif bandwidth in MBytes/s
979 */
980 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
981 {
982 /* Calculate the DMIF Request Bandwidth */
983 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
984 fixed20_12 disp_clk, bandwidth;
985 fixed20_12 a, b;
986
987 a.full = dfixed_const(1000);
988 disp_clk.full = dfixed_const(wm->disp_clk);
989 disp_clk.full = dfixed_div(disp_clk, a);
990 a.full = dfixed_const(32);
991 b.full = dfixed_mul(a, disp_clk);
992
993 a.full = dfixed_const(10);
994 disp_clk_request_efficiency.full = dfixed_const(8);
995 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
996
997 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
998
999 return dfixed_trunc(bandwidth);
1000 }
1001
1002 /**
1003 * dce_v11_0_available_bandwidth - get the min available bandwidth
1004 *
1005 * @wm: watermark calculation data
1006 *
1007 * Calculate the min available bandwidth used for display (CIK).
1008 * Used for display watermark bandwidth calculations
1009 * Returns the min available bandwidth in MBytes/s
1010 */
1011 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
1012 {
1013 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1014 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
1015 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
1016 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
1017
1018 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1019 }
1020
1021 /**
1022 * dce_v11_0_average_bandwidth - get the average available bandwidth
1023 *
1024 * @wm: watermark calculation data
1025 *
1026 * Calculate the average available bandwidth used for display (CIK).
1027 * Used for display watermark bandwidth calculations
1028 * Returns the average available bandwidth in MBytes/s
1029 */
1030 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
1031 {
1032 /* Calculate the display mode Average Bandwidth
1033 * DisplayMode should contain the source and destination dimensions,
1034 * timing, etc.
1035 */
1036 fixed20_12 bpp;
1037 fixed20_12 line_time;
1038 fixed20_12 src_width;
1039 fixed20_12 bandwidth;
1040 fixed20_12 a;
1041
1042 a.full = dfixed_const(1000);
1043 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1044 line_time.full = dfixed_div(line_time, a);
1045 bpp.full = dfixed_const(wm->bytes_per_pixel);
1046 src_width.full = dfixed_const(wm->src_width);
1047 bandwidth.full = dfixed_mul(src_width, bpp);
1048 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1049 bandwidth.full = dfixed_div(bandwidth, line_time);
1050
1051 return dfixed_trunc(bandwidth);
1052 }
1053
1054 /**
1055 * dce_v11_0_latency_watermark - get the latency watermark
1056 *
1057 * @wm: watermark calculation data
1058 *
1059 * Calculate the latency watermark (CIK).
1060 * Used for display watermark bandwidth calculations
1061 * Returns the latency watermark in ns
1062 */
1063 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1064 {
1065 /* First calculate the latency in ns */
1066 u32 mc_latency = 2000; /* 2000 ns. */
1067 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1068 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1069 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1070 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1071 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1072 (wm->num_heads * cursor_line_pair_return_time);
1073 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1074 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1075 u32 tmp, dmif_size = 12288;
1076 fixed20_12 a, b, c;
1077
1078 if (wm->num_heads == 0)
1079 return 0;
1080
1081 a.full = dfixed_const(2);
1082 b.full = dfixed_const(1);
1083 if ((wm->vsc.full > a.full) ||
1084 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1085 (wm->vtaps >= 5) ||
1086 ((wm->vsc.full >= a.full) && wm->interlaced))
1087 max_src_lines_per_dst_line = 4;
1088 else
1089 max_src_lines_per_dst_line = 2;
1090
1091 a.full = dfixed_const(available_bandwidth);
1092 b.full = dfixed_const(wm->num_heads);
1093 a.full = dfixed_div(a, b);
1094
1095 b.full = dfixed_const(mc_latency + 512);
1096 c.full = dfixed_const(wm->disp_clk);
1097 b.full = dfixed_div(b, c);
1098
1099 c.full = dfixed_const(dmif_size);
1100 b.full = dfixed_div(c, b);
1101
1102 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1103
1104 b.full = dfixed_const(1000);
1105 c.full = dfixed_const(wm->disp_clk);
1106 b.full = dfixed_div(c, b);
1107 c.full = dfixed_const(wm->bytes_per_pixel);
1108 b.full = dfixed_mul(b, c);
1109
1110 lb_fill_bw = min(tmp, dfixed_trunc(b));
1111
1112 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1113 b.full = dfixed_const(1000);
1114 c.full = dfixed_const(lb_fill_bw);
1115 b.full = dfixed_div(c, b);
1116 a.full = dfixed_div(a, b);
1117 line_fill_time = dfixed_trunc(a);
1118
1119 if (line_fill_time < wm->active_time)
1120 return latency;
1121 else
1122 return latency + (line_fill_time - wm->active_time);
1123
1124 }
1125
1126 /**
1127 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1128 * average and available dram bandwidth
1129 *
1130 * @wm: watermark calculation data
1131 *
1132 * Check if the display average bandwidth fits in the display
1133 * dram bandwidth (CIK).
1134 * Used for display watermark bandwidth calculations
1135 * Returns true if the display fits, false if not.
1136 */
1137 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1138 {
1139 if (dce_v11_0_average_bandwidth(wm) <=
1140 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1141 return true;
1142 else
1143 return false;
1144 }
1145
1146 /**
1147 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1148 * average and available bandwidth
1149 *
1150 * @wm: watermark calculation data
1151 *
1152 * Check if the display average bandwidth fits in the display
1153 * available bandwidth (CIK).
1154 * Used for display watermark bandwidth calculations
1155 * Returns true if the display fits, false if not.
1156 */
1157 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1158 {
1159 if (dce_v11_0_average_bandwidth(wm) <=
1160 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1161 return true;
1162 else
1163 return false;
1164 }
1165
1166 /**
1167 * dce_v11_0_check_latency_hiding - check latency hiding
1168 *
1169 * @wm: watermark calculation data
1170 *
1171 * Check latency hiding (CIK).
1172 * Used for display watermark bandwidth calculations
1173 * Returns true if the display fits, false if not.
1174 */
1175 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1176 {
1177 u32 lb_partitions = wm->lb_size / wm->src_width;
1178 u32 line_time = wm->active_time + wm->blank_time;
1179 u32 latency_tolerant_lines;
1180 u32 latency_hiding;
1181 fixed20_12 a;
1182
1183 a.full = dfixed_const(1);
1184 if (wm->vsc.full > a.full)
1185 latency_tolerant_lines = 1;
1186 else {
1187 if (lb_partitions <= (wm->vtaps + 1))
1188 latency_tolerant_lines = 1;
1189 else
1190 latency_tolerant_lines = 2;
1191 }
1192
1193 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1194
1195 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1196 return true;
1197 else
1198 return false;
1199 }
1200
1201 /**
1202 * dce_v11_0_program_watermarks - program display watermarks
1203 *
1204 * @adev: amdgpu_device pointer
1205 * @amdgpu_crtc: the selected display controller
1206 * @lb_size: line buffer size
1207 * @num_heads: number of display controllers in use
1208 *
1209 * Calculate and program the display watermarks for the
1210 * selected display controller (CIK).
1211 */
1212 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1213 struct amdgpu_crtc *amdgpu_crtc,
1214 u32 lb_size, u32 num_heads)
1215 {
1216 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1217 struct dce10_wm_params wm_low, wm_high;
1218 u32 pixel_period;
1219 u32 line_time = 0;
1220 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1221 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1222
1223 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1224 pixel_period = 1000000 / (u32)mode->clock;
1225 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1226
1227 /* watermark for high clocks */
1228 if (adev->pm.dpm_enabled) {
1229 wm_high.yclk =
1230 amdgpu_dpm_get_mclk(adev, false) * 10;
1231 wm_high.sclk =
1232 amdgpu_dpm_get_sclk(adev, false) * 10;
1233 } else {
1234 wm_high.yclk = adev->pm.current_mclk * 10;
1235 wm_high.sclk = adev->pm.current_sclk * 10;
1236 }
1237
1238 wm_high.disp_clk = mode->clock;
1239 wm_high.src_width = mode->crtc_hdisplay;
1240 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1241 wm_high.blank_time = line_time - wm_high.active_time;
1242 wm_high.interlaced = false;
1243 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1244 wm_high.interlaced = true;
1245 wm_high.vsc = amdgpu_crtc->vsc;
1246 wm_high.vtaps = 1;
1247 if (amdgpu_crtc->rmx_type != RMX_OFF)
1248 wm_high.vtaps = 2;
1249 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1250 wm_high.lb_size = lb_size;
1251 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1252 wm_high.num_heads = num_heads;
1253
1254 /* set for high clocks */
1255 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1256
1257 /* possibly force display priority to high */
1258 /* should really do this at mode validation time... */
1259 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1260 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1261 !dce_v11_0_check_latency_hiding(&wm_high) ||
1262 (adev->mode_info.disp_priority == 2)) {
1263 DRM_DEBUG_KMS("force priority to high\n");
1264 }
1265
1266 /* watermark for low clocks */
1267 if (adev->pm.dpm_enabled) {
1268 wm_low.yclk =
1269 amdgpu_dpm_get_mclk(adev, true) * 10;
1270 wm_low.sclk =
1271 amdgpu_dpm_get_sclk(adev, true) * 10;
1272 } else {
1273 wm_low.yclk = adev->pm.current_mclk * 10;
1274 wm_low.sclk = adev->pm.current_sclk * 10;
1275 }
1276
1277 wm_low.disp_clk = mode->clock;
1278 wm_low.src_width = mode->crtc_hdisplay;
1279 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1280 wm_low.blank_time = line_time - wm_low.active_time;
1281 wm_low.interlaced = false;
1282 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1283 wm_low.interlaced = true;
1284 wm_low.vsc = amdgpu_crtc->vsc;
1285 wm_low.vtaps = 1;
1286 if (amdgpu_crtc->rmx_type != RMX_OFF)
1287 wm_low.vtaps = 2;
1288 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1289 wm_low.lb_size = lb_size;
1290 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1291 wm_low.num_heads = num_heads;
1292
1293 /* set for low clocks */
1294 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1295
1296 /* possibly force display priority to high */
1297 /* should really do this at mode validation time... */
1298 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1299 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1300 !dce_v11_0_check_latency_hiding(&wm_low) ||
1301 (adev->mode_info.disp_priority == 2)) {
1302 DRM_DEBUG_KMS("force priority to high\n");
1303 }
1304 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1305 }
1306
1307 /* select wm A */
1308 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1309 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1310 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1311 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1312 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1313 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1314 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1315 /* select wm B */
1316 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1317 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1318 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1319 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1320 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1321 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1322 /* restore original selection */
1323 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1324
1325 /* save values for DPM */
1326 amdgpu_crtc->line_time = line_time;
1327 amdgpu_crtc->wm_high = latency_watermark_a;
1328 amdgpu_crtc->wm_low = latency_watermark_b;
1329 /* Save number of lines the linebuffer leads before the scanout */
1330 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1331 }
1332
1333 /**
1334 * dce_v11_0_bandwidth_update - program display watermarks
1335 *
1336 * @adev: amdgpu_device pointer
1337 *
1338 * Calculate and program the display watermarks and line
1339 * buffer allocation (CIK).
1340 */
1341 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1342 {
1343 struct drm_display_mode *mode = NULL;
1344 u32 num_heads = 0, lb_size;
1345 int i;
1346
1347 amdgpu_update_display_priority(adev);
1348
1349 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1350 if (adev->mode_info.crtcs[i]->base.enabled)
1351 num_heads++;
1352 }
1353 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1354 mode = &adev->mode_info.crtcs[i]->base.mode;
1355 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1356 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1357 lb_size, num_heads);
1358 }
1359 }
1360
1361 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1362 {
1363 int i;
1364 u32 offset, tmp;
1365
1366 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1367 offset = adev->mode_info.audio.pin[i].offset;
1368 tmp = RREG32_AUDIO_ENDPT(offset,
1369 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1370 if (((tmp &
1371 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1372 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1373 adev->mode_info.audio.pin[i].connected = false;
1374 else
1375 adev->mode_info.audio.pin[i].connected = true;
1376 }
1377 }
1378
1379 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1380 {
1381 int i;
1382
1383 dce_v11_0_audio_get_connected_pins(adev);
1384
1385 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1386 if (adev->mode_info.audio.pin[i].connected)
1387 return &adev->mode_info.audio.pin[i];
1388 }
1389 DRM_ERROR("No connected audio pins found!\n");
1390 return NULL;
1391 }
1392
1393 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1394 {
1395 struct amdgpu_device *adev = encoder->dev->dev_private;
1396 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1397 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1398 u32 tmp;
1399
1400 if (!dig || !dig->afmt || !dig->afmt->pin)
1401 return;
1402
1403 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1404 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1405 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1406 }
1407
1408 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1409 struct drm_display_mode *mode)
1410 {
1411 struct amdgpu_device *adev = encoder->dev->dev_private;
1412 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1413 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1414 struct drm_connector *connector;
1415 struct amdgpu_connector *amdgpu_connector = NULL;
1416 u32 tmp;
1417 int interlace = 0;
1418
1419 if (!dig || !dig->afmt || !dig->afmt->pin)
1420 return;
1421
1422 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1423 if (connector->encoder == encoder) {
1424 amdgpu_connector = to_amdgpu_connector(connector);
1425 break;
1426 }
1427 }
1428
1429 if (!amdgpu_connector) {
1430 DRM_ERROR("Couldn't find encoder's connector\n");
1431 return;
1432 }
1433
1434 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1435 interlace = 1;
1436 if (connector->latency_present[interlace]) {
1437 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1438 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1439 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1440 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1441 } else {
1442 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1443 VIDEO_LIPSYNC, 0);
1444 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1445 AUDIO_LIPSYNC, 0);
1446 }
1447 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1448 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1449 }
1450
1451 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1452 {
1453 struct amdgpu_device *adev = encoder->dev->dev_private;
1454 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1455 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1456 struct drm_connector *connector;
1457 struct amdgpu_connector *amdgpu_connector = NULL;
1458 u32 tmp;
1459 u8 *sadb = NULL;
1460 int sad_count;
1461
1462 if (!dig || !dig->afmt || !dig->afmt->pin)
1463 return;
1464
1465 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1466 if (connector->encoder == encoder) {
1467 amdgpu_connector = to_amdgpu_connector(connector);
1468 break;
1469 }
1470 }
1471
1472 if (!amdgpu_connector) {
1473 DRM_ERROR("Couldn't find encoder's connector\n");
1474 return;
1475 }
1476
1477 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1478 if (sad_count < 0) {
1479 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1480 sad_count = 0;
1481 }
1482
1483 /* program the speaker allocation */
1484 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1485 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1486 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1487 DP_CONNECTION, 0);
1488 /* set HDMI mode */
1489 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1490 HDMI_CONNECTION, 1);
1491 if (sad_count)
1492 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1493 SPEAKER_ALLOCATION, sadb[0]);
1494 else
1495 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1496 SPEAKER_ALLOCATION, 5); /* stereo */
1497 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1498 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1499
1500 kfree(sadb);
1501 }
1502
1503 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1504 {
1505 struct amdgpu_device *adev = encoder->dev->dev_private;
1506 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1507 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1508 struct drm_connector *connector;
1509 struct amdgpu_connector *amdgpu_connector = NULL;
1510 struct cea_sad *sads;
1511 int i, sad_count;
1512
1513 static const u16 eld_reg_to_type[][2] = {
1514 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1515 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1516 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1517 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1518 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1519 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1520 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1521 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1522 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1523 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1524 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1525 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1526 };
1527
1528 if (!dig || !dig->afmt || !dig->afmt->pin)
1529 return;
1530
1531 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1532 if (connector->encoder == encoder) {
1533 amdgpu_connector = to_amdgpu_connector(connector);
1534 break;
1535 }
1536 }
1537
1538 if (!amdgpu_connector) {
1539 DRM_ERROR("Couldn't find encoder's connector\n");
1540 return;
1541 }
1542
1543 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1544 if (sad_count <= 0) {
1545 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1546 return;
1547 }
1548 BUG_ON(!sads);
1549
1550 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1551 u32 tmp = 0;
1552 u8 stereo_freqs = 0;
1553 int max_channels = -1;
1554 int j;
1555
1556 for (j = 0; j < sad_count; j++) {
1557 struct cea_sad *sad = &sads[j];
1558
1559 if (sad->format == eld_reg_to_type[i][1]) {
1560 if (sad->channels > max_channels) {
1561 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1562 MAX_CHANNELS, sad->channels);
1563 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1564 DESCRIPTOR_BYTE_2, sad->byte2);
1565 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1566 SUPPORTED_FREQUENCIES, sad->freq);
1567 max_channels = sad->channels;
1568 }
1569
1570 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1571 stereo_freqs |= sad->freq;
1572 else
1573 break;
1574 }
1575 }
1576
1577 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1578 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1579 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1580 }
1581
1582 kfree(sads);
1583 }
1584
1585 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1586 struct amdgpu_audio_pin *pin,
1587 bool enable)
1588 {
1589 if (!pin)
1590 return;
1591
1592 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1593 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1594 }
1595
1596 static const u32 pin_offsets[] =
1597 {
1598 AUD0_REGISTER_OFFSET,
1599 AUD1_REGISTER_OFFSET,
1600 AUD2_REGISTER_OFFSET,
1601 AUD3_REGISTER_OFFSET,
1602 AUD4_REGISTER_OFFSET,
1603 AUD5_REGISTER_OFFSET,
1604 AUD6_REGISTER_OFFSET,
1605 AUD7_REGISTER_OFFSET,
1606 };
1607
1608 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1609 {
1610 int i;
1611
1612 if (!amdgpu_audio)
1613 return 0;
1614
1615 adev->mode_info.audio.enabled = true;
1616
1617 switch (adev->asic_type) {
1618 case CHIP_CARRIZO:
1619 case CHIP_STONEY:
1620 adev->mode_info.audio.num_pins = 7;
1621 break;
1622 case CHIP_POLARIS10:
1623 adev->mode_info.audio.num_pins = 8;
1624 break;
1625 case CHIP_POLARIS11:
1626 adev->mode_info.audio.num_pins = 6;
1627 break;
1628 default:
1629 return -EINVAL;
1630 }
1631
1632 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1633 adev->mode_info.audio.pin[i].channels = -1;
1634 adev->mode_info.audio.pin[i].rate = -1;
1635 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1636 adev->mode_info.audio.pin[i].status_bits = 0;
1637 adev->mode_info.audio.pin[i].category_code = 0;
1638 adev->mode_info.audio.pin[i].connected = false;
1639 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1640 adev->mode_info.audio.pin[i].id = i;
1641 /* disable audio. it will be set up later */
1642 /* XXX remove once we switch to ip funcs */
1643 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1644 }
1645
1646 return 0;
1647 }
1648
1649 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1650 {
1651 int i;
1652
1653 if (!amdgpu_audio)
1654 return;
1655
1656 if (!adev->mode_info.audio.enabled)
1657 return;
1658
1659 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1660 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1661
1662 adev->mode_info.audio.enabled = false;
1663 }
1664
1665 /*
1666 * update the N and CTS parameters for a given pixel clock rate
1667 */
1668 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1669 {
1670 struct drm_device *dev = encoder->dev;
1671 struct amdgpu_device *adev = dev->dev_private;
1672 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1673 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1674 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1675 u32 tmp;
1676
1677 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1678 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1679 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1680 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1681 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1682 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1683
1684 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1685 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1686 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1687 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1688 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1689 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1690
1691 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1692 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1693 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1694 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1695 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1696 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1697
1698 }
1699
1700 /*
1701 * build a HDMI Video Info Frame
1702 */
1703 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1704 void *buffer, size_t size)
1705 {
1706 struct drm_device *dev = encoder->dev;
1707 struct amdgpu_device *adev = dev->dev_private;
1708 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1709 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1710 uint8_t *frame = buffer + 3;
1711 uint8_t *header = buffer;
1712
1713 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1714 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1715 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1716 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1717 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1718 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1719 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1720 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1721 }
1722
1723 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1724 {
1725 struct drm_device *dev = encoder->dev;
1726 struct amdgpu_device *adev = dev->dev_private;
1727 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1728 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1729 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1730 u32 dto_phase = 24 * 1000;
1731 u32 dto_modulo = clock;
1732 u32 tmp;
1733
1734 if (!dig || !dig->afmt)
1735 return;
1736
1737 /* XXX two dtos; generally use dto0 for hdmi */
1738 /* Express [24MHz / target pixel clock] as an exact rational
1739 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1740 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1741 */
1742 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1743 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1744 amdgpu_crtc->crtc_id);
1745 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1746 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1747 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1748 }
1749
1750 /*
1751 * update the info frames with the data from the current display mode
1752 */
1753 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1754 struct drm_display_mode *mode)
1755 {
1756 struct drm_device *dev = encoder->dev;
1757 struct amdgpu_device *adev = dev->dev_private;
1758 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1759 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1760 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1761 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1762 struct hdmi_avi_infoframe frame;
1763 ssize_t err;
1764 u32 tmp;
1765 int bpc = 8;
1766
1767 if (!dig || !dig->afmt)
1768 return;
1769
1770 /* Silent, r600_hdmi_enable will raise WARN for us */
1771 if (!dig->afmt->enabled)
1772 return;
1773
1774 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1775 if (encoder->crtc) {
1776 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1777 bpc = amdgpu_crtc->bpc;
1778 }
1779
1780 /* disable audio prior to setting up hw */
1781 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1782 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1783
1784 dce_v11_0_audio_set_dto(encoder, mode->clock);
1785
1786 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1787 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1788 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1789
1790 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1791
1792 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1793 switch (bpc) {
1794 case 0:
1795 case 6:
1796 case 8:
1797 case 16:
1798 default:
1799 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1800 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1801 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1802 connector->name, bpc);
1803 break;
1804 case 10:
1805 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1806 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1807 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1808 connector->name);
1809 break;
1810 case 12:
1811 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1812 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1813 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1814 connector->name);
1815 break;
1816 }
1817 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1818
1819 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1820 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1821 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1822 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1823 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1824
1825 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1826 /* enable audio info frames (frames won't be set until audio is enabled) */
1827 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1828 /* required for audio info values to be updated */
1829 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1830 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1831
1832 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1833 /* required for audio info values to be updated */
1834 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1835 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1836
1837 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1838 /* anything other than 0 */
1839 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1840 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1841
1842 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1843
1844 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1845 /* set the default audio delay */
1846 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1847 /* should be suffient for all audio modes and small enough for all hblanks */
1848 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1849 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1850
1851 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1852 /* allow 60958 channel status fields to be updated */
1853 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1854 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1855
1856 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1857 if (bpc > 8)
1858 /* clear SW CTS value */
1859 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1860 else
1861 /* select SW CTS value */
1862 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1863 /* allow hw to sent ACR packets when required */
1864 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1865 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1866
1867 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1868
1869 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1870 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1871 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1872
1873 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1874 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1875 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1876
1877 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1878 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1879 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1880 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1881 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1882 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1883 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1884 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1885
1886 dce_v11_0_audio_write_speaker_allocation(encoder);
1887
1888 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1889 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1890
1891 dce_v11_0_afmt_audio_select_pin(encoder);
1892 dce_v11_0_audio_write_sad_regs(encoder);
1893 dce_v11_0_audio_write_latency_fields(encoder, mode);
1894
1895 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1896 if (err < 0) {
1897 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1898 return;
1899 }
1900
1901 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1902 if (err < 0) {
1903 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1904 return;
1905 }
1906
1907 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1908
1909 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1910 /* enable AVI info frames */
1911 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1912 /* required for audio info values to be updated */
1913 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1914 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1915
1916 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1917 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1918 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1919
1920 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1921 /* send audio packets */
1922 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1923 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1924
1925 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1926 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1927 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1928 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1929
1930 /* enable audio after to setting up hw */
1931 dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1932 }
1933
1934 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1935 {
1936 struct drm_device *dev = encoder->dev;
1937 struct amdgpu_device *adev = dev->dev_private;
1938 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1939 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1940
1941 if (!dig || !dig->afmt)
1942 return;
1943
1944 /* Silent, r600_hdmi_enable will raise WARN for us */
1945 if (enable && dig->afmt->enabled)
1946 return;
1947 if (!enable && !dig->afmt->enabled)
1948 return;
1949
1950 if (!enable && dig->afmt->pin) {
1951 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1952 dig->afmt->pin = NULL;
1953 }
1954
1955 dig->afmt->enabled = enable;
1956
1957 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1958 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1959 }
1960
1961 static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1962 {
1963 int i;
1964
1965 for (i = 0; i < adev->mode_info.num_dig; i++)
1966 adev->mode_info.afmt[i] = NULL;
1967
1968 /* DCE11 has audio blocks tied to DIG encoders */
1969 for (i = 0; i < adev->mode_info.num_dig; i++) {
1970 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1971 if (adev->mode_info.afmt[i]) {
1972 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1973 adev->mode_info.afmt[i]->id = i;
1974 } else {
1975 int j;
1976 for (j = 0; j < i; j++) {
1977 kfree(adev->mode_info.afmt[j]);
1978 adev->mode_info.afmt[j] = NULL;
1979 }
1980 return -ENOMEM;
1981 }
1982 }
1983 return 0;
1984 }
1985
1986 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1987 {
1988 int i;
1989
1990 for (i = 0; i < adev->mode_info.num_dig; i++) {
1991 kfree(adev->mode_info.afmt[i]);
1992 adev->mode_info.afmt[i] = NULL;
1993 }
1994 }
1995
1996 static const u32 vga_control_regs[6] =
1997 {
1998 mmD1VGA_CONTROL,
1999 mmD2VGA_CONTROL,
2000 mmD3VGA_CONTROL,
2001 mmD4VGA_CONTROL,
2002 mmD5VGA_CONTROL,
2003 mmD6VGA_CONTROL,
2004 };
2005
2006 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
2007 {
2008 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2009 struct drm_device *dev = crtc->dev;
2010 struct amdgpu_device *adev = dev->dev_private;
2011 u32 vga_control;
2012
2013 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2014 if (enable)
2015 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2016 else
2017 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2018 }
2019
2020 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
2021 {
2022 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2023 struct drm_device *dev = crtc->dev;
2024 struct amdgpu_device *adev = dev->dev_private;
2025
2026 if (enable)
2027 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2028 else
2029 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2030 }
2031
2032 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2033 struct drm_framebuffer *fb,
2034 int x, int y, int atomic)
2035 {
2036 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2037 struct drm_device *dev = crtc->dev;
2038 struct amdgpu_device *adev = dev->dev_private;
2039 struct amdgpu_framebuffer *amdgpu_fb;
2040 struct drm_framebuffer *target_fb;
2041 struct drm_gem_object *obj;
2042 struct amdgpu_bo *rbo;
2043 uint64_t fb_location, tiling_flags;
2044 uint32_t fb_format, fb_pitch_pixels;
2045 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2046 u32 pipe_config;
2047 u32 tmp, viewport_w, viewport_h;
2048 int r;
2049 bool bypass_lut = false;
2050
2051 /* no fb bound */
2052 if (!atomic && !crtc->primary->fb) {
2053 DRM_DEBUG_KMS("No FB bound\n");
2054 return 0;
2055 }
2056
2057 if (atomic) {
2058 amdgpu_fb = to_amdgpu_framebuffer(fb);
2059 target_fb = fb;
2060 } else {
2061 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2062 target_fb = crtc->primary->fb;
2063 }
2064
2065 /* If atomic, assume fb object is pinned & idle & fenced and
2066 * just update base pointers
2067 */
2068 obj = amdgpu_fb->obj;
2069 rbo = gem_to_amdgpu_bo(obj);
2070 r = amdgpu_bo_reserve(rbo, false);
2071 if (unlikely(r != 0))
2072 return r;
2073
2074 if (atomic) {
2075 fb_location = amdgpu_bo_gpu_offset(rbo);
2076 } else {
2077 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2078 if (unlikely(r != 0)) {
2079 amdgpu_bo_unreserve(rbo);
2080 return -EINVAL;
2081 }
2082 }
2083
2084 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2085 amdgpu_bo_unreserve(rbo);
2086
2087 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2088
2089 switch (target_fb->pixel_format) {
2090 case DRM_FORMAT_C8:
2091 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2092 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2093 break;
2094 case DRM_FORMAT_XRGB4444:
2095 case DRM_FORMAT_ARGB4444:
2096 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2097 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2098 #ifdef __BIG_ENDIAN
2099 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2100 ENDIAN_8IN16);
2101 #endif
2102 break;
2103 case DRM_FORMAT_XRGB1555:
2104 case DRM_FORMAT_ARGB1555:
2105 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2106 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2107 #ifdef __BIG_ENDIAN
2108 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2109 ENDIAN_8IN16);
2110 #endif
2111 break;
2112 case DRM_FORMAT_BGRX5551:
2113 case DRM_FORMAT_BGRA5551:
2114 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2115 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2116 #ifdef __BIG_ENDIAN
2117 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2118 ENDIAN_8IN16);
2119 #endif
2120 break;
2121 case DRM_FORMAT_RGB565:
2122 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2123 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2124 #ifdef __BIG_ENDIAN
2125 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2126 ENDIAN_8IN16);
2127 #endif
2128 break;
2129 case DRM_FORMAT_XRGB8888:
2130 case DRM_FORMAT_ARGB8888:
2131 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2132 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2133 #ifdef __BIG_ENDIAN
2134 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2135 ENDIAN_8IN32);
2136 #endif
2137 break;
2138 case DRM_FORMAT_XRGB2101010:
2139 case DRM_FORMAT_ARGB2101010:
2140 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2141 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2142 #ifdef __BIG_ENDIAN
2143 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2144 ENDIAN_8IN32);
2145 #endif
2146 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2147 bypass_lut = true;
2148 break;
2149 case DRM_FORMAT_BGRX1010102:
2150 case DRM_FORMAT_BGRA1010102:
2151 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2152 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2153 #ifdef __BIG_ENDIAN
2154 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2155 ENDIAN_8IN32);
2156 #endif
2157 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2158 bypass_lut = true;
2159 break;
2160 default:
2161 DRM_ERROR("Unsupported screen format %s\n",
2162 drm_get_format_name(target_fb->pixel_format));
2163 return -EINVAL;
2164 }
2165
2166 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2167 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2168
2169 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2170 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2171 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2172 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2173 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2174
2175 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2176 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2177 ARRAY_2D_TILED_THIN1);
2178 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2179 tile_split);
2180 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2181 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2182 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2183 mtaspect);
2184 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2185 ADDR_SURF_MICRO_TILING_DISPLAY);
2186 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2187 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2188 ARRAY_1D_TILED_THIN1);
2189 }
2190
2191 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2192 pipe_config);
2193
2194 dce_v11_0_vga_enable(crtc, false);
2195
2196 /* Make sure surface address is updated at vertical blank rather than
2197 * horizontal blank
2198 */
2199 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2200 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2201 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2202 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2203
2204 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2205 upper_32_bits(fb_location));
2206 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2207 upper_32_bits(fb_location));
2208 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2209 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2210 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2211 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2212 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2213 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2214
2215 /*
2216 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2217 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2218 * retain the full precision throughout the pipeline.
2219 */
2220 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2221 if (bypass_lut)
2222 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2223 else
2224 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2225 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2226
2227 if (bypass_lut)
2228 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2229
2230 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2231 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2232 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2233 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2234 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2235 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2236
2237 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2238 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2239
2240 dce_v11_0_grph_enable(crtc, true);
2241
2242 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2243 target_fb->height);
2244
2245 x &= ~3;
2246 y &= ~1;
2247 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2248 (x << 16) | y);
2249 viewport_w = crtc->mode.hdisplay;
2250 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2251 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2252 (viewport_w << 16) | viewport_h);
2253
2254 /* set pageflip to happen only at start of vblank interval (front porch) */
2255 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2256
2257 if (!atomic && fb && fb != crtc->primary->fb) {
2258 amdgpu_fb = to_amdgpu_framebuffer(fb);
2259 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2260 r = amdgpu_bo_reserve(rbo, false);
2261 if (unlikely(r != 0))
2262 return r;
2263 amdgpu_bo_unpin(rbo);
2264 amdgpu_bo_unreserve(rbo);
2265 }
2266
2267 /* Bytes per pixel may have changed */
2268 dce_v11_0_bandwidth_update(adev);
2269
2270 return 0;
2271 }
2272
2273 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2274 struct drm_display_mode *mode)
2275 {
2276 struct drm_device *dev = crtc->dev;
2277 struct amdgpu_device *adev = dev->dev_private;
2278 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2279 u32 tmp;
2280
2281 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2282 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2283 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2284 else
2285 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2286 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2287 }
2288
2289 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2290 {
2291 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2292 struct drm_device *dev = crtc->dev;
2293 struct amdgpu_device *adev = dev->dev_private;
2294 int i;
2295 u32 tmp;
2296
2297 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2298
2299 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2300 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2301 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2302
2303 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2304 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2305 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2306
2307 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2308 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2309 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2310
2311 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2312
2313 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2314 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2315 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2316
2317 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2318 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2319 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2320
2321 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2322 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2323
2324 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2325 for (i = 0; i < 256; i++) {
2326 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2327 (amdgpu_crtc->lut_r[i] << 20) |
2328 (amdgpu_crtc->lut_g[i] << 10) |
2329 (amdgpu_crtc->lut_b[i] << 0));
2330 }
2331
2332 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2333 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2334 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2335 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2336 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2337
2338 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2339 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2340 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2341
2342 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2343 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2344 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2345
2346 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2347 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2348 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2349
2350 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2351 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2352 /* XXX this only needs to be programmed once per crtc at startup,
2353 * not sure where the best place for it is
2354 */
2355 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2356 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2357 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2358 }
2359
2360 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2361 {
2362 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2363 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2364
2365 switch (amdgpu_encoder->encoder_id) {
2366 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2367 if (dig->linkb)
2368 return 1;
2369 else
2370 return 0;
2371 break;
2372 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2373 if (dig->linkb)
2374 return 3;
2375 else
2376 return 2;
2377 break;
2378 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2379 if (dig->linkb)
2380 return 5;
2381 else
2382 return 4;
2383 break;
2384 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2385 return 6;
2386 break;
2387 default:
2388 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2389 return 0;
2390 }
2391 }
2392
2393 /**
2394 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2395 *
2396 * @crtc: drm crtc
2397 *
2398 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2399 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2400 * monitors a dedicated PPLL must be used. If a particular board has
2401 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2402 * as there is no need to program the PLL itself. If we are not able to
2403 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2404 * avoid messing up an existing monitor.
2405 *
2406 * Asic specific PLL information
2407 *
2408 * DCE 10.x
2409 * Tonga
2410 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2411 * CI
2412 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2413 *
2414 */
2415 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2416 {
2417 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2418 struct drm_device *dev = crtc->dev;
2419 struct amdgpu_device *adev = dev->dev_private;
2420 u32 pll_in_use;
2421 int pll;
2422
2423 if ((adev->asic_type == CHIP_POLARIS10) ||
2424 (adev->asic_type == CHIP_POLARIS11)) {
2425 struct amdgpu_encoder *amdgpu_encoder =
2426 to_amdgpu_encoder(amdgpu_crtc->encoder);
2427 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2428
2429 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2430 return ATOM_DP_DTO;
2431
2432 switch (amdgpu_encoder->encoder_id) {
2433 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2434 if (dig->linkb)
2435 return ATOM_COMBOPHY_PLL1;
2436 else
2437 return ATOM_COMBOPHY_PLL0;
2438 break;
2439 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2440 if (dig->linkb)
2441 return ATOM_COMBOPHY_PLL3;
2442 else
2443 return ATOM_COMBOPHY_PLL2;
2444 break;
2445 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2446 if (dig->linkb)
2447 return ATOM_COMBOPHY_PLL5;
2448 else
2449 return ATOM_COMBOPHY_PLL4;
2450 break;
2451 default:
2452 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2453 return ATOM_PPLL_INVALID;
2454 }
2455 }
2456
2457 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2458 if (adev->clock.dp_extclk)
2459 /* skip PPLL programming if using ext clock */
2460 return ATOM_PPLL_INVALID;
2461 else {
2462 /* use the same PPLL for all DP monitors */
2463 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2464 if (pll != ATOM_PPLL_INVALID)
2465 return pll;
2466 }
2467 } else {
2468 /* use the same PPLL for all monitors with the same clock */
2469 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2470 if (pll != ATOM_PPLL_INVALID)
2471 return pll;
2472 }
2473
2474 /* XXX need to determine what plls are available on each DCE11 part */
2475 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2476 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2477 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2478 return ATOM_PPLL1;
2479 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2480 return ATOM_PPLL0;
2481 DRM_ERROR("unable to allocate a PPLL\n");
2482 return ATOM_PPLL_INVALID;
2483 } else {
2484 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2485 return ATOM_PPLL2;
2486 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2487 return ATOM_PPLL1;
2488 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2489 return ATOM_PPLL0;
2490 DRM_ERROR("unable to allocate a PPLL\n");
2491 return ATOM_PPLL_INVALID;
2492 }
2493 return ATOM_PPLL_INVALID;
2494 }
2495
2496 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2497 {
2498 struct amdgpu_device *adev = crtc->dev->dev_private;
2499 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2500 uint32_t cur_lock;
2501
2502 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2503 if (lock)
2504 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2505 else
2506 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2507 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2508 }
2509
2510 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2511 {
2512 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2513 struct amdgpu_device *adev = crtc->dev->dev_private;
2514 u32 tmp;
2515
2516 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2517 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2518 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2519 }
2520
2521 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2522 {
2523 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2524 struct amdgpu_device *adev = crtc->dev->dev_private;
2525 u32 tmp;
2526
2527 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2528 upper_32_bits(amdgpu_crtc->cursor_addr));
2529 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2530 lower_32_bits(amdgpu_crtc->cursor_addr));
2531
2532 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2533 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2534 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2535 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2536 }
2537
2538 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2539 int x, int y)
2540 {
2541 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2542 struct amdgpu_device *adev = crtc->dev->dev_private;
2543 int xorigin = 0, yorigin = 0;
2544
2545 /* avivo cursor are offset into the total surface */
2546 x += crtc->x;
2547 y += crtc->y;
2548 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2549
2550 if (x < 0) {
2551 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2552 x = 0;
2553 }
2554 if (y < 0) {
2555 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2556 y = 0;
2557 }
2558
2559 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2560 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2561 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2562 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2563
2564 amdgpu_crtc->cursor_x = x;
2565 amdgpu_crtc->cursor_y = y;
2566
2567 return 0;
2568 }
2569
2570 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2571 int x, int y)
2572 {
2573 int ret;
2574
2575 dce_v11_0_lock_cursor(crtc, true);
2576 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2577 dce_v11_0_lock_cursor(crtc, false);
2578
2579 return ret;
2580 }
2581
2582 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2583 struct drm_file *file_priv,
2584 uint32_t handle,
2585 uint32_t width,
2586 uint32_t height,
2587 int32_t hot_x,
2588 int32_t hot_y)
2589 {
2590 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2591 struct drm_gem_object *obj;
2592 struct amdgpu_bo *aobj;
2593 int ret;
2594
2595 if (!handle) {
2596 /* turn off cursor */
2597 dce_v11_0_hide_cursor(crtc);
2598 obj = NULL;
2599 goto unpin;
2600 }
2601
2602 if ((width > amdgpu_crtc->max_cursor_width) ||
2603 (height > amdgpu_crtc->max_cursor_height)) {
2604 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2605 return -EINVAL;
2606 }
2607
2608 obj = drm_gem_object_lookup(file_priv, handle);
2609 if (!obj) {
2610 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2611 return -ENOENT;
2612 }
2613
2614 aobj = gem_to_amdgpu_bo(obj);
2615 ret = amdgpu_bo_reserve(aobj, false);
2616 if (ret != 0) {
2617 drm_gem_object_unreference_unlocked(obj);
2618 return ret;
2619 }
2620
2621 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2622 amdgpu_bo_unreserve(aobj);
2623 if (ret) {
2624 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2625 drm_gem_object_unreference_unlocked(obj);
2626 return ret;
2627 }
2628
2629 amdgpu_crtc->cursor_width = width;
2630 amdgpu_crtc->cursor_height = height;
2631
2632 dce_v11_0_lock_cursor(crtc, true);
2633
2634 if (hot_x != amdgpu_crtc->cursor_hot_x ||
2635 hot_y != amdgpu_crtc->cursor_hot_y) {
2636 int x, y;
2637
2638 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2639 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2640
2641 dce_v11_0_cursor_move_locked(crtc, x, y);
2642
2643 amdgpu_crtc->cursor_hot_x = hot_x;
2644 amdgpu_crtc->cursor_hot_y = hot_y;
2645 }
2646
2647 dce_v11_0_show_cursor(crtc);
2648 dce_v11_0_lock_cursor(crtc, false);
2649
2650 unpin:
2651 if (amdgpu_crtc->cursor_bo) {
2652 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2653 ret = amdgpu_bo_reserve(aobj, false);
2654 if (likely(ret == 0)) {
2655 amdgpu_bo_unpin(aobj);
2656 amdgpu_bo_unreserve(aobj);
2657 }
2658 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2659 }
2660
2661 amdgpu_crtc->cursor_bo = obj;
2662 return 0;
2663 }
2664
2665 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2666 {
2667 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2668
2669 if (amdgpu_crtc->cursor_bo) {
2670 dce_v11_0_lock_cursor(crtc, true);
2671
2672 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2673 amdgpu_crtc->cursor_y);
2674
2675 dce_v11_0_show_cursor(crtc);
2676
2677 dce_v11_0_lock_cursor(crtc, false);
2678 }
2679 }
2680
2681 static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2682 u16 *blue, uint32_t start, uint32_t size)
2683 {
2684 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2685 int end = (start + size > 256) ? 256 : start + size, i;
2686
2687 /* userspace palettes are always correct as is */
2688 for (i = start; i < end; i++) {
2689 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2690 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2691 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2692 }
2693 dce_v11_0_crtc_load_lut(crtc);
2694 }
2695
2696 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2697 {
2698 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2699
2700 drm_crtc_cleanup(crtc);
2701 kfree(amdgpu_crtc);
2702 }
2703
2704 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2705 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2706 .cursor_move = dce_v11_0_crtc_cursor_move,
2707 .gamma_set = dce_v11_0_crtc_gamma_set,
2708 .set_config = amdgpu_crtc_set_config,
2709 .destroy = dce_v11_0_crtc_destroy,
2710 .page_flip = amdgpu_crtc_page_flip,
2711 };
2712
2713 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2714 {
2715 struct drm_device *dev = crtc->dev;
2716 struct amdgpu_device *adev = dev->dev_private;
2717 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2718 unsigned type;
2719
2720 switch (mode) {
2721 case DRM_MODE_DPMS_ON:
2722 amdgpu_crtc->enabled = true;
2723 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2724 dce_v11_0_vga_enable(crtc, true);
2725 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2726 dce_v11_0_vga_enable(crtc, false);
2727 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2728 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2729 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2730 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2731 drm_vblank_on(dev, amdgpu_crtc->crtc_id);
2732 dce_v11_0_crtc_load_lut(crtc);
2733 break;
2734 case DRM_MODE_DPMS_STANDBY:
2735 case DRM_MODE_DPMS_SUSPEND:
2736 case DRM_MODE_DPMS_OFF:
2737 drm_vblank_off(dev, amdgpu_crtc->crtc_id);
2738 if (amdgpu_crtc->enabled) {
2739 dce_v11_0_vga_enable(crtc, true);
2740 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2741 dce_v11_0_vga_enable(crtc, false);
2742 }
2743 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2744 amdgpu_crtc->enabled = false;
2745 break;
2746 }
2747 /* adjust pm to dpms */
2748 amdgpu_pm_compute_clocks(adev);
2749 }
2750
2751 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2752 {
2753 /* disable crtc pair power gating before programming */
2754 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2755 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2756 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2757 }
2758
2759 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2760 {
2761 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2762 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2763 }
2764
2765 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2766 {
2767 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2768 struct drm_device *dev = crtc->dev;
2769 struct amdgpu_device *adev = dev->dev_private;
2770 struct amdgpu_atom_ss ss;
2771 int i;
2772
2773 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2774 if (crtc->primary->fb) {
2775 int r;
2776 struct amdgpu_framebuffer *amdgpu_fb;
2777 struct amdgpu_bo *rbo;
2778
2779 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2780 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2781 r = amdgpu_bo_reserve(rbo, false);
2782 if (unlikely(r))
2783 DRM_ERROR("failed to reserve rbo before unpin\n");
2784 else {
2785 amdgpu_bo_unpin(rbo);
2786 amdgpu_bo_unreserve(rbo);
2787 }
2788 }
2789 /* disable the GRPH */
2790 dce_v11_0_grph_enable(crtc, false);
2791
2792 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2793
2794 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2795 if (adev->mode_info.crtcs[i] &&
2796 adev->mode_info.crtcs[i]->enabled &&
2797 i != amdgpu_crtc->crtc_id &&
2798 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2799 /* one other crtc is using this pll don't turn
2800 * off the pll
2801 */
2802 goto done;
2803 }
2804 }
2805
2806 switch (amdgpu_crtc->pll_id) {
2807 case ATOM_PPLL0:
2808 case ATOM_PPLL1:
2809 case ATOM_PPLL2:
2810 /* disable the ppll */
2811 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2812 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2813 break;
2814 case ATOM_COMBOPHY_PLL0:
2815 case ATOM_COMBOPHY_PLL1:
2816 case ATOM_COMBOPHY_PLL2:
2817 case ATOM_COMBOPHY_PLL3:
2818 case ATOM_COMBOPHY_PLL4:
2819 case ATOM_COMBOPHY_PLL5:
2820 /* disable the ppll */
2821 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2822 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2823 break;
2824 default:
2825 break;
2826 }
2827 done:
2828 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2829 amdgpu_crtc->adjusted_clock = 0;
2830 amdgpu_crtc->encoder = NULL;
2831 amdgpu_crtc->connector = NULL;
2832 }
2833
2834 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2835 struct drm_display_mode *mode,
2836 struct drm_display_mode *adjusted_mode,
2837 int x, int y, struct drm_framebuffer *old_fb)
2838 {
2839 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2840 struct drm_device *dev = crtc->dev;
2841 struct amdgpu_device *adev = dev->dev_private;
2842
2843 if (!amdgpu_crtc->adjusted_clock)
2844 return -EINVAL;
2845
2846 if ((adev->asic_type == CHIP_POLARIS10) ||
2847 (adev->asic_type == CHIP_POLARIS11)) {
2848 struct amdgpu_encoder *amdgpu_encoder =
2849 to_amdgpu_encoder(amdgpu_crtc->encoder);
2850 int encoder_mode =
2851 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2852
2853 /* SetPixelClock calculates the plls and ss values now */
2854 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2855 amdgpu_crtc->pll_id,
2856 encoder_mode, amdgpu_encoder->encoder_id,
2857 adjusted_mode->clock, 0, 0, 0, 0,
2858 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2859 } else {
2860 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2861 }
2862 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2863 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2864 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2865 amdgpu_atombios_crtc_scaler_setup(crtc);
2866 dce_v11_0_cursor_reset(crtc);
2867 /* update the hw version fpr dpm */
2868 amdgpu_crtc->hw_mode = *adjusted_mode;
2869
2870 return 0;
2871 }
2872
2873 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2874 const struct drm_display_mode *mode,
2875 struct drm_display_mode *adjusted_mode)
2876 {
2877 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2878 struct drm_device *dev = crtc->dev;
2879 struct drm_encoder *encoder;
2880
2881 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2882 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2883 if (encoder->crtc == crtc) {
2884 amdgpu_crtc->encoder = encoder;
2885 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2886 break;
2887 }
2888 }
2889 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2890 amdgpu_crtc->encoder = NULL;
2891 amdgpu_crtc->connector = NULL;
2892 return false;
2893 }
2894 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2895 return false;
2896 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2897 return false;
2898 /* pick pll */
2899 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2900 /* if we can't get a PPLL for a non-DP encoder, fail */
2901 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2902 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2903 return false;
2904
2905 return true;
2906 }
2907
2908 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2909 struct drm_framebuffer *old_fb)
2910 {
2911 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2912 }
2913
2914 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2915 struct drm_framebuffer *fb,
2916 int x, int y, enum mode_set_atomic state)
2917 {
2918 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2919 }
2920
2921 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2922 .dpms = dce_v11_0_crtc_dpms,
2923 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2924 .mode_set = dce_v11_0_crtc_mode_set,
2925 .mode_set_base = dce_v11_0_crtc_set_base,
2926 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2927 .prepare = dce_v11_0_crtc_prepare,
2928 .commit = dce_v11_0_crtc_commit,
2929 .load_lut = dce_v11_0_crtc_load_lut,
2930 .disable = dce_v11_0_crtc_disable,
2931 };
2932
2933 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2934 {
2935 struct amdgpu_crtc *amdgpu_crtc;
2936 int i;
2937
2938 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2939 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2940 if (amdgpu_crtc == NULL)
2941 return -ENOMEM;
2942
2943 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2944
2945 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2946 amdgpu_crtc->crtc_id = index;
2947 adev->mode_info.crtcs[index] = amdgpu_crtc;
2948
2949 amdgpu_crtc->max_cursor_width = 128;
2950 amdgpu_crtc->max_cursor_height = 128;
2951 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2952 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2953
2954 for (i = 0; i < 256; i++) {
2955 amdgpu_crtc->lut_r[i] = i << 2;
2956 amdgpu_crtc->lut_g[i] = i << 2;
2957 amdgpu_crtc->lut_b[i] = i << 2;
2958 }
2959
2960 switch (amdgpu_crtc->crtc_id) {
2961 case 0:
2962 default:
2963 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2964 break;
2965 case 1:
2966 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2967 break;
2968 case 2:
2969 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2970 break;
2971 case 3:
2972 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2973 break;
2974 case 4:
2975 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2976 break;
2977 case 5:
2978 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2979 break;
2980 }
2981
2982 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2983 amdgpu_crtc->adjusted_clock = 0;
2984 amdgpu_crtc->encoder = NULL;
2985 amdgpu_crtc->connector = NULL;
2986 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2987
2988 return 0;
2989 }
2990
2991 static int dce_v11_0_early_init(void *handle)
2992 {
2993 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2994
2995 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2996 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2997
2998 dce_v11_0_set_display_funcs(adev);
2999 dce_v11_0_set_irq_funcs(adev);
3000
3001 switch (adev->asic_type) {
3002 case CHIP_CARRIZO:
3003 adev->mode_info.num_crtc = 3;
3004 adev->mode_info.num_hpd = 6;
3005 adev->mode_info.num_dig = 9;
3006 break;
3007 case CHIP_STONEY:
3008 adev->mode_info.num_crtc = 2;
3009 adev->mode_info.num_hpd = 6;
3010 adev->mode_info.num_dig = 9;
3011 break;
3012 case CHIP_POLARIS10:
3013 adev->mode_info.num_crtc = 6;
3014 adev->mode_info.num_hpd = 6;
3015 adev->mode_info.num_dig = 6;
3016 break;
3017 case CHIP_POLARIS11:
3018 adev->mode_info.num_crtc = 5;
3019 adev->mode_info.num_hpd = 5;
3020 adev->mode_info.num_dig = 5;
3021 break;
3022 default:
3023 /* FIXME: not supported yet */
3024 return -EINVAL;
3025 }
3026
3027 return 0;
3028 }
3029
3030 static int dce_v11_0_sw_init(void *handle)
3031 {
3032 int r, i;
3033 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3034
3035 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3036 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
3037 if (r)
3038 return r;
3039 }
3040
3041 for (i = 8; i < 20; i += 2) {
3042 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
3043 if (r)
3044 return r;
3045 }
3046
3047 /* HPD hotplug */
3048 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
3049 if (r)
3050 return r;
3051
3052 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
3053
3054 adev->ddev->mode_config.async_page_flip = true;
3055
3056 adev->ddev->mode_config.max_width = 16384;
3057 adev->ddev->mode_config.max_height = 16384;
3058
3059 adev->ddev->mode_config.preferred_depth = 24;
3060 adev->ddev->mode_config.prefer_shadow = 1;
3061
3062 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
3063
3064 r = amdgpu_modeset_create_props(adev);
3065 if (r)
3066 return r;
3067
3068 adev->ddev->mode_config.max_width = 16384;
3069 adev->ddev->mode_config.max_height = 16384;
3070
3071
3072 /* allocate crtcs */
3073 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3074 r = dce_v11_0_crtc_init(adev, i);
3075 if (r)
3076 return r;
3077 }
3078
3079 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3080 amdgpu_print_display_setup(adev->ddev);
3081 else
3082 return -EINVAL;
3083
3084 /* setup afmt */
3085 r = dce_v11_0_afmt_init(adev);
3086 if (r)
3087 return r;
3088
3089 r = dce_v11_0_audio_init(adev);
3090 if (r)
3091 return r;
3092
3093 drm_kms_helper_poll_init(adev->ddev);
3094
3095 adev->mode_info.mode_config_initialized = true;
3096 return 0;
3097 }
3098
3099 static int dce_v11_0_sw_fini(void *handle)
3100 {
3101 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3102
3103 kfree(adev->mode_info.bios_hardcoded_edid);
3104
3105 drm_kms_helper_poll_fini(adev->ddev);
3106
3107 dce_v11_0_audio_fini(adev);
3108
3109 dce_v11_0_afmt_fini(adev);
3110
3111 adev->mode_info.mode_config_initialized = false;
3112
3113 return 0;
3114 }
3115
3116 static int dce_v11_0_hw_init(void *handle)
3117 {
3118 int i;
3119 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3120
3121 dce_v11_0_init_golden_registers(adev);
3122
3123 /* init dig PHYs, disp eng pll */
3124 amdgpu_atombios_crtc_powergate_init(adev);
3125 amdgpu_atombios_encoder_init_dig(adev);
3126 if ((adev->asic_type == CHIP_POLARIS10) ||
3127 (adev->asic_type == CHIP_POLARIS11)) {
3128 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
3129 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
3130 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
3131 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
3132 } else {
3133 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3134 }
3135
3136 /* initialize hpd */
3137 dce_v11_0_hpd_init(adev);
3138
3139 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3140 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3141 }
3142
3143 dce_v11_0_pageflip_interrupt_init(adev);
3144
3145 return 0;
3146 }
3147
3148 static int dce_v11_0_hw_fini(void *handle)
3149 {
3150 int i;
3151 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3152
3153 dce_v11_0_hpd_fini(adev);
3154
3155 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3156 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3157 }
3158
3159 dce_v11_0_pageflip_interrupt_fini(adev);
3160
3161 return 0;
3162 }
3163
3164 static int dce_v11_0_suspend(void *handle)
3165 {
3166 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3167
3168 amdgpu_atombios_scratch_regs_save(adev);
3169
3170 return dce_v11_0_hw_fini(handle);
3171 }
3172
3173 static int dce_v11_0_resume(void *handle)
3174 {
3175 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3176 int ret;
3177
3178 ret = dce_v11_0_hw_init(handle);
3179
3180 amdgpu_atombios_scratch_regs_restore(adev);
3181
3182 /* turn on the BL */
3183 if (adev->mode_info.bl_encoder) {
3184 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3185 adev->mode_info.bl_encoder);
3186 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3187 bl_level);
3188 }
3189
3190 return ret;
3191 }
3192
3193 static bool dce_v11_0_is_idle(void *handle)
3194 {
3195 return true;
3196 }
3197
3198 static int dce_v11_0_wait_for_idle(void *handle)
3199 {
3200 return 0;
3201 }
3202
3203 static int dce_v11_0_soft_reset(void *handle)
3204 {
3205 u32 srbm_soft_reset = 0, tmp;
3206 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3207
3208 if (dce_v11_0_is_display_hung(adev))
3209 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3210
3211 if (srbm_soft_reset) {
3212 tmp = RREG32(mmSRBM_SOFT_RESET);
3213 tmp |= srbm_soft_reset;
3214 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3215 WREG32(mmSRBM_SOFT_RESET, tmp);
3216 tmp = RREG32(mmSRBM_SOFT_RESET);
3217
3218 udelay(50);
3219
3220 tmp &= ~srbm_soft_reset;
3221 WREG32(mmSRBM_SOFT_RESET, tmp);
3222 tmp = RREG32(mmSRBM_SOFT_RESET);
3223
3224 /* Wait a little for things to settle down */
3225 udelay(50);
3226 }
3227 return 0;
3228 }
3229
3230 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3231 int crtc,
3232 enum amdgpu_interrupt_state state)
3233 {
3234 u32 lb_interrupt_mask;
3235
3236 if (crtc >= adev->mode_info.num_crtc) {
3237 DRM_DEBUG("invalid crtc %d\n", crtc);
3238 return;
3239 }
3240
3241 switch (state) {
3242 case AMDGPU_IRQ_STATE_DISABLE:
3243 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3244 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3245 VBLANK_INTERRUPT_MASK, 0);
3246 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3247 break;
3248 case AMDGPU_IRQ_STATE_ENABLE:
3249 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3250 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3251 VBLANK_INTERRUPT_MASK, 1);
3252 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3253 break;
3254 default:
3255 break;
3256 }
3257 }
3258
3259 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3260 int crtc,
3261 enum amdgpu_interrupt_state state)
3262 {
3263 u32 lb_interrupt_mask;
3264
3265 if (crtc >= adev->mode_info.num_crtc) {
3266 DRM_DEBUG("invalid crtc %d\n", crtc);
3267 return;
3268 }
3269
3270 switch (state) {
3271 case AMDGPU_IRQ_STATE_DISABLE:
3272 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3273 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3274 VLINE_INTERRUPT_MASK, 0);
3275 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3276 break;
3277 case AMDGPU_IRQ_STATE_ENABLE:
3278 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3279 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3280 VLINE_INTERRUPT_MASK, 1);
3281 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3282 break;
3283 default:
3284 break;
3285 }
3286 }
3287
3288 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3289 struct amdgpu_irq_src *source,
3290 unsigned hpd,
3291 enum amdgpu_interrupt_state state)
3292 {
3293 u32 tmp;
3294
3295 if (hpd >= adev->mode_info.num_hpd) {
3296 DRM_DEBUG("invalid hdp %d\n", hpd);
3297 return 0;
3298 }
3299
3300 switch (state) {
3301 case AMDGPU_IRQ_STATE_DISABLE:
3302 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3303 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3304 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3305 break;
3306 case AMDGPU_IRQ_STATE_ENABLE:
3307 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3308 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3309 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3310 break;
3311 default:
3312 break;
3313 }
3314
3315 return 0;
3316 }
3317
3318 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3319 struct amdgpu_irq_src *source,
3320 unsigned type,
3321 enum amdgpu_interrupt_state state)
3322 {
3323 switch (type) {
3324 case AMDGPU_CRTC_IRQ_VBLANK1:
3325 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3326 break;
3327 case AMDGPU_CRTC_IRQ_VBLANK2:
3328 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3329 break;
3330 case AMDGPU_CRTC_IRQ_VBLANK3:
3331 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3332 break;
3333 case AMDGPU_CRTC_IRQ_VBLANK4:
3334 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3335 break;
3336 case AMDGPU_CRTC_IRQ_VBLANK5:
3337 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3338 break;
3339 case AMDGPU_CRTC_IRQ_VBLANK6:
3340 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3341 break;
3342 case AMDGPU_CRTC_IRQ_VLINE1:
3343 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3344 break;
3345 case AMDGPU_CRTC_IRQ_VLINE2:
3346 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3347 break;
3348 case AMDGPU_CRTC_IRQ_VLINE3:
3349 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3350 break;
3351 case AMDGPU_CRTC_IRQ_VLINE4:
3352 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3353 break;
3354 case AMDGPU_CRTC_IRQ_VLINE5:
3355 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3356 break;
3357 case AMDGPU_CRTC_IRQ_VLINE6:
3358 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3359 break;
3360 default:
3361 break;
3362 }
3363 return 0;
3364 }
3365
3366 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3367 struct amdgpu_irq_src *src,
3368 unsigned type,
3369 enum amdgpu_interrupt_state state)
3370 {
3371 u32 reg;
3372
3373 if (type >= adev->mode_info.num_crtc) {
3374 DRM_ERROR("invalid pageflip crtc %d\n", type);
3375 return -EINVAL;
3376 }
3377
3378 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3379 if (state == AMDGPU_IRQ_STATE_DISABLE)
3380 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3381 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3382 else
3383 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3384 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3385
3386 return 0;
3387 }
3388
3389 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3390 struct amdgpu_irq_src *source,
3391 struct amdgpu_iv_entry *entry)
3392 {
3393 unsigned long flags;
3394 unsigned crtc_id;
3395 struct amdgpu_crtc *amdgpu_crtc;
3396 struct amdgpu_flip_work *works;
3397
3398 crtc_id = (entry->src_id - 8) >> 1;
3399 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3400
3401 if (crtc_id >= adev->mode_info.num_crtc) {
3402 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3403 return -EINVAL;
3404 }
3405
3406 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3407 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3408 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3409 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3410
3411 /* IRQ could occur when in initial stage */
3412 if(amdgpu_crtc == NULL)
3413 return 0;
3414
3415 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3416 works = amdgpu_crtc->pflip_works;
3417 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3418 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3419 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3420 amdgpu_crtc->pflip_status,
3421 AMDGPU_FLIP_SUBMITTED);
3422 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3423 return 0;
3424 }
3425
3426 /* page flip completed. clean up */
3427 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3428 amdgpu_crtc->pflip_works = NULL;
3429
3430 /* wakeup usersapce */
3431 if(works->event)
3432 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3433
3434 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3435
3436 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
3437 schedule_work(&works->unpin_work);
3438
3439 return 0;
3440 }
3441
3442 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3443 int hpd)
3444 {
3445 u32 tmp;
3446
3447 if (hpd >= adev->mode_info.num_hpd) {
3448 DRM_DEBUG("invalid hdp %d\n", hpd);
3449 return;
3450 }
3451
3452 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3453 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3454 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3455 }
3456
3457 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3458 int crtc)
3459 {
3460 u32 tmp;
3461
3462 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3463 DRM_DEBUG("invalid crtc %d\n", crtc);
3464 return;
3465 }
3466
3467 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3468 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3469 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3470 }
3471
3472 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3473 int crtc)
3474 {
3475 u32 tmp;
3476
3477 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3478 DRM_DEBUG("invalid crtc %d\n", crtc);
3479 return;
3480 }
3481
3482 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3483 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3484 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3485 }
3486
3487 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3488 struct amdgpu_irq_src *source,
3489 struct amdgpu_iv_entry *entry)
3490 {
3491 unsigned crtc = entry->src_id - 1;
3492 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3493 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3494
3495 switch (entry->src_data) {
3496 case 0: /* vblank */
3497 if (disp_int & interrupt_status_offsets[crtc].vblank)
3498 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3499 else
3500 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3501
3502 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3503 drm_handle_vblank(adev->ddev, crtc);
3504 }
3505 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3506
3507 break;
3508 case 1: /* vline */
3509 if (disp_int & interrupt_status_offsets[crtc].vline)
3510 dce_v11_0_crtc_vline_int_ack(adev, crtc);
3511 else
3512 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3513
3514 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3515
3516 break;
3517 default:
3518 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3519 break;
3520 }
3521
3522 return 0;
3523 }
3524
3525 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3526 struct amdgpu_irq_src *source,
3527 struct amdgpu_iv_entry *entry)
3528 {
3529 uint32_t disp_int, mask;
3530 unsigned hpd;
3531
3532 if (entry->src_data >= adev->mode_info.num_hpd) {
3533 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3534 return 0;
3535 }
3536
3537 hpd = entry->src_data;
3538 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3539 mask = interrupt_status_offsets[hpd].hpd;
3540
3541 if (disp_int & mask) {
3542 dce_v11_0_hpd_int_ack(adev, hpd);
3543 schedule_work(&adev->hotplug_work);
3544 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3545 }
3546
3547 return 0;
3548 }
3549
3550 static int dce_v11_0_set_clockgating_state(void *handle,
3551 enum amd_clockgating_state state)
3552 {
3553 return 0;
3554 }
3555
3556 static int dce_v11_0_set_powergating_state(void *handle,
3557 enum amd_powergating_state state)
3558 {
3559 return 0;
3560 }
3561
3562 const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3563 .name = "dce_v11_0",
3564 .early_init = dce_v11_0_early_init,
3565 .late_init = NULL,
3566 .sw_init = dce_v11_0_sw_init,
3567 .sw_fini = dce_v11_0_sw_fini,
3568 .hw_init = dce_v11_0_hw_init,
3569 .hw_fini = dce_v11_0_hw_fini,
3570 .suspend = dce_v11_0_suspend,
3571 .resume = dce_v11_0_resume,
3572 .is_idle = dce_v11_0_is_idle,
3573 .wait_for_idle = dce_v11_0_wait_for_idle,
3574 .soft_reset = dce_v11_0_soft_reset,
3575 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3576 .set_powergating_state = dce_v11_0_set_powergating_state,
3577 };
3578
3579 static void
3580 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3581 struct drm_display_mode *mode,
3582 struct drm_display_mode *adjusted_mode)
3583 {
3584 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3585
3586 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3587
3588 /* need to call this here rather than in prepare() since we need some crtc info */
3589 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3590
3591 /* set scaler clears this on some chips */
3592 dce_v11_0_set_interleave(encoder->crtc, mode);
3593
3594 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3595 dce_v11_0_afmt_enable(encoder, true);
3596 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3597 }
3598 }
3599
3600 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3601 {
3602 struct amdgpu_device *adev = encoder->dev->dev_private;
3603 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3604 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3605
3606 if ((amdgpu_encoder->active_device &
3607 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3608 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3609 ENCODER_OBJECT_ID_NONE)) {
3610 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3611 if (dig) {
3612 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3613 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3614 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3615 }
3616 }
3617
3618 amdgpu_atombios_scratch_regs_lock(adev, true);
3619
3620 if (connector) {
3621 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3622
3623 /* select the clock/data port if it uses a router */
3624 if (amdgpu_connector->router.cd_valid)
3625 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3626
3627 /* turn eDP panel on for mode set */
3628 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3629 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3630 ATOM_TRANSMITTER_ACTION_POWER_ON);
3631 }
3632
3633 /* this is needed for the pll/ss setup to work correctly in some cases */
3634 amdgpu_atombios_encoder_set_crtc_source(encoder);
3635 /* set up the FMT blocks */
3636 dce_v11_0_program_fmt(encoder);
3637 }
3638
3639 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3640 {
3641 struct drm_device *dev = encoder->dev;
3642 struct amdgpu_device *adev = dev->dev_private;
3643
3644 /* need to call this here as we need the crtc set up */
3645 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3646 amdgpu_atombios_scratch_regs_lock(adev, false);
3647 }
3648
3649 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3650 {
3651 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3652 struct amdgpu_encoder_atom_dig *dig;
3653
3654 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3655
3656 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3657 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3658 dce_v11_0_afmt_enable(encoder, false);
3659 dig = amdgpu_encoder->enc_priv;
3660 dig->dig_encoder = -1;
3661 }
3662 amdgpu_encoder->active_device = 0;
3663 }
3664
3665 /* these are handled by the primary encoders */
3666 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3667 {
3668
3669 }
3670
3671 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3672 {
3673
3674 }
3675
3676 static void
3677 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3678 struct drm_display_mode *mode,
3679 struct drm_display_mode *adjusted_mode)
3680 {
3681
3682 }
3683
3684 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3685 {
3686
3687 }
3688
3689 static void
3690 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3691 {
3692
3693 }
3694
3695 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3696 .dpms = dce_v11_0_ext_dpms,
3697 .prepare = dce_v11_0_ext_prepare,
3698 .mode_set = dce_v11_0_ext_mode_set,
3699 .commit = dce_v11_0_ext_commit,
3700 .disable = dce_v11_0_ext_disable,
3701 /* no detect for TMDS/LVDS yet */
3702 };
3703
3704 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3705 .dpms = amdgpu_atombios_encoder_dpms,
3706 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3707 .prepare = dce_v11_0_encoder_prepare,
3708 .mode_set = dce_v11_0_encoder_mode_set,
3709 .commit = dce_v11_0_encoder_commit,
3710 .disable = dce_v11_0_encoder_disable,
3711 .detect = amdgpu_atombios_encoder_dig_detect,
3712 };
3713
3714 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3715 .dpms = amdgpu_atombios_encoder_dpms,
3716 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3717 .prepare = dce_v11_0_encoder_prepare,
3718 .mode_set = dce_v11_0_encoder_mode_set,
3719 .commit = dce_v11_0_encoder_commit,
3720 .detect = amdgpu_atombios_encoder_dac_detect,
3721 };
3722
3723 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3724 {
3725 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3726 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3727 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3728 kfree(amdgpu_encoder->enc_priv);
3729 drm_encoder_cleanup(encoder);
3730 kfree(amdgpu_encoder);
3731 }
3732
3733 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3734 .destroy = dce_v11_0_encoder_destroy,
3735 };
3736
3737 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3738 uint32_t encoder_enum,
3739 uint32_t supported_device,
3740 u16 caps)
3741 {
3742 struct drm_device *dev = adev->ddev;
3743 struct drm_encoder *encoder;
3744 struct amdgpu_encoder *amdgpu_encoder;
3745
3746 /* see if we already added it */
3747 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3748 amdgpu_encoder = to_amdgpu_encoder(encoder);
3749 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3750 amdgpu_encoder->devices |= supported_device;
3751 return;
3752 }
3753
3754 }
3755
3756 /* add a new one */
3757 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3758 if (!amdgpu_encoder)
3759 return;
3760
3761 encoder = &amdgpu_encoder->base;
3762 switch (adev->mode_info.num_crtc) {
3763 case 1:
3764 encoder->possible_crtcs = 0x1;
3765 break;
3766 case 2:
3767 default:
3768 encoder->possible_crtcs = 0x3;
3769 break;
3770 case 4:
3771 encoder->possible_crtcs = 0xf;
3772 break;
3773 case 6:
3774 encoder->possible_crtcs = 0x3f;
3775 break;
3776 }
3777
3778 amdgpu_encoder->enc_priv = NULL;
3779
3780 amdgpu_encoder->encoder_enum = encoder_enum;
3781 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3782 amdgpu_encoder->devices = supported_device;
3783 amdgpu_encoder->rmx_type = RMX_OFF;
3784 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3785 amdgpu_encoder->is_ext_encoder = false;
3786 amdgpu_encoder->caps = caps;
3787
3788 switch (amdgpu_encoder->encoder_id) {
3789 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3790 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3791 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3792 DRM_MODE_ENCODER_DAC, NULL);
3793 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3794 break;
3795 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3796 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3797 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3798 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3799 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3800 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3801 amdgpu_encoder->rmx_type = RMX_FULL;
3802 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3803 DRM_MODE_ENCODER_LVDS, NULL);
3804 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3805 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3806 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3807 DRM_MODE_ENCODER_DAC, NULL);
3808 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3809 } else {
3810 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3811 DRM_MODE_ENCODER_TMDS, NULL);
3812 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3813 }
3814 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3815 break;
3816 case ENCODER_OBJECT_ID_SI170B:
3817 case ENCODER_OBJECT_ID_CH7303:
3818 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3819 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3820 case ENCODER_OBJECT_ID_TITFP513:
3821 case ENCODER_OBJECT_ID_VT1623:
3822 case ENCODER_OBJECT_ID_HDMI_SI1930:
3823 case ENCODER_OBJECT_ID_TRAVIS:
3824 case ENCODER_OBJECT_ID_NUTMEG:
3825 /* these are handled by the primary encoders */
3826 amdgpu_encoder->is_ext_encoder = true;
3827 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3828 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3829 DRM_MODE_ENCODER_LVDS, NULL);
3830 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3831 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3832 DRM_MODE_ENCODER_DAC, NULL);
3833 else
3834 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3835 DRM_MODE_ENCODER_TMDS, NULL);
3836 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3837 break;
3838 }
3839 }
3840
3841 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3842 .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3843 .bandwidth_update = &dce_v11_0_bandwidth_update,
3844 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3845 .vblank_wait = &dce_v11_0_vblank_wait,
3846 .is_display_hung = &dce_v11_0_is_display_hung,
3847 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3848 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3849 .hpd_sense = &dce_v11_0_hpd_sense,
3850 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3851 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3852 .page_flip = &dce_v11_0_page_flip,
3853 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3854 .add_encoder = &dce_v11_0_encoder_add,
3855 .add_connector = &amdgpu_connector_add,
3856 .stop_mc_access = &dce_v11_0_stop_mc_access,
3857 .resume_mc_access = &dce_v11_0_resume_mc_access,
3858 };
3859
3860 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3861 {
3862 if (adev->mode_info.funcs == NULL)
3863 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3864 }
3865
3866 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3867 .set = dce_v11_0_set_crtc_irq_state,
3868 .process = dce_v11_0_crtc_irq,
3869 };
3870
3871 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3872 .set = dce_v11_0_set_pageflip_irq_state,
3873 .process = dce_v11_0_pageflip_irq,
3874 };
3875
3876 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3877 .set = dce_v11_0_set_hpd_irq_state,
3878 .process = dce_v11_0_hpd_irq,
3879 };
3880
3881 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3882 {
3883 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3884 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3885
3886 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3887 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3888
3889 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3890 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3891 }
ubuntu-bionic-kernel mirror