2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
35 #include "dce/dce_8_0_d.h"
36 #include "dce/dce_8_0_sh_mask.h"
38 #include "gca/gfx_7_2_enum.h"
40 #include "gmc/gmc_7_1_d.h"
41 #include "gmc/gmc_7_1_sh_mask.h"
43 #include "oss/oss_2_0_d.h"
44 #include "oss/oss_2_0_sh_mask.h"
46 static void dce_v8_0_set_display_funcs(struct amdgpu_device
*adev
);
47 static void dce_v8_0_set_irq_funcs(struct amdgpu_device
*adev
);
49 static const u32 crtc_offsets
[6] =
51 CRTC0_REGISTER_OFFSET
,
52 CRTC1_REGISTER_OFFSET
,
53 CRTC2_REGISTER_OFFSET
,
54 CRTC3_REGISTER_OFFSET
,
55 CRTC4_REGISTER_OFFSET
,
59 static const uint32_t dig_offsets
[] = {
60 CRTC0_REGISTER_OFFSET
,
61 CRTC1_REGISTER_OFFSET
,
62 CRTC2_REGISTER_OFFSET
,
63 CRTC3_REGISTER_OFFSET
,
64 CRTC4_REGISTER_OFFSET
,
65 CRTC5_REGISTER_OFFSET
,
66 (0x13830 - 0x7030) >> 2,
75 } interrupt_status_offsets
[6] = { {
76 .reg
= mmDISP_INTERRUPT_STATUS
,
77 .vblank
= DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK
,
78 .vline
= DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK
,
79 .hpd
= DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
81 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE
,
82 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK
,
83 .vline
= DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK
,
84 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
86 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE2
,
87 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK
,
88 .vline
= DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK
,
89 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
91 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE3
,
92 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK
,
93 .vline
= DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK
,
94 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
96 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE4
,
97 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK
,
98 .vline
= DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK
,
99 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
101 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE5
,
102 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK
,
103 .vline
= DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK
,
104 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
107 static const uint32_t hpd_int_control_offsets
[6] = {
108 mmDC_HPD1_INT_CONTROL
,
109 mmDC_HPD2_INT_CONTROL
,
110 mmDC_HPD3_INT_CONTROL
,
111 mmDC_HPD4_INT_CONTROL
,
112 mmDC_HPD5_INT_CONTROL
,
113 mmDC_HPD6_INT_CONTROL
,
116 static u32
dce_v8_0_audio_endpt_rreg(struct amdgpu_device
*adev
,
117 u32 block_offset
, u32 reg
)
122 spin_lock_irqsave(&adev
->audio_endpt_idx_lock
, flags
);
123 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
124 r
= RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA
+ block_offset
);
125 spin_unlock_irqrestore(&adev
->audio_endpt_idx_lock
, flags
);
130 static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device
*adev
,
131 u32 block_offset
, u32 reg
, u32 v
)
135 spin_lock_irqsave(&adev
->audio_endpt_idx_lock
, flags
);
136 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
137 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA
+ block_offset
, v
);
138 spin_unlock_irqrestore(&adev
->audio_endpt_idx_lock
, flags
);
141 static bool dce_v8_0_is_in_vblank(struct amdgpu_device
*adev
, int crtc
)
143 if (RREG32(mmCRTC_STATUS
+ crtc_offsets
[crtc
]) &
144 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK
)
150 static bool dce_v8_0_is_counter_moving(struct amdgpu_device
*adev
, int crtc
)
154 pos1
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
155 pos2
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
164 * dce_v8_0_vblank_wait - vblank wait asic callback.
166 * @adev: amdgpu_device pointer
167 * @crtc: crtc to wait for vblank on
169 * Wait for vblank on the requested crtc (evergreen+).
171 static void dce_v8_0_vblank_wait(struct amdgpu_device
*adev
, int crtc
)
175 if (crtc
>= adev
->mode_info
.num_crtc
)
178 if (!(RREG32(mmCRTC_CONTROL
+ crtc_offsets
[crtc
]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK
))
181 /* depending on when we hit vblank, we may be close to active; if so,
182 * wait for another frame.
184 while (dce_v8_0_is_in_vblank(adev
, crtc
)) {
185 if (i
++ % 100 == 0) {
186 if (!dce_v8_0_is_counter_moving(adev
, crtc
))
191 while (!dce_v8_0_is_in_vblank(adev
, crtc
)) {
192 if (i
++ % 100 == 0) {
193 if (!dce_v8_0_is_counter_moving(adev
, crtc
))
199 static u32
dce_v8_0_vblank_get_counter(struct amdgpu_device
*adev
, int crtc
)
201 if (crtc
>= adev
->mode_info
.num_crtc
)
204 return RREG32(mmCRTC_STATUS_FRAME_COUNT
+ crtc_offsets
[crtc
]);
207 static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device
*adev
)
211 /* Enable pflip interrupts */
212 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++)
213 amdgpu_irq_get(adev
, &adev
->pageflip_irq
, i
);
216 static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device
*adev
)
220 /* Disable pflip interrupts */
221 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++)
222 amdgpu_irq_put(adev
, &adev
->pageflip_irq
, i
);
226 * dce_v8_0_page_flip - pageflip callback.
228 * @adev: amdgpu_device pointer
229 * @crtc_id: crtc to cleanup pageflip on
230 * @crtc_base: new address of the crtc (GPU MC address)
232 * Triggers the actual pageflip by updating the primary
233 * surface base address.
235 static void dce_v8_0_page_flip(struct amdgpu_device
*adev
,
236 int crtc_id
, u64 crtc_base
)
238 struct amdgpu_crtc
*amdgpu_crtc
= adev
->mode_info
.crtcs
[crtc_id
];
240 /* update the primary scanout addresses */
241 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
242 upper_32_bits(crtc_base
));
243 /* writing to the low address triggers the update */
244 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
245 lower_32_bits(crtc_base
));
247 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
);
250 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device
*adev
, int crtc
,
251 u32
*vbl
, u32
*position
)
253 if ((crtc
< 0) || (crtc
>= adev
->mode_info
.num_crtc
))
256 *vbl
= RREG32(mmCRTC_V_BLANK_START_END
+ crtc_offsets
[crtc
]);
257 *position
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
263 * dce_v8_0_hpd_sense - hpd sense callback.
265 * @adev: amdgpu_device pointer
266 * @hpd: hpd (hotplug detect) pin
268 * Checks if a digital monitor is connected (evergreen+).
269 * Returns true if connected, false if not connected.
271 static bool dce_v8_0_hpd_sense(struct amdgpu_device
*adev
,
272 enum amdgpu_hpd_id hpd
)
274 bool connected
= false;
278 if (RREG32(mmDC_HPD1_INT_STATUS
) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK
)
282 if (RREG32(mmDC_HPD2_INT_STATUS
) & DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK
)
286 if (RREG32(mmDC_HPD3_INT_STATUS
) & DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK
)
290 if (RREG32(mmDC_HPD4_INT_STATUS
) & DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK
)
294 if (RREG32(mmDC_HPD5_INT_STATUS
) & DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK
)
298 if (RREG32(mmDC_HPD6_INT_STATUS
) & DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK
)
309 * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
311 * @adev: amdgpu_device pointer
312 * @hpd: hpd (hotplug detect) pin
314 * Set the polarity of the hpd pin (evergreen+).
316 static void dce_v8_0_hpd_set_polarity(struct amdgpu_device
*adev
,
317 enum amdgpu_hpd_id hpd
)
320 bool connected
= dce_v8_0_hpd_sense(adev
, hpd
);
324 tmp
= RREG32(mmDC_HPD1_INT_CONTROL
);
326 tmp
&= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK
;
328 tmp
|= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK
;
329 WREG32(mmDC_HPD1_INT_CONTROL
, tmp
);
332 tmp
= RREG32(mmDC_HPD2_INT_CONTROL
);
334 tmp
&= ~DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK
;
336 tmp
|= DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK
;
337 WREG32(mmDC_HPD2_INT_CONTROL
, tmp
);
340 tmp
= RREG32(mmDC_HPD3_INT_CONTROL
);
342 tmp
&= ~DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK
;
344 tmp
|= DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK
;
345 WREG32(mmDC_HPD3_INT_CONTROL
, tmp
);
348 tmp
= RREG32(mmDC_HPD4_INT_CONTROL
);
350 tmp
&= ~DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK
;
352 tmp
|= DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK
;
353 WREG32(mmDC_HPD4_INT_CONTROL
, tmp
);
356 tmp
= RREG32(mmDC_HPD5_INT_CONTROL
);
358 tmp
&= ~DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK
;
360 tmp
|= DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK
;
361 WREG32(mmDC_HPD5_INT_CONTROL
, tmp
);
364 tmp
= RREG32(mmDC_HPD6_INT_CONTROL
);
366 tmp
&= ~DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK
;
368 tmp
|= DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK
;
369 WREG32(mmDC_HPD6_INT_CONTROL
, tmp
);
377 * dce_v8_0_hpd_init - hpd setup callback.
379 * @adev: amdgpu_device pointer
381 * Setup the hpd pins used by the card (evergreen+).
382 * Enable the pin, set the polarity, and enable the hpd interrupts.
384 static void dce_v8_0_hpd_init(struct amdgpu_device
*adev
)
386 struct drm_device
*dev
= adev
->ddev
;
387 struct drm_connector
*connector
;
388 u32 tmp
= (0x9c4 << DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT
) |
389 (0xfa << DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT
) |
390 DC_HPD1_CONTROL__DC_HPD1_EN_MASK
;
392 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
393 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
395 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
||
396 connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
397 /* don't try to enable hpd on eDP or LVDS avoid breaking the
398 * aux dp channel on imac and help (but not completely fix)
399 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
400 * also avoid interrupt storms during dpms.
404 switch (amdgpu_connector
->hpd
.hpd
) {
406 WREG32(mmDC_HPD1_CONTROL
, tmp
);
409 WREG32(mmDC_HPD2_CONTROL
, tmp
);
412 WREG32(mmDC_HPD3_CONTROL
, tmp
);
415 WREG32(mmDC_HPD4_CONTROL
, tmp
);
418 WREG32(mmDC_HPD5_CONTROL
, tmp
);
421 WREG32(mmDC_HPD6_CONTROL
, tmp
);
426 dce_v8_0_hpd_set_polarity(adev
, amdgpu_connector
->hpd
.hpd
);
427 amdgpu_irq_get(adev
, &adev
->hpd_irq
, amdgpu_connector
->hpd
.hpd
);
432 * dce_v8_0_hpd_fini - hpd tear down callback.
434 * @adev: amdgpu_device pointer
436 * Tear down the hpd pins used by the card (evergreen+).
437 * Disable the hpd interrupts.
439 static void dce_v8_0_hpd_fini(struct amdgpu_device
*adev
)
441 struct drm_device
*dev
= adev
->ddev
;
442 struct drm_connector
*connector
;
444 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
445 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
447 switch (amdgpu_connector
->hpd
.hpd
) {
449 WREG32(mmDC_HPD1_CONTROL
, 0);
452 WREG32(mmDC_HPD2_CONTROL
, 0);
455 WREG32(mmDC_HPD3_CONTROL
, 0);
458 WREG32(mmDC_HPD4_CONTROL
, 0);
461 WREG32(mmDC_HPD5_CONTROL
, 0);
464 WREG32(mmDC_HPD6_CONTROL
, 0);
469 amdgpu_irq_put(adev
, &adev
->hpd_irq
, amdgpu_connector
->hpd
.hpd
);
473 static u32
dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device
*adev
)
475 return mmDC_GPIO_HPD_A
;
478 static bool dce_v8_0_is_display_hung(struct amdgpu_device
*adev
)
484 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
485 if (RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK
) {
486 crtc_status
[i
] = RREG32(mmCRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
487 crtc_hung
|= (1 << i
);
491 for (j
= 0; j
< 10; j
++) {
492 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
493 if (crtc_hung
& (1 << i
)) {
494 tmp
= RREG32(mmCRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
495 if (tmp
!= crtc_status
[i
])
496 crtc_hung
&= ~(1 << i
);
507 static void dce_v8_0_stop_mc_access(struct amdgpu_device
*adev
,
508 struct amdgpu_mode_mc_save
*save
)
510 u32 crtc_enabled
, tmp
;
513 save
->vga_render_control
= RREG32(mmVGA_RENDER_CONTROL
);
514 save
->vga_hdp_control
= RREG32(mmVGA_HDP_CONTROL
);
516 /* disable VGA render */
517 tmp
= RREG32(mmVGA_RENDER_CONTROL
);
518 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 0);
519 WREG32(mmVGA_RENDER_CONTROL
, tmp
);
521 /* blank the display controllers */
522 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
523 crtc_enabled
= REG_GET_FIELD(RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]),
524 CRTC_CONTROL
, CRTC_MASTER_EN
);
530 save
->crtc_enabled
[i
] = true;
531 tmp
= RREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
]);
532 if (REG_GET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
) == 0) {
533 amdgpu_display_vblank_wait(adev
, i
);
534 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
535 tmp
= REG_SET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
, 1);
536 WREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
], tmp
);
537 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
539 /* wait for the next frame */
540 frame_count
= amdgpu_display_vblank_get_counter(adev
, i
);
541 for (j
= 0; j
< adev
->usec_timeout
; j
++) {
542 if (amdgpu_display_vblank_get_counter(adev
, i
) != frame_count
)
546 tmp
= RREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
]);
547 if (REG_GET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
) == 0) {
548 tmp
= REG_SET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
, 1);
549 WREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
], tmp
);
551 tmp
= RREG32(mmMASTER_UPDATE_LOCK
+ crtc_offsets
[i
]);
552 if (REG_GET_FIELD(tmp
, MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
) == 0) {
553 tmp
= REG_SET_FIELD(tmp
, MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
, 1);
554 WREG32(mmMASTER_UPDATE_LOCK
+ crtc_offsets
[i
], tmp
);
557 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
558 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
559 tmp
= RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]);
560 tmp
= REG_SET_FIELD(tmp
, CRTC_CONTROL
, CRTC_MASTER_EN
, 0);
561 WREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
], tmp
);
562 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
563 save
->crtc_enabled
[i
] = false;
567 save
->crtc_enabled
[i
] = false;
572 static void dce_v8_0_resume_mc_access(struct amdgpu_device
*adev
,
573 struct amdgpu_mode_mc_save
*save
)
575 u32 tmp
, frame_count
;
578 /* update crtc base addresses */
579 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
580 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ crtc_offsets
[i
],
581 upper_32_bits(adev
->mc
.vram_start
));
582 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ crtc_offsets
[i
],
583 upper_32_bits(adev
->mc
.vram_start
));
584 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ crtc_offsets
[i
],
585 (u32
)adev
->mc
.vram_start
);
586 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS
+ crtc_offsets
[i
],
587 (u32
)adev
->mc
.vram_start
);
589 if (save
->crtc_enabled
[i
]) {
590 tmp
= RREG32(mmMASTER_UPDATE_MODE
+ crtc_offsets
[i
]);
591 if (REG_GET_FIELD(tmp
, MASTER_UPDATE_MODE
, MASTER_UPDATE_MODE
) != 3) {
592 tmp
= REG_SET_FIELD(tmp
, MASTER_UPDATE_MODE
, MASTER_UPDATE_MODE
, 3);
593 WREG32(mmMASTER_UPDATE_MODE
+ crtc_offsets
[i
], tmp
);
595 tmp
= RREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
]);
596 if (REG_GET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
)) {
597 tmp
= REG_SET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
, 0);
598 WREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
], tmp
);
600 tmp
= RREG32(mmMASTER_UPDATE_LOCK
+ crtc_offsets
[i
]);
601 if (REG_GET_FIELD(tmp
, MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
)) {
602 tmp
= REG_SET_FIELD(tmp
, MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
, 0);
603 WREG32(mmMASTER_UPDATE_LOCK
+ crtc_offsets
[i
], tmp
);
605 for (j
= 0; j
< adev
->usec_timeout
; j
++) {
606 tmp
= RREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
]);
607 if (REG_GET_FIELD(tmp
, GRPH_UPDATE
, GRPH_SURFACE_UPDATE_PENDING
) == 0)
611 tmp
= RREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
]);
612 tmp
= REG_SET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
, 0);
613 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
614 WREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
], tmp
);
615 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
616 /* wait for the next frame */
617 frame_count
= amdgpu_display_vblank_get_counter(adev
, i
);
618 for (j
= 0; j
< adev
->usec_timeout
; j
++) {
619 if (amdgpu_display_vblank_get_counter(adev
, i
) != frame_count
)
626 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH
, upper_32_bits(adev
->mc
.vram_start
));
627 WREG32(mmVGA_MEMORY_BASE_ADDRESS
, lower_32_bits(adev
->mc
.vram_start
));
629 /* Unlock vga access */
630 WREG32(mmVGA_HDP_CONTROL
, save
->vga_hdp_control
);
632 WREG32(mmVGA_RENDER_CONTROL
, save
->vga_render_control
);
635 static void dce_v8_0_set_vga_render_state(struct amdgpu_device
*adev
,
640 /* Lockout access through VGA aperture*/
641 tmp
= RREG32(mmVGA_HDP_CONTROL
);
643 tmp
= REG_SET_FIELD(tmp
, VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
, 0);
645 tmp
= REG_SET_FIELD(tmp
, VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
, 1);
646 WREG32(mmVGA_HDP_CONTROL
, tmp
);
648 /* disable VGA render */
649 tmp
= RREG32(mmVGA_RENDER_CONTROL
);
651 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 1);
653 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 0);
654 WREG32(mmVGA_RENDER_CONTROL
, tmp
);
657 static void dce_v8_0_program_fmt(struct drm_encoder
*encoder
)
659 struct drm_device
*dev
= encoder
->dev
;
660 struct amdgpu_device
*adev
= dev
->dev_private
;
661 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
662 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
663 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
666 enum amdgpu_connector_dither dither
= AMDGPU_FMT_DITHER_DISABLE
;
669 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
670 bpc
= amdgpu_connector_get_monitor_bpc(connector
);
671 dither
= amdgpu_connector
->dither
;
674 /* LVDS/eDP FMT is set up by atom */
675 if (amdgpu_encoder
->devices
& ATOM_DEVICE_LCD_SUPPORT
)
678 /* not needed for analog */
679 if ((amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
) ||
680 (amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
))
688 if (dither
== AMDGPU_FMT_DITHER_ENABLE
)
689 /* XXX sort out optimal dither settings */
690 tmp
|= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK
|
691 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK
|
692 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK
|
693 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT
));
695 tmp
|= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK
|
696 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT
));
699 if (dither
== AMDGPU_FMT_DITHER_ENABLE
)
700 /* XXX sort out optimal dither settings */
701 tmp
|= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK
|
702 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK
|
703 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK
|
704 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK
|
705 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT
));
707 tmp
|= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK
|
708 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT
));
711 if (dither
== AMDGPU_FMT_DITHER_ENABLE
)
712 /* XXX sort out optimal dither settings */
713 tmp
|= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK
|
714 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK
|
715 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK
|
716 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK
|
717 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT
));
719 tmp
|= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK
|
720 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT
));
727 WREG32(mmFMT_BIT_DEPTH_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
731 /* display watermark setup */
733 * dce_v8_0_line_buffer_adjust - Set up the line buffer
735 * @adev: amdgpu_device pointer
736 * @amdgpu_crtc: the selected display controller
737 * @mode: the current display mode on the selected display
740 * Setup up the line buffer allocation for
741 * the selected display controller (CIK).
742 * Returns the line buffer size in pixels.
744 static u32
dce_v8_0_line_buffer_adjust(struct amdgpu_device
*adev
,
745 struct amdgpu_crtc
*amdgpu_crtc
,
746 struct drm_display_mode
*mode
)
748 u32 tmp
, buffer_alloc
, i
;
749 u32 pipe_offset
= amdgpu_crtc
->crtc_id
* 0x8;
752 * There are 6 line buffers, one for each display controllers.
753 * There are 3 partitions per LB. Select the number of partitions
754 * to enable based on the display width. For display widths larger
755 * than 4096, you need use to use 2 display controllers and combine
756 * them using the stereo blender.
758 if (amdgpu_crtc
->base
.enabled
&& mode
) {
759 if (mode
->crtc_hdisplay
< 1920) {
762 } else if (mode
->crtc_hdisplay
< 2560) {
765 } else if (mode
->crtc_hdisplay
< 4096) {
767 buffer_alloc
= (adev
->flags
& AMD_IS_APU
) ? 2 : 4;
769 DRM_DEBUG_KMS("Mode too big for LB!\n");
771 buffer_alloc
= (adev
->flags
& AMD_IS_APU
) ? 2 : 4;
778 WREG32(mmLB_MEMORY_CTRL
+ amdgpu_crtc
->crtc_offset
,
779 (tmp
<< LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT
) |
780 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT
));
782 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
,
783 (buffer_alloc
<< PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT
));
784 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
785 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
) &
786 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK
)
791 if (amdgpu_crtc
->base
.enabled
&& mode
) {
803 /* controller not enabled, so no lb used */
808 * cik_get_number_of_dram_channels - get the number of dram channels
810 * @adev: amdgpu_device pointer
812 * Look up the number of video ram channels (CIK).
813 * Used for display watermark bandwidth calculations
814 * Returns the number of dram channels
816 static u32
cik_get_number_of_dram_channels(struct amdgpu_device
*adev
)
818 u32 tmp
= RREG32(mmMC_SHARED_CHMAP
);
820 switch ((tmp
& MC_SHARED_CHMAP__NOOFCHAN_MASK
) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT
) {
843 struct dce8_wm_params
{
844 u32 dram_channels
; /* number of dram channels */
845 u32 yclk
; /* bandwidth per dram data pin in kHz */
846 u32 sclk
; /* engine clock in kHz */
847 u32 disp_clk
; /* display clock in kHz */
848 u32 src_width
; /* viewport width */
849 u32 active_time
; /* active display time in ns */
850 u32 blank_time
; /* blank time in ns */
851 bool interlaced
; /* mode is interlaced */
852 fixed20_12 vsc
; /* vertical scale ratio */
853 u32 num_heads
; /* number of active crtcs */
854 u32 bytes_per_pixel
; /* bytes per pixel display + overlay */
855 u32 lb_size
; /* line buffer allocated to pipe */
856 u32 vtaps
; /* vertical scaler taps */
860 * dce_v8_0_dram_bandwidth - get the dram bandwidth
862 * @wm: watermark calculation data
864 * Calculate the raw dram bandwidth (CIK).
865 * Used for display watermark bandwidth calculations
866 * Returns the dram bandwidth in MBytes/s
868 static u32
dce_v8_0_dram_bandwidth(struct dce8_wm_params
*wm
)
870 /* Calculate raw DRAM Bandwidth */
871 fixed20_12 dram_efficiency
; /* 0.7 */
872 fixed20_12 yclk
, dram_channels
, bandwidth
;
875 a
.full
= dfixed_const(1000);
876 yclk
.full
= dfixed_const(wm
->yclk
);
877 yclk
.full
= dfixed_div(yclk
, a
);
878 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
879 a
.full
= dfixed_const(10);
880 dram_efficiency
.full
= dfixed_const(7);
881 dram_efficiency
.full
= dfixed_div(dram_efficiency
, a
);
882 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
883 bandwidth
.full
= dfixed_mul(bandwidth
, dram_efficiency
);
885 return dfixed_trunc(bandwidth
);
889 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
891 * @wm: watermark calculation data
893 * Calculate the dram bandwidth used for display (CIK).
894 * Used for display watermark bandwidth calculations
895 * Returns the dram bandwidth for display in MBytes/s
897 static u32
dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params
*wm
)
899 /* Calculate DRAM Bandwidth and the part allocated to display. */
900 fixed20_12 disp_dram_allocation
; /* 0.3 to 0.7 */
901 fixed20_12 yclk
, dram_channels
, bandwidth
;
904 a
.full
= dfixed_const(1000);
905 yclk
.full
= dfixed_const(wm
->yclk
);
906 yclk
.full
= dfixed_div(yclk
, a
);
907 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
908 a
.full
= dfixed_const(10);
909 disp_dram_allocation
.full
= dfixed_const(3); /* XXX worse case value 0.3 */
910 disp_dram_allocation
.full
= dfixed_div(disp_dram_allocation
, a
);
911 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
912 bandwidth
.full
= dfixed_mul(bandwidth
, disp_dram_allocation
);
914 return dfixed_trunc(bandwidth
);
918 * dce_v8_0_data_return_bandwidth - get the data return bandwidth
920 * @wm: watermark calculation data
922 * Calculate the data return bandwidth used for display (CIK).
923 * Used for display watermark bandwidth calculations
924 * Returns the data return bandwidth in MBytes/s
926 static u32
dce_v8_0_data_return_bandwidth(struct dce8_wm_params
*wm
)
928 /* Calculate the display Data return Bandwidth */
929 fixed20_12 return_efficiency
; /* 0.8 */
930 fixed20_12 sclk
, bandwidth
;
933 a
.full
= dfixed_const(1000);
934 sclk
.full
= dfixed_const(wm
->sclk
);
935 sclk
.full
= dfixed_div(sclk
, a
);
936 a
.full
= dfixed_const(10);
937 return_efficiency
.full
= dfixed_const(8);
938 return_efficiency
.full
= dfixed_div(return_efficiency
, a
);
939 a
.full
= dfixed_const(32);
940 bandwidth
.full
= dfixed_mul(a
, sclk
);
941 bandwidth
.full
= dfixed_mul(bandwidth
, return_efficiency
);
943 return dfixed_trunc(bandwidth
);
947 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
949 * @wm: watermark calculation data
951 * Calculate the dmif bandwidth used for display (CIK).
952 * Used for display watermark bandwidth calculations
953 * Returns the dmif bandwidth in MBytes/s
955 static u32
dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params
*wm
)
957 /* Calculate the DMIF Request Bandwidth */
958 fixed20_12 disp_clk_request_efficiency
; /* 0.8 */
959 fixed20_12 disp_clk
, bandwidth
;
962 a
.full
= dfixed_const(1000);
963 disp_clk
.full
= dfixed_const(wm
->disp_clk
);
964 disp_clk
.full
= dfixed_div(disp_clk
, a
);
965 a
.full
= dfixed_const(32);
966 b
.full
= dfixed_mul(a
, disp_clk
);
968 a
.full
= dfixed_const(10);
969 disp_clk_request_efficiency
.full
= dfixed_const(8);
970 disp_clk_request_efficiency
.full
= dfixed_div(disp_clk_request_efficiency
, a
);
972 bandwidth
.full
= dfixed_mul(b
, disp_clk_request_efficiency
);
974 return dfixed_trunc(bandwidth
);
978 * dce_v8_0_available_bandwidth - get the min available bandwidth
980 * @wm: watermark calculation data
982 * Calculate the min available bandwidth used for display (CIK).
983 * Used for display watermark bandwidth calculations
984 * Returns the min available bandwidth in MBytes/s
986 static u32
dce_v8_0_available_bandwidth(struct dce8_wm_params
*wm
)
988 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
989 u32 dram_bandwidth
= dce_v8_0_dram_bandwidth(wm
);
990 u32 data_return_bandwidth
= dce_v8_0_data_return_bandwidth(wm
);
991 u32 dmif_req_bandwidth
= dce_v8_0_dmif_request_bandwidth(wm
);
993 return min(dram_bandwidth
, min(data_return_bandwidth
, dmif_req_bandwidth
));
997 * dce_v8_0_average_bandwidth - get the average available bandwidth
999 * @wm: watermark calculation data
1001 * Calculate the average available bandwidth used for display (CIK).
1002 * Used for display watermark bandwidth calculations
1003 * Returns the average available bandwidth in MBytes/s
1005 static u32
dce_v8_0_average_bandwidth(struct dce8_wm_params
*wm
)
1007 /* Calculate the display mode Average Bandwidth
1008 * DisplayMode should contain the source and destination dimensions,
1012 fixed20_12 line_time
;
1013 fixed20_12 src_width
;
1014 fixed20_12 bandwidth
;
1017 a
.full
= dfixed_const(1000);
1018 line_time
.full
= dfixed_const(wm
->active_time
+ wm
->blank_time
);
1019 line_time
.full
= dfixed_div(line_time
, a
);
1020 bpp
.full
= dfixed_const(wm
->bytes_per_pixel
);
1021 src_width
.full
= dfixed_const(wm
->src_width
);
1022 bandwidth
.full
= dfixed_mul(src_width
, bpp
);
1023 bandwidth
.full
= dfixed_mul(bandwidth
, wm
->vsc
);
1024 bandwidth
.full
= dfixed_div(bandwidth
, line_time
);
1026 return dfixed_trunc(bandwidth
);
1030 * dce_v8_0_latency_watermark - get the latency watermark
1032 * @wm: watermark calculation data
1034 * Calculate the latency watermark (CIK).
1035 * Used for display watermark bandwidth calculations
1036 * Returns the latency watermark in ns
1038 static u32
dce_v8_0_latency_watermark(struct dce8_wm_params
*wm
)
1040 /* First calculate the latency in ns */
1041 u32 mc_latency
= 2000; /* 2000 ns. */
1042 u32 available_bandwidth
= dce_v8_0_available_bandwidth(wm
);
1043 u32 worst_chunk_return_time
= (512 * 8 * 1000) / available_bandwidth
;
1044 u32 cursor_line_pair_return_time
= (128 * 4 * 1000) / available_bandwidth
;
1045 u32 dc_latency
= 40000000 / wm
->disp_clk
; /* dc pipe latency */
1046 u32 other_heads_data_return_time
= ((wm
->num_heads
+ 1) * worst_chunk_return_time
) +
1047 (wm
->num_heads
* cursor_line_pair_return_time
);
1048 u32 latency
= mc_latency
+ other_heads_data_return_time
+ dc_latency
;
1049 u32 max_src_lines_per_dst_line
, lb_fill_bw
, line_fill_time
;
1050 u32 tmp
, dmif_size
= 12288;
1053 if (wm
->num_heads
== 0)
1056 a
.full
= dfixed_const(2);
1057 b
.full
= dfixed_const(1);
1058 if ((wm
->vsc
.full
> a
.full
) ||
1059 ((wm
->vsc
.full
> b
.full
) && (wm
->vtaps
>= 3)) ||
1061 ((wm
->vsc
.full
>= a
.full
) && wm
->interlaced
))
1062 max_src_lines_per_dst_line
= 4;
1064 max_src_lines_per_dst_line
= 2;
1066 a
.full
= dfixed_const(available_bandwidth
);
1067 b
.full
= dfixed_const(wm
->num_heads
);
1068 a
.full
= dfixed_div(a
, b
);
1070 b
.full
= dfixed_const(mc_latency
+ 512);
1071 c
.full
= dfixed_const(wm
->disp_clk
);
1072 b
.full
= dfixed_div(b
, c
);
1074 c
.full
= dfixed_const(dmif_size
);
1075 b
.full
= dfixed_div(c
, b
);
1077 tmp
= min(dfixed_trunc(a
), dfixed_trunc(b
));
1079 b
.full
= dfixed_const(1000);
1080 c
.full
= dfixed_const(wm
->disp_clk
);
1081 b
.full
= dfixed_div(c
, b
);
1082 c
.full
= dfixed_const(wm
->bytes_per_pixel
);
1083 b
.full
= dfixed_mul(b
, c
);
1085 lb_fill_bw
= min(tmp
, dfixed_trunc(b
));
1087 a
.full
= dfixed_const(max_src_lines_per_dst_line
* wm
->src_width
* wm
->bytes_per_pixel
);
1088 b
.full
= dfixed_const(1000);
1089 c
.full
= dfixed_const(lb_fill_bw
);
1090 b
.full
= dfixed_div(c
, b
);
1091 a
.full
= dfixed_div(a
, b
);
1092 line_fill_time
= dfixed_trunc(a
);
1094 if (line_fill_time
< wm
->active_time
)
1097 return latency
+ (line_fill_time
- wm
->active_time
);
1102 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1103 * average and available dram bandwidth
1105 * @wm: watermark calculation data
1107 * Check if the display average bandwidth fits in the display
1108 * dram bandwidth (CIK).
1109 * Used for display watermark bandwidth calculations
1110 * Returns true if the display fits, false if not.
1112 static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params
*wm
)
1114 if (dce_v8_0_average_bandwidth(wm
) <=
1115 (dce_v8_0_dram_bandwidth_for_display(wm
) / wm
->num_heads
))
1122 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
1123 * average and available bandwidth
1125 * @wm: watermark calculation data
1127 * Check if the display average bandwidth fits in the display
1128 * available bandwidth (CIK).
1129 * Used for display watermark bandwidth calculations
1130 * Returns true if the display fits, false if not.
1132 static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params
*wm
)
1134 if (dce_v8_0_average_bandwidth(wm
) <=
1135 (dce_v8_0_available_bandwidth(wm
) / wm
->num_heads
))
1142 * dce_v8_0_check_latency_hiding - check latency hiding
1144 * @wm: watermark calculation data
1146 * Check latency hiding (CIK).
1147 * Used for display watermark bandwidth calculations
1148 * Returns true if the display fits, false if not.
1150 static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params
*wm
)
1152 u32 lb_partitions
= wm
->lb_size
/ wm
->src_width
;
1153 u32 line_time
= wm
->active_time
+ wm
->blank_time
;
1154 u32 latency_tolerant_lines
;
1158 a
.full
= dfixed_const(1);
1159 if (wm
->vsc
.full
> a
.full
)
1160 latency_tolerant_lines
= 1;
1162 if (lb_partitions
<= (wm
->vtaps
+ 1))
1163 latency_tolerant_lines
= 1;
1165 latency_tolerant_lines
= 2;
1168 latency_hiding
= (latency_tolerant_lines
* line_time
+ wm
->blank_time
);
1170 if (dce_v8_0_latency_watermark(wm
) <= latency_hiding
)
1177 * dce_v8_0_program_watermarks - program display watermarks
1179 * @adev: amdgpu_device pointer
1180 * @amdgpu_crtc: the selected display controller
1181 * @lb_size: line buffer size
1182 * @num_heads: number of display controllers in use
1184 * Calculate and program the display watermarks for the
1185 * selected display controller (CIK).
1187 static void dce_v8_0_program_watermarks(struct amdgpu_device
*adev
,
1188 struct amdgpu_crtc
*amdgpu_crtc
,
1189 u32 lb_size
, u32 num_heads
)
1191 struct drm_display_mode
*mode
= &amdgpu_crtc
->base
.mode
;
1192 struct dce8_wm_params wm_low
, wm_high
;
1195 u32 latency_watermark_a
= 0, latency_watermark_b
= 0;
1196 u32 tmp
, wm_mask
, lb_vblank_lead_lines
= 0;
1198 if (amdgpu_crtc
->base
.enabled
&& num_heads
&& mode
) {
1199 pixel_period
= 1000000 / (u32
)mode
->clock
;
1200 line_time
= min((u32
)mode
->crtc_htotal
* pixel_period
, (u32
)65535);
1202 /* watermark for high clocks */
1203 if (adev
->pm
.dpm_enabled
) {
1205 amdgpu_dpm_get_mclk(adev
, false) * 10;
1207 amdgpu_dpm_get_sclk(adev
, false) * 10;
1209 wm_high
.yclk
= adev
->pm
.current_mclk
* 10;
1210 wm_high
.sclk
= adev
->pm
.current_sclk
* 10;
1213 wm_high
.disp_clk
= mode
->clock
;
1214 wm_high
.src_width
= mode
->crtc_hdisplay
;
1215 wm_high
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
1216 wm_high
.blank_time
= line_time
- wm_high
.active_time
;
1217 wm_high
.interlaced
= false;
1218 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1219 wm_high
.interlaced
= true;
1220 wm_high
.vsc
= amdgpu_crtc
->vsc
;
1222 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
)
1224 wm_high
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1225 wm_high
.lb_size
= lb_size
;
1226 wm_high
.dram_channels
= cik_get_number_of_dram_channels(adev
);
1227 wm_high
.num_heads
= num_heads
;
1229 /* set for high clocks */
1230 latency_watermark_a
= min(dce_v8_0_latency_watermark(&wm_high
), (u32
)65535);
1232 /* possibly force display priority to high */
1233 /* should really do this at mode validation time... */
1234 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high
) ||
1235 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high
) ||
1236 !dce_v8_0_check_latency_hiding(&wm_high
) ||
1237 (adev
->mode_info
.disp_priority
== 2)) {
1238 DRM_DEBUG_KMS("force priority to high\n");
1241 /* watermark for low clocks */
1242 if (adev
->pm
.dpm_enabled
) {
1244 amdgpu_dpm_get_mclk(adev
, true) * 10;
1246 amdgpu_dpm_get_sclk(adev
, true) * 10;
1248 wm_low
.yclk
= adev
->pm
.current_mclk
* 10;
1249 wm_low
.sclk
= adev
->pm
.current_sclk
* 10;
1252 wm_low
.disp_clk
= mode
->clock
;
1253 wm_low
.src_width
= mode
->crtc_hdisplay
;
1254 wm_low
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
1255 wm_low
.blank_time
= line_time
- wm_low
.active_time
;
1256 wm_low
.interlaced
= false;
1257 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1258 wm_low
.interlaced
= true;
1259 wm_low
.vsc
= amdgpu_crtc
->vsc
;
1261 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
)
1263 wm_low
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1264 wm_low
.lb_size
= lb_size
;
1265 wm_low
.dram_channels
= cik_get_number_of_dram_channels(adev
);
1266 wm_low
.num_heads
= num_heads
;
1268 /* set for low clocks */
1269 latency_watermark_b
= min(dce_v8_0_latency_watermark(&wm_low
), (u32
)65535);
1271 /* possibly force display priority to high */
1272 /* should really do this at mode validation time... */
1273 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low
) ||
1274 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low
) ||
1275 !dce_v8_0_check_latency_hiding(&wm_low
) ||
1276 (adev
->mode_info
.disp_priority
== 2)) {
1277 DRM_DEBUG_KMS("force priority to high\n");
1279 lb_vblank_lead_lines
= DIV_ROUND_UP(lb_size
, mode
->crtc_hdisplay
);
1283 wm_mask
= RREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1285 tmp
&= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
);
1286 tmp
|= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
);
1287 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1288 WREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
,
1289 ((latency_watermark_a
<< DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
) |
1290 (line_time
<< DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
)));
1292 tmp
= RREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1293 tmp
&= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
);
1294 tmp
|= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
);
1295 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1296 WREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
,
1297 ((latency_watermark_b
<< DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
) |
1298 (line_time
<< DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
)));
1299 /* restore original selection */
1300 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, wm_mask
);
1302 /* save values for DPM */
1303 amdgpu_crtc
->line_time
= line_time
;
1304 amdgpu_crtc
->wm_high
= latency_watermark_a
;
1305 amdgpu_crtc
->wm_low
= latency_watermark_b
;
1306 /* Save number of lines the linebuffer leads before the scanout */
1307 amdgpu_crtc
->lb_vblank_lead_lines
= lb_vblank_lead_lines
;
1311 * dce_v8_0_bandwidth_update - program display watermarks
1313 * @adev: amdgpu_device pointer
1315 * Calculate and program the display watermarks and line
1316 * buffer allocation (CIK).
1318 static void dce_v8_0_bandwidth_update(struct amdgpu_device
*adev
)
1320 struct drm_display_mode
*mode
= NULL
;
1321 u32 num_heads
= 0, lb_size
;
1324 amdgpu_update_display_priority(adev
);
1326 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
1327 if (adev
->mode_info
.crtcs
[i
]->base
.enabled
)
1330 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
1331 mode
= &adev
->mode_info
.crtcs
[i
]->base
.mode
;
1332 lb_size
= dce_v8_0_line_buffer_adjust(adev
, adev
->mode_info
.crtcs
[i
], mode
);
1333 dce_v8_0_program_watermarks(adev
, adev
->mode_info
.crtcs
[i
],
1334 lb_size
, num_heads
);
1338 static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device
*adev
)
1343 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1344 offset
= adev
->mode_info
.audio
.pin
[i
].offset
;
1345 tmp
= RREG32_AUDIO_ENDPT(offset
,
1346 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
);
1348 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
) >>
1349 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
) == 1)
1350 adev
->mode_info
.audio
.pin
[i
].connected
= false;
1352 adev
->mode_info
.audio
.pin
[i
].connected
= true;
1356 static struct amdgpu_audio_pin
*dce_v8_0_audio_get_pin(struct amdgpu_device
*adev
)
1360 dce_v8_0_audio_get_connected_pins(adev
);
1362 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1363 if (adev
->mode_info
.audio
.pin
[i
].connected
)
1364 return &adev
->mode_info
.audio
.pin
[i
];
1366 DRM_ERROR("No connected audio pins found!\n");
1370 static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder
*encoder
)
1372 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1373 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1374 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1377 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1380 offset
= dig
->afmt
->offset
;
1382 WREG32(mmAFMT_AUDIO_SRC_CONTROL
+ offset
,
1383 (dig
->afmt
->pin
->id
<< AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT
));
1386 static void dce_v8_0_audio_write_latency_fields(struct drm_encoder
*encoder
,
1387 struct drm_display_mode
*mode
)
1389 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1390 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1391 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1392 struct drm_connector
*connector
;
1393 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1394 u32 tmp
= 0, offset
;
1396 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1399 offset
= dig
->afmt
->pin
->offset
;
1401 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1402 if (connector
->encoder
== encoder
) {
1403 amdgpu_connector
= to_amdgpu_connector(connector
);
1408 if (!amdgpu_connector
) {
1409 DRM_ERROR("Couldn't find encoder's connector\n");
1413 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
1414 if (connector
->latency_present
[1])
1416 (connector
->video_latency
[1] <<
1417 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
) |
1418 (connector
->audio_latency
[1] <<
1419 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
);
1423 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
) |
1425 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
);
1427 if (connector
->latency_present
[0])
1429 (connector
->video_latency
[0] <<
1430 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
) |
1431 (connector
->audio_latency
[0] <<
1432 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
);
1436 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
) |
1438 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
);
1441 WREG32_AUDIO_ENDPT(offset
, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
, tmp
);
1444 static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder
*encoder
)
1446 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1447 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1448 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1449 struct drm_connector
*connector
;
1450 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1455 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1458 offset
= dig
->afmt
->pin
->offset
;
1460 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1461 if (connector
->encoder
== encoder
) {
1462 amdgpu_connector
= to_amdgpu_connector(connector
);
1467 if (!amdgpu_connector
) {
1468 DRM_ERROR("Couldn't find encoder's connector\n");
1472 sad_count
= drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector
), &sadb
);
1473 if (sad_count
< 0) {
1474 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count
);
1478 /* program the speaker allocation */
1479 tmp
= RREG32_AUDIO_ENDPT(offset
, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
);
1480 tmp
&= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK
|
1481 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK
);
1483 tmp
|= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK
;
1485 tmp
|= (sadb
[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT
);
1487 tmp
|= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT
); /* stereo */
1488 WREG32_AUDIO_ENDPT(offset
, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
, tmp
);
1493 static void dce_v8_0_audio_write_sad_regs(struct drm_encoder
*encoder
)
1495 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1496 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1497 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1499 struct drm_connector
*connector
;
1500 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1501 struct cea_sad
*sads
;
1504 static const u16 eld_reg_to_type
[][2] = {
1505 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
, HDMI_AUDIO_CODING_TYPE_PCM
},
1506 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
, HDMI_AUDIO_CODING_TYPE_AC3
},
1507 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
, HDMI_AUDIO_CODING_TYPE_MPEG1
},
1508 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
, HDMI_AUDIO_CODING_TYPE_MP3
},
1509 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
, HDMI_AUDIO_CODING_TYPE_MPEG2
},
1510 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
, HDMI_AUDIO_CODING_TYPE_AAC_LC
},
1511 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
, HDMI_AUDIO_CODING_TYPE_DTS
},
1512 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
, HDMI_AUDIO_CODING_TYPE_ATRAC
},
1513 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
, HDMI_AUDIO_CODING_TYPE_EAC3
},
1514 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
, HDMI_AUDIO_CODING_TYPE_DTS_HD
},
1515 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
, HDMI_AUDIO_CODING_TYPE_MLP
},
1516 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
, HDMI_AUDIO_CODING_TYPE_WMA_PRO
},
1519 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1522 offset
= dig
->afmt
->pin
->offset
;
1524 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1525 if (connector
->encoder
== encoder
) {
1526 amdgpu_connector
= to_amdgpu_connector(connector
);
1531 if (!amdgpu_connector
) {
1532 DRM_ERROR("Couldn't find encoder's connector\n");
1536 sad_count
= drm_edid_to_sad(amdgpu_connector_edid(connector
), &sads
);
1537 if (sad_count
<= 0) {
1538 DRM_ERROR("Couldn't read SADs: %d\n", sad_count
);
1543 for (i
= 0; i
< ARRAY_SIZE(eld_reg_to_type
); i
++) {
1545 u8 stereo_freqs
= 0;
1546 int max_channels
= -1;
1549 for (j
= 0; j
< sad_count
; j
++) {
1550 struct cea_sad
*sad
= &sads
[j
];
1552 if (sad
->format
== eld_reg_to_type
[i
][1]) {
1553 if (sad
->channels
> max_channels
) {
1554 value
= (sad
->channels
<<
1555 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT
) |
1557 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT
) |
1559 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT
);
1560 max_channels
= sad
->channels
;
1563 if (sad
->format
== HDMI_AUDIO_CODING_TYPE_PCM
)
1564 stereo_freqs
|= sad
->freq
;
1570 value
|= (stereo_freqs
<<
1571 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT
);
1573 WREG32_AUDIO_ENDPT(offset
, eld_reg_to_type
[i
][0], value
);
1579 static void dce_v8_0_audio_enable(struct amdgpu_device
*adev
,
1580 struct amdgpu_audio_pin
*pin
,
1586 WREG32_AUDIO_ENDPT(pin
->offset
, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
,
1587 enable
? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
: 0);
1590 static const u32 pin_offsets
[7] =
1601 static int dce_v8_0_audio_init(struct amdgpu_device
*adev
)
1608 adev
->mode_info
.audio
.enabled
= true;
1610 if (adev
->asic_type
== CHIP_KAVERI
) /* KV: 4 streams, 7 endpoints */
1611 adev
->mode_info
.audio
.num_pins
= 7;
1612 else if ((adev
->asic_type
== CHIP_KABINI
) ||
1613 (adev
->asic_type
== CHIP_MULLINS
)) /* KB/ML: 2 streams, 3 endpoints */
1614 adev
->mode_info
.audio
.num_pins
= 3;
1615 else if ((adev
->asic_type
== CHIP_BONAIRE
) ||
1616 (adev
->asic_type
== CHIP_HAWAII
))/* BN/HW: 6 streams, 7 endpoints */
1617 adev
->mode_info
.audio
.num_pins
= 7;
1619 adev
->mode_info
.audio
.num_pins
= 3;
1621 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1622 adev
->mode_info
.audio
.pin
[i
].channels
= -1;
1623 adev
->mode_info
.audio
.pin
[i
].rate
= -1;
1624 adev
->mode_info
.audio
.pin
[i
].bits_per_sample
= -1;
1625 adev
->mode_info
.audio
.pin
[i
].status_bits
= 0;
1626 adev
->mode_info
.audio
.pin
[i
].category_code
= 0;
1627 adev
->mode_info
.audio
.pin
[i
].connected
= false;
1628 adev
->mode_info
.audio
.pin
[i
].offset
= pin_offsets
[i
];
1629 adev
->mode_info
.audio
.pin
[i
].id
= i
;
1630 /* disable audio. it will be set up later */
1631 /* XXX remove once we switch to ip funcs */
1632 dce_v8_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
1638 static void dce_v8_0_audio_fini(struct amdgpu_device
*adev
)
1642 if (!adev
->mode_info
.audio
.enabled
)
1645 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++)
1646 dce_v8_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
1648 adev
->mode_info
.audio
.enabled
= false;
1652 * update the N and CTS parameters for a given pixel clock rate
1654 static void dce_v8_0_afmt_update_ACR(struct drm_encoder
*encoder
, uint32_t clock
)
1656 struct drm_device
*dev
= encoder
->dev
;
1657 struct amdgpu_device
*adev
= dev
->dev_private
;
1658 struct amdgpu_afmt_acr acr
= amdgpu_afmt_acr(clock
);
1659 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1660 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1661 uint32_t offset
= dig
->afmt
->offset
;
1663 WREG32(mmHDMI_ACR_32_0
+ offset
, (acr
.cts_32khz
<< HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT
));
1664 WREG32(mmHDMI_ACR_32_1
+ offset
, acr
.n_32khz
);
1666 WREG32(mmHDMI_ACR_44_0
+ offset
, (acr
.cts_44_1khz
<< HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT
));
1667 WREG32(mmHDMI_ACR_44_1
+ offset
, acr
.n_44_1khz
);
1669 WREG32(mmHDMI_ACR_48_0
+ offset
, (acr
.cts_48khz
<< HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT
));
1670 WREG32(mmHDMI_ACR_48_1
+ offset
, acr
.n_48khz
);
1674 * build a HDMI Video Info Frame
1676 static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder
*encoder
,
1677 void *buffer
, size_t size
)
1679 struct drm_device
*dev
= encoder
->dev
;
1680 struct amdgpu_device
*adev
= dev
->dev_private
;
1681 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1682 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1683 uint32_t offset
= dig
->afmt
->offset
;
1684 uint8_t *frame
= buffer
+ 3;
1685 uint8_t *header
= buffer
;
1687 WREG32(mmAFMT_AVI_INFO0
+ offset
,
1688 frame
[0x0] | (frame
[0x1] << 8) | (frame
[0x2] << 16) | (frame
[0x3] << 24));
1689 WREG32(mmAFMT_AVI_INFO1
+ offset
,
1690 frame
[0x4] | (frame
[0x5] << 8) | (frame
[0x6] << 16) | (frame
[0x7] << 24));
1691 WREG32(mmAFMT_AVI_INFO2
+ offset
,
1692 frame
[0x8] | (frame
[0x9] << 8) | (frame
[0xA] << 16) | (frame
[0xB] << 24));
1693 WREG32(mmAFMT_AVI_INFO3
+ offset
,
1694 frame
[0xC] | (frame
[0xD] << 8) | (header
[1] << 24));
1697 static void dce_v8_0_audio_set_dto(struct drm_encoder
*encoder
, u32 clock
)
1699 struct drm_device
*dev
= encoder
->dev
;
1700 struct amdgpu_device
*adev
= dev
->dev_private
;
1701 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1702 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1703 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1704 u32 dto_phase
= 24 * 1000;
1705 u32 dto_modulo
= clock
;
1707 if (!dig
|| !dig
->afmt
)
1710 /* XXX two dtos; generally use dto0 for hdmi */
1711 /* Express [24MHz / target pixel clock] as an exact rational
1712 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1713 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1715 WREG32(mmDCCG_AUDIO_DTO_SOURCE
, (amdgpu_crtc
->crtc_id
<< DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT
));
1716 WREG32(mmDCCG_AUDIO_DTO0_PHASE
, dto_phase
);
1717 WREG32(mmDCCG_AUDIO_DTO0_MODULE
, dto_modulo
);
1721 * update the info frames with the data from the current display mode
1723 static void dce_v8_0_afmt_setmode(struct drm_encoder
*encoder
,
1724 struct drm_display_mode
*mode
)
1726 struct drm_device
*dev
= encoder
->dev
;
1727 struct amdgpu_device
*adev
= dev
->dev_private
;
1728 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1729 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1730 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
1731 u8 buffer
[HDMI_INFOFRAME_HEADER_SIZE
+ HDMI_AVI_INFOFRAME_SIZE
];
1732 struct hdmi_avi_infoframe frame
;
1733 uint32_t offset
, val
;
1737 if (!dig
|| !dig
->afmt
)
1740 /* Silent, r600_hdmi_enable will raise WARN for us */
1741 if (!dig
->afmt
->enabled
)
1743 offset
= dig
->afmt
->offset
;
1745 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1746 if (encoder
->crtc
) {
1747 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1748 bpc
= amdgpu_crtc
->bpc
;
1751 /* disable audio prior to setting up hw */
1752 dig
->afmt
->pin
= dce_v8_0_audio_get_pin(adev
);
1753 dce_v8_0_audio_enable(adev
, dig
->afmt
->pin
, false);
1755 dce_v8_0_audio_set_dto(encoder
, mode
->clock
);
1757 WREG32(mmHDMI_VBI_PACKET_CONTROL
+ offset
,
1758 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK
); /* send null packets when required */
1760 WREG32(mmAFMT_AUDIO_CRC_CONTROL
+ offset
, 0x1000);
1762 val
= RREG32(mmHDMI_CONTROL
+ offset
);
1763 val
&= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK
;
1764 val
&= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK
;
1772 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1773 connector
->name
, bpc
);
1776 val
|= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK
;
1777 val
|= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT
;
1778 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1782 val
|= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK
;
1783 val
|= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT
;
1784 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1789 WREG32(mmHDMI_CONTROL
+ offset
, val
);
1791 WREG32(mmHDMI_VBI_PACKET_CONTROL
+ offset
,
1792 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK
| /* send null packets when required */
1793 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK
| /* send general control packets */
1794 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK
); /* send general control packets every frame */
1796 WREG32(mmHDMI_INFOFRAME_CONTROL0
+ offset
,
1797 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK
| /* enable audio info frames (frames won't be set until audio is enabled) */
1798 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK
); /* required for audio info values to be updated */
1800 WREG32(mmAFMT_INFOFRAME_CONTROL0
+ offset
,
1801 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK
); /* required for audio info values to be updated */
1803 WREG32(mmHDMI_INFOFRAME_CONTROL1
+ offset
,
1804 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT
)); /* anything other than 0 */
1806 WREG32(mmHDMI_GC
+ offset
, 0); /* unset HDMI_GC_AVMUTE */
1808 WREG32(mmHDMI_AUDIO_PACKET_CONTROL
+ offset
,
1809 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT
) | /* set the default audio delay */
1810 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT
)); /* should be suffient for all audio modes and small enough for all hblanks */
1812 WREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ offset
,
1813 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK
); /* allow 60958 channel status fields to be updated */
1815 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1818 WREG32(mmHDMI_ACR_PACKET_CONTROL
+ offset
,
1819 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK
); /* allow hw to sent ACR packets when required */
1821 WREG32(mmHDMI_ACR_PACKET_CONTROL
+ offset
,
1822 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK
| /* select SW CTS value */
1823 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK
); /* allow hw to sent ACR packets when required */
1825 dce_v8_0_afmt_update_ACR(encoder
, mode
->clock
);
1827 WREG32(mmAFMT_60958_0
+ offset
,
1828 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT
));
1830 WREG32(mmAFMT_60958_1
+ offset
,
1831 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT
));
1833 WREG32(mmAFMT_60958_2
+ offset
,
1834 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT
) |
1835 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT
) |
1836 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT
) |
1837 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT
) |
1838 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT
) |
1839 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT
));
1841 dce_v8_0_audio_write_speaker_allocation(encoder
);
1844 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2
+ offset
,
1845 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT
));
1847 dce_v8_0_afmt_audio_select_pin(encoder
);
1848 dce_v8_0_audio_write_sad_regs(encoder
);
1849 dce_v8_0_audio_write_latency_fields(encoder
, mode
);
1851 err
= drm_hdmi_avi_infoframe_from_display_mode(&frame
, mode
);
1853 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err
);
1857 err
= hdmi_avi_infoframe_pack(&frame
, buffer
, sizeof(buffer
));
1859 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err
);
1863 dce_v8_0_afmt_update_avi_infoframe(encoder
, buffer
, sizeof(buffer
));
1865 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0
+ offset
,
1866 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK
| /* enable AVI info frames */
1867 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK
); /* required for audio info values to be updated */
1869 WREG32_P(mmHDMI_INFOFRAME_CONTROL1
+ offset
,
1870 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT
), /* anything other than 0 */
1871 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK
);
1873 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL
+ offset
,
1874 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK
); /* send audio packets */
1876 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
1877 WREG32(mmAFMT_RAMP_CONTROL0
+ offset
, 0x00FFFFFF);
1878 WREG32(mmAFMT_RAMP_CONTROL1
+ offset
, 0x007FFFFF);
1879 WREG32(mmAFMT_RAMP_CONTROL2
+ offset
, 0x00000001);
1880 WREG32(mmAFMT_RAMP_CONTROL3
+ offset
, 0x00000001);
1882 /* enable audio after to setting up hw */
1883 dce_v8_0_audio_enable(adev
, dig
->afmt
->pin
, true);
1886 static void dce_v8_0_afmt_enable(struct drm_encoder
*encoder
, bool enable
)
1888 struct drm_device
*dev
= encoder
->dev
;
1889 struct amdgpu_device
*adev
= dev
->dev_private
;
1890 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1891 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1893 if (!dig
|| !dig
->afmt
)
1896 /* Silent, r600_hdmi_enable will raise WARN for us */
1897 if (enable
&& dig
->afmt
->enabled
)
1899 if (!enable
&& !dig
->afmt
->enabled
)
1902 if (!enable
&& dig
->afmt
->pin
) {
1903 dce_v8_0_audio_enable(adev
, dig
->afmt
->pin
, false);
1904 dig
->afmt
->pin
= NULL
;
1907 dig
->afmt
->enabled
= enable
;
1909 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1910 enable
? "En" : "Dis", dig
->afmt
->offset
, amdgpu_encoder
->encoder_id
);
1913 static void dce_v8_0_afmt_init(struct amdgpu_device
*adev
)
1917 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++)
1918 adev
->mode_info
.afmt
[i
] = NULL
;
1920 /* DCE8 has audio blocks tied to DIG encoders */
1921 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++) {
1922 adev
->mode_info
.afmt
[i
] = kzalloc(sizeof(struct amdgpu_afmt
), GFP_KERNEL
);
1923 if (adev
->mode_info
.afmt
[i
]) {
1924 adev
->mode_info
.afmt
[i
]->offset
= dig_offsets
[i
];
1925 adev
->mode_info
.afmt
[i
]->id
= i
;
1930 static void dce_v8_0_afmt_fini(struct amdgpu_device
*adev
)
1934 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++) {
1935 kfree(adev
->mode_info
.afmt
[i
]);
1936 adev
->mode_info
.afmt
[i
] = NULL
;
1940 static const u32 vga_control_regs
[6] =
1950 static void dce_v8_0_vga_enable(struct drm_crtc
*crtc
, bool enable
)
1952 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
1953 struct drm_device
*dev
= crtc
->dev
;
1954 struct amdgpu_device
*adev
= dev
->dev_private
;
1957 vga_control
= RREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
]) & ~1;
1959 WREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
], vga_control
| 1);
1961 WREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
], vga_control
);
1964 static void dce_v8_0_grph_enable(struct drm_crtc
*crtc
, bool enable
)
1966 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
1967 struct drm_device
*dev
= crtc
->dev
;
1968 struct amdgpu_device
*adev
= dev
->dev_private
;
1971 WREG32(mmGRPH_ENABLE
+ amdgpu_crtc
->crtc_offset
, 1);
1973 WREG32(mmGRPH_ENABLE
+ amdgpu_crtc
->crtc_offset
, 0);
1976 static int dce_v8_0_crtc_do_set_base(struct drm_crtc
*crtc
,
1977 struct drm_framebuffer
*fb
,
1978 int x
, int y
, int atomic
)
1980 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
1981 struct drm_device
*dev
= crtc
->dev
;
1982 struct amdgpu_device
*adev
= dev
->dev_private
;
1983 struct amdgpu_framebuffer
*amdgpu_fb
;
1984 struct drm_framebuffer
*target_fb
;
1985 struct drm_gem_object
*obj
;
1986 struct amdgpu_bo
*rbo
;
1987 uint64_t fb_location
, tiling_flags
;
1988 uint32_t fb_format
, fb_pitch_pixels
;
1989 u32 fb_swap
= (GRPH_ENDIAN_NONE
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
1991 u32 tmp
, viewport_w
, viewport_h
;
1993 bool bypass_lut
= false;
1996 if (!atomic
&& !crtc
->primary
->fb
) {
1997 DRM_DEBUG_KMS("No FB bound\n");
2002 amdgpu_fb
= to_amdgpu_framebuffer(fb
);
2006 amdgpu_fb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
2007 target_fb
= crtc
->primary
->fb
;
2010 /* If atomic, assume fb object is pinned & idle & fenced and
2011 * just update base pointers
2013 obj
= amdgpu_fb
->obj
;
2014 rbo
= gem_to_amdgpu_bo(obj
);
2015 r
= amdgpu_bo_reserve(rbo
, false);
2016 if (unlikely(r
!= 0))
2020 fb_location
= amdgpu_bo_gpu_offset(rbo
);
2022 r
= amdgpu_bo_pin(rbo
, AMDGPU_GEM_DOMAIN_VRAM
, &fb_location
);
2023 if (unlikely(r
!= 0)) {
2024 amdgpu_bo_unreserve(rbo
);
2029 amdgpu_bo_get_tiling_flags(rbo
, &tiling_flags
);
2030 amdgpu_bo_unreserve(rbo
);
2032 pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
2034 switch (target_fb
->pixel_format
) {
2036 fb_format
= ((GRPH_DEPTH_8BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2037 (GRPH_FORMAT_INDEXED
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2039 case DRM_FORMAT_XRGB4444
:
2040 case DRM_FORMAT_ARGB4444
:
2041 fb_format
= ((GRPH_DEPTH_16BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2042 (GRPH_FORMAT_ARGB1555
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2044 fb_swap
= (GRPH_ENDIAN_8IN16
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2047 case DRM_FORMAT_XRGB1555
:
2048 case DRM_FORMAT_ARGB1555
:
2049 fb_format
= ((GRPH_DEPTH_16BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2050 (GRPH_FORMAT_ARGB1555
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2052 fb_swap
= (GRPH_ENDIAN_8IN16
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2055 case DRM_FORMAT_BGRX5551
:
2056 case DRM_FORMAT_BGRA5551
:
2057 fb_format
= ((GRPH_DEPTH_16BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2058 (GRPH_FORMAT_BGRA5551
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2060 fb_swap
= (GRPH_ENDIAN_8IN16
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2063 case DRM_FORMAT_RGB565
:
2064 fb_format
= ((GRPH_DEPTH_16BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2065 (GRPH_FORMAT_ARGB565
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2067 fb_swap
= (GRPH_ENDIAN_8IN16
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2070 case DRM_FORMAT_XRGB8888
:
2071 case DRM_FORMAT_ARGB8888
:
2072 fb_format
= ((GRPH_DEPTH_32BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2073 (GRPH_FORMAT_ARGB8888
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2075 fb_swap
= (GRPH_ENDIAN_8IN32
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2078 case DRM_FORMAT_XRGB2101010
:
2079 case DRM_FORMAT_ARGB2101010
:
2080 fb_format
= ((GRPH_DEPTH_32BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2081 (GRPH_FORMAT_ARGB2101010
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2083 fb_swap
= (GRPH_ENDIAN_8IN32
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2085 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2088 case DRM_FORMAT_BGRX1010102
:
2089 case DRM_FORMAT_BGRA1010102
:
2090 fb_format
= ((GRPH_DEPTH_32BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2091 (GRPH_FORMAT_BGRA1010102
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2093 fb_swap
= (GRPH_ENDIAN_8IN32
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2095 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2099 DRM_ERROR("Unsupported screen format %s\n",
2100 drm_get_format_name(target_fb
->pixel_format
));
2104 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == ARRAY_2D_TILED_THIN1
) {
2105 unsigned bankw
, bankh
, mtaspect
, tile_split
, num_banks
;
2107 bankw
= AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
2108 bankh
= AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
2109 mtaspect
= AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
2110 tile_split
= AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
);
2111 num_banks
= AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
2113 fb_format
|= (num_banks
<< GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT
);
2114 fb_format
|= (GRPH_ARRAY_2D_TILED_THIN1
<< GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT
);
2115 fb_format
|= (tile_split
<< GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT
);
2116 fb_format
|= (bankw
<< GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT
);
2117 fb_format
|= (bankh
<< GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT
);
2118 fb_format
|= (mtaspect
<< GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT
);
2119 fb_format
|= (DISPLAY_MICRO_TILING
<< GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT
);
2120 } else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == ARRAY_1D_TILED_THIN1
) {
2121 fb_format
|= (GRPH_ARRAY_1D_TILED_THIN1
<< GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT
);
2124 fb_format
|= (pipe_config
<< GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT
);
2126 dce_v8_0_vga_enable(crtc
, false);
2128 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2129 upper_32_bits(fb_location
));
2130 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2131 upper_32_bits(fb_location
));
2132 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2133 (u32
)fb_location
& GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
);
2134 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2135 (u32
) fb_location
& GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
);
2136 WREG32(mmGRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
, fb_format
);
2137 WREG32(mmGRPH_SWAP_CNTL
+ amdgpu_crtc
->crtc_offset
, fb_swap
);
2140 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2141 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2142 * retain the full precision throughout the pipeline.
2144 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2145 (bypass_lut
? LUT_10BIT_BYPASS_EN
: 0),
2146 ~LUT_10BIT_BYPASS_EN
);
2149 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2151 WREG32(mmGRPH_SURFACE_OFFSET_X
+ amdgpu_crtc
->crtc_offset
, 0);
2152 WREG32(mmGRPH_SURFACE_OFFSET_Y
+ amdgpu_crtc
->crtc_offset
, 0);
2153 WREG32(mmGRPH_X_START
+ amdgpu_crtc
->crtc_offset
, 0);
2154 WREG32(mmGRPH_Y_START
+ amdgpu_crtc
->crtc_offset
, 0);
2155 WREG32(mmGRPH_X_END
+ amdgpu_crtc
->crtc_offset
, target_fb
->width
);
2156 WREG32(mmGRPH_Y_END
+ amdgpu_crtc
->crtc_offset
, target_fb
->height
);
2158 fb_pitch_pixels
= target_fb
->pitches
[0] / (target_fb
->bits_per_pixel
/ 8);
2159 WREG32(mmGRPH_PITCH
+ amdgpu_crtc
->crtc_offset
, fb_pitch_pixels
);
2161 dce_v8_0_grph_enable(crtc
, true);
2163 WREG32(mmLB_DESKTOP_HEIGHT
+ amdgpu_crtc
->crtc_offset
,
2168 WREG32(mmVIEWPORT_START
+ amdgpu_crtc
->crtc_offset
,
2170 viewport_w
= crtc
->mode
.hdisplay
;
2171 viewport_h
= (crtc
->mode
.vdisplay
+ 1) & ~1;
2172 WREG32(mmVIEWPORT_SIZE
+ amdgpu_crtc
->crtc_offset
,
2173 (viewport_w
<< 16) | viewport_h
);
2175 /* pageflip setup */
2176 /* make sure flip is at vb rather than hb */
2177 tmp
= RREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2178 tmp
&= ~GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK
;
2179 WREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2181 /* set pageflip to happen only at start of vblank interval (front porch) */
2182 WREG32(mmMASTER_UPDATE_MODE
+ amdgpu_crtc
->crtc_offset
, 3);
2184 if (!atomic
&& fb
&& fb
!= crtc
->primary
->fb
) {
2185 amdgpu_fb
= to_amdgpu_framebuffer(fb
);
2186 rbo
= gem_to_amdgpu_bo(amdgpu_fb
->obj
);
2187 r
= amdgpu_bo_reserve(rbo
, false);
2188 if (unlikely(r
!= 0))
2190 amdgpu_bo_unpin(rbo
);
2191 amdgpu_bo_unreserve(rbo
);
2194 /* Bytes per pixel may have changed */
2195 dce_v8_0_bandwidth_update(adev
);
2200 static void dce_v8_0_set_interleave(struct drm_crtc
*crtc
,
2201 struct drm_display_mode
*mode
)
2203 struct drm_device
*dev
= crtc
->dev
;
2204 struct amdgpu_device
*adev
= dev
->dev_private
;
2205 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2207 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
2208 WREG32(mmLB_DATA_FORMAT
+ amdgpu_crtc
->crtc_offset
,
2209 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT
);
2211 WREG32(mmLB_DATA_FORMAT
+ amdgpu_crtc
->crtc_offset
, 0);
2214 static void dce_v8_0_crtc_load_lut(struct drm_crtc
*crtc
)
2216 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2217 struct drm_device
*dev
= crtc
->dev
;
2218 struct amdgpu_device
*adev
= dev
->dev_private
;
2221 DRM_DEBUG_KMS("%d\n", amdgpu_crtc
->crtc_id
);
2223 WREG32(mmINPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2224 ((INPUT_CSC_BYPASS
<< INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT
) |
2225 (INPUT_CSC_BYPASS
<< INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT
)));
2226 WREG32(mmPRESCALE_GRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2227 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK
);
2228 WREG32(mmPRESCALE_OVL_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2229 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK
);
2230 WREG32(mmINPUT_GAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2231 ((INPUT_GAMMA_USE_LUT
<< INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT
) |
2232 (INPUT_GAMMA_USE_LUT
<< INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT
)));
2234 WREG32(mmDC_LUT_CONTROL
+ amdgpu_crtc
->crtc_offset
, 0);
2236 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE
+ amdgpu_crtc
->crtc_offset
, 0);
2237 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN
+ amdgpu_crtc
->crtc_offset
, 0);
2238 WREG32(mmDC_LUT_BLACK_OFFSET_RED
+ amdgpu_crtc
->crtc_offset
, 0);
2240 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2241 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2242 WREG32(mmDC_LUT_WHITE_OFFSET_RED
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2244 WREG32(mmDC_LUT_RW_MODE
+ amdgpu_crtc
->crtc_offset
, 0);
2245 WREG32(mmDC_LUT_WRITE_EN_MASK
+ amdgpu_crtc
->crtc_offset
, 0x00000007);
2247 WREG32(mmDC_LUT_RW_INDEX
+ amdgpu_crtc
->crtc_offset
, 0);
2248 for (i
= 0; i
< 256; i
++) {
2249 WREG32(mmDC_LUT_30_COLOR
+ amdgpu_crtc
->crtc_offset
,
2250 (amdgpu_crtc
->lut_r
[i
] << 20) |
2251 (amdgpu_crtc
->lut_g
[i
] << 10) |
2252 (amdgpu_crtc
->lut_b
[i
] << 0));
2255 WREG32(mmDEGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2256 ((DEGAMMA_BYPASS
<< DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT
) |
2257 (DEGAMMA_BYPASS
<< DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT
) |
2258 (DEGAMMA_BYPASS
<< DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT
)));
2259 WREG32(mmGAMUT_REMAP_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2260 ((GAMUT_REMAP_BYPASS
<< GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT
) |
2261 (GAMUT_REMAP_BYPASS
<< GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT
)));
2262 WREG32(mmREGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2263 ((REGAMMA_BYPASS
<< REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT
) |
2264 (REGAMMA_BYPASS
<< REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT
)));
2265 WREG32(mmOUTPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2266 ((OUTPUT_CSC_BYPASS
<< OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT
) |
2267 (OUTPUT_CSC_BYPASS
<< OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT
)));
2268 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2269 WREG32(0x1a50 + amdgpu_crtc
->crtc_offset
, 0);
2270 /* XXX this only needs to be programmed once per crtc at startup,
2271 * not sure where the best place for it is
2273 WREG32(mmALPHA_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2274 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK
);
2277 static int dce_v8_0_pick_dig_encoder(struct drm_encoder
*encoder
)
2279 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
2280 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
2282 switch (amdgpu_encoder
->encoder_id
) {
2283 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2289 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2295 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2301 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2305 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder
->encoder_id
);
2311 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2315 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2316 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2317 * monitors a dedicated PPLL must be used. If a particular board has
2318 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2319 * as there is no need to program the PLL itself. If we are not able to
2320 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2321 * avoid messing up an existing monitor.
2323 * Asic specific PLL information
2327 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2329 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2332 static u32
dce_v8_0_pick_pll(struct drm_crtc
*crtc
)
2334 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2335 struct drm_device
*dev
= crtc
->dev
;
2336 struct amdgpu_device
*adev
= dev
->dev_private
;
2340 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
))) {
2341 if (adev
->clock
.dp_extclk
)
2342 /* skip PPLL programming if using ext clock */
2343 return ATOM_PPLL_INVALID
;
2345 /* use the same PPLL for all DP monitors */
2346 pll
= amdgpu_pll_get_shared_dp_ppll(crtc
);
2347 if (pll
!= ATOM_PPLL_INVALID
)
2351 /* use the same PPLL for all monitors with the same clock */
2352 pll
= amdgpu_pll_get_shared_nondp_ppll(crtc
);
2353 if (pll
!= ATOM_PPLL_INVALID
)
2356 /* otherwise, pick one of the plls */
2357 if ((adev
->asic_type
== CHIP_KABINI
) ||
2358 (adev
->asic_type
== CHIP_MULLINS
)) {
2359 /* KB/ML has PPLL1 and PPLL2 */
2360 pll_in_use
= amdgpu_pll_get_use_mask(crtc
);
2361 if (!(pll_in_use
& (1 << ATOM_PPLL2
)))
2363 if (!(pll_in_use
& (1 << ATOM_PPLL1
)))
2365 DRM_ERROR("unable to allocate a PPLL\n");
2366 return ATOM_PPLL_INVALID
;
2368 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2369 pll_in_use
= amdgpu_pll_get_use_mask(crtc
);
2370 if (!(pll_in_use
& (1 << ATOM_PPLL2
)))
2372 if (!(pll_in_use
& (1 << ATOM_PPLL1
)))
2374 if (!(pll_in_use
& (1 << ATOM_PPLL0
)))
2376 DRM_ERROR("unable to allocate a PPLL\n");
2377 return ATOM_PPLL_INVALID
;
2379 return ATOM_PPLL_INVALID
;
2382 static void dce_v8_0_lock_cursor(struct drm_crtc
*crtc
, bool lock
)
2384 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2385 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2388 cur_lock
= RREG32(mmCUR_UPDATE
+ amdgpu_crtc
->crtc_offset
);
2390 cur_lock
|= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK
;
2392 cur_lock
&= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK
;
2393 WREG32(mmCUR_UPDATE
+ amdgpu_crtc
->crtc_offset
, cur_lock
);
2396 static void dce_v8_0_hide_cursor(struct drm_crtc
*crtc
)
2398 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2399 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2401 WREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2402 (CURSOR_24_8_PRE_MULT
<< CUR_CONTROL__CURSOR_MODE__SHIFT
) |
2403 (CURSOR_URGENT_1_2
<< CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT
));
2406 static void dce_v8_0_show_cursor(struct drm_crtc
*crtc
)
2408 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2409 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2411 WREG32(mmCUR_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2412 upper_32_bits(amdgpu_crtc
->cursor_addr
));
2413 WREG32(mmCUR_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2414 lower_32_bits(amdgpu_crtc
->cursor_addr
));
2416 WREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2417 CUR_CONTROL__CURSOR_EN_MASK
|
2418 (CURSOR_24_8_PRE_MULT
<< CUR_CONTROL__CURSOR_MODE__SHIFT
) |
2419 (CURSOR_URGENT_1_2
<< CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT
));
2422 static int dce_v8_0_cursor_move_locked(struct drm_crtc
*crtc
,
2425 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2426 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2427 int xorigin
= 0, yorigin
= 0;
2429 /* avivo cursor are offset into the total surface */
2432 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x
, y
, crtc
->x
, crtc
->y
);
2435 xorigin
= min(-x
, amdgpu_crtc
->max_cursor_width
- 1);
2439 yorigin
= min(-y
, amdgpu_crtc
->max_cursor_height
- 1);
2443 WREG32(mmCUR_POSITION
+ amdgpu_crtc
->crtc_offset
, (x
<< 16) | y
);
2444 WREG32(mmCUR_HOT_SPOT
+ amdgpu_crtc
->crtc_offset
, (xorigin
<< 16) | yorigin
);
2445 WREG32(mmCUR_SIZE
+ amdgpu_crtc
->crtc_offset
,
2446 ((amdgpu_crtc
->cursor_width
- 1) << 16) | (amdgpu_crtc
->cursor_height
- 1));
2448 amdgpu_crtc
->cursor_x
= x
;
2449 amdgpu_crtc
->cursor_y
= y
;
2454 static int dce_v8_0_crtc_cursor_move(struct drm_crtc
*crtc
,
2459 dce_v8_0_lock_cursor(crtc
, true);
2460 ret
= dce_v8_0_cursor_move_locked(crtc
, x
, y
);
2461 dce_v8_0_lock_cursor(crtc
, false);
2466 static int dce_v8_0_crtc_cursor_set2(struct drm_crtc
*crtc
,
2467 struct drm_file
*file_priv
,
2474 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2475 struct drm_gem_object
*obj
;
2476 struct amdgpu_bo
*aobj
;
2480 /* turn off cursor */
2481 dce_v8_0_hide_cursor(crtc
);
2486 if ((width
> amdgpu_crtc
->max_cursor_width
) ||
2487 (height
> amdgpu_crtc
->max_cursor_height
)) {
2488 DRM_ERROR("bad cursor width or height %d x %d\n", width
, height
);
2492 obj
= drm_gem_object_lookup(crtc
->dev
, file_priv
, handle
);
2494 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle
, amdgpu_crtc
->crtc_id
);
2498 aobj
= gem_to_amdgpu_bo(obj
);
2499 ret
= amdgpu_bo_reserve(aobj
, false);
2501 drm_gem_object_unreference_unlocked(obj
);
2505 ret
= amdgpu_bo_pin(aobj
, AMDGPU_GEM_DOMAIN_VRAM
, &amdgpu_crtc
->cursor_addr
);
2506 amdgpu_bo_unreserve(aobj
);
2508 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret
);
2509 drm_gem_object_unreference_unlocked(obj
);
2513 amdgpu_crtc
->cursor_width
= width
;
2514 amdgpu_crtc
->cursor_height
= height
;
2516 dce_v8_0_lock_cursor(crtc
, true);
2518 if (hot_x
!= amdgpu_crtc
->cursor_hot_x
||
2519 hot_y
!= amdgpu_crtc
->cursor_hot_y
) {
2522 x
= amdgpu_crtc
->cursor_x
+ amdgpu_crtc
->cursor_hot_x
- hot_x
;
2523 y
= amdgpu_crtc
->cursor_y
+ amdgpu_crtc
->cursor_hot_y
- hot_y
;
2525 dce_v8_0_cursor_move_locked(crtc
, x
, y
);
2527 amdgpu_crtc
->cursor_hot_x
= hot_x
;
2528 amdgpu_crtc
->cursor_hot_y
= hot_y
;
2531 dce_v8_0_show_cursor(crtc
);
2532 dce_v8_0_lock_cursor(crtc
, false);
2535 if (amdgpu_crtc
->cursor_bo
) {
2536 struct amdgpu_bo
*aobj
= gem_to_amdgpu_bo(amdgpu_crtc
->cursor_bo
);
2537 ret
= amdgpu_bo_reserve(aobj
, false);
2538 if (likely(ret
== 0)) {
2539 amdgpu_bo_unpin(aobj
);
2540 amdgpu_bo_unreserve(aobj
);
2542 drm_gem_object_unreference_unlocked(amdgpu_crtc
->cursor_bo
);
2545 amdgpu_crtc
->cursor_bo
= obj
;
2549 static void dce_v8_0_cursor_reset(struct drm_crtc
*crtc
)
2551 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2553 if (amdgpu_crtc
->cursor_bo
) {
2554 dce_v8_0_lock_cursor(crtc
, true);
2556 dce_v8_0_cursor_move_locked(crtc
, amdgpu_crtc
->cursor_x
,
2557 amdgpu_crtc
->cursor_y
);
2559 dce_v8_0_show_cursor(crtc
);
2561 dce_v8_0_lock_cursor(crtc
, false);
2565 static void dce_v8_0_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
2566 u16
*blue
, uint32_t start
, uint32_t size
)
2568 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2569 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
2571 /* userspace palettes are always correct as is */
2572 for (i
= start
; i
< end
; i
++) {
2573 amdgpu_crtc
->lut_r
[i
] = red
[i
] >> 6;
2574 amdgpu_crtc
->lut_g
[i
] = green
[i
] >> 6;
2575 amdgpu_crtc
->lut_b
[i
] = blue
[i
] >> 6;
2577 dce_v8_0_crtc_load_lut(crtc
);
2580 static void dce_v8_0_crtc_destroy(struct drm_crtc
*crtc
)
2582 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2584 drm_crtc_cleanup(crtc
);
2585 destroy_workqueue(amdgpu_crtc
->pflip_queue
);
2589 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs
= {
2590 .cursor_set2
= dce_v8_0_crtc_cursor_set2
,
2591 .cursor_move
= dce_v8_0_crtc_cursor_move
,
2592 .gamma_set
= dce_v8_0_crtc_gamma_set
,
2593 .set_config
= amdgpu_crtc_set_config
,
2594 .destroy
= dce_v8_0_crtc_destroy
,
2595 .page_flip
= amdgpu_crtc_page_flip
,
2598 static void dce_v8_0_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2600 struct drm_device
*dev
= crtc
->dev
;
2601 struct amdgpu_device
*adev
= dev
->dev_private
;
2602 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2606 case DRM_MODE_DPMS_ON
:
2607 amdgpu_crtc
->enabled
= true;
2608 amdgpu_atombios_crtc_enable(crtc
, ATOM_ENABLE
);
2609 dce_v8_0_vga_enable(crtc
, true);
2610 amdgpu_atombios_crtc_blank(crtc
, ATOM_DISABLE
);
2611 dce_v8_0_vga_enable(crtc
, false);
2612 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2613 type
= amdgpu_crtc_idx_to_irq_type(adev
, amdgpu_crtc
->crtc_id
);
2614 amdgpu_irq_update(adev
, &adev
->crtc_irq
, type
);
2615 amdgpu_irq_update(adev
, &adev
->pageflip_irq
, type
);
2616 drm_vblank_post_modeset(dev
, amdgpu_crtc
->crtc_id
);
2617 dce_v8_0_crtc_load_lut(crtc
);
2619 case DRM_MODE_DPMS_STANDBY
:
2620 case DRM_MODE_DPMS_SUSPEND
:
2621 case DRM_MODE_DPMS_OFF
:
2622 drm_vblank_pre_modeset(dev
, amdgpu_crtc
->crtc_id
);
2623 if (amdgpu_crtc
->enabled
) {
2624 dce_v8_0_vga_enable(crtc
, true);
2625 amdgpu_atombios_crtc_blank(crtc
, ATOM_ENABLE
);
2626 dce_v8_0_vga_enable(crtc
, false);
2628 amdgpu_atombios_crtc_enable(crtc
, ATOM_DISABLE
);
2629 amdgpu_crtc
->enabled
= false;
2632 /* adjust pm to dpms */
2633 amdgpu_pm_compute_clocks(adev
);
2636 static void dce_v8_0_crtc_prepare(struct drm_crtc
*crtc
)
2638 /* disable crtc pair power gating before programming */
2639 amdgpu_atombios_crtc_powergate(crtc
, ATOM_DISABLE
);
2640 amdgpu_atombios_crtc_lock(crtc
, ATOM_ENABLE
);
2641 dce_v8_0_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
2644 static void dce_v8_0_crtc_commit(struct drm_crtc
*crtc
)
2646 dce_v8_0_crtc_dpms(crtc
, DRM_MODE_DPMS_ON
);
2647 amdgpu_atombios_crtc_lock(crtc
, ATOM_DISABLE
);
2650 static void dce_v8_0_crtc_disable(struct drm_crtc
*crtc
)
2652 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2653 struct drm_device
*dev
= crtc
->dev
;
2654 struct amdgpu_device
*adev
= dev
->dev_private
;
2655 struct amdgpu_atom_ss ss
;
2658 dce_v8_0_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
2659 if (crtc
->primary
->fb
) {
2661 struct amdgpu_framebuffer
*amdgpu_fb
;
2662 struct amdgpu_bo
*rbo
;
2664 amdgpu_fb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
2665 rbo
= gem_to_amdgpu_bo(amdgpu_fb
->obj
);
2666 r
= amdgpu_bo_reserve(rbo
, false);
2668 DRM_ERROR("failed to reserve rbo before unpin\n");
2670 amdgpu_bo_unpin(rbo
);
2671 amdgpu_bo_unreserve(rbo
);
2674 /* disable the GRPH */
2675 dce_v8_0_grph_enable(crtc
, false);
2677 amdgpu_atombios_crtc_powergate(crtc
, ATOM_ENABLE
);
2679 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2680 if (adev
->mode_info
.crtcs
[i
] &&
2681 adev
->mode_info
.crtcs
[i
]->enabled
&&
2682 i
!= amdgpu_crtc
->crtc_id
&&
2683 amdgpu_crtc
->pll_id
== adev
->mode_info
.crtcs
[i
]->pll_id
) {
2684 /* one other crtc is using this pll don't turn
2691 switch (amdgpu_crtc
->pll_id
) {
2694 /* disable the ppll */
2695 amdgpu_atombios_crtc_program_pll(crtc
, amdgpu_crtc
->crtc_id
, amdgpu_crtc
->pll_id
,
2696 0, 0, ATOM_DISABLE
, 0, 0, 0, 0, 0, false, &ss
);
2699 /* disable the ppll */
2700 if ((adev
->asic_type
== CHIP_KAVERI
) ||
2701 (adev
->asic_type
== CHIP_BONAIRE
) ||
2702 (adev
->asic_type
== CHIP_HAWAII
))
2703 amdgpu_atombios_crtc_program_pll(crtc
, amdgpu_crtc
->crtc_id
, amdgpu_crtc
->pll_id
,
2704 0, 0, ATOM_DISABLE
, 0, 0, 0, 0, 0, false, &ss
);
2710 amdgpu_crtc
->pll_id
= ATOM_PPLL_INVALID
;
2711 amdgpu_crtc
->adjusted_clock
= 0;
2712 amdgpu_crtc
->encoder
= NULL
;
2713 amdgpu_crtc
->connector
= NULL
;
2716 static int dce_v8_0_crtc_mode_set(struct drm_crtc
*crtc
,
2717 struct drm_display_mode
*mode
,
2718 struct drm_display_mode
*adjusted_mode
,
2719 int x
, int y
, struct drm_framebuffer
*old_fb
)
2721 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2723 if (!amdgpu_crtc
->adjusted_clock
)
2726 amdgpu_atombios_crtc_set_pll(crtc
, adjusted_mode
);
2727 amdgpu_atombios_crtc_set_dtd_timing(crtc
, adjusted_mode
);
2728 dce_v8_0_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
2729 amdgpu_atombios_crtc_overscan_setup(crtc
, mode
, adjusted_mode
);
2730 amdgpu_atombios_crtc_scaler_setup(crtc
);
2731 dce_v8_0_cursor_reset(crtc
);
2732 /* update the hw version fpr dpm */
2733 amdgpu_crtc
->hw_mode
= *adjusted_mode
;
2738 static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc
*crtc
,
2739 const struct drm_display_mode
*mode
,
2740 struct drm_display_mode
*adjusted_mode
)
2742 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2743 struct drm_device
*dev
= crtc
->dev
;
2744 struct drm_encoder
*encoder
;
2746 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2747 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2748 if (encoder
->crtc
== crtc
) {
2749 amdgpu_crtc
->encoder
= encoder
;
2750 amdgpu_crtc
->connector
= amdgpu_get_connector_for_encoder(encoder
);
2754 if ((amdgpu_crtc
->encoder
== NULL
) || (amdgpu_crtc
->connector
== NULL
)) {
2755 amdgpu_crtc
->encoder
= NULL
;
2756 amdgpu_crtc
->connector
= NULL
;
2759 if (!amdgpu_crtc_scaling_mode_fixup(crtc
, mode
, adjusted_mode
))
2761 if (amdgpu_atombios_crtc_prepare_pll(crtc
, adjusted_mode
))
2764 amdgpu_crtc
->pll_id
= dce_v8_0_pick_pll(crtc
);
2765 /* if we can't get a PPLL for a non-DP encoder, fail */
2766 if ((amdgpu_crtc
->pll_id
== ATOM_PPLL_INVALID
) &&
2767 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
)))
2773 static int dce_v8_0_crtc_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2774 struct drm_framebuffer
*old_fb
)
2776 return dce_v8_0_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
2779 static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc
*crtc
,
2780 struct drm_framebuffer
*fb
,
2781 int x
, int y
, enum mode_set_atomic state
)
2783 return dce_v8_0_crtc_do_set_base(crtc
, fb
, x
, y
, 1);
2786 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs
= {
2787 .dpms
= dce_v8_0_crtc_dpms
,
2788 .mode_fixup
= dce_v8_0_crtc_mode_fixup
,
2789 .mode_set
= dce_v8_0_crtc_mode_set
,
2790 .mode_set_base
= dce_v8_0_crtc_set_base
,
2791 .mode_set_base_atomic
= dce_v8_0_crtc_set_base_atomic
,
2792 .prepare
= dce_v8_0_crtc_prepare
,
2793 .commit
= dce_v8_0_crtc_commit
,
2794 .load_lut
= dce_v8_0_crtc_load_lut
,
2795 .disable
= dce_v8_0_crtc_disable
,
2798 static int dce_v8_0_crtc_init(struct amdgpu_device
*adev
, int index
)
2800 struct amdgpu_crtc
*amdgpu_crtc
;
2803 amdgpu_crtc
= kzalloc(sizeof(struct amdgpu_crtc
) +
2804 (AMDGPUFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
2805 if (amdgpu_crtc
== NULL
)
2808 drm_crtc_init(adev
->ddev
, &amdgpu_crtc
->base
, &dce_v8_0_crtc_funcs
);
2810 drm_mode_crtc_set_gamma_size(&amdgpu_crtc
->base
, 256);
2811 amdgpu_crtc
->crtc_id
= index
;
2812 amdgpu_crtc
->pflip_queue
= create_singlethread_workqueue("amdgpu-pageflip-queue");
2813 adev
->mode_info
.crtcs
[index
] = amdgpu_crtc
;
2815 amdgpu_crtc
->max_cursor_width
= CIK_CURSOR_WIDTH
;
2816 amdgpu_crtc
->max_cursor_height
= CIK_CURSOR_HEIGHT
;
2817 adev
->ddev
->mode_config
.cursor_width
= amdgpu_crtc
->max_cursor_width
;
2818 adev
->ddev
->mode_config
.cursor_height
= amdgpu_crtc
->max_cursor_height
;
2820 for (i
= 0; i
< 256; i
++) {
2821 amdgpu_crtc
->lut_r
[i
] = i
<< 2;
2822 amdgpu_crtc
->lut_g
[i
] = i
<< 2;
2823 amdgpu_crtc
->lut_b
[i
] = i
<< 2;
2826 amdgpu_crtc
->crtc_offset
= crtc_offsets
[amdgpu_crtc
->crtc_id
];
2828 amdgpu_crtc
->pll_id
= ATOM_PPLL_INVALID
;
2829 amdgpu_crtc
->adjusted_clock
= 0;
2830 amdgpu_crtc
->encoder
= NULL
;
2831 amdgpu_crtc
->connector
= NULL
;
2832 drm_crtc_helper_add(&amdgpu_crtc
->base
, &dce_v8_0_crtc_helper_funcs
);
2837 static int dce_v8_0_early_init(void *handle
)
2839 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2841 adev
->audio_endpt_rreg
= &dce_v8_0_audio_endpt_rreg
;
2842 adev
->audio_endpt_wreg
= &dce_v8_0_audio_endpt_wreg
;
2844 dce_v8_0_set_display_funcs(adev
);
2845 dce_v8_0_set_irq_funcs(adev
);
2847 switch (adev
->asic_type
) {
2850 adev
->mode_info
.num_crtc
= 6;
2851 adev
->mode_info
.num_hpd
= 6;
2852 adev
->mode_info
.num_dig
= 6;
2855 adev
->mode_info
.num_crtc
= 4;
2856 adev
->mode_info
.num_hpd
= 6;
2857 adev
->mode_info
.num_dig
= 7;
2861 adev
->mode_info
.num_crtc
= 2;
2862 adev
->mode_info
.num_hpd
= 6;
2863 adev
->mode_info
.num_dig
= 6; /* ? */
2866 /* FIXME: not supported yet */
2873 static int dce_v8_0_sw_init(void *handle
)
2876 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2878 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2879 r
= amdgpu_irq_add_id(adev
, i
+ 1, &adev
->crtc_irq
);
2884 for (i
= 8; i
< 20; i
+= 2) {
2885 r
= amdgpu_irq_add_id(adev
, i
, &adev
->pageflip_irq
);
2891 r
= amdgpu_irq_add_id(adev
, 42, &adev
->hpd_irq
);
2895 adev
->mode_info
.mode_config_initialized
= true;
2897 adev
->ddev
->mode_config
.funcs
= &amdgpu_mode_funcs
;
2899 adev
->ddev
->mode_config
.max_width
= 16384;
2900 adev
->ddev
->mode_config
.max_height
= 16384;
2902 adev
->ddev
->mode_config
.preferred_depth
= 24;
2903 adev
->ddev
->mode_config
.prefer_shadow
= 1;
2905 adev
->ddev
->mode_config
.fb_base
= adev
->mc
.aper_base
;
2907 r
= amdgpu_modeset_create_props(adev
);
2911 adev
->ddev
->mode_config
.max_width
= 16384;
2912 adev
->ddev
->mode_config
.max_height
= 16384;
2914 /* allocate crtcs */
2915 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2916 r
= dce_v8_0_crtc_init(adev
, i
);
2921 if (amdgpu_atombios_get_connector_info_from_object_table(adev
))
2922 amdgpu_print_display_setup(adev
->ddev
);
2927 dce_v8_0_afmt_init(adev
);
2929 r
= dce_v8_0_audio_init(adev
);
2933 drm_kms_helper_poll_init(adev
->ddev
);
2938 static int dce_v8_0_sw_fini(void *handle
)
2940 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2942 kfree(adev
->mode_info
.bios_hardcoded_edid
);
2944 drm_kms_helper_poll_fini(adev
->ddev
);
2946 dce_v8_0_audio_fini(adev
);
2948 dce_v8_0_afmt_fini(adev
);
2950 drm_mode_config_cleanup(adev
->ddev
);
2951 adev
->mode_info
.mode_config_initialized
= false;
2956 static int dce_v8_0_hw_init(void *handle
)
2959 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2961 /* init dig PHYs, disp eng pll */
2962 amdgpu_atombios_encoder_init_dig(adev
);
2963 amdgpu_atombios_crtc_set_disp_eng_pll(adev
, adev
->clock
.default_dispclk
);
2965 /* initialize hpd */
2966 dce_v8_0_hpd_init(adev
);
2968 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
2969 dce_v8_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
2972 dce_v8_0_pageflip_interrupt_init(adev
);
2977 static int dce_v8_0_hw_fini(void *handle
)
2980 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2982 dce_v8_0_hpd_fini(adev
);
2984 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
2985 dce_v8_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
2988 dce_v8_0_pageflip_interrupt_fini(adev
);
2993 static int dce_v8_0_suspend(void *handle
)
2995 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2997 amdgpu_atombios_scratch_regs_save(adev
);
2999 return dce_v8_0_hw_fini(handle
);
3002 static int dce_v8_0_resume(void *handle
)
3004 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3007 ret
= dce_v8_0_hw_init(handle
);
3009 amdgpu_atombios_scratch_regs_restore(adev
);
3011 /* turn on the BL */
3012 if (adev
->mode_info
.bl_encoder
) {
3013 u8 bl_level
= amdgpu_display_backlight_get_level(adev
,
3014 adev
->mode_info
.bl_encoder
);
3015 amdgpu_display_backlight_set_level(adev
, adev
->mode_info
.bl_encoder
,
3022 static bool dce_v8_0_is_idle(void *handle
)
3027 static int dce_v8_0_wait_for_idle(void *handle
)
3032 static void dce_v8_0_print_status(void *handle
)
3034 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3036 dev_info(adev
->dev
, "DCE 8.x registers\n");
3040 static int dce_v8_0_soft_reset(void *handle
)
3042 u32 srbm_soft_reset
= 0, tmp
;
3043 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3045 if (dce_v8_0_is_display_hung(adev
))
3046 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK
;
3048 if (srbm_soft_reset
) {
3049 dce_v8_0_print_status((void *)adev
);
3051 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3052 tmp
|= srbm_soft_reset
;
3053 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
3054 WREG32(mmSRBM_SOFT_RESET
, tmp
);
3055 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3059 tmp
&= ~srbm_soft_reset
;
3060 WREG32(mmSRBM_SOFT_RESET
, tmp
);
3061 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3063 /* Wait a little for things to settle down */
3065 dce_v8_0_print_status((void *)adev
);
3070 static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device
*adev
,
3072 enum amdgpu_interrupt_state state
)
3074 u32 reg_block
, lb_interrupt_mask
;
3076 if (crtc
>= adev
->mode_info
.num_crtc
) {
3077 DRM_DEBUG("invalid crtc %d\n", crtc
);
3083 reg_block
= CRTC0_REGISTER_OFFSET
;
3086 reg_block
= CRTC1_REGISTER_OFFSET
;
3089 reg_block
= CRTC2_REGISTER_OFFSET
;
3092 reg_block
= CRTC3_REGISTER_OFFSET
;
3095 reg_block
= CRTC4_REGISTER_OFFSET
;
3098 reg_block
= CRTC5_REGISTER_OFFSET
;
3101 DRM_DEBUG("invalid crtc %d\n", crtc
);
3106 case AMDGPU_IRQ_STATE_DISABLE
:
3107 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ reg_block
);
3108 lb_interrupt_mask
&= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK
;
3109 WREG32(mmLB_INTERRUPT_MASK
+ reg_block
, lb_interrupt_mask
);
3111 case AMDGPU_IRQ_STATE_ENABLE
:
3112 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ reg_block
);
3113 lb_interrupt_mask
|= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK
;
3114 WREG32(mmLB_INTERRUPT_MASK
+ reg_block
, lb_interrupt_mask
);
3121 static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device
*adev
,
3123 enum amdgpu_interrupt_state state
)
3125 u32 reg_block
, lb_interrupt_mask
;
3127 if (crtc
>= adev
->mode_info
.num_crtc
) {
3128 DRM_DEBUG("invalid crtc %d\n", crtc
);
3134 reg_block
= CRTC0_REGISTER_OFFSET
;
3137 reg_block
= CRTC1_REGISTER_OFFSET
;
3140 reg_block
= CRTC2_REGISTER_OFFSET
;
3143 reg_block
= CRTC3_REGISTER_OFFSET
;
3146 reg_block
= CRTC4_REGISTER_OFFSET
;
3149 reg_block
= CRTC5_REGISTER_OFFSET
;
3152 DRM_DEBUG("invalid crtc %d\n", crtc
);
3157 case AMDGPU_IRQ_STATE_DISABLE
:
3158 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ reg_block
);
3159 lb_interrupt_mask
&= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK
;
3160 WREG32(mmLB_INTERRUPT_MASK
+ reg_block
, lb_interrupt_mask
);
3162 case AMDGPU_IRQ_STATE_ENABLE
:
3163 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ reg_block
);
3164 lb_interrupt_mask
|= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK
;
3165 WREG32(mmLB_INTERRUPT_MASK
+ reg_block
, lb_interrupt_mask
);
3172 static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device
*adev
,
3173 struct amdgpu_irq_src
*src
,
3175 enum amdgpu_interrupt_state state
)
3177 u32 dc_hpd_int_cntl_reg
, dc_hpd_int_cntl
;
3181 dc_hpd_int_cntl_reg
= mmDC_HPD1_INT_CONTROL
;
3184 dc_hpd_int_cntl_reg
= mmDC_HPD2_INT_CONTROL
;
3187 dc_hpd_int_cntl_reg
= mmDC_HPD3_INT_CONTROL
;
3190 dc_hpd_int_cntl_reg
= mmDC_HPD4_INT_CONTROL
;
3193 dc_hpd_int_cntl_reg
= mmDC_HPD5_INT_CONTROL
;
3196 dc_hpd_int_cntl_reg
= mmDC_HPD6_INT_CONTROL
;
3199 DRM_DEBUG("invalid hdp %d\n", type
);
3204 case AMDGPU_IRQ_STATE_DISABLE
:
3205 dc_hpd_int_cntl
= RREG32(dc_hpd_int_cntl_reg
);
3206 dc_hpd_int_cntl
&= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK
;
3207 WREG32(dc_hpd_int_cntl_reg
, dc_hpd_int_cntl
);
3209 case AMDGPU_IRQ_STATE_ENABLE
:
3210 dc_hpd_int_cntl
= RREG32(dc_hpd_int_cntl_reg
);
3211 dc_hpd_int_cntl
|= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK
;
3212 WREG32(dc_hpd_int_cntl_reg
, dc_hpd_int_cntl
);
3221 static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device
*adev
,
3222 struct amdgpu_irq_src
*src
,
3224 enum amdgpu_interrupt_state state
)
3227 case AMDGPU_CRTC_IRQ_VBLANK1
:
3228 dce_v8_0_set_crtc_vblank_interrupt_state(adev
, 0, state
);
3230 case AMDGPU_CRTC_IRQ_VBLANK2
:
3231 dce_v8_0_set_crtc_vblank_interrupt_state(adev
, 1, state
);
3233 case AMDGPU_CRTC_IRQ_VBLANK3
:
3234 dce_v8_0_set_crtc_vblank_interrupt_state(adev
, 2, state
);
3236 case AMDGPU_CRTC_IRQ_VBLANK4
:
3237 dce_v8_0_set_crtc_vblank_interrupt_state(adev
, 3, state
);
3239 case AMDGPU_CRTC_IRQ_VBLANK5
:
3240 dce_v8_0_set_crtc_vblank_interrupt_state(adev
, 4, state
);
3242 case AMDGPU_CRTC_IRQ_VBLANK6
:
3243 dce_v8_0_set_crtc_vblank_interrupt_state(adev
, 5, state
);
3245 case AMDGPU_CRTC_IRQ_VLINE1
:
3246 dce_v8_0_set_crtc_vline_interrupt_state(adev
, 0, state
);
3248 case AMDGPU_CRTC_IRQ_VLINE2
:
3249 dce_v8_0_set_crtc_vline_interrupt_state(adev
, 1, state
);
3251 case AMDGPU_CRTC_IRQ_VLINE3
:
3252 dce_v8_0_set_crtc_vline_interrupt_state(adev
, 2, state
);
3254 case AMDGPU_CRTC_IRQ_VLINE4
:
3255 dce_v8_0_set_crtc_vline_interrupt_state(adev
, 3, state
);
3257 case AMDGPU_CRTC_IRQ_VLINE5
:
3258 dce_v8_0_set_crtc_vline_interrupt_state(adev
, 4, state
);
3260 case AMDGPU_CRTC_IRQ_VLINE6
:
3261 dce_v8_0_set_crtc_vline_interrupt_state(adev
, 5, state
);
3269 static int dce_v8_0_crtc_irq(struct amdgpu_device
*adev
,
3270 struct amdgpu_irq_src
*source
,
3271 struct amdgpu_iv_entry
*entry
)
3273 unsigned crtc
= entry
->src_id
- 1;
3274 uint32_t disp_int
= RREG32(interrupt_status_offsets
[crtc
].reg
);
3275 unsigned irq_type
= amdgpu_crtc_idx_to_irq_type(adev
, crtc
);
3277 switch (entry
->src_data
) {
3278 case 0: /* vblank */
3279 if (disp_int
& interrupt_status_offsets
[crtc
].vblank
)
3280 WREG32(mmLB_VBLANK_STATUS
+ crtc_offsets
[crtc
], LB_VBLANK_STATUS__VBLANK_ACK_MASK
);
3282 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3284 if (amdgpu_irq_enabled(adev
, source
, irq_type
)) {
3285 drm_handle_vblank(adev
->ddev
, crtc
);
3287 DRM_DEBUG("IH: D%d vblank\n", crtc
+ 1);
3291 if (disp_int
& interrupt_status_offsets
[crtc
].vline
)
3292 WREG32(mmLB_VLINE_STATUS
+ crtc_offsets
[crtc
], LB_VLINE_STATUS__VLINE_ACK_MASK
);
3294 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3296 DRM_DEBUG("IH: D%d vline\n", crtc
+ 1);
3300 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry
->src_id
, entry
->src_data
);
3307 static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device
*adev
,
3308 struct amdgpu_irq_src
*src
,
3310 enum amdgpu_interrupt_state state
)
3314 if (type
>= adev
->mode_info
.num_crtc
) {
3315 DRM_ERROR("invalid pageflip crtc %d\n", type
);
3319 reg
= RREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
]);
3320 if (state
== AMDGPU_IRQ_STATE_DISABLE
)
3321 WREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
],
3322 reg
& ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
);
3324 WREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
],
3325 reg
| GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
);
3330 static int dce_v8_0_pageflip_irq(struct amdgpu_device
*adev
,
3331 struct amdgpu_irq_src
*source
,
3332 struct amdgpu_iv_entry
*entry
)
3334 unsigned long flags
;
3336 struct amdgpu_crtc
*amdgpu_crtc
;
3337 struct amdgpu_flip_work
*works
;
3339 crtc_id
= (entry
->src_id
- 8) >> 1;
3340 amdgpu_crtc
= adev
->mode_info
.crtcs
[crtc_id
];
3342 if (crtc_id
>= adev
->mode_info
.num_crtc
) {
3343 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id
);
3347 if (RREG32(mmGRPH_INTERRUPT_STATUS
+ crtc_offsets
[crtc_id
]) &
3348 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
)
3349 WREG32(mmGRPH_INTERRUPT_STATUS
+ crtc_offsets
[crtc_id
],
3350 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
);
3352 /* IRQ could occur when in initial stage */
3353 if (amdgpu_crtc
== NULL
)
3356 spin_lock_irqsave(&adev
->ddev
->event_lock
, flags
);
3357 works
= amdgpu_crtc
->pflip_works
;
3358 if (amdgpu_crtc
->pflip_status
!= AMDGPU_FLIP_SUBMITTED
){
3359 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3360 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3361 amdgpu_crtc
->pflip_status
,
3362 AMDGPU_FLIP_SUBMITTED
);
3363 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
3367 /* page flip completed. clean up */
3368 amdgpu_crtc
->pflip_status
= AMDGPU_FLIP_NONE
;
3369 amdgpu_crtc
->pflip_works
= NULL
;
3371 /* wakeup usersapce */
3373 drm_send_vblank_event(adev
->ddev
, crtc_id
, works
->event
);
3375 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
3377 drm_vblank_put(adev
->ddev
, amdgpu_crtc
->crtc_id
);
3378 queue_work(amdgpu_crtc
->pflip_queue
, &works
->unpin_work
);
3383 static int dce_v8_0_hpd_irq(struct amdgpu_device
*adev
,
3384 struct amdgpu_irq_src
*source
,
3385 struct amdgpu_iv_entry
*entry
)
3387 uint32_t disp_int
, mask
, int_control
, tmp
;
3390 if (entry
->src_data
>= adev
->mode_info
.num_hpd
) {
3391 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry
->src_id
, entry
->src_data
);
3395 hpd
= entry
->src_data
;
3396 disp_int
= RREG32(interrupt_status_offsets
[hpd
].reg
);
3397 mask
= interrupt_status_offsets
[hpd
].hpd
;
3398 int_control
= hpd_int_control_offsets
[hpd
];
3400 if (disp_int
& mask
) {
3401 tmp
= RREG32(int_control
);
3402 tmp
|= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK
;
3403 WREG32(int_control
, tmp
);
3404 schedule_work(&adev
->hotplug_work
);
3405 DRM_DEBUG("IH: HPD%d\n", hpd
+ 1);
3412 static int dce_v8_0_set_clockgating_state(void *handle
,
3413 enum amd_clockgating_state state
)
3418 static int dce_v8_0_set_powergating_state(void *handle
,
3419 enum amd_powergating_state state
)
3424 const struct amd_ip_funcs dce_v8_0_ip_funcs
= {
3425 .early_init
= dce_v8_0_early_init
,
3427 .sw_init
= dce_v8_0_sw_init
,
3428 .sw_fini
= dce_v8_0_sw_fini
,
3429 .hw_init
= dce_v8_0_hw_init
,
3430 .hw_fini
= dce_v8_0_hw_fini
,
3431 .suspend
= dce_v8_0_suspend
,
3432 .resume
= dce_v8_0_resume
,
3433 .is_idle
= dce_v8_0_is_idle
,
3434 .wait_for_idle
= dce_v8_0_wait_for_idle
,
3435 .soft_reset
= dce_v8_0_soft_reset
,
3436 .print_status
= dce_v8_0_print_status
,
3437 .set_clockgating_state
= dce_v8_0_set_clockgating_state
,
3438 .set_powergating_state
= dce_v8_0_set_powergating_state
,
3442 dce_v8_0_encoder_mode_set(struct drm_encoder
*encoder
,
3443 struct drm_display_mode
*mode
,
3444 struct drm_display_mode
*adjusted_mode
)
3446 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3448 amdgpu_encoder
->pixel_clock
= adjusted_mode
->clock
;
3450 /* need to call this here rather than in prepare() since we need some crtc info */
3451 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
3453 /* set scaler clears this on some chips */
3454 dce_v8_0_set_interleave(encoder
->crtc
, mode
);
3456 if (amdgpu_atombios_encoder_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
) {
3457 dce_v8_0_afmt_enable(encoder
, true);
3458 dce_v8_0_afmt_setmode(encoder
, adjusted_mode
);
3462 static void dce_v8_0_encoder_prepare(struct drm_encoder
*encoder
)
3464 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
3465 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3466 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
3468 if ((amdgpu_encoder
->active_device
&
3469 (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
3470 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) !=
3471 ENCODER_OBJECT_ID_NONE
)) {
3472 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
3474 dig
->dig_encoder
= dce_v8_0_pick_dig_encoder(encoder
);
3475 if (amdgpu_encoder
->active_device
& ATOM_DEVICE_DFP_SUPPORT
)
3476 dig
->afmt
= adev
->mode_info
.afmt
[dig
->dig_encoder
];
3480 amdgpu_atombios_scratch_regs_lock(adev
, true);
3483 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
3485 /* select the clock/data port if it uses a router */
3486 if (amdgpu_connector
->router
.cd_valid
)
3487 amdgpu_i2c_router_select_cd_port(amdgpu_connector
);
3489 /* turn eDP panel on for mode set */
3490 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3491 amdgpu_atombios_encoder_set_edp_panel_power(connector
,
3492 ATOM_TRANSMITTER_ACTION_POWER_ON
);
3495 /* this is needed for the pll/ss setup to work correctly in some cases */
3496 amdgpu_atombios_encoder_set_crtc_source(encoder
);
3497 /* set up the FMT blocks */
3498 dce_v8_0_program_fmt(encoder
);
3501 static void dce_v8_0_encoder_commit(struct drm_encoder
*encoder
)
3503 struct drm_device
*dev
= encoder
->dev
;
3504 struct amdgpu_device
*adev
= dev
->dev_private
;
3506 /* need to call this here as we need the crtc set up */
3507 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_ON
);
3508 amdgpu_atombios_scratch_regs_lock(adev
, false);
3511 static void dce_v8_0_encoder_disable(struct drm_encoder
*encoder
)
3513 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3514 struct amdgpu_encoder_atom_dig
*dig
;
3516 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
3518 if (amdgpu_atombios_encoder_is_digital(encoder
)) {
3519 if (amdgpu_atombios_encoder_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
)
3520 dce_v8_0_afmt_enable(encoder
, false);
3521 dig
= amdgpu_encoder
->enc_priv
;
3522 dig
->dig_encoder
= -1;
3524 amdgpu_encoder
->active_device
= 0;
3527 /* these are handled by the primary encoders */
3528 static void dce_v8_0_ext_prepare(struct drm_encoder
*encoder
)
3533 static void dce_v8_0_ext_commit(struct drm_encoder
*encoder
)
3539 dce_v8_0_ext_mode_set(struct drm_encoder
*encoder
,
3540 struct drm_display_mode
*mode
,
3541 struct drm_display_mode
*adjusted_mode
)
3546 static void dce_v8_0_ext_disable(struct drm_encoder
*encoder
)
3552 dce_v8_0_ext_dpms(struct drm_encoder
*encoder
, int mode
)
3557 static bool dce_v8_0_ext_mode_fixup(struct drm_encoder
*encoder
,
3558 const struct drm_display_mode
*mode
,
3559 struct drm_display_mode
*adjusted_mode
)
3564 static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs
= {
3565 .dpms
= dce_v8_0_ext_dpms
,
3566 .mode_fixup
= dce_v8_0_ext_mode_fixup
,
3567 .prepare
= dce_v8_0_ext_prepare
,
3568 .mode_set
= dce_v8_0_ext_mode_set
,
3569 .commit
= dce_v8_0_ext_commit
,
3570 .disable
= dce_v8_0_ext_disable
,
3571 /* no detect for TMDS/LVDS yet */
3574 static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs
= {
3575 .dpms
= amdgpu_atombios_encoder_dpms
,
3576 .mode_fixup
= amdgpu_atombios_encoder_mode_fixup
,
3577 .prepare
= dce_v8_0_encoder_prepare
,
3578 .mode_set
= dce_v8_0_encoder_mode_set
,
3579 .commit
= dce_v8_0_encoder_commit
,
3580 .disable
= dce_v8_0_encoder_disable
,
3581 .detect
= amdgpu_atombios_encoder_dig_detect
,
3584 static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs
= {
3585 .dpms
= amdgpu_atombios_encoder_dpms
,
3586 .mode_fixup
= amdgpu_atombios_encoder_mode_fixup
,
3587 .prepare
= dce_v8_0_encoder_prepare
,
3588 .mode_set
= dce_v8_0_encoder_mode_set
,
3589 .commit
= dce_v8_0_encoder_commit
,
3590 .detect
= amdgpu_atombios_encoder_dac_detect
,
3593 static void dce_v8_0_encoder_destroy(struct drm_encoder
*encoder
)
3595 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3596 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
3597 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder
);
3598 kfree(amdgpu_encoder
->enc_priv
);
3599 drm_encoder_cleanup(encoder
);
3600 kfree(amdgpu_encoder
);
3603 static const struct drm_encoder_funcs dce_v8_0_encoder_funcs
= {
3604 .destroy
= dce_v8_0_encoder_destroy
,
3607 static void dce_v8_0_encoder_add(struct amdgpu_device
*adev
,
3608 uint32_t encoder_enum
,
3609 uint32_t supported_device
,
3612 struct drm_device
*dev
= adev
->ddev
;
3613 struct drm_encoder
*encoder
;
3614 struct amdgpu_encoder
*amdgpu_encoder
;
3616 /* see if we already added it */
3617 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3618 amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3619 if (amdgpu_encoder
->encoder_enum
== encoder_enum
) {
3620 amdgpu_encoder
->devices
|= supported_device
;
3627 amdgpu_encoder
= kzalloc(sizeof(struct amdgpu_encoder
), GFP_KERNEL
);
3628 if (!amdgpu_encoder
)
3631 encoder
= &amdgpu_encoder
->base
;
3632 switch (adev
->mode_info
.num_crtc
) {
3634 encoder
->possible_crtcs
= 0x1;
3638 encoder
->possible_crtcs
= 0x3;
3641 encoder
->possible_crtcs
= 0xf;
3644 encoder
->possible_crtcs
= 0x3f;
3648 amdgpu_encoder
->enc_priv
= NULL
;
3650 amdgpu_encoder
->encoder_enum
= encoder_enum
;
3651 amdgpu_encoder
->encoder_id
= (encoder_enum
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
3652 amdgpu_encoder
->devices
= supported_device
;
3653 amdgpu_encoder
->rmx_type
= RMX_OFF
;
3654 amdgpu_encoder
->underscan_type
= UNDERSCAN_OFF
;
3655 amdgpu_encoder
->is_ext_encoder
= false;
3656 amdgpu_encoder
->caps
= caps
;
3658 switch (amdgpu_encoder
->encoder_id
) {
3659 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
3660 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
3661 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3662 DRM_MODE_ENCODER_DAC
);
3663 drm_encoder_helper_add(encoder
, &dce_v8_0_dac_helper_funcs
);
3665 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
3666 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
3667 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
3668 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
3669 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
3670 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
3671 amdgpu_encoder
->rmx_type
= RMX_FULL
;
3672 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3673 DRM_MODE_ENCODER_LVDS
);
3674 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder
);
3675 } else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
3676 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3677 DRM_MODE_ENCODER_DAC
);
3678 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder
);
3680 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3681 DRM_MODE_ENCODER_TMDS
);
3682 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder
);
3684 drm_encoder_helper_add(encoder
, &dce_v8_0_dig_helper_funcs
);
3686 case ENCODER_OBJECT_ID_SI170B
:
3687 case ENCODER_OBJECT_ID_CH7303
:
3688 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA
:
3689 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB
:
3690 case ENCODER_OBJECT_ID_TITFP513
:
3691 case ENCODER_OBJECT_ID_VT1623
:
3692 case ENCODER_OBJECT_ID_HDMI_SI1930
:
3693 case ENCODER_OBJECT_ID_TRAVIS
:
3694 case ENCODER_OBJECT_ID_NUTMEG
:
3695 /* these are handled by the primary encoders */
3696 amdgpu_encoder
->is_ext_encoder
= true;
3697 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
3698 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3699 DRM_MODE_ENCODER_LVDS
);
3700 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
))
3701 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3702 DRM_MODE_ENCODER_DAC
);
3704 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3705 DRM_MODE_ENCODER_TMDS
);
3706 drm_encoder_helper_add(encoder
, &dce_v8_0_ext_helper_funcs
);
3711 static const struct amdgpu_display_funcs dce_v8_0_display_funcs
= {
3712 .set_vga_render_state
= &dce_v8_0_set_vga_render_state
,
3713 .bandwidth_update
= &dce_v8_0_bandwidth_update
,
3714 .vblank_get_counter
= &dce_v8_0_vblank_get_counter
,
3715 .vblank_wait
= &dce_v8_0_vblank_wait
,
3716 .is_display_hung
= &dce_v8_0_is_display_hung
,
3717 .backlight_set_level
= &amdgpu_atombios_encoder_set_backlight_level
,
3718 .backlight_get_level
= &amdgpu_atombios_encoder_get_backlight_level
,
3719 .hpd_sense
= &dce_v8_0_hpd_sense
,
3720 .hpd_set_polarity
= &dce_v8_0_hpd_set_polarity
,
3721 .hpd_get_gpio_reg
= &dce_v8_0_hpd_get_gpio_reg
,
3722 .page_flip
= &dce_v8_0_page_flip
,
3723 .page_flip_get_scanoutpos
= &dce_v8_0_crtc_get_scanoutpos
,
3724 .add_encoder
= &dce_v8_0_encoder_add
,
3725 .add_connector
= &amdgpu_connector_add
,
3726 .stop_mc_access
= &dce_v8_0_stop_mc_access
,
3727 .resume_mc_access
= &dce_v8_0_resume_mc_access
,
3730 static void dce_v8_0_set_display_funcs(struct amdgpu_device
*adev
)
3732 if (adev
->mode_info
.funcs
== NULL
)
3733 adev
->mode_info
.funcs
= &dce_v8_0_display_funcs
;
3736 static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs
= {
3737 .set
= dce_v8_0_set_crtc_interrupt_state
,
3738 .process
= dce_v8_0_crtc_irq
,
3741 static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs
= {
3742 .set
= dce_v8_0_set_pageflip_interrupt_state
,
3743 .process
= dce_v8_0_pageflip_irq
,
3746 static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs
= {
3747 .set
= dce_v8_0_set_hpd_interrupt_state
,
3748 .process
= dce_v8_0_hpd_irq
,
3751 static void dce_v8_0_set_irq_funcs(struct amdgpu_device
*adev
)
3753 adev
->crtc_irq
.num_types
= AMDGPU_CRTC_IRQ_LAST
;
3754 adev
->crtc_irq
.funcs
= &dce_v8_0_crtc_irq_funcs
;
3756 adev
->pageflip_irq
.num_types
= AMDGPU_PAGEFLIP_IRQ_LAST
;
3757 adev
->pageflip_irq
.funcs
= &dce_v8_0_pageflip_irq_funcs
;
3759 adev
->hpd_irq
.num_types
= AMDGPU_HPD_LAST
;
3760 adev
->hpd_irq
.funcs
= &dce_v8_0_hpd_irq_funcs
;