2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "fiji_ppsmc.h"
28 #include "fiji_smum.h"
29 #include "smu_ucode_xfer_vi.h"
30 #include "amdgpu_ucode.h"
32 #include "smu/smu_7_1_3_d.h"
33 #include "smu/smu_7_1_3_sh_mask.h"
35 #define FIJI_SMC_SIZE 0x20000
37 static int fiji_set_smc_sram_address(struct amdgpu_device
*adev
, uint32_t smc_address
, uint32_t limit
)
44 if ((smc_address
+ 3) > limit
)
47 WREG32(mmSMC_IND_INDEX_0
, smc_address
);
49 val
= RREG32(mmSMC_IND_ACCESS_CNTL
);
50 val
= REG_SET_FIELD(val
, SMC_IND_ACCESS_CNTL
, AUTO_INCREMENT_IND_0
, 0);
51 WREG32(mmSMC_IND_ACCESS_CNTL
, val
);
56 static int fiji_copy_bytes_to_smc(struct amdgpu_device
*adev
, uint32_t smc_start_address
, const uint8_t *src
, uint32_t byte_count
, uint32_t limit
)
59 uint32_t data
, orig_data
;
64 if (smc_start_address
& 3)
67 if ((smc_start_address
+ byte_count
) > limit
)
70 addr
= smc_start_address
;
72 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
73 while (byte_count
>= 4) {
74 /* Bytes are written into the SMC addres space with the MSB first */
75 data
= (src
[0] << 24) + (src
[1] << 16) + (src
[2] << 8) + src
[3];
77 result
= fiji_set_smc_sram_address(adev
, addr
, limit
);
82 WREG32(mmSMC_IND_DATA_0
, data
);
89 if (0 != byte_count
) {
90 /* Now write odd bytes left, do a read modify write cycle */
93 result
= fiji_set_smc_sram_address(adev
, addr
, limit
);
97 orig_data
= RREG32(mmSMC_IND_DATA_0
);
98 extra_shift
= 8 * (4 - byte_count
);
100 while (byte_count
> 0) {
101 data
= (data
<< 8) + *src
++;
105 data
<<= extra_shift
;
106 data
|= (orig_data
& ~((~0UL) << extra_shift
));
108 result
= fiji_set_smc_sram_address(adev
, addr
, limit
);
112 WREG32(mmSMC_IND_DATA_0
, data
);
116 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
120 static int fiji_program_jump_on_start(struct amdgpu_device
*adev
)
122 static unsigned char data
[] = {0xE0, 0x00, 0x80, 0x40};
123 fiji_copy_bytes_to_smc(adev
, 0x0, data
, 4, sizeof(data
)+1);
128 static bool fiji_is_smc_ram_running(struct amdgpu_device
*adev
)
130 uint32_t val
= RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0
);
131 val
= REG_GET_FIELD(val
, SMC_SYSCON_CLOCK_CNTL_0
, ck_disable
);
133 return ((0 == val
) && (0x20100 <= RREG32_SMC(ixSMC_PC_C
)));
136 static int wait_smu_response(struct amdgpu_device
*adev
)
141 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
142 val
= RREG32(mmSMC_RESP_0
);
143 if (REG_GET_FIELD(val
, SMC_RESP_0
, SMC_RESP
))
148 if (i
== adev
->usec_timeout
)
154 static int fiji_send_msg_to_smc_offset(struct amdgpu_device
*adev
)
156 if (wait_smu_response(adev
)) {
157 DRM_ERROR("Failed to send previous message\n");
161 WREG32(mmSMC_MSG_ARG_0
, 0x20000);
162 WREG32(mmSMC_MESSAGE_0
, PPSMC_MSG_Test
);
164 if (wait_smu_response(adev
)) {
165 DRM_ERROR("Failed to send message\n");
172 static int fiji_send_msg_to_smc(struct amdgpu_device
*adev
, PPSMC_Msg msg
)
174 if (!fiji_is_smc_ram_running(adev
))
179 if (wait_smu_response(adev
)) {
180 DRM_ERROR("Failed to send previous message\n");
184 WREG32(mmSMC_MESSAGE_0
, msg
);
186 if (wait_smu_response(adev
)) {
187 DRM_ERROR("Failed to send message\n");
194 static int fiji_send_msg_to_smc_without_waiting(struct amdgpu_device
*adev
,
197 if (wait_smu_response(adev
)) {
198 DRM_ERROR("Failed to send previous message\n");
202 WREG32(mmSMC_MESSAGE_0
, msg
);
207 static int fiji_send_msg_to_smc_with_parameter(struct amdgpu_device
*adev
,
211 if (!fiji_is_smc_ram_running(adev
))
214 if (wait_smu_response(adev
)) {
215 DRM_ERROR("Failed to send previous message\n");
219 WREG32(mmSMC_MSG_ARG_0
, parameter
);
221 return fiji_send_msg_to_smc(adev
, msg
);
224 static int fiji_send_msg_to_smc_with_parameter_without_waiting(
225 struct amdgpu_device
*adev
,
226 PPSMC_Msg msg
, uint32_t parameter
)
228 if (wait_smu_response(adev
)) {
229 DRM_ERROR("Failed to send previous message\n");
233 WREG32(mmSMC_MSG_ARG_0
, parameter
);
235 return fiji_send_msg_to_smc_without_waiting(adev
, msg
);
238 #if 0 /* not used yet */
239 static int fiji_wait_for_smc_inactive(struct amdgpu_device
*adev
)
244 if (!fiji_is_smc_ram_running(adev
))
247 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
248 val
= RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0
);
249 if (REG_GET_FIELD(val
, SMC_SYSCON_CLOCK_CNTL_0
, cken
) == 0)
254 if (i
== adev
->usec_timeout
)
261 static int fiji_smu_upload_firmware_image(struct amdgpu_device
*adev
)
263 const struct smc_firmware_header_v1_0
*hdr
;
265 uint32_t ucode_start_address
;
275 /* Skip SMC ucode loading on SR-IOV capable boards.
276 * vbios does this for us in asic_init in that case.
278 if (adev
->virtualization
.supports_sr_iov
)
281 hdr
= (const struct smc_firmware_header_v1_0
*)adev
->pm
.fw
->data
;
282 amdgpu_ucode_print_smc_hdr(&hdr
->header
);
284 adev
->pm
.fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
285 ucode_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
);
286 ucode_start_address
= le32_to_cpu(hdr
->ucode_start_addr
);
287 src
= (const uint8_t *)
288 (adev
->pm
.fw
->data
+ le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
290 if (ucode_size
& 3) {
291 DRM_ERROR("SMC ucode is not 4 bytes aligned\n");
295 if (ucode_size
> FIJI_SMC_SIZE
) {
296 DRM_ERROR("SMC address is beyond the SMC RAM area\n");
300 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
301 WREG32(mmSMC_IND_INDEX_0
, ucode_start_address
);
303 val
= RREG32(mmSMC_IND_ACCESS_CNTL
);
304 val
= REG_SET_FIELD(val
, SMC_IND_ACCESS_CNTL
, AUTO_INCREMENT_IND_0
, 1);
305 WREG32(mmSMC_IND_ACCESS_CNTL
, val
);
307 byte_count
= ucode_size
;
308 data
= (uint32_t *)src
;
309 for (; byte_count
>= 4; data
++, byte_count
-= 4)
310 WREG32(mmSMC_IND_DATA_0
, data
[0]);
312 val
= RREG32(mmSMC_IND_ACCESS_CNTL
);
313 val
= REG_SET_FIELD(val
, SMC_IND_ACCESS_CNTL
, AUTO_INCREMENT_IND_0
, 0);
314 WREG32(mmSMC_IND_ACCESS_CNTL
, val
);
315 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
320 #if 0 /* not used yet */
321 static int fiji_read_smc_sram_dword(struct amdgpu_device
*adev
,
322 uint32_t smc_address
,
329 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
330 result
= fiji_set_smc_sram_address(adev
, smc_address
, limit
);
332 *value
= RREG32(mmSMC_IND_DATA_0
);
333 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
337 static int fiji_write_smc_sram_dword(struct amdgpu_device
*adev
,
338 uint32_t smc_address
,
345 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
346 result
= fiji_set_smc_sram_address(adev
, smc_address
, limit
);
348 WREG32(mmSMC_IND_DATA_0
, value
);
349 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
353 static int fiji_smu_stop_smc(struct amdgpu_device
*adev
)
355 uint32_t val
= RREG32_SMC(ixSMC_SYSCON_RESET_CNTL
);
356 val
= REG_SET_FIELD(val
, SMC_SYSCON_RESET_CNTL
, rst_reg
, 1);
357 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL
, val
);
359 val
= RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0
);
360 val
= REG_SET_FIELD(val
, SMC_SYSCON_CLOCK_CNTL_0
, ck_disable
, 1);
361 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0
, val
);
367 static enum AMDGPU_UCODE_ID
fiji_convert_fw_type(uint32_t fw_type
)
371 return AMDGPU_UCODE_ID_SDMA0
;
373 return AMDGPU_UCODE_ID_SDMA1
;
375 return AMDGPU_UCODE_ID_CP_CE
;
376 case UCODE_ID_CP_PFP
:
377 return AMDGPU_UCODE_ID_CP_PFP
;
379 return AMDGPU_UCODE_ID_CP_ME
;
380 case UCODE_ID_CP_MEC
:
381 case UCODE_ID_CP_MEC_JT1
:
382 case UCODE_ID_CP_MEC_JT2
:
383 return AMDGPU_UCODE_ID_CP_MEC1
;
385 return AMDGPU_UCODE_ID_RLC_G
;
387 DRM_ERROR("ucode type is out of range!\n");
388 return AMDGPU_UCODE_ID_MAXIMUM
;
392 static int fiji_smu_populate_single_firmware_entry(struct amdgpu_device
*adev
,
394 struct SMU_Entry
*entry
)
396 enum AMDGPU_UCODE_ID id
= fiji_convert_fw_type(fw_type
);
397 struct amdgpu_firmware_info
*ucode
= &adev
->firmware
.ucode
[id
];
398 const struct gfx_firmware_header_v1_0
*header
= NULL
;
402 if (ucode
->fw
== NULL
)
404 gpu_addr
= ucode
->mc_addr
;
405 header
= (const struct gfx_firmware_header_v1_0
*)ucode
->fw
->data
;
406 data_size
= le32_to_cpu(header
->header
.ucode_size_bytes
);
408 if ((fw_type
== UCODE_ID_CP_MEC_JT1
) ||
409 (fw_type
== UCODE_ID_CP_MEC_JT2
)) {
410 gpu_addr
+= le32_to_cpu(header
->jt_offset
) << 2;
411 data_size
= le32_to_cpu(header
->jt_size
) << 2;
414 entry
->version
= (uint16_t)le32_to_cpu(header
->header
.ucode_version
);
415 entry
->id
= (uint16_t)fw_type
;
416 entry
->image_addr_high
= upper_32_bits(gpu_addr
);
417 entry
->image_addr_low
= lower_32_bits(gpu_addr
);
418 entry
->meta_data_addr_high
= 0;
419 entry
->meta_data_addr_low
= 0;
420 entry
->data_size_byte
= data_size
;
421 entry
->num_register_entries
= 0;
423 if (fw_type
== UCODE_ID_RLC_G
)
431 static int fiji_smu_request_load_fw(struct amdgpu_device
*adev
)
433 struct fiji_smu_private_data
*private = (struct fiji_smu_private_data
*)adev
->smu
.priv
;
434 struct SMU_DRAMData_TOC
*toc
;
437 WREG32_SMC(ixSOFT_REGISTERS_TABLE_28
, 0);
439 fiji_send_msg_to_smc_with_parameter(adev
, PPSMC_MSG_SMU_DRAM_ADDR_HI
, private->smu_buffer_addr_high
);
440 fiji_send_msg_to_smc_with_parameter(adev
, PPSMC_MSG_SMU_DRAM_ADDR_LO
, private->smu_buffer_addr_low
);
442 toc
= (struct SMU_DRAMData_TOC
*)private->header
;
443 toc
->num_entries
= 0;
444 toc
->structure_version
= 1;
446 if (!adev
->firmware
.smu_load
)
449 if (fiji_smu_populate_single_firmware_entry(adev
, UCODE_ID_RLC_G
,
450 &toc
->entry
[toc
->num_entries
++])) {
451 DRM_ERROR("Failed to get firmware entry for RLC\n");
455 if (fiji_smu_populate_single_firmware_entry(adev
, UCODE_ID_CP_CE
,
456 &toc
->entry
[toc
->num_entries
++])) {
457 DRM_ERROR("Failed to get firmware entry for CE\n");
461 if (fiji_smu_populate_single_firmware_entry(adev
, UCODE_ID_CP_PFP
,
462 &toc
->entry
[toc
->num_entries
++])) {
463 DRM_ERROR("Failed to get firmware entry for PFP\n");
467 if (fiji_smu_populate_single_firmware_entry(adev
, UCODE_ID_CP_ME
,
468 &toc
->entry
[toc
->num_entries
++])) {
469 DRM_ERROR("Failed to get firmware entry for ME\n");
473 if (fiji_smu_populate_single_firmware_entry(adev
, UCODE_ID_CP_MEC
,
474 &toc
->entry
[toc
->num_entries
++])) {
475 DRM_ERROR("Failed to get firmware entry for MEC\n");
479 if (fiji_smu_populate_single_firmware_entry(adev
, UCODE_ID_CP_MEC_JT1
,
480 &toc
->entry
[toc
->num_entries
++])) {
481 DRM_ERROR("Failed to get firmware entry for MEC_JT1\n");
485 if (fiji_smu_populate_single_firmware_entry(adev
, UCODE_ID_CP_MEC_JT2
,
486 &toc
->entry
[toc
->num_entries
++])) {
487 DRM_ERROR("Failed to get firmware entry for MEC_JT2\n");
491 if (fiji_smu_populate_single_firmware_entry(adev
, UCODE_ID_SDMA0
,
492 &toc
->entry
[toc
->num_entries
++])) {
493 DRM_ERROR("Failed to get firmware entry for SDMA0\n");
497 if (fiji_smu_populate_single_firmware_entry(adev
, UCODE_ID_SDMA1
,
498 &toc
->entry
[toc
->num_entries
++])) {
499 DRM_ERROR("Failed to get firmware entry for SDMA1\n");
503 fiji_send_msg_to_smc_with_parameter(adev
, PPSMC_MSG_DRV_DRAM_ADDR_HI
, private->header_addr_high
);
504 fiji_send_msg_to_smc_with_parameter(adev
, PPSMC_MSG_DRV_DRAM_ADDR_LO
, private->header_addr_low
);
506 fw_to_load
= UCODE_ID_RLC_G_MASK
|
507 UCODE_ID_SDMA0_MASK
|
508 UCODE_ID_SDMA1_MASK
|
509 UCODE_ID_CP_CE_MASK
|
510 UCODE_ID_CP_ME_MASK
|
511 UCODE_ID_CP_PFP_MASK
|
512 UCODE_ID_CP_MEC_MASK
;
514 if (fiji_send_msg_to_smc_with_parameter_without_waiting(adev
, PPSMC_MSG_LoadUcodes
, fw_to_load
)) {
515 DRM_ERROR("Fail to request SMU load ucode\n");
522 static uint32_t fiji_smu_get_mask_for_fw_type(uint32_t fw_type
)
525 case AMDGPU_UCODE_ID_SDMA0
:
526 return UCODE_ID_SDMA0_MASK
;
527 case AMDGPU_UCODE_ID_SDMA1
:
528 return UCODE_ID_SDMA1_MASK
;
529 case AMDGPU_UCODE_ID_CP_CE
:
530 return UCODE_ID_CP_CE_MASK
;
531 case AMDGPU_UCODE_ID_CP_PFP
:
532 return UCODE_ID_CP_PFP_MASK
;
533 case AMDGPU_UCODE_ID_CP_ME
:
534 return UCODE_ID_CP_ME_MASK
;
535 case AMDGPU_UCODE_ID_CP_MEC1
:
536 return UCODE_ID_CP_MEC_MASK
;
537 case AMDGPU_UCODE_ID_CP_MEC2
:
538 return UCODE_ID_CP_MEC_MASK
;
539 case AMDGPU_UCODE_ID_RLC_G
:
540 return UCODE_ID_RLC_G_MASK
;
542 DRM_ERROR("ucode type is out of range!\n");
547 static int fiji_smu_check_fw_load_finish(struct amdgpu_device
*adev
,
550 uint32_t fw_mask
= fiji_smu_get_mask_for_fw_type(fw_type
);
553 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
554 if (fw_mask
== (RREG32_SMC(ixSOFT_REGISTERS_TABLE_28
) & fw_mask
))
559 if (i
== adev
->usec_timeout
) {
560 DRM_ERROR("check firmware loading failed\n");
567 static int fiji_smu_start_in_protection_mode(struct amdgpu_device
*adev
)
574 val
= RREG32_SMC(ixSMC_SYSCON_RESET_CNTL
);
575 val
= REG_SET_FIELD(val
, SMC_SYSCON_RESET_CNTL
, rst_reg
, 1);
576 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL
, val
);
578 result
= fiji_smu_upload_firmware_image(adev
);
583 WREG32_SMC(ixSMU_STATUS
, 0);
586 val
= RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0
);
587 val
= REG_SET_FIELD(val
, SMC_SYSCON_CLOCK_CNTL_0
, ck_disable
, 0);
588 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0
, val
);
590 /* De-assert reset */
591 val
= RREG32_SMC(ixSMC_SYSCON_RESET_CNTL
);
592 val
= REG_SET_FIELD(val
, SMC_SYSCON_RESET_CNTL
, rst_reg
, 0);
593 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL
, val
);
595 /* Set SMU Auto Start */
596 val
= RREG32_SMC(ixSMU_INPUT_DATA
);
597 val
= REG_SET_FIELD(val
, SMU_INPUT_DATA
, AUTO_START
, 1);
598 WREG32_SMC(ixSMU_INPUT_DATA
, val
);
600 /* Clear firmware interrupt enable flag */
601 WREG32_SMC(ixFIRMWARE_FLAGS
, 0);
603 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
604 val
= RREG32_SMC(ixRCU_UC_EVENTS
);
605 if (REG_GET_FIELD(val
, RCU_UC_EVENTS
, INTERRUPTS_ENABLED
))
610 if (i
== adev
->usec_timeout
) {
611 DRM_ERROR("Interrupt is not enabled by firmware\n");
615 /* Call Test SMU message with 0x20000 offset
616 * to trigger SMU start
618 fiji_send_msg_to_smc_offset(adev
);
619 DRM_INFO("[FM]try triger smu start\n");
620 /* Wait for done bit to be set */
621 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
622 val
= RREG32_SMC(ixSMU_STATUS
);
623 if (REG_GET_FIELD(val
, SMU_STATUS
, SMU_DONE
))
628 if (i
== adev
->usec_timeout
) {
629 DRM_ERROR("Timeout for SMU start\n");
633 /* Check pass/failed indicator */
634 val
= RREG32_SMC(ixSMU_STATUS
);
635 if (!REG_GET_FIELD(val
, SMU_STATUS
, SMU_PASS
)) {
636 DRM_ERROR("SMU Firmware start failed\n");
639 DRM_INFO("[FM]smu started\n");
640 /* Wait for firmware to initialize */
641 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
642 val
= RREG32_SMC(ixFIRMWARE_FLAGS
);
643 if(REG_GET_FIELD(val
, FIRMWARE_FLAGS
, INTERRUPTS_ENABLED
))
648 if (i
== adev
->usec_timeout
) {
649 DRM_ERROR("SMU firmware initialization failed\n");
652 DRM_INFO("[FM]smu initialized\n");
657 static int fiji_smu_start_in_non_protection_mode(struct amdgpu_device
*adev
)
662 /* wait for smc boot up */
663 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
664 val
= RREG32_SMC(ixRCU_UC_EVENTS
);
665 val
= REG_GET_FIELD(val
, RCU_UC_EVENTS
, boot_seq_done
);
671 if (i
== adev
->usec_timeout
) {
672 DRM_ERROR("SMC boot sequence is not completed\n");
676 /* Clear firmware interrupt enable flag */
677 WREG32_SMC(ixFIRMWARE_FLAGS
, 0);
680 val
= RREG32_SMC(ixSMC_SYSCON_RESET_CNTL
);
681 val
= REG_SET_FIELD(val
, SMC_SYSCON_RESET_CNTL
, rst_reg
, 1);
682 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL
, val
);
684 result
= fiji_smu_upload_firmware_image(adev
);
688 /* Set smc instruct start point at 0x0 */
689 fiji_program_jump_on_start(adev
);
692 val
= RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0
);
693 val
= REG_SET_FIELD(val
, SMC_SYSCON_CLOCK_CNTL_0
, ck_disable
, 0);
694 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0
, val
);
696 /* De-assert reset */
697 val
= RREG32_SMC(ixSMC_SYSCON_RESET_CNTL
);
698 val
= REG_SET_FIELD(val
, SMC_SYSCON_RESET_CNTL
, rst_reg
, 0);
699 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL
, val
);
701 /* Wait for firmware to initialize */
702 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
703 val
= RREG32_SMC(ixFIRMWARE_FLAGS
);
704 if (REG_GET_FIELD(val
, FIRMWARE_FLAGS
, INTERRUPTS_ENABLED
))
709 if (i
== adev
->usec_timeout
) {
710 DRM_ERROR("Timeout for SMC firmware initialization\n");
717 int fiji_smu_start(struct amdgpu_device
*adev
)
722 if (!fiji_is_smc_ram_running(adev
)) {
723 val
= RREG32_SMC(ixSMU_FIRMWARE
);
724 if (!REG_GET_FIELD(val
, SMU_FIRMWARE
, SMU_MODE
)) {
725 DRM_INFO("[FM]start smu in nonprotection mode\n");
726 result
= fiji_smu_start_in_non_protection_mode(adev
);
730 DRM_INFO("[FM]start smu in protection mode\n");
731 result
= fiji_smu_start_in_protection_mode(adev
);
737 return fiji_smu_request_load_fw(adev
);
740 static const struct amdgpu_smumgr_funcs fiji_smumgr_funcs
= {
741 .check_fw_load_finish
= fiji_smu_check_fw_load_finish
,
742 .request_smu_load_fw
= NULL
,
743 .request_smu_specific_fw
= NULL
,
746 int fiji_smu_init(struct amdgpu_device
*adev
)
748 struct fiji_smu_private_data
*private;
749 uint32_t image_size
= ((sizeof(struct SMU_DRAMData_TOC
) / 4096) + 1) * 4096;
750 uint32_t smu_internal_buffer_size
= 200*4096;
751 struct amdgpu_bo
**toc_buf
= &adev
->smu
.toc_buf
;
752 struct amdgpu_bo
**smu_buf
= &adev
->smu
.smu_buf
;
758 private = kzalloc(sizeof(struct fiji_smu_private_data
), GFP_KERNEL
);
762 /* allocate firmware buffers */
763 if (adev
->firmware
.smu_load
)
764 amdgpu_ucode_init_bo(adev
);
766 adev
->smu
.priv
= private;
767 adev
->smu
.fw_flags
= 0;
769 /* Allocate FW image data structure and header buffer */
770 ret
= amdgpu_bo_create(adev
, image_size
, PAGE_SIZE
,
771 true, AMDGPU_GEM_DOMAIN_VRAM
,
772 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
773 NULL
, NULL
, toc_buf
);
775 DRM_ERROR("Failed to allocate memory for TOC buffer\n");
779 /* Allocate buffer for SMU internal buffer */
780 ret
= amdgpu_bo_create(adev
, smu_internal_buffer_size
, PAGE_SIZE
,
781 true, AMDGPU_GEM_DOMAIN_VRAM
,
782 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
783 NULL
, NULL
, smu_buf
);
785 DRM_ERROR("Failed to allocate memory for SMU internal buffer\n");
789 /* Retrieve GPU address for header buffer and internal buffer */
790 ret
= amdgpu_bo_reserve(adev
->smu
.toc_buf
, false);
792 amdgpu_bo_unref(&adev
->smu
.toc_buf
);
793 DRM_ERROR("Failed to reserve the TOC buffer\n");
797 ret
= amdgpu_bo_pin(adev
->smu
.toc_buf
, AMDGPU_GEM_DOMAIN_VRAM
, &mc_addr
);
799 amdgpu_bo_unreserve(adev
->smu
.toc_buf
);
800 amdgpu_bo_unref(&adev
->smu
.toc_buf
);
801 DRM_ERROR("Failed to pin the TOC buffer\n");
805 ret
= amdgpu_bo_kmap(*toc_buf
, &toc_buf_ptr
);
807 amdgpu_bo_unreserve(adev
->smu
.toc_buf
);
808 amdgpu_bo_unref(&adev
->smu
.toc_buf
);
809 DRM_ERROR("Failed to map the TOC buffer\n");
813 amdgpu_bo_unreserve(adev
->smu
.toc_buf
);
814 private->header_addr_low
= lower_32_bits(mc_addr
);
815 private->header_addr_high
= upper_32_bits(mc_addr
);
816 private->header
= toc_buf_ptr
;
818 ret
= amdgpu_bo_reserve(adev
->smu
.smu_buf
, false);
820 amdgpu_bo_unref(&adev
->smu
.smu_buf
);
821 amdgpu_bo_unref(&adev
->smu
.toc_buf
);
822 DRM_ERROR("Failed to reserve the SMU internal buffer\n");
826 ret
= amdgpu_bo_pin(adev
->smu
.smu_buf
, AMDGPU_GEM_DOMAIN_VRAM
, &mc_addr
);
828 amdgpu_bo_unreserve(adev
->smu
.smu_buf
);
829 amdgpu_bo_unref(&adev
->smu
.smu_buf
);
830 amdgpu_bo_unref(&adev
->smu
.toc_buf
);
831 DRM_ERROR("Failed to pin the SMU internal buffer\n");
835 ret
= amdgpu_bo_kmap(*smu_buf
, &smu_buf_ptr
);
837 amdgpu_bo_unreserve(adev
->smu
.smu_buf
);
838 amdgpu_bo_unref(&adev
->smu
.smu_buf
);
839 amdgpu_bo_unref(&adev
->smu
.toc_buf
);
840 DRM_ERROR("Failed to map the SMU internal buffer\n");
844 amdgpu_bo_unreserve(adev
->smu
.smu_buf
);
845 private->smu_buffer_addr_low
= lower_32_bits(mc_addr
);
846 private->smu_buffer_addr_high
= upper_32_bits(mc_addr
);
848 adev
->smu
.smumgr_funcs
= &fiji_smumgr_funcs
;
853 int fiji_smu_fini(struct amdgpu_device
*adev
)
855 amdgpu_bo_unref(&adev
->smu
.toc_buf
);
856 amdgpu_bo_unref(&adev
->smu
.smu_buf
);
857 kfree(adev
->smu
.priv
);
858 adev
->smu
.priv
= NULL
;
859 if (adev
->firmware
.fw_buf
)
860 amdgpu_ucode_fini_bo(adev
);