drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "smuio/smuio_11_0_0_offset.h"
  39 #include "smuio/smuio_11_0_0_sh_mask.h"
  40 #include "navi10_enum.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "soc15_common.h"
  47 #include "clearstate_gfx10.h"
  48 #include "v10_structs.h"
  49 #include "gfx_v10_0.h"
  50 #include "nbio_v2_3.h"
  51
  52 /**
  53  * Navi10 has two graphic rings to share each graphic pipe.
  54  * 1. Primary ring
  55  * 2. Async ring
  56  */
  57 #define GFX10_NUM_GFX_RINGS_NV1X        1
  58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  59 #define GFX10_MEC_HPD_SIZE      2048
  60
  61 #define F32_CE_PROGRAM_RAM_SIZE         65536
  62 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  63
  64 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  70
  71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  73
  74 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  76 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
  97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
  98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
  99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 101
 102 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 103 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 104 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 105 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 106 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 107 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 108 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 109 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 110 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 111 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 112 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 113 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 114 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 115 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 116 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 117 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 118
 119 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 120 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 121 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 122 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 123 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 124 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 125 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 126 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 127 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 128 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 129 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 130 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 131
 132 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 133 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 134 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 135 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 136 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 137 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 138
 139 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 140 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 141 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 142 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 143 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 144 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 145 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 146 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 147 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 148 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 149 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 150
 151 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 152 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 153 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 154 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 155 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 156 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 157
 158 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 159 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 160 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 161 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 162 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 163 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 164
 165 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 166 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 167 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 168 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 169 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 170 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 171
 172 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 173 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 174 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 175 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 176 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 177 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 178
 179 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 180 {
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 221 };
 222
 223 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 224 {
 225         /* Pending on emulation bring up */
 226 };
 227
 228 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 229 {
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1282 };
1283
1284 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1285 {
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1324 };
1325
1326 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1327 {
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1368 };
1369
1370 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1371 {
1372         static void *scratch_reg0;
1373         static void *scratch_reg1;
1374         static void *scratch_reg2;
1375         static void *scratch_reg3;
1376         static void *spare_int;
1377         static uint32_t grbm_cntl;
1378         static uint32_t grbm_idx;
1379         uint32_t i = 0;
1380         uint32_t retries = 50000;
1381
1382         scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1383         scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1384         scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
1385         scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
1386         spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1387
1388         grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1389         grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1390
1391         if (amdgpu_sriov_runtime(adev)) {
1392                 pr_err("shouldn't call rlcg write register during runtime\n");
1393                 return;
1394         }
1395
1396         writel(v, scratch_reg0);
1397         writel(offset | 0x80000000, scratch_reg1);
1398         writel(1, spare_int);
1399         for (i = 0; i < retries; i++) {
1400                 u32 tmp;
1401
1402                 tmp = readl(scratch_reg1);
1403                 if (!(tmp & 0x80000000))
1404                         break;
1405
1406                 udelay(10);
1407         }
1408
1409         if (i >= retries)
1410                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1411 }
1412
1413 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1414 {
1415         /* Pending on emulation bring up */
1416 };
1417
1418 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1419 {
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2040 };
2041
2042 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2043 {
2044         /* Pending on emulation bring up */
2045 };
2046
2047 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2048 {
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3101 };
3102
3103 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3104 {
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3141 };
3142
3143 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3144 {
3145         /* Pending on emulation bring up */
3146 };
3147
3148 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3149 {
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
3188 };
3189
3190 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3191 {
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
3200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3215 };
3216
3217 #define DEFAULT_SH_MEM_CONFIG \
3218         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3219          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3220          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3221          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3222
3223
3224 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3225 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3226 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3227 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3228 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3229                                  struct amdgpu_cu_info *cu_info);
3230 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3231 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3232                                    u32 sh_num, u32 instance);
3233 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3234
3235 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3236 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3237 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3238 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3239 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3240 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3241 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3242
3243 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3244 {
3245         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3246         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3247                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3248         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3249         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3250         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3251         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3252         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3253         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3254 }
3255
3256 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3257                                  struct amdgpu_ring *ring)
3258 {
3259         struct amdgpu_device *adev = kiq_ring->adev;
3260         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3261         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3262         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3263
3264         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3265         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3266         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3267                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3268                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3269                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3270                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3271                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3272                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3273                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3274                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3275                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3276         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3277         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3278         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3279         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3280         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3281 }
3282
3283 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3284                                    struct amdgpu_ring *ring,
3285                                    enum amdgpu_unmap_queues_action action,
3286                                    u64 gpu_addr, u64 seq)
3287 {
3288         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3289
3290         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3291         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3292                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3293                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3294                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3295                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3296         amdgpu_ring_write(kiq_ring,
3297                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3298
3299         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3300                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3301                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3302                 amdgpu_ring_write(kiq_ring, seq);
3303         } else {
3304                 amdgpu_ring_write(kiq_ring, 0);
3305                 amdgpu_ring_write(kiq_ring, 0);
3306                 amdgpu_ring_write(kiq_ring, 0);
3307         }
3308 }
3309
3310 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3311                                    struct amdgpu_ring *ring,
3312                                    u64 addr,
3313                                    u64 seq)
3314 {
3315         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3316
3317         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3318         amdgpu_ring_write(kiq_ring,
3319                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3320                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3321                           PACKET3_QUERY_STATUS_COMMAND(2));
3322         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3323                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3324                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3325         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3326         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3327         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3328         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3329 }
3330
3331 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3332                                 uint16_t pasid, uint32_t flush_type,
3333                                 bool all_hub)
3334 {
3335         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3336         amdgpu_ring_write(kiq_ring,
3337                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3338                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3339                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3340                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3341 }
3342
3343 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3344         .kiq_set_resources = gfx10_kiq_set_resources,
3345         .kiq_map_queues = gfx10_kiq_map_queues,
3346         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3347         .kiq_query_status = gfx10_kiq_query_status,
3348         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3349         .set_resources_size = 8,
3350         .map_queues_size = 7,
3351         .unmap_queues_size = 6,
3352         .query_status_size = 7,
3353         .invalidate_tlbs_size = 2,
3354 };
3355
3356 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3357 {
3358         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3359 }
3360
3361 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3362 {
3363         switch (adev->asic_type) {
3364         case CHIP_NAVI10:
3365                 soc15_program_register_sequence(adev,
3366                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3367                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3368                 break;
3369         case CHIP_NAVI14:
3370                 soc15_program_register_sequence(adev,
3371                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3372                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3373                 break;
3374         case CHIP_NAVI12:
3375                 soc15_program_register_sequence(adev,
3376                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3377                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3378                 break;
3379         default:
3380                 break;
3381         }
3382 }
3383
3384 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3385 {
3386         switch (adev->asic_type) {
3387         case CHIP_NAVI10:
3388                 soc15_program_register_sequence(adev,
3389                                                 golden_settings_gc_10_1,
3390                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3391                 soc15_program_register_sequence(adev,
3392                                                 golden_settings_gc_10_0_nv10,
3393                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3394                 break;
3395         case CHIP_NAVI14:
3396                 soc15_program_register_sequence(adev,
3397                                                 golden_settings_gc_10_1_1,
3398                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3399                 soc15_program_register_sequence(adev,
3400                                                 golden_settings_gc_10_1_nv14,
3401                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3402                 break;
3403         case CHIP_NAVI12:
3404                 soc15_program_register_sequence(adev,
3405                                                 golden_settings_gc_10_1_2,
3406                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3407                 soc15_program_register_sequence(adev,
3408                                                 golden_settings_gc_10_1_2_nv12,
3409                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3410                 break;
3411         case CHIP_SIENNA_CICHLID:
3412                 soc15_program_register_sequence(adev,
3413                                                 golden_settings_gc_10_3,
3414                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3415                 soc15_program_register_sequence(adev,
3416                                                 golden_settings_gc_10_3_sienna_cichlid,
3417                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3418                 break;
3419         case CHIP_NAVY_FLOUNDER:
3420                 soc15_program_register_sequence(adev,
3421                                                 golden_settings_gc_10_3_2,
3422                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3423                 break;
3424         case CHIP_VANGOGH:
3425                 soc15_program_register_sequence(adev,
3426                                                 golden_settings_gc_10_3_vangogh,
3427                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3428                 break;
3429         default:
3430                 break;
3431         }
3432         gfx_v10_0_init_spm_golden_registers(adev);
3433 }
3434
3435 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3436 {
3437         adev->gfx.scratch.num_reg = 8;
3438         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3439         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3440 }
3441
3442 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3443                                        bool wc, uint32_t reg, uint32_t val)
3444 {
3445         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3446         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3447                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3448         amdgpu_ring_write(ring, reg);
3449         amdgpu_ring_write(ring, 0);
3450         amdgpu_ring_write(ring, val);
3451 }
3452
3453 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3454                                   int mem_space, int opt, uint32_t addr0,
3455                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3456                                   uint32_t inv)
3457 {
3458         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3459         amdgpu_ring_write(ring,
3460                           /* memory (1) or register (0) */
3461                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3462                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3463                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3464                            WAIT_REG_MEM_ENGINE(eng_sel)));
3465
3466         if (mem_space)
3467                 BUG_ON(addr0 & 0x3); /* Dword align */
3468         amdgpu_ring_write(ring, addr0);
3469         amdgpu_ring_write(ring, addr1);
3470         amdgpu_ring_write(ring, ref);
3471         amdgpu_ring_write(ring, mask);
3472         amdgpu_ring_write(ring, inv); /* poll interval */
3473 }
3474
3475 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3476 {
3477         struct amdgpu_device *adev = ring->adev;
3478         uint32_t scratch;
3479         uint32_t tmp = 0;
3480         unsigned i;
3481         int r;
3482
3483         r = amdgpu_gfx_scratch_get(adev, &scratch);
3484         if (r) {
3485                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3486                 return r;
3487         }
3488
3489         WREG32(scratch, 0xCAFEDEAD);
3490
3491         r = amdgpu_ring_alloc(ring, 3);
3492         if (r) {
3493                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3494                           ring->idx, r);
3495                 amdgpu_gfx_scratch_free(adev, scratch);
3496                 return r;
3497         }
3498
3499         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3500         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3501         amdgpu_ring_write(ring, 0xDEADBEEF);
3502         amdgpu_ring_commit(ring);
3503
3504         for (i = 0; i < adev->usec_timeout; i++) {
3505                 tmp = RREG32(scratch);
3506                 if (tmp == 0xDEADBEEF)
3507                         break;
3508                 if (amdgpu_emu_mode == 1)
3509                         msleep(1);
3510                 else
3511                         udelay(1);
3512         }
3513
3514         if (i >= adev->usec_timeout)
3515                 r = -ETIMEDOUT;
3516
3517         amdgpu_gfx_scratch_free(adev, scratch);
3518
3519         return r;
3520 }
3521
3522 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3523 {
3524         struct amdgpu_device *adev = ring->adev;
3525         struct amdgpu_ib ib;
3526         struct dma_fence *f = NULL;
3527         unsigned index;
3528         uint64_t gpu_addr;
3529         uint32_t tmp;
3530         long r;
3531
3532         r = amdgpu_device_wb_get(adev, &index);
3533         if (r)
3534                 return r;
3535
3536         gpu_addr = adev->wb.gpu_addr + (index * 4);
3537         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3538         memset(&ib, 0, sizeof(ib));
3539         r = amdgpu_ib_get(adev, NULL, 16,
3540                                         AMDGPU_IB_POOL_DIRECT, &ib);
3541         if (r)
3542                 goto err1;
3543
3544         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3545         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3546         ib.ptr[2] = lower_32_bits(gpu_addr);
3547         ib.ptr[3] = upper_32_bits(gpu_addr);
3548         ib.ptr[4] = 0xDEADBEEF;
3549         ib.length_dw = 5;
3550
3551         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3552         if (r)
3553                 goto err2;
3554
3555         r = dma_fence_wait_timeout(f, false, timeout);
3556         if (r == 0) {
3557                 r = -ETIMEDOUT;
3558                 goto err2;
3559         } else if (r < 0) {
3560                 goto err2;
3561         }
3562
3563         tmp = adev->wb.wb[index];
3564         if (tmp == 0xDEADBEEF)
3565                 r = 0;
3566         else
3567                 r = -EINVAL;
3568 err2:
3569         amdgpu_ib_free(adev, &ib, NULL);
3570         dma_fence_put(f);
3571 err1:
3572         amdgpu_device_wb_free(adev, index);
3573         return r;
3574 }
3575
3576 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3577 {
3578         release_firmware(adev->gfx.pfp_fw);
3579         adev->gfx.pfp_fw = NULL;
3580         release_firmware(adev->gfx.me_fw);
3581         adev->gfx.me_fw = NULL;
3582         release_firmware(adev->gfx.ce_fw);
3583         adev->gfx.ce_fw = NULL;
3584         release_firmware(adev->gfx.rlc_fw);
3585         adev->gfx.rlc_fw = NULL;
3586         release_firmware(adev->gfx.mec_fw);
3587         adev->gfx.mec_fw = NULL;
3588         release_firmware(adev->gfx.mec2_fw);
3589         adev->gfx.mec2_fw = NULL;
3590
3591         kfree(adev->gfx.rlc.register_list_format);
3592 }
3593
3594 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3595 {
3596         adev->gfx.cp_fw_write_wait = false;
3597
3598         switch (adev->asic_type) {
3599         case CHIP_NAVI10:
3600         case CHIP_NAVI12:
3601         case CHIP_NAVI14:
3602                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3603                     (adev->gfx.me_feature_version >= 27) &&
3604                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3605                     (adev->gfx.pfp_feature_version >= 27) &&
3606                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3607                     (adev->gfx.mec_feature_version >= 27))
3608                         adev->gfx.cp_fw_write_wait = true;
3609                 break;
3610         case CHIP_SIENNA_CICHLID:
3611         case CHIP_NAVY_FLOUNDER:
3612         case CHIP_VANGOGH:
3613                 adev->gfx.cp_fw_write_wait = true;
3614                 break;
3615         default:
3616                 break;
3617         }
3618
3619         if (!adev->gfx.cp_fw_write_wait)
3620                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3621 }
3622
3623
3624 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3625 {
3626         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3627
3628         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3629         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3630         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3631         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3632         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3633         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3634         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3635         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3636         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3637         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3638         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3639         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3640         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3641         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3642                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3643 }
3644
3645 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3646 {
3647         bool ret = false;
3648
3649         switch (adev->pdev->revision) {
3650         case 0xc2:
3651         case 0xc3:
3652                 ret = true;
3653                 break;
3654         default:
3655                 ret = false;
3656                 break;
3657         }
3658
3659         return ret ;
3660 }
3661
3662 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3663 {
3664         switch (adev->asic_type) {
3665         case CHIP_NAVI10:
3666                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3667                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3668                 break;
3669         case CHIP_NAVY_FLOUNDER:
3670                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3671                 break;
3672         default:
3673                 break;
3674         }
3675 }
3676
3677 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3678 {
3679         const char *chip_name;
3680         char fw_name[40];
3681         char wks[10];
3682         int err;
3683         struct amdgpu_firmware_info *info = NULL;
3684         const struct common_firmware_header *header = NULL;
3685         const struct gfx_firmware_header_v1_0 *cp_hdr;
3686         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3687         unsigned int *tmp = NULL;
3688         unsigned int i = 0;
3689         uint16_t version_major;
3690         uint16_t version_minor;
3691
3692         DRM_DEBUG("\n");
3693
3694         memset(wks, 0, sizeof(wks));
3695         switch (adev->asic_type) {
3696         case CHIP_NAVI10:
3697                 chip_name = "navi10";
3698                 break;
3699         case CHIP_NAVI14:
3700                 chip_name = "navi14";
3701                 if (!(adev->pdev->device == 0x7340 &&
3702                       adev->pdev->revision != 0x00))
3703                         snprintf(wks, sizeof(wks), "_wks");
3704                 break;
3705         case CHIP_NAVI12:
3706                 chip_name = "navi12";
3707                 break;
3708         case CHIP_SIENNA_CICHLID:
3709                 chip_name = "sienna_cichlid";
3710                 break;
3711         case CHIP_NAVY_FLOUNDER:
3712                 chip_name = "navy_flounder";
3713                 break;
3714         case CHIP_VANGOGH:
3715                 chip_name = "vangogh";
3716                 break;
3717         default:
3718                 BUG();
3719         }
3720
3721         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3722         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3723         if (err)
3724                 goto out;
3725         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3726         if (err)
3727                 goto out;
3728         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3729         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3730         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3731
3732         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3733         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3734         if (err)
3735                 goto out;
3736         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3737         if (err)
3738                 goto out;
3739         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3740         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3741         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3742
3743         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3744         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3745         if (err)
3746                 goto out;
3747         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3748         if (err)
3749                 goto out;
3750         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3751         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3752         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3753
3754         if (!amdgpu_sriov_vf(adev)) {
3755                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3756                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3757                 if (err)
3758                         goto out;
3759                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3760                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3761                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3762                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3763                 if (version_major == 2 && version_minor == 1)
3764                         adev->gfx.rlc.is_rlc_v2_1 = true;
3765
3766                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3767                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3768                 adev->gfx.rlc.save_and_restore_offset =
3769                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3770                 adev->gfx.rlc.clear_state_descriptor_offset =
3771                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3772                 adev->gfx.rlc.avail_scratch_ram_locations =
3773                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3774                 adev->gfx.rlc.reg_restore_list_size =
3775                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3776                 adev->gfx.rlc.reg_list_format_start =
3777                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3778                 adev->gfx.rlc.reg_list_format_separate_start =
3779                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3780                 adev->gfx.rlc.starting_offsets_start =
3781                         le32_to_cpu(rlc_hdr->starting_offsets_start);
3782                 adev->gfx.rlc.reg_list_format_size_bytes =
3783                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3784                 adev->gfx.rlc.reg_list_size_bytes =
3785                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3786                 adev->gfx.rlc.register_list_format =
3787                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3788                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3789                 if (!adev->gfx.rlc.register_list_format) {
3790                         err = -ENOMEM;
3791                         goto out;
3792                 }
3793
3794                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3795                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3796                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3797                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
3798
3799                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3800
3801                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3802                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3803                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3804                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3805
3806                 if (adev->gfx.rlc.is_rlc_v2_1)
3807                         gfx_v10_0_init_rlc_ext_microcode(adev);
3808         }
3809
3810         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3811         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3812         if (err)
3813                 goto out;
3814         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3815         if (err)
3816                 goto out;
3817         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3818         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3819         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3820
3821         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3822         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3823         if (!err) {
3824                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3825                 if (err)
3826                         goto out;
3827                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3828                 adev->gfx.mec2_fw->data;
3829                 adev->gfx.mec2_fw_version =
3830                 le32_to_cpu(cp_hdr->header.ucode_version);
3831                 adev->gfx.mec2_feature_version =
3832                 le32_to_cpu(cp_hdr->ucode_feature_version);
3833         } else {
3834                 err = 0;
3835                 adev->gfx.mec2_fw = NULL;
3836         }
3837
3838         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3839                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3840                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3841                 info->fw = adev->gfx.pfp_fw;
3842                 header = (const struct common_firmware_header *)info->fw->data;
3843                 adev->firmware.fw_size +=
3844                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3845
3846                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3847                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3848                 info->fw = adev->gfx.me_fw;
3849                 header = (const struct common_firmware_header *)info->fw->data;
3850                 adev->firmware.fw_size +=
3851                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3852
3853                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3854                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3855                 info->fw = adev->gfx.ce_fw;
3856                 header = (const struct common_firmware_header *)info->fw->data;
3857                 adev->firmware.fw_size +=
3858                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3859
3860                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3861                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3862                 info->fw = adev->gfx.rlc_fw;
3863                 if (info->fw) {
3864                         header = (const struct common_firmware_header *)info->fw->data;
3865                         adev->firmware.fw_size +=
3866                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3867                 }
3868                 if (adev->gfx.rlc.is_rlc_v2_1 &&
3869                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3870                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3871                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3872                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3873                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3874                         info->fw = adev->gfx.rlc_fw;
3875                         adev->firmware.fw_size +=
3876                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3877
3878                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3879                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3880                         info->fw = adev->gfx.rlc_fw;
3881                         adev->firmware.fw_size +=
3882                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
3883
3884                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
3885                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
3886                         info->fw = adev->gfx.rlc_fw;
3887                         adev->firmware.fw_size +=
3888                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
3889                 }
3890
3891                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
3892                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
3893                 info->fw = adev->gfx.mec_fw;
3894                 header = (const struct common_firmware_header *)info->fw->data;
3895                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3896                 adev->firmware.fw_size +=
3897                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3898                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3899
3900                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
3901                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
3902                 info->fw = adev->gfx.mec_fw;
3903                 adev->firmware.fw_size +=
3904                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3905
3906                 if (adev->gfx.mec2_fw) {
3907                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
3908                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
3909                         info->fw = adev->gfx.mec2_fw;
3910                         header = (const struct common_firmware_header *)info->fw->data;
3911                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3912                         adev->firmware.fw_size +=
3913                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3914                                       le32_to_cpu(cp_hdr->jt_size) * 4,
3915                                       PAGE_SIZE);
3916                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
3917                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
3918                         info->fw = adev->gfx.mec2_fw;
3919                         adev->firmware.fw_size +=
3920                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
3921                                       PAGE_SIZE);
3922                 }
3923         }
3924
3925         gfx_v10_0_check_fw_write_wait(adev);
3926 out:
3927         if (err) {
3928                 dev_err(adev->dev,
3929                         "gfx10: Failed to load firmware \"%s\"\n",
3930                         fw_name);
3931                 release_firmware(adev->gfx.pfp_fw);
3932                 adev->gfx.pfp_fw = NULL;
3933                 release_firmware(adev->gfx.me_fw);
3934                 adev->gfx.me_fw = NULL;
3935                 release_firmware(adev->gfx.ce_fw);
3936                 adev->gfx.ce_fw = NULL;
3937                 release_firmware(adev->gfx.rlc_fw);
3938                 adev->gfx.rlc_fw = NULL;
3939                 release_firmware(adev->gfx.mec_fw);
3940                 adev->gfx.mec_fw = NULL;
3941                 release_firmware(adev->gfx.mec2_fw);
3942                 adev->gfx.mec2_fw = NULL;
3943         }
3944
3945         gfx_v10_0_check_gfxoff_flag(adev);
3946
3947         return err;
3948 }
3949
3950 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
3951 {
3952         u32 count = 0;
3953         const struct cs_section_def *sect = NULL;
3954         const struct cs_extent_def *ext = NULL;
3955
3956         /* begin clear state */
3957         count += 2;
3958         /* context control state */
3959         count += 3;
3960
3961         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
3962                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3963                         if (sect->id == SECT_CONTEXT)
3964                                 count += 2 + ext->reg_count;
3965                         else
3966                                 return 0;
3967                 }
3968         }
3969
3970         /* set PA_SC_TILE_STEERING_OVERRIDE */
3971         count += 3;
3972         /* end clear state */
3973         count += 2;
3974         /* clear state */
3975         count += 2;
3976
3977         return count;
3978 }
3979
3980 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
3981                                     volatile u32 *buffer)
3982 {
3983         u32 count = 0, i;
3984         const struct cs_section_def *sect = NULL;
3985         const struct cs_extent_def *ext = NULL;
3986         int ctx_reg_offset;
3987
3988         if (adev->gfx.rlc.cs_data == NULL)
3989                 return;
3990         if (buffer == NULL)
3991                 return;
3992
3993         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3994         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3995
3996         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3997         buffer[count++] = cpu_to_le32(0x80000000);
3998         buffer[count++] = cpu_to_le32(0x80000000);
3999
4000         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4001                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4002                         if (sect->id == SECT_CONTEXT) {
4003                                 buffer[count++] =
4004                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4005                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4006                                                 PACKET3_SET_CONTEXT_REG_START);
4007                                 for (i = 0; i < ext->reg_count; i++)
4008                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4009                         } else {
4010                                 return;
4011                         }
4012                 }
4013         }
4014
4015         ctx_reg_offset =
4016                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4017         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4018         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4019         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4020
4021         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4022         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4023
4024         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4025         buffer[count++] = cpu_to_le32(0);
4026 }
4027
4028 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4029 {
4030         /* clear state block */
4031         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4032                         &adev->gfx.rlc.clear_state_gpu_addr,
4033                         (void **)&adev->gfx.rlc.cs_ptr);
4034
4035         /* jump table block */
4036         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4037                         &adev->gfx.rlc.cp_table_gpu_addr,
4038                         (void **)&adev->gfx.rlc.cp_table_ptr);
4039 }
4040
4041 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4042 {
4043         const struct cs_section_def *cs_data;
4044         int r;
4045
4046         adev->gfx.rlc.cs_data = gfx10_cs_data;
4047
4048         cs_data = adev->gfx.rlc.cs_data;
4049
4050         if (cs_data) {
4051                 /* init clear state block */
4052                 r = amdgpu_gfx_rlc_init_csb(adev);
4053                 if (r)
4054                         return r;
4055         }
4056
4057         /* init spm vmid with 0xf */
4058         if (adev->gfx.rlc.funcs->update_spm_vmid)
4059                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4060
4061         return 0;
4062 }
4063
4064 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4065 {
4066         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4067         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4068 }
4069
4070 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4071 {
4072         int r;
4073
4074         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4075
4076         amdgpu_gfx_graphics_queue_acquire(adev);
4077
4078         r = gfx_v10_0_init_microcode(adev);
4079         if (r)
4080                 DRM_ERROR("Failed to load gfx firmware!\n");
4081
4082         return r;
4083 }
4084
4085 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4086 {
4087         int r;
4088         u32 *hpd;
4089         const __le32 *fw_data = NULL;
4090         unsigned fw_size;
4091         u32 *fw = NULL;
4092         size_t mec_hpd_size;
4093
4094         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4095
4096         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4097
4098         /* take ownership of the relevant compute queues */
4099         amdgpu_gfx_compute_queue_acquire(adev);
4100         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4101
4102         if (mec_hpd_size) {
4103                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4104                                               AMDGPU_GEM_DOMAIN_GTT,
4105                                               &adev->gfx.mec.hpd_eop_obj,
4106                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4107                                               (void **)&hpd);
4108                 if (r) {
4109                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4110                         gfx_v10_0_mec_fini(adev);
4111                         return r;
4112                 }
4113
4114                 memset(hpd, 0, mec_hpd_size);
4115
4116                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4117                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4118         }
4119
4120         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4121                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4122
4123                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4124                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4125                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4126
4127                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4128                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4129                                               &adev->gfx.mec.mec_fw_obj,
4130                                               &adev->gfx.mec.mec_fw_gpu_addr,
4131                                               (void **)&fw);
4132                 if (r) {
4133                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4134                         gfx_v10_0_mec_fini(adev);
4135                         return r;
4136                 }
4137
4138                 memcpy(fw, fw_data, fw_size);
4139
4140                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4141                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4142         }
4143
4144         return 0;
4145 }
4146
4147 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4148 {
4149         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4150                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4151                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4152         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4153 }
4154
4155 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4156                            uint32_t thread, uint32_t regno,
4157                            uint32_t num, uint32_t *out)
4158 {
4159         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4160                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4161                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4162                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4163                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4164         while (num--)
4165                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4166 }
4167
4168 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4169 {
4170         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4171          * field when performing a select_se_sh so it should be
4172          * zero here */
4173         WARN_ON(simd != 0);
4174
4175         /* type 2 wave data */
4176         dst[(*no_fields)++] = 2;
4177         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4178         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4179         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4180         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4181         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4182         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4183         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4184         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4185         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4186         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4187         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4188         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4189         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4190         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4191         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4192 }
4193
4194 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4195                                      uint32_t wave, uint32_t start,
4196                                      uint32_t size, uint32_t *dst)
4197 {
4198         WARN_ON(simd != 0);
4199
4200         wave_read_regs(
4201                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4202                 dst);
4203 }
4204
4205 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4206                                       uint32_t wave, uint32_t thread,
4207                                       uint32_t start, uint32_t size,
4208                                       uint32_t *dst)
4209 {
4210         wave_read_regs(
4211                 adev, wave, thread,
4212                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4213 }
4214
4215 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4216                                                                           u32 me, u32 pipe, u32 q, u32 vm)
4217  {
4218        nv_grbm_select(adev, me, pipe, q, vm);
4219  }
4220
4221
4222 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4223         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4224         .select_se_sh = &gfx_v10_0_select_se_sh,
4225         .read_wave_data = &gfx_v10_0_read_wave_data,
4226         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4227         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4228         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4229         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4230 };
4231
4232 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4233 {
4234         u32 gb_addr_config;
4235
4236         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4237
4238         switch (adev->asic_type) {
4239         case CHIP_NAVI10:
4240         case CHIP_NAVI14:
4241         case CHIP_NAVI12:
4242                 adev->gfx.config.max_hw_contexts = 8;
4243                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4244                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4245                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4246                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4247                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4248                 break;
4249         case CHIP_SIENNA_CICHLID:
4250         case CHIP_NAVY_FLOUNDER:
4251         case CHIP_VANGOGH:
4252                 adev->gfx.config.max_hw_contexts = 8;
4253                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4254                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4255                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4256                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4257                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4258                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4259                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4260                 break;
4261         default:
4262                 BUG();
4263                 break;
4264         }
4265
4266         adev->gfx.config.gb_addr_config = gb_addr_config;
4267
4268         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4269                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4270                                       GB_ADDR_CONFIG, NUM_PIPES);
4271
4272         adev->gfx.config.max_tile_pipes =
4273                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4274
4275         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4276                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4277                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4278         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4279                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4280                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4281         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4282                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4283                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4284         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4285                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4286                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4287 }
4288
4289 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4290                                    int me, int pipe, int queue)
4291 {
4292         int r;
4293         struct amdgpu_ring *ring;
4294         unsigned int irq_type;
4295
4296         ring = &adev->gfx.gfx_ring[ring_id];
4297
4298         ring->me = me;
4299         ring->pipe = pipe;
4300         ring->queue = queue;
4301
4302         ring->ring_obj = NULL;
4303         ring->use_doorbell = true;
4304
4305         if (!ring_id)
4306                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4307         else
4308                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4309         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4310
4311         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4312         r = amdgpu_ring_init(adev, ring, 1024,
4313                              &adev->gfx.eop_irq, irq_type,
4314                              AMDGPU_RING_PRIO_DEFAULT);
4315         if (r)
4316                 return r;
4317         return 0;
4318 }
4319
4320 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4321                                        int mec, int pipe, int queue)
4322 {
4323         int r;
4324         unsigned irq_type;
4325         struct amdgpu_ring *ring;
4326         unsigned int hw_prio;
4327
4328         ring = &adev->gfx.compute_ring[ring_id];
4329
4330         /* mec0 is me1 */
4331         ring->me = mec + 1;
4332         ring->pipe = pipe;
4333         ring->queue = queue;
4334
4335         ring->ring_obj = NULL;
4336         ring->use_doorbell = true;
4337         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4338         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4339                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4340         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4341
4342         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4343                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4344                 + ring->pipe;
4345         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
4346                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4347         /* type-2 packets are deprecated on MEC, use type-3 instead */
4348         r = amdgpu_ring_init(adev, ring, 1024,
4349                              &adev->gfx.eop_irq, irq_type, hw_prio);
4350         if (r)
4351                 return r;
4352
4353         return 0;
4354 }
4355
4356 static int gfx_v10_0_sw_init(void *handle)
4357 {
4358         int i, j, k, r, ring_id = 0;
4359         struct amdgpu_kiq *kiq;
4360         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4361
4362         switch (adev->asic_type) {
4363         case CHIP_NAVI10:
4364         case CHIP_NAVI14:
4365         case CHIP_NAVI12:
4366                 adev->gfx.me.num_me = 1;
4367                 adev->gfx.me.num_pipe_per_me = 1;
4368                 adev->gfx.me.num_queue_per_pipe = 1;
4369                 adev->gfx.mec.num_mec = 2;
4370                 adev->gfx.mec.num_pipe_per_mec = 4;
4371                 adev->gfx.mec.num_queue_per_pipe = 8;
4372                 break;
4373         case CHIP_SIENNA_CICHLID:
4374         case CHIP_NAVY_FLOUNDER:
4375         case CHIP_VANGOGH:
4376                 adev->gfx.me.num_me = 1;
4377                 adev->gfx.me.num_pipe_per_me = 1;
4378                 adev->gfx.me.num_queue_per_pipe = 1;
4379                 adev->gfx.mec.num_mec = 2;
4380                 adev->gfx.mec.num_pipe_per_mec = 4;
4381                 adev->gfx.mec.num_queue_per_pipe = 4;
4382                 break;
4383         default:
4384                 adev->gfx.me.num_me = 1;
4385                 adev->gfx.me.num_pipe_per_me = 1;
4386                 adev->gfx.me.num_queue_per_pipe = 1;
4387                 adev->gfx.mec.num_mec = 1;
4388                 adev->gfx.mec.num_pipe_per_mec = 4;
4389                 adev->gfx.mec.num_queue_per_pipe = 8;
4390                 break;
4391         }
4392
4393         /* KIQ event */
4394         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4395                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4396                               &adev->gfx.kiq.irq);
4397         if (r)
4398                 return r;
4399
4400         /* EOP Event */
4401         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4402                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4403                               &adev->gfx.eop_irq);
4404         if (r)
4405                 return r;
4406
4407         /* Privileged reg */
4408         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4409                               &adev->gfx.priv_reg_irq);
4410         if (r)
4411                 return r;
4412
4413         /* Privileged inst */
4414         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4415                               &adev->gfx.priv_inst_irq);
4416         if (r)
4417                 return r;
4418
4419         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4420
4421         gfx_v10_0_scratch_init(adev);
4422
4423         r = gfx_v10_0_me_init(adev);
4424         if (r)
4425                 return r;
4426
4427         r = gfx_v10_0_rlc_init(adev);
4428         if (r) {
4429                 DRM_ERROR("Failed to init rlc BOs!\n");
4430                 return r;
4431         }
4432
4433         r = gfx_v10_0_mec_init(adev);
4434         if (r) {
4435                 DRM_ERROR("Failed to init MEC BOs!\n");
4436                 return r;
4437         }
4438
4439         /* set up the gfx ring */
4440         for (i = 0; i < adev->gfx.me.num_me; i++) {
4441                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4442                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4443                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4444                                         continue;
4445
4446                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4447                                                             i, k, j);
4448                                 if (r)
4449                                         return r;
4450                                 ring_id++;
4451                         }
4452                 }
4453         }
4454
4455         ring_id = 0;
4456         /* set up the compute queues - allocate horizontally across pipes */
4457         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4458                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4459                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4460                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4461                                                                      j))
4462                                         continue;
4463
4464                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4465                                                                 i, k, j);
4466                                 if (r)
4467                                         return r;
4468
4469                                 ring_id++;
4470                         }
4471                 }
4472         }
4473
4474         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4475         if (r) {
4476                 DRM_ERROR("Failed to init KIQ BOs!\n");
4477                 return r;
4478         }
4479
4480         kiq = &adev->gfx.kiq;
4481         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4482         if (r)
4483                 return r;
4484
4485         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4486         if (r)
4487                 return r;
4488
4489         /* allocate visible FB for rlc auto-loading fw */
4490         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4491                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4492                 if (r)
4493                         return r;
4494         }
4495
4496         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4497
4498         gfx_v10_0_gpu_early_init(adev);
4499
4500         return 0;
4501 }
4502
4503 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4504 {
4505         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4506                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4507                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4508 }
4509
4510 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4511 {
4512         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4513                               &adev->gfx.ce.ce_fw_gpu_addr,
4514                               (void **)&adev->gfx.ce.ce_fw_ptr);
4515 }
4516
4517 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4518 {
4519         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4520                               &adev->gfx.me.me_fw_gpu_addr,
4521                               (void **)&adev->gfx.me.me_fw_ptr);
4522 }
4523
4524 static int gfx_v10_0_sw_fini(void *handle)
4525 {
4526         int i;
4527         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4528
4529         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4530                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4531         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4532                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4533
4534         amdgpu_gfx_mqd_sw_fini(adev);
4535         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4536         amdgpu_gfx_kiq_fini(adev);
4537
4538         gfx_v10_0_pfp_fini(adev);
4539         gfx_v10_0_ce_fini(adev);
4540         gfx_v10_0_me_fini(adev);
4541         gfx_v10_0_rlc_fini(adev);
4542         gfx_v10_0_mec_fini(adev);
4543
4544         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4545                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4546
4547         gfx_v10_0_free_microcode(adev);
4548
4549         return 0;
4550 }
4551
4552 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4553                                    u32 sh_num, u32 instance)
4554 {
4555         u32 data;
4556
4557         if (instance == 0xffffffff)
4558                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4559                                      INSTANCE_BROADCAST_WRITES, 1);
4560         else
4561                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4562                                      instance);
4563
4564         if (se_num == 0xffffffff)
4565                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4566                                      1);
4567         else
4568                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4569
4570         if (sh_num == 0xffffffff)
4571                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4572                                      1);
4573         else
4574                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4575
4576         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4577 }
4578
4579 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4580 {
4581         u32 data, mask;
4582
4583         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4584         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4585
4586         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4587         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4588
4589         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4590                                          adev->gfx.config.max_sh_per_se);
4591
4592         return (~data) & mask;
4593 }
4594
4595 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4596 {
4597         int i, j;
4598         u32 data;
4599         u32 active_rbs = 0;
4600         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4601                                         adev->gfx.config.max_sh_per_se;
4602
4603         mutex_lock(&adev->grbm_idx_mutex);
4604         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4605                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4606                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4607                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4608                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4609                                                rb_bitmap_width_per_sh);
4610                 }
4611         }
4612         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4613         mutex_unlock(&adev->grbm_idx_mutex);
4614
4615         adev->gfx.config.backend_enable_mask = active_rbs;
4616         adev->gfx.config.num_rbs = hweight32(active_rbs);
4617 }
4618
4619 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4620 {
4621         uint32_t num_sc;
4622         uint32_t enabled_rb_per_sh;
4623         uint32_t active_rb_bitmap;
4624         uint32_t num_rb_per_sc;
4625         uint32_t num_packer_per_sc;
4626         uint32_t pa_sc_tile_steering_override;
4627
4628         /* for ASICs that integrates GFX v10.3
4629          * pa_sc_tile_steering_override should be set to 0 */
4630         if (adev->asic_type == CHIP_SIENNA_CICHLID ||
4631             adev->asic_type == CHIP_NAVY_FLOUNDER ||
4632             adev->asic_type == CHIP_VANGOGH)
4633                 return 0;
4634
4635         /* init num_sc */
4636         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4637                         adev->gfx.config.num_sc_per_sh;
4638         /* init num_rb_per_sc */
4639         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4640         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4641         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4642         /* init num_packer_per_sc */
4643         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4644
4645         pa_sc_tile_steering_override = 0;
4646         pa_sc_tile_steering_override |=
4647                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4648                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4649         pa_sc_tile_steering_override |=
4650                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4651                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4652         pa_sc_tile_steering_override |=
4653                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4654                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4655
4656         return pa_sc_tile_steering_override;
4657 }
4658
4659 #define DEFAULT_SH_MEM_BASES    (0x6000)
4660
4661 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4662 {
4663         int i;
4664         uint32_t sh_mem_bases;
4665
4666         /*
4667          * Configure apertures:
4668          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4669          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4670          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4671          */
4672         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4673
4674         mutex_lock(&adev->srbm_mutex);
4675         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4676                 nv_grbm_select(adev, 0, 0, 0, i);
4677                 /* CP and shaders */
4678                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4679                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4680         }
4681         nv_grbm_select(adev, 0, 0, 0, 0);
4682         mutex_unlock(&adev->srbm_mutex);
4683
4684         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4685            acccess. These should be enabled by FW for target VMIDs. */
4686         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4687                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4688                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4689                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4690                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4691         }
4692 }
4693
4694 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4695 {
4696         int vmid;
4697
4698         /*
4699          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4700          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4701          * the driver can enable them for graphics. VMID0 should maintain
4702          * access so that HWS firmware can save/restore entries.
4703          */
4704         for (vmid = 1; vmid < 16; vmid++) {
4705                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4706                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4707                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4708                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4709         }
4710 }
4711
4712
4713 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4714 {
4715         int i, j, k;
4716         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4717         u32 tmp, wgp_active_bitmap = 0;
4718         u32 gcrd_targets_disable_tcp = 0;
4719         u32 utcl_invreq_disable = 0;
4720         /*
4721          * GCRD_TARGETS_DISABLE field contains
4722          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4723          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4724          */
4725         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4726                 2 * max_wgp_per_sh + /* TCP */
4727                 max_wgp_per_sh + /* SQC */
4728                 4); /* GL1C */
4729         /*
4730          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4731          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4732          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4733          */
4734         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4735                 2 * max_wgp_per_sh + /* TCP */
4736                 2 * max_wgp_per_sh + /* SQC */
4737                 4 + /* RMI */
4738                 1); /* SQG */
4739
4740         if (adev->asic_type == CHIP_NAVI10 ||
4741             adev->asic_type == CHIP_NAVI14 ||
4742             adev->asic_type == CHIP_NAVI12) {
4743                 mutex_lock(&adev->grbm_idx_mutex);
4744                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4745                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4746                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4747                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4748                                 /*
4749                                  * Set corresponding TCP bits for the inactive WGPs in
4750                                  * GCRD_SA_TARGETS_DISABLE
4751                                  */
4752                                 gcrd_targets_disable_tcp = 0;
4753                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4754                                 utcl_invreq_disable = 0;
4755
4756                                 for (k = 0; k < max_wgp_per_sh; k++) {
4757                                         if (!(wgp_active_bitmap & (1 << k))) {
4758                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
4759                                                 utcl_invreq_disable |= (3 << (2 * k)) |
4760                                                         (3 << (2 * (max_wgp_per_sh + k)));
4761                                         }
4762                                 }
4763
4764                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4765                                 /* only override TCP & SQC bits */
4766                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4767                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4768                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4769
4770                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4771                                 /* only override TCP bits */
4772                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4773                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4774                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4775                         }
4776                 }
4777
4778                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4779                 mutex_unlock(&adev->grbm_idx_mutex);
4780         }
4781 }
4782
4783 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4784 {
4785         /* TCCs are global (not instanced). */
4786         uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4787                                RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4788
4789         adev->gfx.config.tcc_disabled_mask =
4790                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4791                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4792 }
4793
4794 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4795 {
4796         u32 tmp;
4797         int i;
4798
4799         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4800
4801         gfx_v10_0_setup_rb(adev);
4802         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4803         gfx_v10_0_get_tcc_info(adev);
4804         adev->gfx.config.pa_sc_tile_steering_override =
4805                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4806
4807         /* XXX SH_MEM regs */
4808         /* where to put LDS, scratch, GPUVM in FSA64 space */
4809         mutex_lock(&adev->srbm_mutex);
4810         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4811                 nv_grbm_select(adev, 0, 0, 0, i);
4812                 /* CP and shaders */
4813                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4814                 if (i != 0) {
4815                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4816                                 (adev->gmc.private_aperture_start >> 48));
4817                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4818                                 (adev->gmc.shared_aperture_start >> 48));
4819                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4820                 }
4821         }
4822         nv_grbm_select(adev, 0, 0, 0, 0);
4823
4824         mutex_unlock(&adev->srbm_mutex);
4825
4826         gfx_v10_0_init_compute_vmid(adev);
4827         gfx_v10_0_init_gds_vmid(adev);
4828
4829 }
4830
4831 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4832                                                bool enable)
4833 {
4834         u32 tmp;
4835
4836         if (amdgpu_sriov_vf(adev))
4837                 return;
4838
4839         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
4840
4841         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
4842                             enable ? 1 : 0);
4843         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
4844                             enable ? 1 : 0);
4845         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
4846                             enable ? 1 : 0);
4847         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
4848                             enable ? 1 : 0);
4849
4850         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
4851 }
4852
4853 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
4854 {
4855         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
4856
4857         /* csib */
4858         if (adev->asic_type == CHIP_NAVI12) {
4859                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
4860                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
4861                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
4862                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4863                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4864         } else {
4865                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
4866                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
4867                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
4868                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4869                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4870         }
4871         return 0;
4872 }
4873
4874 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
4875 {
4876         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4877
4878         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
4879         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
4880 }
4881
4882 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
4883 {
4884         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4885         udelay(50);
4886         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4887         udelay(50);
4888 }
4889
4890 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
4891                                              bool enable)
4892 {
4893         uint32_t rlc_pg_cntl;
4894
4895         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
4896
4897         if (!enable) {
4898                 /* RLC_PG_CNTL[23] = 0 (default)
4899                  * RLC will wait for handshake acks with SMU
4900                  * GFXOFF will be enabled
4901                  * RLC_PG_CNTL[23] = 1
4902                  * RLC will not issue any message to SMU
4903                  * hence no handshake between SMU & RLC
4904                  * GFXOFF will be disabled
4905                  */
4906                 rlc_pg_cntl |= 0x800000;
4907         } else
4908                 rlc_pg_cntl &= ~0x800000;
4909         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
4910 }
4911
4912 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
4913 {
4914         /* TODO: enable rlc & smu handshake until smu
4915          * and gfxoff feature works as expected */
4916         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
4917                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
4918
4919         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
4920         udelay(50);
4921 }
4922
4923 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
4924 {
4925         uint32_t tmp;
4926
4927         /* enable Save Restore Machine */
4928         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
4929         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
4930         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
4931         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
4932 }
4933
4934 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
4935 {
4936         const struct rlc_firmware_header_v2_0 *hdr;
4937         const __le32 *fw_data;
4938         unsigned i, fw_size;
4939
4940         if (!adev->gfx.rlc_fw)
4941                 return -EINVAL;
4942
4943         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4944         amdgpu_ucode_print_rlc_hdr(&hdr->header);
4945
4946         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
4947                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4948         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
4949
4950         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
4951                      RLCG_UCODE_LOADING_START_ADDRESS);
4952
4953         for (i = 0; i < fw_size; i++)
4954                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
4955                              le32_to_cpup(fw_data++));
4956
4957         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
4958
4959         return 0;
4960 }
4961
4962 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
4963 {
4964         int r;
4965
4966         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4967
4968                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4969                 if (r)
4970                         return r;
4971
4972                 gfx_v10_0_init_csb(adev);
4973
4974                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
4975                         gfx_v10_0_rlc_enable_srm(adev);
4976         } else {
4977                 if (amdgpu_sriov_vf(adev)) {
4978                         gfx_v10_0_init_csb(adev);
4979                         return 0;
4980                 }
4981
4982                 adev->gfx.rlc.funcs->stop(adev);
4983
4984                 /* disable CG */
4985                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
4986
4987                 /* disable PG */
4988                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
4989
4990                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4991                         /* legacy rlc firmware loading */
4992                         r = gfx_v10_0_rlc_load_microcode(adev);
4993                         if (r)
4994                                 return r;
4995                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4996                         /* rlc backdoor autoload firmware */
4997                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
4998                         if (r)
4999                                 return r;
5000                 }
5001
5002                 gfx_v10_0_init_csb(adev);
5003
5004                 adev->gfx.rlc.funcs->start(adev);
5005
5006                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5007                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5008                         if (r)
5009                                 return r;
5010                 }
5011         }
5012         return 0;
5013 }
5014
5015 static struct {
5016         FIRMWARE_ID     id;
5017         unsigned int    offset;
5018         unsigned int    size;
5019 } rlc_autoload_info[FIRMWARE_ID_MAX];
5020
5021 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5022 {
5023         int ret;
5024         RLC_TABLE_OF_CONTENT *rlc_toc;
5025
5026         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5027                                         AMDGPU_GEM_DOMAIN_GTT,
5028                                         &adev->gfx.rlc.rlc_toc_bo,
5029                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5030                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5031         if (ret) {
5032                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5033                 return ret;
5034         }
5035
5036         /* Copy toc from psp sos fw to rlc toc buffer */
5037         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5038
5039         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5040         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5041                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5042                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5043                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5044                         /* Offset needs 4KB alignment */
5045                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5046                 }
5047
5048                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5049                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5050                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5051
5052                 rlc_toc++;
5053         }
5054
5055         return 0;
5056 }
5057
5058 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5059 {
5060         uint32_t total_size = 0;
5061         FIRMWARE_ID id;
5062         int ret;
5063
5064         ret = gfx_v10_0_parse_rlc_toc(adev);
5065         if (ret) {
5066                 dev_err(adev->dev, "failed to parse rlc toc\n");
5067                 return 0;
5068         }
5069
5070         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5071                 total_size += rlc_autoload_info[id].size;
5072
5073         /* In case the offset in rlc toc ucode is aligned */
5074         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5075                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5076                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5077
5078         return total_size;
5079 }
5080
5081 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5082 {
5083         int r;
5084         uint32_t total_size;
5085
5086         total_size = gfx_v10_0_calc_toc_total_size(adev);
5087
5088         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5089                                       AMDGPU_GEM_DOMAIN_GTT,
5090                                       &adev->gfx.rlc.rlc_autoload_bo,
5091                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5092                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5093         if (r) {
5094                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5095                 return r;
5096         }
5097
5098         return 0;
5099 }
5100
5101 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5102 {
5103         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5104                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5105                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5106         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5107                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5108                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5109 }
5110
5111 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5112                                                        FIRMWARE_ID id,
5113                                                        const void *fw_data,
5114                                                        uint32_t fw_size)
5115 {
5116         uint32_t toc_offset;
5117         uint32_t toc_fw_size;
5118         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5119
5120         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5121                 return;
5122
5123         toc_offset = rlc_autoload_info[id].offset;
5124         toc_fw_size = rlc_autoload_info[id].size;
5125
5126         if (fw_size == 0)
5127                 fw_size = toc_fw_size;
5128
5129         if (fw_size > toc_fw_size)
5130                 fw_size = toc_fw_size;
5131
5132         memcpy(ptr + toc_offset, fw_data, fw_size);
5133
5134         if (fw_size < toc_fw_size)
5135                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5136 }
5137
5138 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5139 {
5140         void *data;
5141         uint32_t size;
5142
5143         data = adev->gfx.rlc.rlc_toc_buf;
5144         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5145
5146         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5147                                                    FIRMWARE_ID_RLC_TOC,
5148                                                    data, size);
5149 }
5150
5151 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5152 {
5153         const __le32 *fw_data;
5154         uint32_t fw_size;
5155         const struct gfx_firmware_header_v1_0 *cp_hdr;
5156         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5157
5158         /* pfp ucode */
5159         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5160                 adev->gfx.pfp_fw->data;
5161         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5162                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5163         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5164         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5165                                                    FIRMWARE_ID_CP_PFP,
5166                                                    fw_data, fw_size);
5167
5168         /* ce ucode */
5169         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5170                 adev->gfx.ce_fw->data;
5171         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5172                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5173         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5174         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5175                                                    FIRMWARE_ID_CP_CE,
5176                                                    fw_data, fw_size);
5177
5178         /* me ucode */
5179         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5180                 adev->gfx.me_fw->data;
5181         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5182                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5183         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5184         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5185                                                    FIRMWARE_ID_CP_ME,
5186                                                    fw_data, fw_size);
5187
5188         /* rlc ucode */
5189         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5190                 adev->gfx.rlc_fw->data;
5191         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5192                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5193         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5194         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5195                                                    FIRMWARE_ID_RLC_G_UCODE,
5196                                                    fw_data, fw_size);
5197
5198         /* mec1 ucode */
5199         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5200                 adev->gfx.mec_fw->data;
5201         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5202                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5203         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5204                 cp_hdr->jt_size * 4;
5205         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5206                                                    FIRMWARE_ID_CP_MEC,
5207                                                    fw_data, fw_size);
5208         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5209 }
5210
5211 /* Temporarily put sdma part here */
5212 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5213 {
5214         const __le32 *fw_data;
5215         uint32_t fw_size;
5216         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5217         int i;
5218
5219         for (i = 0; i < adev->sdma.num_instances; i++) {
5220                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5221                         adev->sdma.instance[i].fw->data;
5222                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5223                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5224                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5225
5226                 if (i == 0) {
5227                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5228                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5229                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5230                                 FIRMWARE_ID_SDMA0_JT,
5231                                 (uint32_t *)fw_data +
5232                                 sdma_hdr->jt_offset,
5233                                 sdma_hdr->jt_size * 4);
5234                 } else if (i == 1) {
5235                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5236                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5237                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5238                                 FIRMWARE_ID_SDMA1_JT,
5239                                 (uint32_t *)fw_data +
5240                                 sdma_hdr->jt_offset,
5241                                 sdma_hdr->jt_size * 4);
5242                 }
5243         }
5244 }
5245
5246 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5247 {
5248         uint32_t rlc_g_offset, rlc_g_size, tmp;
5249         uint64_t gpu_addr;
5250
5251         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5252         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5253         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5254
5255         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5256         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5257         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5258
5259         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5260         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5261         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5262
5263         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5264         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5265                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5266                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5267                 return -EINVAL;
5268         }
5269
5270         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5271         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5272                 DRM_ERROR("RLC ROM should halt itself\n");
5273                 return -EINVAL;
5274         }
5275
5276         return 0;
5277 }
5278
5279 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5280 {
5281         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5282         uint32_t tmp;
5283         int i;
5284         uint64_t addr;
5285
5286         /* Trigger an invalidation of the L1 instruction caches */
5287         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5288         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5289         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5290
5291         /* Wait for invalidation complete */
5292         for (i = 0; i < usec_timeout; i++) {
5293                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5294                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5295                         INVALIDATE_CACHE_COMPLETE))
5296                         break;
5297                 udelay(1);
5298         }
5299
5300         if (i >= usec_timeout) {
5301                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5302                 return -EINVAL;
5303         }
5304
5305         /* Program me ucode address into intruction cache address register */
5306         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5307                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5308         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5309                         lower_32_bits(addr) & 0xFFFFF000);
5310         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5311                         upper_32_bits(addr));
5312
5313         return 0;
5314 }
5315
5316 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5317 {
5318         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5319         uint32_t tmp;
5320         int i;
5321         uint64_t addr;
5322
5323         /* Trigger an invalidation of the L1 instruction caches */
5324         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5325         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5326         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5327
5328         /* Wait for invalidation complete */
5329         for (i = 0; i < usec_timeout; i++) {
5330                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5331                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5332                         INVALIDATE_CACHE_COMPLETE))
5333                         break;
5334                 udelay(1);
5335         }
5336
5337         if (i >= usec_timeout) {
5338                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5339                 return -EINVAL;
5340         }
5341
5342         /* Program ce ucode address into intruction cache address register */
5343         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5344                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5345         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5346                         lower_32_bits(addr) & 0xFFFFF000);
5347         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5348                         upper_32_bits(addr));
5349
5350         return 0;
5351 }
5352
5353 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5354 {
5355         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5356         uint32_t tmp;
5357         int i;
5358         uint64_t addr;
5359
5360         /* Trigger an invalidation of the L1 instruction caches */
5361         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5362         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5363         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5364
5365         /* Wait for invalidation complete */
5366         for (i = 0; i < usec_timeout; i++) {
5367                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5368                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5369                         INVALIDATE_CACHE_COMPLETE))
5370                         break;
5371                 udelay(1);
5372         }
5373
5374         if (i >= usec_timeout) {
5375                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5376                 return -EINVAL;
5377         }
5378
5379         /* Program pfp ucode address into intruction cache address register */
5380         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5381                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5382         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5383                         lower_32_bits(addr) & 0xFFFFF000);
5384         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5385                         upper_32_bits(addr));
5386
5387         return 0;
5388 }
5389
5390 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5391 {
5392         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5393         uint32_t tmp;
5394         int i;
5395         uint64_t addr;
5396
5397         /* Trigger an invalidation of the L1 instruction caches */
5398         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5399         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5400         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5401
5402         /* Wait for invalidation complete */
5403         for (i = 0; i < usec_timeout; i++) {
5404                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5405                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5406                         INVALIDATE_CACHE_COMPLETE))
5407                         break;
5408                 udelay(1);
5409         }
5410
5411         if (i >= usec_timeout) {
5412                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5413                 return -EINVAL;
5414         }
5415
5416         /* Program mec1 ucode address into intruction cache address register */
5417         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5418                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5419         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5420                         lower_32_bits(addr) & 0xFFFFF000);
5421         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5422                         upper_32_bits(addr));
5423
5424         return 0;
5425 }
5426
5427 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5428 {
5429         uint32_t cp_status;
5430         uint32_t bootload_status;
5431         int i, r;
5432
5433         for (i = 0; i < adev->usec_timeout; i++) {
5434                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5435                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5436                 if ((cp_status == 0) &&
5437                     (REG_GET_FIELD(bootload_status,
5438                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5439                         break;
5440                 }
5441                 udelay(1);
5442         }
5443
5444         if (i >= adev->usec_timeout) {
5445                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5446                 return -ETIMEDOUT;
5447         }
5448
5449         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5450                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5451                 if (r)
5452                         return r;
5453
5454                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5455                 if (r)
5456                         return r;
5457
5458                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5459                 if (r)
5460                         return r;
5461
5462                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5463                 if (r)
5464                         return r;
5465         }
5466
5467         return 0;
5468 }
5469
5470 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5471 {
5472         int i;
5473         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5474
5475         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5476         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5477         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5478
5479         if (adev->asic_type == CHIP_NAVI12) {
5480                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5481         } else {
5482                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5483         }
5484
5485         for (i = 0; i < adev->usec_timeout; i++) {
5486                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5487                         break;
5488                 udelay(1);
5489         }
5490
5491         if (i >= adev->usec_timeout)
5492                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5493
5494         return 0;
5495 }
5496
5497 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5498 {
5499         int r;
5500         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5501         const __le32 *fw_data;
5502         unsigned i, fw_size;
5503         uint32_t tmp;
5504         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5505
5506         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5507                 adev->gfx.pfp_fw->data;
5508
5509         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5510
5511         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5512                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5513         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5514
5515         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5516                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5517                                       &adev->gfx.pfp.pfp_fw_obj,
5518                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5519                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5520         if (r) {
5521                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5522                 gfx_v10_0_pfp_fini(adev);
5523                 return r;
5524         }
5525
5526         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5527
5528         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5529         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5530
5531         /* Trigger an invalidation of the L1 instruction caches */
5532         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5533         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5534         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5535
5536         /* Wait for invalidation complete */
5537         for (i = 0; i < usec_timeout; i++) {
5538                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5539                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5540                         INVALIDATE_CACHE_COMPLETE))
5541                         break;
5542                 udelay(1);
5543         }
5544
5545         if (i >= usec_timeout) {
5546                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5547                 return -EINVAL;
5548         }
5549
5550         if (amdgpu_emu_mode == 1)
5551                 adev->nbio.funcs->hdp_flush(adev, NULL);
5552
5553         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5554         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5555         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5556         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5557         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5558         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5559         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5560                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5561         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5562                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5563
5564         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5565
5566         for (i = 0; i < pfp_hdr->jt_size; i++)
5567                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5568                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5569
5570         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5571
5572         return 0;
5573 }
5574
5575 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5576 {
5577         int r;
5578         const struct gfx_firmware_header_v1_0 *ce_hdr;
5579         const __le32 *fw_data;
5580         unsigned i, fw_size;
5581         uint32_t tmp;
5582         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5583
5584         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5585                 adev->gfx.ce_fw->data;
5586
5587         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5588
5589         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5590                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5591         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5592
5593         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5594                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5595                                       &adev->gfx.ce.ce_fw_obj,
5596                                       &adev->gfx.ce.ce_fw_gpu_addr,
5597                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5598         if (r) {
5599                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5600                 gfx_v10_0_ce_fini(adev);
5601                 return r;
5602         }
5603
5604         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5605
5606         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5607         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5608
5609         /* Trigger an invalidation of the L1 instruction caches */
5610         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5611         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5612         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5613
5614         /* Wait for invalidation complete */
5615         for (i = 0; i < usec_timeout; i++) {
5616                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5617                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5618                         INVALIDATE_CACHE_COMPLETE))
5619                         break;
5620                 udelay(1);
5621         }
5622
5623         if (i >= usec_timeout) {
5624                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5625                 return -EINVAL;
5626         }
5627
5628         if (amdgpu_emu_mode == 1)
5629                 adev->nbio.funcs->hdp_flush(adev, NULL);
5630
5631         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5632         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5633         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5634         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5635         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5636         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5637                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5638         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5639                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5640
5641         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5642
5643         for (i = 0; i < ce_hdr->jt_size; i++)
5644                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5645                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5646
5647         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5648
5649         return 0;
5650 }
5651
5652 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5653 {
5654         int r;
5655         const struct gfx_firmware_header_v1_0 *me_hdr;
5656         const __le32 *fw_data;
5657         unsigned i, fw_size;
5658         uint32_t tmp;
5659         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5660
5661         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5662                 adev->gfx.me_fw->data;
5663
5664         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5665
5666         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5667                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5668         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5669
5670         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5671                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5672                                       &adev->gfx.me.me_fw_obj,
5673                                       &adev->gfx.me.me_fw_gpu_addr,
5674                                       (void **)&adev->gfx.me.me_fw_ptr);
5675         if (r) {
5676                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5677                 gfx_v10_0_me_fini(adev);
5678                 return r;
5679         }
5680
5681         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5682
5683         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5684         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5685
5686         /* Trigger an invalidation of the L1 instruction caches */
5687         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5688         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5689         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5690
5691         /* Wait for invalidation complete */
5692         for (i = 0; i < usec_timeout; i++) {
5693                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5694                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5695                         INVALIDATE_CACHE_COMPLETE))
5696                         break;
5697                 udelay(1);
5698         }
5699
5700         if (i >= usec_timeout) {
5701                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5702                 return -EINVAL;
5703         }
5704
5705         if (amdgpu_emu_mode == 1)
5706                 adev->nbio.funcs->hdp_flush(adev, NULL);
5707
5708         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5709         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5710         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5711         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5712         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5713         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5714                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5715         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5716                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5717
5718         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5719
5720         for (i = 0; i < me_hdr->jt_size; i++)
5721                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5722                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5723
5724         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5725
5726         return 0;
5727 }
5728
5729 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5730 {
5731         int r;
5732
5733         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5734                 return -EINVAL;
5735
5736         gfx_v10_0_cp_gfx_enable(adev, false);
5737
5738         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5739         if (r) {
5740                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5741                 return r;
5742         }
5743
5744         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5745         if (r) {
5746                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5747                 return r;
5748         }
5749
5750         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5751         if (r) {
5752                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5753                 return r;
5754         }
5755
5756         return 0;
5757 }
5758
5759 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5760 {
5761         struct amdgpu_ring *ring;
5762         const struct cs_section_def *sect = NULL;
5763         const struct cs_extent_def *ext = NULL;
5764         int r, i;
5765         int ctx_reg_offset;
5766
5767         /* init the CP */
5768         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5769                      adev->gfx.config.max_hw_contexts - 1);
5770         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5771
5772         gfx_v10_0_cp_gfx_enable(adev, true);
5773
5774         ring = &adev->gfx.gfx_ring[0];
5775         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5776         if (r) {
5777                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5778                 return r;
5779         }
5780
5781         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5782         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5783
5784         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5785         amdgpu_ring_write(ring, 0x80000000);
5786         amdgpu_ring_write(ring, 0x80000000);
5787
5788         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5789                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5790                         if (sect->id == SECT_CONTEXT) {
5791                                 amdgpu_ring_write(ring,
5792                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5793                                                           ext->reg_count));
5794                                 amdgpu_ring_write(ring, ext->reg_index -
5795                                                   PACKET3_SET_CONTEXT_REG_START);
5796                                 for (i = 0; i < ext->reg_count; i++)
5797                                         amdgpu_ring_write(ring, ext->extent[i]);
5798                         }
5799                 }
5800         }
5801
5802         ctx_reg_offset =
5803                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5804         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5805         amdgpu_ring_write(ring, ctx_reg_offset);
5806         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5807
5808         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5809         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5810
5811         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5812         amdgpu_ring_write(ring, 0);
5813
5814         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5815         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5816         amdgpu_ring_write(ring, 0x8000);
5817         amdgpu_ring_write(ring, 0x8000);
5818
5819         amdgpu_ring_commit(ring);
5820
5821         /* submit cs packet to copy state 0 to next available state */
5822         if (adev->gfx.num_gfx_rings > 1) {
5823                 /* maximum supported gfx ring is 2 */
5824                 ring = &adev->gfx.gfx_ring[1];
5825                 r = amdgpu_ring_alloc(ring, 2);
5826                 if (r) {
5827                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5828                         return r;
5829                 }
5830
5831                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5832                 amdgpu_ring_write(ring, 0);
5833
5834                 amdgpu_ring_commit(ring);
5835         }
5836         return 0;
5837 }
5838
5839 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
5840                                          CP_PIPE_ID pipe)
5841 {
5842         u32 tmp;
5843
5844         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
5845         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
5846
5847         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
5848 }
5849
5850 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
5851                                           struct amdgpu_ring *ring)
5852 {
5853         u32 tmp;
5854
5855         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
5856         if (ring->use_doorbell) {
5857                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5858                                     DOORBELL_OFFSET, ring->doorbell_index);
5859                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5860                                     DOORBELL_EN, 1);
5861         } else {
5862                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5863                                     DOORBELL_EN, 0);
5864         }
5865         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
5866         switch (adev->asic_type) {
5867         case CHIP_SIENNA_CICHLID:
5868         case CHIP_NAVY_FLOUNDER:
5869         case CHIP_VANGOGH:
5870                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5871                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
5872                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5873
5874                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5875                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
5876                 break;
5877         default:
5878                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5879                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
5880                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5881
5882                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5883                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
5884                 break;
5885         }
5886 }
5887
5888 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
5889 {
5890         struct amdgpu_ring *ring;
5891         u32 tmp;
5892         u32 rb_bufsz;
5893         u64 rb_addr, rptr_addr, wptr_gpu_addr;
5894         u32 i;
5895
5896         /* Set the write pointer delay */
5897         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
5898
5899         /* set the RB to use vmid 0 */
5900         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
5901
5902         /* Init gfx ring 0 for pipe 0 */
5903         mutex_lock(&adev->srbm_mutex);
5904         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5905
5906         /* Set ring buffer size */
5907         ring = &adev->gfx.gfx_ring[0];
5908         rb_bufsz = order_base_2(ring->ring_size / 8);
5909         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
5910         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
5911 #ifdef __BIG_ENDIAN
5912         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
5913 #endif
5914         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5915
5916         /* Initialize the ring buffer's write pointers */
5917         ring->wptr = 0;
5918         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
5919         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
5920
5921         /* set the wb address wether it's enabled or not */
5922         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5923         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
5924         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5925                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5926
5927         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5928         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5929                      lower_32_bits(wptr_gpu_addr));
5930         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5931                      upper_32_bits(wptr_gpu_addr));
5932
5933         mdelay(1);
5934         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5935
5936         rb_addr = ring->gpu_addr >> 8;
5937         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
5938         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
5939
5940         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
5941
5942         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5943         mutex_unlock(&adev->srbm_mutex);
5944
5945         /* Init gfx ring 1 for pipe 1 */
5946         if (adev->gfx.num_gfx_rings > 1) {
5947                 mutex_lock(&adev->srbm_mutex);
5948                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
5949                 /* maximum supported gfx ring is 2 */
5950                 ring = &adev->gfx.gfx_ring[1];
5951                 rb_bufsz = order_base_2(ring->ring_size / 8);
5952                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
5953                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
5954                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5955                 /* Initialize the ring buffer's write pointers */
5956                 ring->wptr = 0;
5957                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
5958                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
5959                 /* Set the wb address wether it's enabled or not */
5960                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5961                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
5962                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5963                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5964                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5965                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5966                              lower_32_bits(wptr_gpu_addr));
5967                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5968                              upper_32_bits(wptr_gpu_addr));
5969
5970                 mdelay(1);
5971                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5972
5973                 rb_addr = ring->gpu_addr >> 8;
5974                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
5975                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
5976                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
5977
5978                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5979                 mutex_unlock(&adev->srbm_mutex);
5980         }
5981         /* Switch to pipe 0 */
5982         mutex_lock(&adev->srbm_mutex);
5983         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5984         mutex_unlock(&adev->srbm_mutex);
5985
5986         /* start the ring */
5987         gfx_v10_0_cp_gfx_start(adev);
5988
5989         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5990                 ring = &adev->gfx.gfx_ring[i];
5991                 ring->sched.ready = true;
5992         }
5993
5994         return 0;
5995 }
5996
5997 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
5998 {
5999         if (enable) {
6000                 switch (adev->asic_type) {
6001                 case CHIP_SIENNA_CICHLID:
6002                 case CHIP_NAVY_FLOUNDER:
6003                 case CHIP_VANGOGH:
6004                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6005                         break;
6006                 default:
6007                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6008                         break;
6009                 }
6010         } else {
6011                 switch (adev->asic_type) {
6012                 case CHIP_SIENNA_CICHLID:
6013                 case CHIP_NAVY_FLOUNDER:
6014                 case CHIP_VANGOGH:
6015                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6016                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6017                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6018                         break;
6019                 default:
6020                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6021                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6022                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6023                         break;
6024                 }
6025                 adev->gfx.kiq.ring.sched.ready = false;
6026         }
6027         udelay(50);
6028 }
6029
6030 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6031 {
6032         const struct gfx_firmware_header_v1_0 *mec_hdr;
6033         const __le32 *fw_data;
6034         unsigned i;
6035         u32 tmp;
6036         u32 usec_timeout = 50000; /* Wait for 50 ms */
6037
6038         if (!adev->gfx.mec_fw)
6039                 return -EINVAL;
6040
6041         gfx_v10_0_cp_compute_enable(adev, false);
6042
6043         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6044         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6045
6046         fw_data = (const __le32 *)
6047                 (adev->gfx.mec_fw->data +
6048                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6049
6050         /* Trigger an invalidation of the L1 instruction caches */
6051         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6052         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6053         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6054
6055         /* Wait for invalidation complete */
6056         for (i = 0; i < usec_timeout; i++) {
6057                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6058                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6059                                        INVALIDATE_CACHE_COMPLETE))
6060                         break;
6061                 udelay(1);
6062         }
6063
6064         if (i >= usec_timeout) {
6065                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6066                 return -EINVAL;
6067         }
6068
6069         if (amdgpu_emu_mode == 1)
6070                 adev->nbio.funcs->hdp_flush(adev, NULL);
6071
6072         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6073         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6074         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6075         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6076         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6077
6078         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6079                      0xFFFFF000);
6080         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6081                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6082
6083         /* MEC1 */
6084         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6085
6086         for (i = 0; i < mec_hdr->jt_size; i++)
6087                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6088                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6089
6090         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6091
6092         /*
6093          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6094          * different microcode than MEC1.
6095          */
6096
6097         return 0;
6098 }
6099
6100 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6101 {
6102         uint32_t tmp;
6103         struct amdgpu_device *adev = ring->adev;
6104
6105         /* tell RLC which is KIQ queue */
6106         switch (adev->asic_type) {
6107         case CHIP_SIENNA_CICHLID:
6108         case CHIP_NAVY_FLOUNDER:
6109         case CHIP_VANGOGH:
6110                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6111                 tmp &= 0xffffff00;
6112                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6113                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6114                 tmp |= 0x80;
6115                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6116                 break;
6117         default:
6118                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6119                 tmp &= 0xffffff00;
6120                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6121                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6122                 tmp |= 0x80;
6123                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6124                 break;
6125         }
6126 }
6127
6128 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6129 {
6130         struct amdgpu_device *adev = ring->adev;
6131         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6132         uint64_t hqd_gpu_addr, wb_gpu_addr;
6133         uint32_t tmp;
6134         uint32_t rb_bufsz;
6135
6136         /* set up gfx hqd wptr */
6137         mqd->cp_gfx_hqd_wptr = 0;
6138         mqd->cp_gfx_hqd_wptr_hi = 0;
6139
6140         /* set the pointer to the MQD */
6141         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6142         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6143
6144         /* set up mqd control */
6145         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6146         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6147         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6148         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6149         mqd->cp_gfx_mqd_control = tmp;
6150
6151         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6152         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6153         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6154         mqd->cp_gfx_hqd_vmid = 0;
6155
6156         /* set up default queue priority level
6157          * 0x0 = low priority, 0x1 = high priority */
6158         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6159         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6160         mqd->cp_gfx_hqd_queue_priority = tmp;
6161
6162         /* set up time quantum */
6163         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6164         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6165         mqd->cp_gfx_hqd_quantum = tmp;
6166
6167         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6168         hqd_gpu_addr = ring->gpu_addr >> 8;
6169         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6170         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6171
6172         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6173         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6174         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6175         mqd->cp_gfx_hqd_rptr_addr_hi =
6176                 upper_32_bits(wb_gpu_addr) & 0xffff;
6177
6178         /* set up rb_wptr_poll addr */
6179         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6180         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6181         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6182
6183         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6184         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6185         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6186         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6187         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6188 #ifdef __BIG_ENDIAN
6189         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6190 #endif
6191         mqd->cp_gfx_hqd_cntl = tmp;
6192
6193         /* set up cp_doorbell_control */
6194         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6195         if (ring->use_doorbell) {
6196                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6197                                     DOORBELL_OFFSET, ring->doorbell_index);
6198                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6199                                     DOORBELL_EN, 1);
6200         } else
6201                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6202                                     DOORBELL_EN, 0);
6203         mqd->cp_rb_doorbell_control = tmp;
6204
6205         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6206         ring->wptr = 0;
6207         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6208
6209         /* active the queue */
6210         mqd->cp_gfx_hqd_active = 1;
6211
6212         return 0;
6213 }
6214
6215 #ifdef BRING_UP_DEBUG
6216 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6217 {
6218         struct amdgpu_device *adev = ring->adev;
6219         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6220
6221         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6222         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6223         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6224
6225         /* set GFX_MQD_BASE */
6226         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6227         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6228
6229         /* set GFX_MQD_CONTROL */
6230         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6231
6232         /* set GFX_HQD_VMID to 0 */
6233         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6234
6235         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6236                         mqd->cp_gfx_hqd_queue_priority);
6237         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6238
6239         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6240         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6241         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6242
6243         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6244         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6245         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6246
6247         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6248         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6249
6250         /* set RB_WPTR_POLL_ADDR */
6251         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6252         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6253
6254         /* set RB_DOORBELL_CONTROL */
6255         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6256
6257         /* active the queue */
6258         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6259
6260         return 0;
6261 }
6262 #endif
6263
6264 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6265 {
6266         struct amdgpu_device *adev = ring->adev;
6267         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6268         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6269
6270         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6271                 memset((void *)mqd, 0, sizeof(*mqd));
6272                 mutex_lock(&adev->srbm_mutex);
6273                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6274                 gfx_v10_0_gfx_mqd_init(ring);
6275 #ifdef BRING_UP_DEBUG
6276                 gfx_v10_0_gfx_queue_init_register(ring);
6277 #endif
6278                 nv_grbm_select(adev, 0, 0, 0, 0);
6279                 mutex_unlock(&adev->srbm_mutex);
6280                 if (adev->gfx.me.mqd_backup[mqd_idx])
6281                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6282         } else if (amdgpu_in_reset(adev)) {
6283                 /* reset mqd with the backup copy */
6284                 if (adev->gfx.me.mqd_backup[mqd_idx])
6285                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6286                 /* reset the ring */
6287                 ring->wptr = 0;
6288                 adev->wb.wb[ring->wptr_offs] = 0;
6289                 amdgpu_ring_clear_ring(ring);
6290 #ifdef BRING_UP_DEBUG
6291                 mutex_lock(&adev->srbm_mutex);
6292                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6293                 gfx_v10_0_gfx_queue_init_register(ring);
6294                 nv_grbm_select(adev, 0, 0, 0, 0);
6295                 mutex_unlock(&adev->srbm_mutex);
6296 #endif
6297         } else {
6298                 amdgpu_ring_clear_ring(ring);
6299         }
6300
6301         return 0;
6302 }
6303
6304 #ifndef BRING_UP_DEBUG
6305 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6306 {
6307         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6308         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6309         int r, i;
6310
6311         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6312                 return -EINVAL;
6313
6314         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6315                                         adev->gfx.num_gfx_rings);
6316         if (r) {
6317                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6318                 return r;
6319         }
6320
6321         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6322                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6323
6324         return amdgpu_ring_test_helper(kiq_ring);
6325 }
6326 #endif
6327
6328 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6329 {
6330         int r, i;
6331         struct amdgpu_ring *ring;
6332
6333         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6334                 ring = &adev->gfx.gfx_ring[i];
6335
6336                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6337                 if (unlikely(r != 0))
6338                         goto done;
6339
6340                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6341                 if (!r) {
6342                         r = gfx_v10_0_gfx_init_queue(ring);
6343                         amdgpu_bo_kunmap(ring->mqd_obj);
6344                         ring->mqd_ptr = NULL;
6345                 }
6346                 amdgpu_bo_unreserve(ring->mqd_obj);
6347                 if (r)
6348                         goto done;
6349         }
6350 #ifndef BRING_UP_DEBUG
6351         r = gfx_v10_0_kiq_enable_kgq(adev);
6352         if (r)
6353                 goto done;
6354 #endif
6355         r = gfx_v10_0_cp_gfx_start(adev);
6356         if (r)
6357                 goto done;
6358
6359         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6360                 ring = &adev->gfx.gfx_ring[i];
6361                 ring->sched.ready = true;
6362         }
6363 done:
6364         return r;
6365 }
6366
6367 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6368 {
6369         struct amdgpu_device *adev = ring->adev;
6370
6371         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6372                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
6373                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6374                         mqd->cp_hqd_queue_priority =
6375                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6376                 }
6377         }
6378 }
6379
6380 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6381 {
6382         struct amdgpu_device *adev = ring->adev;
6383         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6384         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6385         uint32_t tmp;
6386
6387         mqd->header = 0xC0310800;
6388         mqd->compute_pipelinestat_enable = 0x00000001;
6389         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6390         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6391         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6392         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6393         mqd->compute_misc_reserved = 0x00000003;
6394
6395         eop_base_addr = ring->eop_gpu_addr >> 8;
6396         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6397         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6398
6399         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6400         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6401         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6402                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6403
6404         mqd->cp_hqd_eop_control = tmp;
6405
6406         /* enable doorbell? */
6407         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6408
6409         if (ring->use_doorbell) {
6410                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6411                                     DOORBELL_OFFSET, ring->doorbell_index);
6412                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6413                                     DOORBELL_EN, 1);
6414                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6415                                     DOORBELL_SOURCE, 0);
6416                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6417                                     DOORBELL_HIT, 0);
6418         } else {
6419                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6420                                     DOORBELL_EN, 0);
6421         }
6422
6423         mqd->cp_hqd_pq_doorbell_control = tmp;
6424
6425         /* disable the queue if it's active */
6426         ring->wptr = 0;
6427         mqd->cp_hqd_dequeue_request = 0;
6428         mqd->cp_hqd_pq_rptr = 0;
6429         mqd->cp_hqd_pq_wptr_lo = 0;
6430         mqd->cp_hqd_pq_wptr_hi = 0;
6431
6432         /* set the pointer to the MQD */
6433         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6434         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6435
6436         /* set MQD vmid to 0 */
6437         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6438         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6439         mqd->cp_mqd_control = tmp;
6440
6441         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6442         hqd_gpu_addr = ring->gpu_addr >> 8;
6443         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6444         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6445
6446         /* set up the HQD, this is similar to CP_RB0_CNTL */
6447         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6448         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6449                             (order_base_2(ring->ring_size / 4) - 1));
6450         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6451                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6452 #ifdef __BIG_ENDIAN
6453         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6454 #endif
6455         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6456         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6457         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6458         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6459         mqd->cp_hqd_pq_control = tmp;
6460
6461         /* set the wb address whether it's enabled or not */
6462         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6463         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6464         mqd->cp_hqd_pq_rptr_report_addr_hi =
6465                 upper_32_bits(wb_gpu_addr) & 0xffff;
6466
6467         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6468         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6469         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6470         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6471
6472         tmp = 0;
6473         /* enable the doorbell if requested */
6474         if (ring->use_doorbell) {
6475                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6476                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6477                                 DOORBELL_OFFSET, ring->doorbell_index);
6478
6479                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6480                                     DOORBELL_EN, 1);
6481                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6482                                     DOORBELL_SOURCE, 0);
6483                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6484                                     DOORBELL_HIT, 0);
6485         }
6486
6487         mqd->cp_hqd_pq_doorbell_control = tmp;
6488
6489         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6490         ring->wptr = 0;
6491         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6492
6493         /* set the vmid for the queue */
6494         mqd->cp_hqd_vmid = 0;
6495
6496         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6497         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6498         mqd->cp_hqd_persistent_state = tmp;
6499
6500         /* set MIN_IB_AVAIL_SIZE */
6501         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6502         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6503         mqd->cp_hqd_ib_control = tmp;
6504
6505         /* set static priority for a compute queue/ring */
6506         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6507
6508         /* map_queues packet doesn't need activate the queue,
6509          * so only kiq need set this field.
6510          */
6511         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6512                 mqd->cp_hqd_active = 1;
6513
6514         return 0;
6515 }
6516
6517 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6518 {
6519         struct amdgpu_device *adev = ring->adev;
6520         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6521         int j;
6522
6523         /* inactivate the queue */
6524         if (amdgpu_sriov_vf(adev))
6525                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6526
6527         /* disable wptr polling */
6528         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6529
6530         /* write the EOP addr */
6531         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6532                mqd->cp_hqd_eop_base_addr_lo);
6533         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6534                mqd->cp_hqd_eop_base_addr_hi);
6535
6536         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6537         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6538                mqd->cp_hqd_eop_control);
6539
6540         /* enable doorbell? */
6541         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6542                mqd->cp_hqd_pq_doorbell_control);
6543
6544         /* disable the queue if it's active */
6545         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6546                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6547                 for (j = 0; j < adev->usec_timeout; j++) {
6548                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6549                                 break;
6550                         udelay(1);
6551                 }
6552                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6553                        mqd->cp_hqd_dequeue_request);
6554                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6555                        mqd->cp_hqd_pq_rptr);
6556                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6557                        mqd->cp_hqd_pq_wptr_lo);
6558                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6559                        mqd->cp_hqd_pq_wptr_hi);
6560         }
6561
6562         /* set the pointer to the MQD */
6563         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6564                mqd->cp_mqd_base_addr_lo);
6565         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6566                mqd->cp_mqd_base_addr_hi);
6567
6568         /* set MQD vmid to 0 */
6569         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6570                mqd->cp_mqd_control);
6571
6572         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6573         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6574                mqd->cp_hqd_pq_base_lo);
6575         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6576                mqd->cp_hqd_pq_base_hi);
6577
6578         /* set up the HQD, this is similar to CP_RB0_CNTL */
6579         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6580                mqd->cp_hqd_pq_control);
6581
6582         /* set the wb address whether it's enabled or not */
6583         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6584                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6585         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6586                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6587
6588         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6589         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6590                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6591         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6592                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6593
6594         /* enable the doorbell if requested */
6595         if (ring->use_doorbell) {
6596                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6597                         (adev->doorbell_index.kiq * 2) << 2);
6598                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6599                         (adev->doorbell_index.userqueue_end * 2) << 2);
6600         }
6601
6602         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6603                mqd->cp_hqd_pq_doorbell_control);
6604
6605         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6606         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6607                mqd->cp_hqd_pq_wptr_lo);
6608         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6609                mqd->cp_hqd_pq_wptr_hi);
6610
6611         /* set the vmid for the queue */
6612         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6613
6614         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6615                mqd->cp_hqd_persistent_state);
6616
6617         /* activate the queue */
6618         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6619                mqd->cp_hqd_active);
6620
6621         if (ring->use_doorbell)
6622                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6623
6624         return 0;
6625 }
6626
6627 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6628 {
6629         struct amdgpu_device *adev = ring->adev;
6630         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6631         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6632
6633         gfx_v10_0_kiq_setting(ring);
6634
6635         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6636                 /* reset MQD to a clean status */
6637                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6638                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6639
6640                 /* reset ring buffer */
6641                 ring->wptr = 0;
6642                 amdgpu_ring_clear_ring(ring);
6643
6644                 mutex_lock(&adev->srbm_mutex);
6645                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6646                 gfx_v10_0_kiq_init_register(ring);
6647                 nv_grbm_select(adev, 0, 0, 0, 0);
6648                 mutex_unlock(&adev->srbm_mutex);
6649         } else {
6650                 memset((void *)mqd, 0, sizeof(*mqd));
6651                 mutex_lock(&adev->srbm_mutex);
6652                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6653                 gfx_v10_0_compute_mqd_init(ring);
6654                 gfx_v10_0_kiq_init_register(ring);
6655                 nv_grbm_select(adev, 0, 0, 0, 0);
6656                 mutex_unlock(&adev->srbm_mutex);
6657
6658                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6659                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6660         }
6661
6662         return 0;
6663 }
6664
6665 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6666 {
6667         struct amdgpu_device *adev = ring->adev;
6668         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6669         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6670
6671         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6672                 memset((void *)mqd, 0, sizeof(*mqd));
6673                 mutex_lock(&adev->srbm_mutex);
6674                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6675                 gfx_v10_0_compute_mqd_init(ring);
6676                 nv_grbm_select(adev, 0, 0, 0, 0);
6677                 mutex_unlock(&adev->srbm_mutex);
6678
6679                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6680                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6681         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6682                 /* reset MQD to a clean status */
6683                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6684                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6685
6686                 /* reset ring buffer */
6687                 ring->wptr = 0;
6688                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6689                 amdgpu_ring_clear_ring(ring);
6690         } else {
6691                 amdgpu_ring_clear_ring(ring);
6692         }
6693
6694         return 0;
6695 }
6696
6697 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6698 {
6699         struct amdgpu_ring *ring;
6700         int r;
6701
6702         ring = &adev->gfx.kiq.ring;
6703
6704         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6705         if (unlikely(r != 0))
6706                 return r;
6707
6708         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6709         if (unlikely(r != 0))
6710                 return r;
6711
6712         gfx_v10_0_kiq_init_queue(ring);
6713         amdgpu_bo_kunmap(ring->mqd_obj);
6714         ring->mqd_ptr = NULL;
6715         amdgpu_bo_unreserve(ring->mqd_obj);
6716         ring->sched.ready = true;
6717         return 0;
6718 }
6719
6720 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6721 {
6722         struct amdgpu_ring *ring = NULL;
6723         int r = 0, i;
6724
6725         gfx_v10_0_cp_compute_enable(adev, true);
6726
6727         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6728                 ring = &adev->gfx.compute_ring[i];
6729
6730                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6731                 if (unlikely(r != 0))
6732                         goto done;
6733                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6734                 if (!r) {
6735                         r = gfx_v10_0_kcq_init_queue(ring);
6736                         amdgpu_bo_kunmap(ring->mqd_obj);
6737                         ring->mqd_ptr = NULL;
6738                 }
6739                 amdgpu_bo_unreserve(ring->mqd_obj);
6740                 if (r)
6741                         goto done;
6742         }
6743
6744         r = amdgpu_gfx_enable_kcq(adev);
6745 done:
6746         return r;
6747 }
6748
6749 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6750 {
6751         int r, i;
6752         struct amdgpu_ring *ring;
6753
6754         if (!(adev->flags & AMD_IS_APU))
6755                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6756
6757         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6758                 /* legacy firmware loading */
6759                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6760                 if (r)
6761                         return r;
6762
6763                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6764                 if (r)
6765                         return r;
6766         }
6767
6768         r = gfx_v10_0_kiq_resume(adev);
6769         if (r)
6770                 return r;
6771
6772         r = gfx_v10_0_kcq_resume(adev);
6773         if (r)
6774                 return r;
6775
6776         if (!amdgpu_async_gfx_ring) {
6777                 r = gfx_v10_0_cp_gfx_resume(adev);
6778                 if (r)
6779                         return r;
6780         } else {
6781                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6782                 if (r)
6783                         return r;
6784         }
6785
6786         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6787                 ring = &adev->gfx.gfx_ring[i];
6788                 r = amdgpu_ring_test_helper(ring);
6789                 if (r)
6790                         return r;
6791         }
6792
6793         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6794                 ring = &adev->gfx.compute_ring[i];
6795                 r = amdgpu_ring_test_helper(ring);
6796                 if (r)
6797                         return r;
6798         }
6799
6800         return 0;
6801 }
6802
6803 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6804 {
6805         gfx_v10_0_cp_gfx_enable(adev, enable);
6806         gfx_v10_0_cp_compute_enable(adev, enable);
6807 }
6808
6809 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6810 {
6811         uint32_t data, pattern = 0xDEADBEEF;
6812
6813         /* check if mmVGT_ESGS_RING_SIZE_UMD
6814          * has been remapped to mmVGT_ESGS_RING_SIZE */
6815         switch (adev->asic_type) {
6816         case CHIP_SIENNA_CICHLID:
6817         case CHIP_NAVY_FLOUNDER:
6818                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6819                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6820                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6821
6822                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6823                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
6824                         return true;
6825                 } else {
6826                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6827                         return false;
6828                 }
6829                 break;
6830         case CHIP_VANGOGH:
6831                 return true;
6832         default:
6833                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6834                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6835                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6836
6837                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6838                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6839                         return true;
6840                 } else {
6841                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
6842                         return false;
6843                 }
6844                 break;
6845         }
6846 }
6847
6848 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6849 {
6850         uint32_t data;
6851
6852         /* initialize cam_index to 0
6853          * index will auto-inc after each data writting */
6854         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
6855
6856         switch (adev->asic_type) {
6857         case CHIP_SIENNA_CICHLID:
6858         case CHIP_NAVY_FLOUNDER:
6859         case CHIP_VANGOGH:
6860                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6861                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6862                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6863                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
6864                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6865                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6866                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6867
6868                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6869                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6870                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6871                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
6872                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6873                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6874                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6875
6876                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6877                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6878                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6879                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
6880                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6881                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6882                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6883
6884                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6885                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6886                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6887                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
6888                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6889                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6890                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6891
6892                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6893                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6894                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6895                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
6896                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6897                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6898                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6899
6900                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6901                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6902                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6903                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
6904                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6905                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6906                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6907
6908                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6909                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6910                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6911                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
6912                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6913                 break;
6914         default:
6915                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6916                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6917                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6918                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
6919                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6920                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6921                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6922
6923                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6924                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6925                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6926                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
6927                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6928                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6929                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6930
6931                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6932                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6933                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6934                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
6935                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6936                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6937                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6938
6939                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6940                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6941                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6942                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
6943                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6944                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6945                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6946
6947                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6948                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6949                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6950                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
6951                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6952                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6953                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6954
6955                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6956                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6957                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6958                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
6959                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6960                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6961                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6962
6963                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6964                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6965                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6966                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
6967                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6968                 break;
6969         }
6970
6971         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6972         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6973 }
6974
6975 static int gfx_v10_0_hw_init(void *handle)
6976 {
6977         int r;
6978         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6979
6980         if (!amdgpu_emu_mode)
6981                 gfx_v10_0_init_golden_registers(adev);
6982
6983         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6984                 /**
6985                  * For gfx 10, rlc firmware loading relies on smu firmware is
6986                  * loaded firstly, so in direct type, it has to load smc ucode
6987                  * here before rlc.
6988                  */
6989                 if (adev->smu.ppt_funcs != NULL) {
6990                         r = smu_load_microcode(&adev->smu);
6991                         if (r)
6992                                 return r;
6993
6994                         r = smu_check_fw_status(&adev->smu);
6995                         if (r) {
6996                                 pr_err("SMC firmware status is not correct\n");
6997                                 return r;
6998                         }
6999                 }
7000         }
7001
7002         /* if GRBM CAM not remapped, set up the remapping */
7003         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7004                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7005
7006         gfx_v10_0_constants_init(adev);
7007
7008         r = gfx_v10_0_rlc_resume(adev);
7009         if (r)
7010                 return r;
7011
7012         /*
7013          * init golden registers and rlc resume may override some registers,
7014          * reconfig them here
7015          */
7016         gfx_v10_0_tcp_harvest(adev);
7017
7018         r = gfx_v10_0_cp_resume(adev);
7019         if (r)
7020                 return r;
7021
7022         return r;
7023 }
7024
7025 #ifndef BRING_UP_DEBUG
7026 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7027 {
7028         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7029         struct amdgpu_ring *kiq_ring = &kiq->ring;
7030         int i;
7031
7032         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7033                 return -EINVAL;
7034
7035         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7036                                         adev->gfx.num_gfx_rings))
7037                 return -ENOMEM;
7038
7039         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7040                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7041                                            PREEMPT_QUEUES, 0, 0);
7042
7043         return amdgpu_ring_test_helper(kiq_ring);
7044 }
7045 #endif
7046
7047 static int gfx_v10_0_hw_fini(void *handle)
7048 {
7049         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7050         int r;
7051         uint32_t tmp;
7052
7053         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7054         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7055
7056         if (!adev->in_pci_err_recovery) {
7057 #ifndef BRING_UP_DEBUG
7058                 if (amdgpu_async_gfx_ring) {
7059                         r = gfx_v10_0_kiq_disable_kgq(adev);
7060                         if (r)
7061                                 DRM_ERROR("KGQ disable failed\n");
7062                 }
7063 #endif
7064                 if (amdgpu_gfx_disable_kcq(adev))
7065                         DRM_ERROR("KCQ disable failed\n");
7066         }
7067
7068         if (amdgpu_sriov_vf(adev)) {
7069                 gfx_v10_0_cp_gfx_enable(adev, false);
7070                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7071                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7072                 tmp &= 0xffffff00;
7073                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7074
7075                 return 0;
7076         }
7077         gfx_v10_0_cp_enable(adev, false);
7078         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7079
7080         return 0;
7081 }
7082
7083 static int gfx_v10_0_suspend(void *handle)
7084 {
7085         return gfx_v10_0_hw_fini(handle);
7086 }
7087
7088 static int gfx_v10_0_resume(void *handle)
7089 {
7090         return gfx_v10_0_hw_init(handle);
7091 }
7092
7093 static bool gfx_v10_0_is_idle(void *handle)
7094 {
7095         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7096
7097         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7098                                 GRBM_STATUS, GUI_ACTIVE))
7099                 return false;
7100         else
7101                 return true;
7102 }
7103
7104 static int gfx_v10_0_wait_for_idle(void *handle)
7105 {
7106         unsigned i;
7107         u32 tmp;
7108         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7109
7110         for (i = 0; i < adev->usec_timeout; i++) {
7111                 /* read MC_STATUS */
7112                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7113                         GRBM_STATUS__GUI_ACTIVE_MASK;
7114
7115                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7116                         return 0;
7117                 udelay(1);
7118         }
7119         return -ETIMEDOUT;
7120 }
7121
7122 static int gfx_v10_0_soft_reset(void *handle)
7123 {
7124         u32 grbm_soft_reset = 0;
7125         u32 tmp;
7126         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7127
7128         /* GRBM_STATUS */
7129         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7130         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7131                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7132                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7133                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7134                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7135                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7136                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7137                                                 1);
7138                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7139                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7140                                                 1);
7141         }
7142
7143         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7144                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7145                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7146                                                 1);
7147         }
7148
7149         /* GRBM_STATUS2 */
7150         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7151         switch (adev->asic_type) {
7152         case CHIP_SIENNA_CICHLID:
7153         case CHIP_NAVY_FLOUNDER:
7154         case CHIP_VANGOGH:
7155                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7156                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7157                                                         GRBM_SOFT_RESET,
7158                                                         SOFT_RESET_RLC,
7159                                                         1);
7160                 break;
7161         default:
7162                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7163                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7164                                                         GRBM_SOFT_RESET,
7165                                                         SOFT_RESET_RLC,
7166                                                         1);
7167                 break;
7168         }
7169
7170         if (grbm_soft_reset) {
7171                 /* stop the rlc */
7172                 gfx_v10_0_rlc_stop(adev);
7173
7174                 /* Disable GFX parsing/prefetching */
7175                 gfx_v10_0_cp_gfx_enable(adev, false);
7176
7177                 /* Disable MEC parsing/prefetching */
7178                 gfx_v10_0_cp_compute_enable(adev, false);
7179
7180                 if (grbm_soft_reset) {
7181                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7182                         tmp |= grbm_soft_reset;
7183                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7184                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7185                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7186
7187                         udelay(50);
7188
7189                         tmp &= ~grbm_soft_reset;
7190                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7191                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7192                 }
7193
7194                 /* Wait a little for things to settle down */
7195                 udelay(50);
7196         }
7197         return 0;
7198 }
7199
7200 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7201 {
7202         uint64_t clock;
7203
7204         amdgpu_gfx_off_ctrl(adev, false);
7205         mutex_lock(&adev->gfx.gpu_clock_mutex);
7206         clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7207                 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7208         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7209         amdgpu_gfx_off_ctrl(adev, true);
7210         return clock;
7211 }
7212
7213 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7214                                            uint32_t vmid,
7215                                            uint32_t gds_base, uint32_t gds_size,
7216                                            uint32_t gws_base, uint32_t gws_size,
7217                                            uint32_t oa_base, uint32_t oa_size)
7218 {
7219         struct amdgpu_device *adev = ring->adev;
7220
7221         /* GDS Base */
7222         gfx_v10_0_write_data_to_reg(ring, 0, false,
7223                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7224                                     gds_base);
7225
7226         /* GDS Size */
7227         gfx_v10_0_write_data_to_reg(ring, 0, false,
7228                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7229                                     gds_size);
7230
7231         /* GWS */
7232         gfx_v10_0_write_data_to_reg(ring, 0, false,
7233                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7234                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7235
7236         /* OA */
7237         gfx_v10_0_write_data_to_reg(ring, 0, false,
7238                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7239                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7240 }
7241
7242 static int gfx_v10_0_early_init(void *handle)
7243 {
7244         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7245
7246         switch (adev->asic_type) {
7247         case CHIP_NAVI10:
7248         case CHIP_NAVI14:
7249         case CHIP_NAVI12:
7250                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7251                 break;
7252         case CHIP_SIENNA_CICHLID:
7253         case CHIP_NAVY_FLOUNDER:
7254         case CHIP_VANGOGH:
7255                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7256                 break;
7257         default:
7258                 break;
7259         }
7260
7261         adev->gfx.num_compute_rings = amdgpu_num_kcq;
7262
7263         gfx_v10_0_set_kiq_pm4_funcs(adev);
7264         gfx_v10_0_set_ring_funcs(adev);
7265         gfx_v10_0_set_irq_funcs(adev);
7266         gfx_v10_0_set_gds_init(adev);
7267         gfx_v10_0_set_rlc_funcs(adev);
7268
7269         return 0;
7270 }
7271
7272 static int gfx_v10_0_late_init(void *handle)
7273 {
7274         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7275         int r;
7276
7277         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7278         if (r)
7279                 return r;
7280
7281         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7282         if (r)
7283                 return r;
7284
7285         return 0;
7286 }
7287
7288 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7289 {
7290         uint32_t rlc_cntl;
7291
7292         /* if RLC is not enabled, do nothing */
7293         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7294         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7295 }
7296
7297 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7298 {
7299         uint32_t data;
7300         unsigned i;
7301
7302         data = RLC_SAFE_MODE__CMD_MASK;
7303         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7304
7305         switch (adev->asic_type) {
7306         case CHIP_SIENNA_CICHLID:
7307         case CHIP_NAVY_FLOUNDER:
7308         case CHIP_VANGOGH:
7309                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7310
7311                 /* wait for RLC_SAFE_MODE */
7312                 for (i = 0; i < adev->usec_timeout; i++) {
7313                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7314                                            RLC_SAFE_MODE, CMD))
7315                                 break;
7316                         udelay(1);
7317                 }
7318                 break;
7319         default:
7320                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7321
7322                 /* wait for RLC_SAFE_MODE */
7323                 for (i = 0; i < adev->usec_timeout; i++) {
7324                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7325                                            RLC_SAFE_MODE, CMD))
7326                                 break;
7327                         udelay(1);
7328                 }
7329                 break;
7330         }
7331 }
7332
7333 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7334 {
7335         uint32_t data;
7336
7337         data = RLC_SAFE_MODE__CMD_MASK;
7338         switch (adev->asic_type) {
7339         case CHIP_SIENNA_CICHLID:
7340         case CHIP_NAVY_FLOUNDER:
7341         case CHIP_VANGOGH:
7342                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7343                 break;
7344         default:
7345                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7346                 break;
7347         }
7348 }
7349
7350 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7351                                                       bool enable)
7352 {
7353         uint32_t data, def;
7354
7355         /* It is disabled by HW by default */
7356         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7357                 /* 0 - Disable some blocks' MGCG */
7358                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7359                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7360                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7361                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7362
7363                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7364                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7365                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7366                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7367                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7368                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7369
7370                 if (def != data)
7371                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7372
7373                 /* MGLS is a global flag to control all MGLS in GFX */
7374                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7375                         /* 2 - RLC memory Light sleep */
7376                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7377                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7378                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7379                                 if (def != data)
7380                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7381                         }
7382                         /* 3 - CP memory Light sleep */
7383                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7384                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7385                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7386                                 if (def != data)
7387                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7388                         }
7389                 }
7390         } else {
7391                 /* 1 - MGCG_OVERRIDE */
7392                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7393                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7394                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7395                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7396                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7397                 if (def != data)
7398                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7399
7400                 /* 2 - disable MGLS in CP */
7401                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7402                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7403                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7404                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7405                 }
7406
7407                 /* 3 - disable MGLS in RLC */
7408                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7409                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7410                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7411                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7412                 }
7413
7414         }
7415 }
7416
7417 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7418                                            bool enable)
7419 {
7420         uint32_t data, def;
7421
7422         /* Enable 3D CGCG/CGLS */
7423         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7424                 /* write cmd to clear cgcg/cgls ov */
7425                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7426                 /* unset CGCG override */
7427                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7428                 /* update CGCG and CGLS override bits */
7429                 if (def != data)
7430                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7431                 /* enable 3Dcgcg FSM(0x0000363f) */
7432                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7433                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7434                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7435                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7436                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7437                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7438                 if (def != data)
7439                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7440
7441                 /* set IDLE_POLL_COUNT(0x00900100) */
7442                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7443                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7444                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7445                 if (def != data)
7446                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7447         } else {
7448                 /* Disable CGCG/CGLS */
7449                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7450                 /* disable cgcg, cgls should be disabled */
7451                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7452                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7453                 /* disable cgcg and cgls in FSM */
7454                 if (def != data)
7455                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7456         }
7457 }
7458
7459 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7460                                                       bool enable)
7461 {
7462         uint32_t def, data;
7463
7464         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7465                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7466                 /* unset CGCG override */
7467                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7468                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7469                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7470                 else
7471                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7472                 /* update CGCG and CGLS override bits */
7473                 if (def != data)
7474                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7475
7476                 /* enable cgcg FSM(0x0000363F) */
7477                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7478                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7479                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7480                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7481                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7482                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7483                 if (def != data)
7484                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7485
7486                 /* set IDLE_POLL_COUNT(0x00900100) */
7487                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7488                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7489                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7490                 if (def != data)
7491                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7492         } else {
7493                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7494                 /* reset CGCG/CGLS bits */
7495                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7496                 /* disable cgcg and cgls in FSM */
7497                 if (def != data)
7498                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7499         }
7500 }
7501
7502 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7503                                             bool enable)
7504 {
7505         amdgpu_gfx_rlc_enter_safe_mode(adev);
7506
7507         if (enable) {
7508                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7509                  * ===  MGCG + MGLS ===
7510                  */
7511                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7512                 /* ===  CGCG /CGLS for GFX 3D Only === */
7513                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7514                 /* ===  CGCG + CGLS === */
7515                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7516         } else {
7517                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7518                  * ===  CGCG + CGLS ===
7519                  */
7520                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7521                 /* ===  CGCG /CGLS for GFX 3D Only === */
7522                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7523                 /* ===  MGCG + MGLS === */
7524                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7525         }
7526
7527         if (adev->cg_flags &
7528             (AMD_CG_SUPPORT_GFX_MGCG |
7529              AMD_CG_SUPPORT_GFX_CGLS |
7530              AMD_CG_SUPPORT_GFX_CGCG |
7531              AMD_CG_SUPPORT_GFX_3D_CGCG |
7532              AMD_CG_SUPPORT_GFX_3D_CGLS))
7533                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7534
7535         amdgpu_gfx_rlc_exit_safe_mode(adev);
7536
7537         return 0;
7538 }
7539
7540 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7541 {
7542         u32 reg, data;
7543
7544         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7545         if (amdgpu_sriov_is_pp_one_vf(adev))
7546                 data = RREG32_NO_KIQ(reg);
7547         else
7548                 data = RREG32(reg);
7549
7550         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7551         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7552
7553         if (amdgpu_sriov_is_pp_one_vf(adev))
7554                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7555         else
7556                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7557 }
7558
7559 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7560                                         uint32_t offset,
7561                                         struct soc15_reg_rlcg *entries, int arr_size)
7562 {
7563         int i;
7564         uint32_t reg;
7565
7566         if (!entries)
7567                 return false;
7568
7569         for (i = 0; i < arr_size; i++) {
7570                 const struct soc15_reg_rlcg *entry;
7571
7572                 entry = &entries[i];
7573                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7574                 if (offset == reg)
7575                         return true;
7576         }
7577
7578         return false;
7579 }
7580
7581 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7582 {
7583         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7584 }
7585
7586 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7587         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7588         .set_safe_mode = gfx_v10_0_set_safe_mode,
7589         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7590         .init = gfx_v10_0_rlc_init,
7591         .get_csb_size = gfx_v10_0_get_csb_size,
7592         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7593         .resume = gfx_v10_0_rlc_resume,
7594         .stop = gfx_v10_0_rlc_stop,
7595         .reset = gfx_v10_0_rlc_reset,
7596         .start = gfx_v10_0_rlc_start,
7597         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7598 };
7599
7600 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7601         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7602         .set_safe_mode = gfx_v10_0_set_safe_mode,
7603         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7604         .init = gfx_v10_0_rlc_init,
7605         .get_csb_size = gfx_v10_0_get_csb_size,
7606         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7607         .resume = gfx_v10_0_rlc_resume,
7608         .stop = gfx_v10_0_rlc_stop,
7609         .reset = gfx_v10_0_rlc_reset,
7610         .start = gfx_v10_0_rlc_start,
7611         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7612         .rlcg_wreg = gfx_v10_rlcg_wreg,
7613         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7614 };
7615
7616 static int gfx_v10_0_set_powergating_state(void *handle,
7617                                           enum amd_powergating_state state)
7618 {
7619         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7620         bool enable = (state == AMD_PG_STATE_GATE);
7621
7622         if (amdgpu_sriov_vf(adev))
7623                 return 0;
7624
7625         switch (adev->asic_type) {
7626         case CHIP_NAVI10:
7627         case CHIP_NAVI14:
7628         case CHIP_NAVI12:
7629         case CHIP_SIENNA_CICHLID:
7630         case CHIP_NAVY_FLOUNDER:
7631                 amdgpu_gfx_off_ctrl(adev, enable);
7632                 break;
7633         default:
7634                 break;
7635         }
7636         return 0;
7637 }
7638
7639 static int gfx_v10_0_set_clockgating_state(void *handle,
7640                                           enum amd_clockgating_state state)
7641 {
7642         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7643
7644         if (amdgpu_sriov_vf(adev))
7645                 return 0;
7646
7647         switch (adev->asic_type) {
7648         case CHIP_NAVI10:
7649         case CHIP_NAVI14:
7650         case CHIP_NAVI12:
7651         case CHIP_SIENNA_CICHLID:
7652         case CHIP_NAVY_FLOUNDER:
7653         case CHIP_VANGOGH:
7654                 gfx_v10_0_update_gfx_clock_gating(adev,
7655                                                  state == AMD_CG_STATE_GATE);
7656                 break;
7657         default:
7658                 break;
7659         }
7660         return 0;
7661 }
7662
7663 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7664 {
7665         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7666         int data;
7667
7668         /* AMD_CG_SUPPORT_GFX_MGCG */
7669         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7670         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7671                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
7672
7673         /* AMD_CG_SUPPORT_GFX_CGCG */
7674         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
7675         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7676                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
7677
7678         /* AMD_CG_SUPPORT_GFX_CGLS */
7679         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7680                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
7681
7682         /* AMD_CG_SUPPORT_GFX_RLC_LS */
7683         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
7684         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7685                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7686
7687         /* AMD_CG_SUPPORT_GFX_CP_LS */
7688         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
7689         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7690                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7691
7692         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
7693         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
7694         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7695                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7696
7697         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
7698         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7699                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7700 }
7701
7702 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7703 {
7704         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7705 }
7706
7707 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
7708 {
7709         struct amdgpu_device *adev = ring->adev;
7710         u64 wptr;
7711
7712         /* XXX check if swapping is necessary on BE */
7713         if (ring->use_doorbell) {
7714                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
7715         } else {
7716                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
7717                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
7718         }
7719
7720         return wptr;
7721 }
7722
7723 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
7724 {
7725         struct amdgpu_device *adev = ring->adev;
7726
7727         if (ring->use_doorbell) {
7728                 /* XXX check if swapping is necessary on BE */
7729                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7730                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7731         } else {
7732                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
7733                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
7734         }
7735 }
7736
7737 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
7738 {
7739         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
7740 }
7741
7742 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
7743 {
7744         u64 wptr;
7745
7746         /* XXX check if swapping is necessary on BE */
7747         if (ring->use_doorbell)
7748                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
7749         else
7750                 BUG();
7751         return wptr;
7752 }
7753
7754 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
7755 {
7756         struct amdgpu_device *adev = ring->adev;
7757
7758         /* XXX check if swapping is necessary on BE */
7759         if (ring->use_doorbell) {
7760                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7761                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7762         } else {
7763                 BUG(); /* only DOORBELL method supported on gfx10 now */
7764         }
7765 }
7766
7767 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
7768 {
7769         struct amdgpu_device *adev = ring->adev;
7770         u32 ref_and_mask, reg_mem_engine;
7771         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
7772
7773         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
7774                 switch (ring->me) {
7775                 case 1:
7776                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
7777                         break;
7778                 case 2:
7779                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
7780                         break;
7781                 default:
7782                         return;
7783                 }
7784                 reg_mem_engine = 0;
7785         } else {
7786                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
7787                 reg_mem_engine = 1; /* pfp */
7788         }
7789
7790         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
7791                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
7792                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
7793                                ref_and_mask, ref_and_mask, 0x20);
7794 }
7795
7796 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
7797                                        struct amdgpu_job *job,
7798                                        struct amdgpu_ib *ib,
7799                                        uint32_t flags)
7800 {
7801         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7802         u32 header, control = 0;
7803
7804         if (ib->flags & AMDGPU_IB_FLAG_CE)
7805                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
7806         else
7807                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
7808
7809         control |= ib->length_dw | (vmid << 24);
7810
7811         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
7812                 control |= INDIRECT_BUFFER_PRE_ENB(1);
7813
7814                 if (flags & AMDGPU_IB_PREEMPTED)
7815                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
7816
7817                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
7818                         gfx_v10_0_ring_emit_de_meta(ring,
7819                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7820         }
7821
7822         amdgpu_ring_write(ring, header);
7823         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7824         amdgpu_ring_write(ring,
7825 #ifdef __BIG_ENDIAN
7826                 (2 << 0) |
7827 #endif
7828                 lower_32_bits(ib->gpu_addr));
7829         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7830         amdgpu_ring_write(ring, control);
7831 }
7832
7833 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
7834                                            struct amdgpu_job *job,
7835                                            struct amdgpu_ib *ib,
7836                                            uint32_t flags)
7837 {
7838         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7839         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
7840
7841         /* Currently, there is a high possibility to get wave ID mismatch
7842          * between ME and GDS, leading to a hw deadlock, because ME generates
7843          * different wave IDs than the GDS expects. This situation happens
7844          * randomly when at least 5 compute pipes use GDS ordered append.
7845          * The wave IDs generated by ME are also wrong after suspend/resume.
7846          * Those are probably bugs somewhere else in the kernel driver.
7847          *
7848          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
7849          * GDS to 0 for this ring (me/pipe).
7850          */
7851         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
7852                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
7853                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
7854                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
7855         }
7856
7857         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
7858         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7859         amdgpu_ring_write(ring,
7860 #ifdef __BIG_ENDIAN
7861                                 (2 << 0) |
7862 #endif
7863                                 lower_32_bits(ib->gpu_addr));
7864         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7865         amdgpu_ring_write(ring, control);
7866 }
7867
7868 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
7869                                      u64 seq, unsigned flags)
7870 {
7871         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
7872         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
7873
7874         /* RELEASE_MEM - flush caches, send int */
7875         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
7876         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
7877                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
7878                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
7879                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
7880                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
7881                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
7882                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
7883         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
7884                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
7885
7886         /*
7887          * the address should be Qword aligned if 64bit write, Dword
7888          * aligned if only send 32bit data low (discard data high)
7889          */
7890         if (write64bit)
7891                 BUG_ON(addr & 0x7);
7892         else
7893                 BUG_ON(addr & 0x3);
7894         amdgpu_ring_write(ring, lower_32_bits(addr));
7895         amdgpu_ring_write(ring, upper_32_bits(addr));
7896         amdgpu_ring_write(ring, lower_32_bits(seq));
7897         amdgpu_ring_write(ring, upper_32_bits(seq));
7898         amdgpu_ring_write(ring, 0);
7899 }
7900
7901 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
7902 {
7903         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
7904         uint32_t seq = ring->fence_drv.sync_seq;
7905         uint64_t addr = ring->fence_drv.gpu_addr;
7906
7907         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
7908                                upper_32_bits(addr), seq, 0xffffffff, 4);
7909 }
7910
7911 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
7912                                          unsigned vmid, uint64_t pd_addr)
7913 {
7914         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
7915
7916         /* compute doesn't have PFP */
7917         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
7918                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
7919                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
7920                 amdgpu_ring_write(ring, 0x0);
7921         }
7922 }
7923
7924 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
7925                                           u64 seq, unsigned int flags)
7926 {
7927         struct amdgpu_device *adev = ring->adev;
7928
7929         /* we only allocate 32bit for each seq wb address */
7930         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
7931
7932         /* write fence seq to the "addr" */
7933         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7934         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7935                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
7936         amdgpu_ring_write(ring, lower_32_bits(addr));
7937         amdgpu_ring_write(ring, upper_32_bits(addr));
7938         amdgpu_ring_write(ring, lower_32_bits(seq));
7939
7940         if (flags & AMDGPU_FENCE_FLAG_INT) {
7941                 /* set register to trigger INT */
7942                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7943                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7944                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
7945                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
7946                 amdgpu_ring_write(ring, 0);
7947                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
7948         }
7949 }
7950
7951 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
7952 {
7953         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
7954         amdgpu_ring_write(ring, 0);
7955 }
7956
7957 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
7958                                          uint32_t flags)
7959 {
7960         uint32_t dw2 = 0;
7961
7962         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
7963                 gfx_v10_0_ring_emit_ce_meta(ring,
7964                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7965
7966         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
7967         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
7968                 /* set load_global_config & load_global_uconfig */
7969                 dw2 |= 0x8001;
7970                 /* set load_cs_sh_regs */
7971                 dw2 |= 0x01000000;
7972                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
7973                 dw2 |= 0x10002;
7974
7975                 /* set load_ce_ram if preamble presented */
7976                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
7977                         dw2 |= 0x10000000;
7978         } else {
7979                 /* still load_ce_ram if this is the first time preamble presented
7980                  * although there is no context switch happens.
7981                  */
7982                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
7983                         dw2 |= 0x10000000;
7984         }
7985
7986         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
7987         amdgpu_ring_write(ring, dw2);
7988         amdgpu_ring_write(ring, 0);
7989 }
7990
7991 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
7992 {
7993         unsigned ret;
7994
7995         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
7996         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
7997         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
7998         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
7999         ret = ring->wptr & ring->buf_mask;
8000         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8001
8002         return ret;
8003 }
8004
8005 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8006 {
8007         unsigned cur;
8008         BUG_ON(offset > ring->buf_mask);
8009         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8010
8011         cur = (ring->wptr - 1) & ring->buf_mask;
8012         if (likely(cur > offset))
8013                 ring->ring[offset] = cur - offset;
8014         else
8015                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8016 }
8017
8018 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8019 {
8020         int i, r = 0;
8021         struct amdgpu_device *adev = ring->adev;
8022         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8023         struct amdgpu_ring *kiq_ring = &kiq->ring;
8024         unsigned long flags;
8025
8026         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8027                 return -EINVAL;
8028
8029         spin_lock_irqsave(&kiq->ring_lock, flags);
8030
8031         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8032                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8033                 return -ENOMEM;
8034         }
8035
8036         /* assert preemption condition */
8037         amdgpu_ring_set_preempt_cond_exec(ring, false);
8038
8039         /* assert IB preemption, emit the trailing fence */
8040         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8041                                    ring->trail_fence_gpu_addr,
8042                                    ++ring->trail_seq);
8043         amdgpu_ring_commit(kiq_ring);
8044
8045         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8046
8047         /* poll the trailing fence */
8048         for (i = 0; i < adev->usec_timeout; i++) {
8049                 if (ring->trail_seq ==
8050                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8051                         break;
8052                 udelay(1);
8053         }
8054
8055         if (i >= adev->usec_timeout) {
8056                 r = -EINVAL;
8057                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8058         }
8059
8060         /* deassert preemption condition */
8061         amdgpu_ring_set_preempt_cond_exec(ring, true);
8062         return r;
8063 }
8064
8065 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8066 {
8067         struct amdgpu_device *adev = ring->adev;
8068         struct v10_ce_ib_state ce_payload = {0};
8069         uint64_t csa_addr;
8070         int cnt;
8071
8072         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8073         csa_addr = amdgpu_csa_vaddr(ring->adev);
8074
8075         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8076         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8077                                  WRITE_DATA_DST_SEL(8) |
8078                                  WR_CONFIRM) |
8079                                  WRITE_DATA_CACHE_POLICY(0));
8080         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8081                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8082         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8083                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8084
8085         if (resume)
8086                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8087                                            offsetof(struct v10_gfx_meta_data,
8088                                                     ce_payload),
8089                                            sizeof(ce_payload) >> 2);
8090         else
8091                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8092                                            sizeof(ce_payload) >> 2);
8093 }
8094
8095 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8096 {
8097         struct amdgpu_device *adev = ring->adev;
8098         struct v10_de_ib_state de_payload = {0};
8099         uint64_t csa_addr, gds_addr;
8100         int cnt;
8101
8102         csa_addr = amdgpu_csa_vaddr(ring->adev);
8103         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8104                          PAGE_SIZE);
8105         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8106         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8107
8108         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8109         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8110         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8111                                  WRITE_DATA_DST_SEL(8) |
8112                                  WR_CONFIRM) |
8113                                  WRITE_DATA_CACHE_POLICY(0));
8114         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8115                               offsetof(struct v10_gfx_meta_data, de_payload)));
8116         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8117                               offsetof(struct v10_gfx_meta_data, de_payload)));
8118
8119         if (resume)
8120                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8121                                            offsetof(struct v10_gfx_meta_data,
8122                                                     de_payload),
8123                                            sizeof(de_payload) >> 2);
8124         else
8125                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8126                                            sizeof(de_payload) >> 2);
8127 }
8128
8129 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8130                                     bool secure)
8131 {
8132         uint32_t v = secure ? FRAME_TMZ : 0;
8133
8134         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8135         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8136 }
8137
8138 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8139                                      uint32_t reg_val_offs)
8140 {
8141         struct amdgpu_device *adev = ring->adev;
8142
8143         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8144         amdgpu_ring_write(ring, 0 |     /* src: register*/
8145                                 (5 << 8) |      /* dst: memory */
8146                                 (1 << 20));     /* write confirm */
8147         amdgpu_ring_write(ring, reg);
8148         amdgpu_ring_write(ring, 0);
8149         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8150                                 reg_val_offs * 4));
8151         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8152                                 reg_val_offs * 4));
8153 }
8154
8155 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8156                                    uint32_t val)
8157 {
8158         uint32_t cmd = 0;
8159
8160         switch (ring->funcs->type) {
8161         case AMDGPU_RING_TYPE_GFX:
8162                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8163                 break;
8164         case AMDGPU_RING_TYPE_KIQ:
8165                 cmd = (1 << 16); /* no inc addr */
8166                 break;
8167         default:
8168                 cmd = WR_CONFIRM;
8169                 break;
8170         }
8171         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8172         amdgpu_ring_write(ring, cmd);
8173         amdgpu_ring_write(ring, reg);
8174         amdgpu_ring_write(ring, 0);
8175         amdgpu_ring_write(ring, val);
8176 }
8177
8178 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8179                                         uint32_t val, uint32_t mask)
8180 {
8181         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8182 }
8183
8184 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8185                                                    uint32_t reg0, uint32_t reg1,
8186                                                    uint32_t ref, uint32_t mask)
8187 {
8188         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8189         struct amdgpu_device *adev = ring->adev;
8190         bool fw_version_ok = false;
8191
8192         fw_version_ok = adev->gfx.cp_fw_write_wait;
8193
8194         if (fw_version_ok)
8195                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8196                                        ref, mask, 0x20);
8197         else
8198                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8199                                                            ref, mask);
8200 }
8201
8202 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8203                                          unsigned vmid)
8204 {
8205         struct amdgpu_device *adev = ring->adev;
8206         uint32_t value = 0;
8207
8208         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8209         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8210         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8211         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8212         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8213 }
8214
8215 static void
8216 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8217                                       uint32_t me, uint32_t pipe,
8218                                       enum amdgpu_interrupt_state state)
8219 {
8220         uint32_t cp_int_cntl, cp_int_cntl_reg;
8221
8222         if (!me) {
8223                 switch (pipe) {
8224                 case 0:
8225                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8226                         break;
8227                 case 1:
8228                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8229                         break;
8230                 default:
8231                         DRM_DEBUG("invalid pipe %d\n", pipe);
8232                         return;
8233                 }
8234         } else {
8235                 DRM_DEBUG("invalid me %d\n", me);
8236                 return;
8237         }
8238
8239         switch (state) {
8240         case AMDGPU_IRQ_STATE_DISABLE:
8241                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8242                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8243                                             TIME_STAMP_INT_ENABLE, 0);
8244                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8245                 break;
8246         case AMDGPU_IRQ_STATE_ENABLE:
8247                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8248                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8249                                             TIME_STAMP_INT_ENABLE, 1);
8250                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8251                 break;
8252         default:
8253                 break;
8254         }
8255 }
8256
8257 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8258                                                      int me, int pipe,
8259                                                      enum amdgpu_interrupt_state state)
8260 {
8261         u32 mec_int_cntl, mec_int_cntl_reg;
8262
8263         /*
8264          * amdgpu controls only the first MEC. That's why this function only
8265          * handles the setting of interrupts for this specific MEC. All other
8266          * pipes' interrupts are set by amdkfd.
8267          */
8268
8269         if (me == 1) {
8270                 switch (pipe) {
8271                 case 0:
8272                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8273                         break;
8274                 case 1:
8275                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8276                         break;
8277                 case 2:
8278                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8279                         break;
8280                 case 3:
8281                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8282                         break;
8283                 default:
8284                         DRM_DEBUG("invalid pipe %d\n", pipe);
8285                         return;
8286                 }
8287         } else {
8288                 DRM_DEBUG("invalid me %d\n", me);
8289                 return;
8290         }
8291
8292         switch (state) {
8293         case AMDGPU_IRQ_STATE_DISABLE:
8294                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8295                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8296                                              TIME_STAMP_INT_ENABLE, 0);
8297                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8298                 break;
8299         case AMDGPU_IRQ_STATE_ENABLE:
8300                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8301                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8302                                              TIME_STAMP_INT_ENABLE, 1);
8303                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8304                 break;
8305         default:
8306                 break;
8307         }
8308 }
8309
8310 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8311                                             struct amdgpu_irq_src *src,
8312                                             unsigned type,
8313                                             enum amdgpu_interrupt_state state)
8314 {
8315         switch (type) {
8316         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8317                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8318                 break;
8319         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8320                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8321                 break;
8322         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8323                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8324                 break;
8325         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8326                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8327                 break;
8328         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8329                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8330                 break;
8331         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8332                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8333                 break;
8334         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8335                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8336                 break;
8337         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8338                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8339                 break;
8340         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8341                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8342                 break;
8343         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8344                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8345                 break;
8346         default:
8347                 break;
8348         }
8349         return 0;
8350 }
8351
8352 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8353                              struct amdgpu_irq_src *source,
8354                              struct amdgpu_iv_entry *entry)
8355 {
8356         int i;
8357         u8 me_id, pipe_id, queue_id;
8358         struct amdgpu_ring *ring;
8359
8360         DRM_DEBUG("IH: CP EOP\n");
8361         me_id = (entry->ring_id & 0x0c) >> 2;
8362         pipe_id = (entry->ring_id & 0x03) >> 0;
8363         queue_id = (entry->ring_id & 0x70) >> 4;
8364
8365         switch (me_id) {
8366         case 0:
8367                 if (pipe_id == 0)
8368                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8369                 else
8370                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8371                 break;
8372         case 1:
8373         case 2:
8374                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8375                         ring = &adev->gfx.compute_ring[i];
8376                         /* Per-queue interrupt is supported for MEC starting from VI.
8377                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8378                           */
8379                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8380                                 amdgpu_fence_process(ring);
8381                 }
8382                 break;
8383         }
8384         return 0;
8385 }
8386
8387 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8388                                               struct amdgpu_irq_src *source,
8389                                               unsigned type,
8390                                               enum amdgpu_interrupt_state state)
8391 {
8392         switch (state) {
8393         case AMDGPU_IRQ_STATE_DISABLE:
8394         case AMDGPU_IRQ_STATE_ENABLE:
8395                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8396                                PRIV_REG_INT_ENABLE,
8397                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8398                 break;
8399         default:
8400                 break;
8401         }
8402
8403         return 0;
8404 }
8405
8406 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8407                                                struct amdgpu_irq_src *source,
8408                                                unsigned type,
8409                                                enum amdgpu_interrupt_state state)
8410 {
8411         switch (state) {
8412         case AMDGPU_IRQ_STATE_DISABLE:
8413         case AMDGPU_IRQ_STATE_ENABLE:
8414                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8415                                PRIV_INSTR_INT_ENABLE,
8416                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8417         default:
8418                 break;
8419         }
8420
8421         return 0;
8422 }
8423
8424 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8425                                         struct amdgpu_iv_entry *entry)
8426 {
8427         u8 me_id, pipe_id, queue_id;
8428         struct amdgpu_ring *ring;
8429         int i;
8430
8431         me_id = (entry->ring_id & 0x0c) >> 2;
8432         pipe_id = (entry->ring_id & 0x03) >> 0;
8433         queue_id = (entry->ring_id & 0x70) >> 4;
8434
8435         switch (me_id) {
8436         case 0:
8437                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8438                         ring = &adev->gfx.gfx_ring[i];
8439                         /* we only enabled 1 gfx queue per pipe for now */
8440                         if (ring->me == me_id && ring->pipe == pipe_id)
8441                                 drm_sched_fault(&ring->sched);
8442                 }
8443                 break;
8444         case 1:
8445         case 2:
8446                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8447                         ring = &adev->gfx.compute_ring[i];
8448                         if (ring->me == me_id && ring->pipe == pipe_id &&
8449                             ring->queue == queue_id)
8450                                 drm_sched_fault(&ring->sched);
8451                 }
8452                 break;
8453         default:
8454                 BUG();
8455         }
8456 }
8457
8458 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8459                                   struct amdgpu_irq_src *source,
8460                                   struct amdgpu_iv_entry *entry)
8461 {
8462         DRM_ERROR("Illegal register access in command stream\n");
8463         gfx_v10_0_handle_priv_fault(adev, entry);
8464         return 0;
8465 }
8466
8467 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8468                                    struct amdgpu_irq_src *source,
8469                                    struct amdgpu_iv_entry *entry)
8470 {
8471         DRM_ERROR("Illegal instruction in command stream\n");
8472         gfx_v10_0_handle_priv_fault(adev, entry);
8473         return 0;
8474 }
8475
8476 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8477                                              struct amdgpu_irq_src *src,
8478                                              unsigned int type,
8479                                              enum amdgpu_interrupt_state state)
8480 {
8481         uint32_t tmp, target;
8482         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8483
8484         if (ring->me == 1)
8485                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8486         else
8487                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8488         target += ring->pipe;
8489
8490         switch (type) {
8491         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8492                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8493                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8494                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8495                                             GENERIC2_INT_ENABLE, 0);
8496                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8497
8498                         tmp = RREG32(target);
8499                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8500                                             GENERIC2_INT_ENABLE, 0);
8501                         WREG32(target, tmp);
8502                 } else {
8503                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8504                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8505                                             GENERIC2_INT_ENABLE, 1);
8506                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8507
8508                         tmp = RREG32(target);
8509                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8510                                             GENERIC2_INT_ENABLE, 1);
8511                         WREG32(target, tmp);
8512                 }
8513                 break;
8514         default:
8515                 BUG(); /* kiq only support GENERIC2_INT now */
8516                 break;
8517         }
8518         return 0;
8519 }
8520
8521 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8522                              struct amdgpu_irq_src *source,
8523                              struct amdgpu_iv_entry *entry)
8524 {
8525         u8 me_id, pipe_id, queue_id;
8526         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8527
8528         me_id = (entry->ring_id & 0x0c) >> 2;
8529         pipe_id = (entry->ring_id & 0x03) >> 0;
8530         queue_id = (entry->ring_id & 0x70) >> 4;
8531         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8532                    me_id, pipe_id, queue_id);
8533
8534         amdgpu_fence_process(ring);
8535         return 0;
8536 }
8537
8538 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8539 {
8540         const unsigned int gcr_cntl =
8541                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8542                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8543                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8544                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8545                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8546                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8547                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8548                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8549
8550         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8551         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8552         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8553         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8554         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8555         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8556         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8557         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8558         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8559 }
8560
8561 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8562         .name = "gfx_v10_0",
8563         .early_init = gfx_v10_0_early_init,
8564         .late_init = gfx_v10_0_late_init,
8565         .sw_init = gfx_v10_0_sw_init,
8566         .sw_fini = gfx_v10_0_sw_fini,
8567         .hw_init = gfx_v10_0_hw_init,
8568         .hw_fini = gfx_v10_0_hw_fini,
8569         .suspend = gfx_v10_0_suspend,
8570         .resume = gfx_v10_0_resume,
8571         .is_idle = gfx_v10_0_is_idle,
8572         .wait_for_idle = gfx_v10_0_wait_for_idle,
8573         .soft_reset = gfx_v10_0_soft_reset,
8574         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8575         .set_powergating_state = gfx_v10_0_set_powergating_state,
8576         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8577 };
8578
8579 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8580         .type = AMDGPU_RING_TYPE_GFX,
8581         .align_mask = 0xff,
8582         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8583         .support_64bit_ptrs = true,
8584         .vmhub = AMDGPU_GFXHUB_0,
8585         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8586         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8587         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8588         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8589                 5 + /* COND_EXEC */
8590                 7 + /* PIPELINE_SYNC */
8591                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8592                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8593                 2 + /* VM_FLUSH */
8594                 8 + /* FENCE for VM_FLUSH */
8595                 20 + /* GDS switch */
8596                 4 + /* double SWITCH_BUFFER,
8597                      * the first COND_EXEC jump to the place
8598                      * just prior to this double SWITCH_BUFFER
8599                      */
8600                 5 + /* COND_EXEC */
8601                 7 + /* HDP_flush */
8602                 4 + /* VGT_flush */
8603                 14 + /* CE_META */
8604                 31 + /* DE_META */
8605                 3 + /* CNTX_CTRL */
8606                 5 + /* HDP_INVL */
8607                 8 + 8 + /* FENCE x2 */
8608                 2 + /* SWITCH_BUFFER */
8609                 8, /* gfx_v10_0_emit_mem_sync */
8610         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8611         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8612         .emit_fence = gfx_v10_0_ring_emit_fence,
8613         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8614         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8615         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8616         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8617         .test_ring = gfx_v10_0_ring_test_ring,
8618         .test_ib = gfx_v10_0_ring_test_ib,
8619         .insert_nop = amdgpu_ring_insert_nop,
8620         .pad_ib = amdgpu_ring_generic_pad_ib,
8621         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8622         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8623         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8624         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8625         .preempt_ib = gfx_v10_0_ring_preempt_ib,
8626         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8627         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8628         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8629         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8630         .soft_recovery = gfx_v10_0_ring_soft_recovery,
8631         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8632 };
8633
8634 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8635         .type = AMDGPU_RING_TYPE_COMPUTE,
8636         .align_mask = 0xff,
8637         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8638         .support_64bit_ptrs = true,
8639         .vmhub = AMDGPU_GFXHUB_0,
8640         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8641         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8642         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8643         .emit_frame_size =
8644                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8645                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8646                 5 + /* hdp invalidate */
8647                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8648                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8649                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8650                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8651                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8652                 8, /* gfx_v10_0_emit_mem_sync */
8653         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8654         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8655         .emit_fence = gfx_v10_0_ring_emit_fence,
8656         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8657         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8658         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8659         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8660         .test_ring = gfx_v10_0_ring_test_ring,
8661         .test_ib = gfx_v10_0_ring_test_ib,
8662         .insert_nop = amdgpu_ring_insert_nop,
8663         .pad_ib = amdgpu_ring_generic_pad_ib,
8664         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8665         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8666         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8667         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8668 };
8669
8670 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8671         .type = AMDGPU_RING_TYPE_KIQ,
8672         .align_mask = 0xff,
8673         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8674         .support_64bit_ptrs = true,
8675         .vmhub = AMDGPU_GFXHUB_0,
8676         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8677         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8678         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8679         .emit_frame_size =
8680                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8681                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8682                 5 + /*hdp invalidate */
8683                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8684                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8685                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8686                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8687                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8688         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8689         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8690         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8691         .test_ring = gfx_v10_0_ring_test_ring,
8692         .test_ib = gfx_v10_0_ring_test_ib,
8693         .insert_nop = amdgpu_ring_insert_nop,
8694         .pad_ib = amdgpu_ring_generic_pad_ib,
8695         .emit_rreg = gfx_v10_0_ring_emit_rreg,
8696         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8697         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8698         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8699 };
8700
8701 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8702 {
8703         int i;
8704
8705         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
8706
8707         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
8708                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
8709
8710         for (i = 0; i < adev->gfx.num_compute_rings; i++)
8711                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
8712 }
8713
8714 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
8715         .set = gfx_v10_0_set_eop_interrupt_state,
8716         .process = gfx_v10_0_eop_irq,
8717 };
8718
8719 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
8720         .set = gfx_v10_0_set_priv_reg_fault_state,
8721         .process = gfx_v10_0_priv_reg_irq,
8722 };
8723
8724 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
8725         .set = gfx_v10_0_set_priv_inst_fault_state,
8726         .process = gfx_v10_0_priv_inst_irq,
8727 };
8728
8729 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
8730         .set = gfx_v10_0_kiq_set_interrupt_state,
8731         .process = gfx_v10_0_kiq_irq,
8732 };
8733
8734 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
8735 {
8736         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
8737         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
8738
8739         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
8740         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
8741
8742         adev->gfx.priv_reg_irq.num_types = 1;
8743         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
8744
8745         adev->gfx.priv_inst_irq.num_types = 1;
8746         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
8747 }
8748
8749 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
8750 {
8751         switch (adev->asic_type) {
8752         case CHIP_NAVI10:
8753         case CHIP_NAVI14:
8754         case CHIP_SIENNA_CICHLID:
8755         case CHIP_NAVY_FLOUNDER:
8756         case CHIP_VANGOGH:
8757                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
8758                 break;
8759         case CHIP_NAVI12:
8760                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
8761                 break;
8762         default:
8763                 break;
8764         }
8765 }
8766
8767 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
8768 {
8769         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
8770                             adev->gfx.config.max_sh_per_se *
8771                             adev->gfx.config.max_shader_engines;
8772
8773         adev->gds.gds_size = 0x10000;
8774         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
8775         adev->gds.gws_size = 64;
8776         adev->gds.oa_size = 16;
8777 }
8778
8779 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
8780                                                           u32 bitmap)
8781 {
8782         u32 data;
8783
8784         if (!bitmap)
8785                 return;
8786
8787         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8788         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8789
8790         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
8791 }
8792
8793 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
8794 {
8795         u32 data, wgp_bitmask;
8796         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
8797         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
8798
8799         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8800         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8801
8802         wgp_bitmask =
8803                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
8804
8805         return (~data) & wgp_bitmask;
8806 }
8807
8808 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
8809 {
8810         u32 wgp_idx, wgp_active_bitmap;
8811         u32 cu_bitmap_per_wgp, cu_active_bitmap;
8812
8813         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
8814         cu_active_bitmap = 0;
8815
8816         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
8817                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
8818                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
8819                 if (wgp_active_bitmap & (1 << wgp_idx))
8820                         cu_active_bitmap |= cu_bitmap_per_wgp;
8821         }
8822
8823         return cu_active_bitmap;
8824 }
8825
8826 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
8827                                  struct amdgpu_cu_info *cu_info)
8828 {
8829         int i, j, k, counter, active_cu_number = 0;
8830         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
8831         unsigned disable_masks[4 * 2];
8832
8833         if (!adev || !cu_info)
8834                 return -EINVAL;
8835
8836         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
8837
8838         mutex_lock(&adev->grbm_idx_mutex);
8839         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
8840                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
8841                         mask = 1;
8842                         ao_bitmap = 0;
8843                         counter = 0;
8844                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
8845                         if (i < 4 && j < 2)
8846                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
8847                                         adev, disable_masks[i * 2 + j]);
8848                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
8849                         cu_info->bitmap[i][j] = bitmap;
8850
8851                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
8852                                 if (bitmap & mask) {
8853                                         if (counter < adev->gfx.config.max_cu_per_sh)
8854                                                 ao_bitmap |= mask;
8855                                         counter++;
8856                                 }
8857                                 mask <<= 1;
8858                         }
8859                         active_cu_number += counter;
8860                         if (i < 2 && j < 2)
8861                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
8862                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
8863                 }
8864         }
8865         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
8866         mutex_unlock(&adev->grbm_idx_mutex);
8867
8868         cu_info->number = active_cu_number;
8869         cu_info->ao_cu_mask = ao_cu_mask;
8870         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
8871
8872         return 0;
8873 }
8874
8875 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
8876 {
8877         .type = AMD_IP_BLOCK_TYPE_GFX,
8878         .major = 10,
8879         .minor = 0,
8880         .rev = 0,
8881         .funcs = &gfx_v10_0_ip_funcs,
8882 };