2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
26 #include "amdgpu_ih.h"
27 #include "amdgpu_gfx.h"
30 #include "cik_structs.h"
32 #include "amdgpu_ucode.h"
33 #include "clearstate_ci.h"
35 #include "dce/dce_8_0_d.h"
36 #include "dce/dce_8_0_sh_mask.h"
38 #include "bif/bif_4_1_d.h"
39 #include "bif/bif_4_1_sh_mask.h"
41 #include "gca/gfx_7_0_d.h"
42 #include "gca/gfx_7_2_enum.h"
43 #include "gca/gfx_7_2_sh_mask.h"
45 #include "gmc/gmc_7_0_d.h"
46 #include "gmc/gmc_7_0_sh_mask.h"
48 #include "oss/oss_2_0_d.h"
49 #include "oss/oss_2_0_sh_mask.h"
51 #define GFX7_NUM_GFX_RINGS 1
52 #define GFX7_NUM_COMPUTE_RINGS 8
53 #define GFX7_MEC_HPD_SIZE 2048
55 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device
*adev
);
56 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device
*adev
);
57 static void gfx_v7_0_set_gds_init(struct amdgpu_device
*adev
);
59 MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
60 MODULE_FIRMWARE("radeon/bonaire_me.bin");
61 MODULE_FIRMWARE("radeon/bonaire_ce.bin");
62 MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
63 MODULE_FIRMWARE("radeon/bonaire_mec.bin");
65 MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
66 MODULE_FIRMWARE("radeon/hawaii_me.bin");
67 MODULE_FIRMWARE("radeon/hawaii_ce.bin");
68 MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
69 MODULE_FIRMWARE("radeon/hawaii_mec.bin");
71 MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
72 MODULE_FIRMWARE("radeon/kaveri_me.bin");
73 MODULE_FIRMWARE("radeon/kaveri_ce.bin");
74 MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
75 MODULE_FIRMWARE("radeon/kaveri_mec.bin");
76 MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
78 MODULE_FIRMWARE("radeon/kabini_pfp.bin");
79 MODULE_FIRMWARE("radeon/kabini_me.bin");
80 MODULE_FIRMWARE("radeon/kabini_ce.bin");
81 MODULE_FIRMWARE("radeon/kabini_rlc.bin");
82 MODULE_FIRMWARE("radeon/kabini_mec.bin");
84 MODULE_FIRMWARE("radeon/mullins_pfp.bin");
85 MODULE_FIRMWARE("radeon/mullins_me.bin");
86 MODULE_FIRMWARE("radeon/mullins_ce.bin");
87 MODULE_FIRMWARE("radeon/mullins_rlc.bin");
88 MODULE_FIRMWARE("radeon/mullins_mec.bin");
90 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset
[] =
92 {mmGDS_VMID0_BASE
, mmGDS_VMID0_SIZE
, mmGDS_GWS_VMID0
, mmGDS_OA_VMID0
},
93 {mmGDS_VMID1_BASE
, mmGDS_VMID1_SIZE
, mmGDS_GWS_VMID1
, mmGDS_OA_VMID1
},
94 {mmGDS_VMID2_BASE
, mmGDS_VMID2_SIZE
, mmGDS_GWS_VMID2
, mmGDS_OA_VMID2
},
95 {mmGDS_VMID3_BASE
, mmGDS_VMID3_SIZE
, mmGDS_GWS_VMID3
, mmGDS_OA_VMID3
},
96 {mmGDS_VMID4_BASE
, mmGDS_VMID4_SIZE
, mmGDS_GWS_VMID4
, mmGDS_OA_VMID4
},
97 {mmGDS_VMID5_BASE
, mmGDS_VMID5_SIZE
, mmGDS_GWS_VMID5
, mmGDS_OA_VMID5
},
98 {mmGDS_VMID6_BASE
, mmGDS_VMID6_SIZE
, mmGDS_GWS_VMID6
, mmGDS_OA_VMID6
},
99 {mmGDS_VMID7_BASE
, mmGDS_VMID7_SIZE
, mmGDS_GWS_VMID7
, mmGDS_OA_VMID7
},
100 {mmGDS_VMID8_BASE
, mmGDS_VMID8_SIZE
, mmGDS_GWS_VMID8
, mmGDS_OA_VMID8
},
101 {mmGDS_VMID9_BASE
, mmGDS_VMID9_SIZE
, mmGDS_GWS_VMID9
, mmGDS_OA_VMID9
},
102 {mmGDS_VMID10_BASE
, mmGDS_VMID10_SIZE
, mmGDS_GWS_VMID10
, mmGDS_OA_VMID10
},
103 {mmGDS_VMID11_BASE
, mmGDS_VMID11_SIZE
, mmGDS_GWS_VMID11
, mmGDS_OA_VMID11
},
104 {mmGDS_VMID12_BASE
, mmGDS_VMID12_SIZE
, mmGDS_GWS_VMID12
, mmGDS_OA_VMID12
},
105 {mmGDS_VMID13_BASE
, mmGDS_VMID13_SIZE
, mmGDS_GWS_VMID13
, mmGDS_OA_VMID13
},
106 {mmGDS_VMID14_BASE
, mmGDS_VMID14_SIZE
, mmGDS_GWS_VMID14
, mmGDS_OA_VMID14
},
107 {mmGDS_VMID15_BASE
, mmGDS_VMID15_SIZE
, mmGDS_GWS_VMID15
, mmGDS_OA_VMID15
}
110 static const u32 spectre_rlc_save_restore_register_list
[] =
112 (0x0e00 << 16) | (0xc12c >> 2),
114 (0x0e00 << 16) | (0xc140 >> 2),
116 (0x0e00 << 16) | (0xc150 >> 2),
118 (0x0e00 << 16) | (0xc15c >> 2),
120 (0x0e00 << 16) | (0xc168 >> 2),
122 (0x0e00 << 16) | (0xc170 >> 2),
124 (0x0e00 << 16) | (0xc178 >> 2),
126 (0x0e00 << 16) | (0xc204 >> 2),
128 (0x0e00 << 16) | (0xc2b4 >> 2),
130 (0x0e00 << 16) | (0xc2b8 >> 2),
132 (0x0e00 << 16) | (0xc2bc >> 2),
134 (0x0e00 << 16) | (0xc2c0 >> 2),
136 (0x0e00 << 16) | (0x8228 >> 2),
138 (0x0e00 << 16) | (0x829c >> 2),
140 (0x0e00 << 16) | (0x869c >> 2),
142 (0x0600 << 16) | (0x98f4 >> 2),
144 (0x0e00 << 16) | (0x98f8 >> 2),
146 (0x0e00 << 16) | (0x9900 >> 2),
148 (0x0e00 << 16) | (0xc260 >> 2),
150 (0x0e00 << 16) | (0x90e8 >> 2),
152 (0x0e00 << 16) | (0x3c000 >> 2),
154 (0x0e00 << 16) | (0x3c00c >> 2),
156 (0x0e00 << 16) | (0x8c1c >> 2),
158 (0x0e00 << 16) | (0x9700 >> 2),
160 (0x0e00 << 16) | (0xcd20 >> 2),
162 (0x4e00 << 16) | (0xcd20 >> 2),
164 (0x5e00 << 16) | (0xcd20 >> 2),
166 (0x6e00 << 16) | (0xcd20 >> 2),
168 (0x7e00 << 16) | (0xcd20 >> 2),
170 (0x8e00 << 16) | (0xcd20 >> 2),
172 (0x9e00 << 16) | (0xcd20 >> 2),
174 (0xae00 << 16) | (0xcd20 >> 2),
176 (0xbe00 << 16) | (0xcd20 >> 2),
178 (0x0e00 << 16) | (0x89bc >> 2),
180 (0x0e00 << 16) | (0x8900 >> 2),
183 (0x0e00 << 16) | (0xc130 >> 2),
185 (0x0e00 << 16) | (0xc134 >> 2),
187 (0x0e00 << 16) | (0xc1fc >> 2),
189 (0x0e00 << 16) | (0xc208 >> 2),
191 (0x0e00 << 16) | (0xc264 >> 2),
193 (0x0e00 << 16) | (0xc268 >> 2),
195 (0x0e00 << 16) | (0xc26c >> 2),
197 (0x0e00 << 16) | (0xc270 >> 2),
199 (0x0e00 << 16) | (0xc274 >> 2),
201 (0x0e00 << 16) | (0xc278 >> 2),
203 (0x0e00 << 16) | (0xc27c >> 2),
205 (0x0e00 << 16) | (0xc280 >> 2),
207 (0x0e00 << 16) | (0xc284 >> 2),
209 (0x0e00 << 16) | (0xc288 >> 2),
211 (0x0e00 << 16) | (0xc28c >> 2),
213 (0x0e00 << 16) | (0xc290 >> 2),
215 (0x0e00 << 16) | (0xc294 >> 2),
217 (0x0e00 << 16) | (0xc298 >> 2),
219 (0x0e00 << 16) | (0xc29c >> 2),
221 (0x0e00 << 16) | (0xc2a0 >> 2),
223 (0x0e00 << 16) | (0xc2a4 >> 2),
225 (0x0e00 << 16) | (0xc2a8 >> 2),
227 (0x0e00 << 16) | (0xc2ac >> 2),
229 (0x0e00 << 16) | (0xc2b0 >> 2),
231 (0x0e00 << 16) | (0x301d0 >> 2),
233 (0x0e00 << 16) | (0x30238 >> 2),
235 (0x0e00 << 16) | (0x30250 >> 2),
237 (0x0e00 << 16) | (0x30254 >> 2),
239 (0x0e00 << 16) | (0x30258 >> 2),
241 (0x0e00 << 16) | (0x3025c >> 2),
243 (0x4e00 << 16) | (0xc900 >> 2),
245 (0x5e00 << 16) | (0xc900 >> 2),
247 (0x6e00 << 16) | (0xc900 >> 2),
249 (0x7e00 << 16) | (0xc900 >> 2),
251 (0x8e00 << 16) | (0xc900 >> 2),
253 (0x9e00 << 16) | (0xc900 >> 2),
255 (0xae00 << 16) | (0xc900 >> 2),
257 (0xbe00 << 16) | (0xc900 >> 2),
259 (0x4e00 << 16) | (0xc904 >> 2),
261 (0x5e00 << 16) | (0xc904 >> 2),
263 (0x6e00 << 16) | (0xc904 >> 2),
265 (0x7e00 << 16) | (0xc904 >> 2),
267 (0x8e00 << 16) | (0xc904 >> 2),
269 (0x9e00 << 16) | (0xc904 >> 2),
271 (0xae00 << 16) | (0xc904 >> 2),
273 (0xbe00 << 16) | (0xc904 >> 2),
275 (0x4e00 << 16) | (0xc908 >> 2),
277 (0x5e00 << 16) | (0xc908 >> 2),
279 (0x6e00 << 16) | (0xc908 >> 2),
281 (0x7e00 << 16) | (0xc908 >> 2),
283 (0x8e00 << 16) | (0xc908 >> 2),
285 (0x9e00 << 16) | (0xc908 >> 2),
287 (0xae00 << 16) | (0xc908 >> 2),
289 (0xbe00 << 16) | (0xc908 >> 2),
291 (0x4e00 << 16) | (0xc90c >> 2),
293 (0x5e00 << 16) | (0xc90c >> 2),
295 (0x6e00 << 16) | (0xc90c >> 2),
297 (0x7e00 << 16) | (0xc90c >> 2),
299 (0x8e00 << 16) | (0xc90c >> 2),
301 (0x9e00 << 16) | (0xc90c >> 2),
303 (0xae00 << 16) | (0xc90c >> 2),
305 (0xbe00 << 16) | (0xc90c >> 2),
307 (0x4e00 << 16) | (0xc910 >> 2),
309 (0x5e00 << 16) | (0xc910 >> 2),
311 (0x6e00 << 16) | (0xc910 >> 2),
313 (0x7e00 << 16) | (0xc910 >> 2),
315 (0x8e00 << 16) | (0xc910 >> 2),
317 (0x9e00 << 16) | (0xc910 >> 2),
319 (0xae00 << 16) | (0xc910 >> 2),
321 (0xbe00 << 16) | (0xc910 >> 2),
323 (0x0e00 << 16) | (0xc99c >> 2),
325 (0x0e00 << 16) | (0x9834 >> 2),
327 (0x0000 << 16) | (0x30f00 >> 2),
329 (0x0001 << 16) | (0x30f00 >> 2),
331 (0x0000 << 16) | (0x30f04 >> 2),
333 (0x0001 << 16) | (0x30f04 >> 2),
335 (0x0000 << 16) | (0x30f08 >> 2),
337 (0x0001 << 16) | (0x30f08 >> 2),
339 (0x0000 << 16) | (0x30f0c >> 2),
341 (0x0001 << 16) | (0x30f0c >> 2),
343 (0x0600 << 16) | (0x9b7c >> 2),
345 (0x0e00 << 16) | (0x8a14 >> 2),
347 (0x0e00 << 16) | (0x8a18 >> 2),
349 (0x0600 << 16) | (0x30a00 >> 2),
351 (0x0e00 << 16) | (0x8bf0 >> 2),
353 (0x0e00 << 16) | (0x8bcc >> 2),
355 (0x0e00 << 16) | (0x8b24 >> 2),
357 (0x0e00 << 16) | (0x30a04 >> 2),
359 (0x0600 << 16) | (0x30a10 >> 2),
361 (0x0600 << 16) | (0x30a14 >> 2),
363 (0x0600 << 16) | (0x30a18 >> 2),
365 (0x0600 << 16) | (0x30a2c >> 2),
367 (0x0e00 << 16) | (0xc700 >> 2),
369 (0x0e00 << 16) | (0xc704 >> 2),
371 (0x0e00 << 16) | (0xc708 >> 2),
373 (0x0e00 << 16) | (0xc768 >> 2),
375 (0x0400 << 16) | (0xc770 >> 2),
377 (0x0400 << 16) | (0xc774 >> 2),
379 (0x0400 << 16) | (0xc778 >> 2),
381 (0x0400 << 16) | (0xc77c >> 2),
383 (0x0400 << 16) | (0xc780 >> 2),
385 (0x0400 << 16) | (0xc784 >> 2),
387 (0x0400 << 16) | (0xc788 >> 2),
389 (0x0400 << 16) | (0xc78c >> 2),
391 (0x0400 << 16) | (0xc798 >> 2),
393 (0x0400 << 16) | (0xc79c >> 2),
395 (0x0400 << 16) | (0xc7a0 >> 2),
397 (0x0400 << 16) | (0xc7a4 >> 2),
399 (0x0400 << 16) | (0xc7a8 >> 2),
401 (0x0400 << 16) | (0xc7ac >> 2),
403 (0x0400 << 16) | (0xc7b0 >> 2),
405 (0x0400 << 16) | (0xc7b4 >> 2),
407 (0x0e00 << 16) | (0x9100 >> 2),
409 (0x0e00 << 16) | (0x3c010 >> 2),
411 (0x0e00 << 16) | (0x92a8 >> 2),
413 (0x0e00 << 16) | (0x92ac >> 2),
415 (0x0e00 << 16) | (0x92b4 >> 2),
417 (0x0e00 << 16) | (0x92b8 >> 2),
419 (0x0e00 << 16) | (0x92bc >> 2),
421 (0x0e00 << 16) | (0x92c0 >> 2),
423 (0x0e00 << 16) | (0x92c4 >> 2),
425 (0x0e00 << 16) | (0x92c8 >> 2),
427 (0x0e00 << 16) | (0x92cc >> 2),
429 (0x0e00 << 16) | (0x92d0 >> 2),
431 (0x0e00 << 16) | (0x8c00 >> 2),
433 (0x0e00 << 16) | (0x8c04 >> 2),
435 (0x0e00 << 16) | (0x8c20 >> 2),
437 (0x0e00 << 16) | (0x8c38 >> 2),
439 (0x0e00 << 16) | (0x8c3c >> 2),
441 (0x0e00 << 16) | (0xae00 >> 2),
443 (0x0e00 << 16) | (0x9604 >> 2),
445 (0x0e00 << 16) | (0xac08 >> 2),
447 (0x0e00 << 16) | (0xac0c >> 2),
449 (0x0e00 << 16) | (0xac10 >> 2),
451 (0x0e00 << 16) | (0xac14 >> 2),
453 (0x0e00 << 16) | (0xac58 >> 2),
455 (0x0e00 << 16) | (0xac68 >> 2),
457 (0x0e00 << 16) | (0xac6c >> 2),
459 (0x0e00 << 16) | (0xac70 >> 2),
461 (0x0e00 << 16) | (0xac74 >> 2),
463 (0x0e00 << 16) | (0xac78 >> 2),
465 (0x0e00 << 16) | (0xac7c >> 2),
467 (0x0e00 << 16) | (0xac80 >> 2),
469 (0x0e00 << 16) | (0xac84 >> 2),
471 (0x0e00 << 16) | (0xac88 >> 2),
473 (0x0e00 << 16) | (0xac8c >> 2),
475 (0x0e00 << 16) | (0x970c >> 2),
477 (0x0e00 << 16) | (0x9714 >> 2),
479 (0x0e00 << 16) | (0x9718 >> 2),
481 (0x0e00 << 16) | (0x971c >> 2),
483 (0x0e00 << 16) | (0x31068 >> 2),
485 (0x4e00 << 16) | (0x31068 >> 2),
487 (0x5e00 << 16) | (0x31068 >> 2),
489 (0x6e00 << 16) | (0x31068 >> 2),
491 (0x7e00 << 16) | (0x31068 >> 2),
493 (0x8e00 << 16) | (0x31068 >> 2),
495 (0x9e00 << 16) | (0x31068 >> 2),
497 (0xae00 << 16) | (0x31068 >> 2),
499 (0xbe00 << 16) | (0x31068 >> 2),
501 (0x0e00 << 16) | (0xcd10 >> 2),
503 (0x0e00 << 16) | (0xcd14 >> 2),
505 (0x0e00 << 16) | (0x88b0 >> 2),
507 (0x0e00 << 16) | (0x88b4 >> 2),
509 (0x0e00 << 16) | (0x88b8 >> 2),
511 (0x0e00 << 16) | (0x88bc >> 2),
513 (0x0400 << 16) | (0x89c0 >> 2),
515 (0x0e00 << 16) | (0x88c4 >> 2),
517 (0x0e00 << 16) | (0x88c8 >> 2),
519 (0x0e00 << 16) | (0x88d0 >> 2),
521 (0x0e00 << 16) | (0x88d4 >> 2),
523 (0x0e00 << 16) | (0x88d8 >> 2),
525 (0x0e00 << 16) | (0x8980 >> 2),
527 (0x0e00 << 16) | (0x30938 >> 2),
529 (0x0e00 << 16) | (0x3093c >> 2),
531 (0x0e00 << 16) | (0x30940 >> 2),
533 (0x0e00 << 16) | (0x89a0 >> 2),
535 (0x0e00 << 16) | (0x30900 >> 2),
537 (0x0e00 << 16) | (0x30904 >> 2),
539 (0x0e00 << 16) | (0x89b4 >> 2),
541 (0x0e00 << 16) | (0x3c210 >> 2),
543 (0x0e00 << 16) | (0x3c214 >> 2),
545 (0x0e00 << 16) | (0x3c218 >> 2),
547 (0x0e00 << 16) | (0x8904 >> 2),
550 (0x0e00 << 16) | (0x8c28 >> 2),
551 (0x0e00 << 16) | (0x8c2c >> 2),
552 (0x0e00 << 16) | (0x8c30 >> 2),
553 (0x0e00 << 16) | (0x8c34 >> 2),
554 (0x0e00 << 16) | (0x9600 >> 2),
557 static const u32 kalindi_rlc_save_restore_register_list
[] =
559 (0x0e00 << 16) | (0xc12c >> 2),
561 (0x0e00 << 16) | (0xc140 >> 2),
563 (0x0e00 << 16) | (0xc150 >> 2),
565 (0x0e00 << 16) | (0xc15c >> 2),
567 (0x0e00 << 16) | (0xc168 >> 2),
569 (0x0e00 << 16) | (0xc170 >> 2),
571 (0x0e00 << 16) | (0xc204 >> 2),
573 (0x0e00 << 16) | (0xc2b4 >> 2),
575 (0x0e00 << 16) | (0xc2b8 >> 2),
577 (0x0e00 << 16) | (0xc2bc >> 2),
579 (0x0e00 << 16) | (0xc2c0 >> 2),
581 (0x0e00 << 16) | (0x8228 >> 2),
583 (0x0e00 << 16) | (0x829c >> 2),
585 (0x0e00 << 16) | (0x869c >> 2),
587 (0x0600 << 16) | (0x98f4 >> 2),
589 (0x0e00 << 16) | (0x98f8 >> 2),
591 (0x0e00 << 16) | (0x9900 >> 2),
593 (0x0e00 << 16) | (0xc260 >> 2),
595 (0x0e00 << 16) | (0x90e8 >> 2),
597 (0x0e00 << 16) | (0x3c000 >> 2),
599 (0x0e00 << 16) | (0x3c00c >> 2),
601 (0x0e00 << 16) | (0x8c1c >> 2),
603 (0x0e00 << 16) | (0x9700 >> 2),
605 (0x0e00 << 16) | (0xcd20 >> 2),
607 (0x4e00 << 16) | (0xcd20 >> 2),
609 (0x5e00 << 16) | (0xcd20 >> 2),
611 (0x6e00 << 16) | (0xcd20 >> 2),
613 (0x7e00 << 16) | (0xcd20 >> 2),
615 (0x0e00 << 16) | (0x89bc >> 2),
617 (0x0e00 << 16) | (0x8900 >> 2),
620 (0x0e00 << 16) | (0xc130 >> 2),
622 (0x0e00 << 16) | (0xc134 >> 2),
624 (0x0e00 << 16) | (0xc1fc >> 2),
626 (0x0e00 << 16) | (0xc208 >> 2),
628 (0x0e00 << 16) | (0xc264 >> 2),
630 (0x0e00 << 16) | (0xc268 >> 2),
632 (0x0e00 << 16) | (0xc26c >> 2),
634 (0x0e00 << 16) | (0xc270 >> 2),
636 (0x0e00 << 16) | (0xc274 >> 2),
638 (0x0e00 << 16) | (0xc28c >> 2),
640 (0x0e00 << 16) | (0xc290 >> 2),
642 (0x0e00 << 16) | (0xc294 >> 2),
644 (0x0e00 << 16) | (0xc298 >> 2),
646 (0x0e00 << 16) | (0xc2a0 >> 2),
648 (0x0e00 << 16) | (0xc2a4 >> 2),
650 (0x0e00 << 16) | (0xc2a8 >> 2),
652 (0x0e00 << 16) | (0xc2ac >> 2),
654 (0x0e00 << 16) | (0x301d0 >> 2),
656 (0x0e00 << 16) | (0x30238 >> 2),
658 (0x0e00 << 16) | (0x30250 >> 2),
660 (0x0e00 << 16) | (0x30254 >> 2),
662 (0x0e00 << 16) | (0x30258 >> 2),
664 (0x0e00 << 16) | (0x3025c >> 2),
666 (0x4e00 << 16) | (0xc900 >> 2),
668 (0x5e00 << 16) | (0xc900 >> 2),
670 (0x6e00 << 16) | (0xc900 >> 2),
672 (0x7e00 << 16) | (0xc900 >> 2),
674 (0x4e00 << 16) | (0xc904 >> 2),
676 (0x5e00 << 16) | (0xc904 >> 2),
678 (0x6e00 << 16) | (0xc904 >> 2),
680 (0x7e00 << 16) | (0xc904 >> 2),
682 (0x4e00 << 16) | (0xc908 >> 2),
684 (0x5e00 << 16) | (0xc908 >> 2),
686 (0x6e00 << 16) | (0xc908 >> 2),
688 (0x7e00 << 16) | (0xc908 >> 2),
690 (0x4e00 << 16) | (0xc90c >> 2),
692 (0x5e00 << 16) | (0xc90c >> 2),
694 (0x6e00 << 16) | (0xc90c >> 2),
696 (0x7e00 << 16) | (0xc90c >> 2),
698 (0x4e00 << 16) | (0xc910 >> 2),
700 (0x5e00 << 16) | (0xc910 >> 2),
702 (0x6e00 << 16) | (0xc910 >> 2),
704 (0x7e00 << 16) | (0xc910 >> 2),
706 (0x0e00 << 16) | (0xc99c >> 2),
708 (0x0e00 << 16) | (0x9834 >> 2),
710 (0x0000 << 16) | (0x30f00 >> 2),
712 (0x0000 << 16) | (0x30f04 >> 2),
714 (0x0000 << 16) | (0x30f08 >> 2),
716 (0x0000 << 16) | (0x30f0c >> 2),
718 (0x0600 << 16) | (0x9b7c >> 2),
720 (0x0e00 << 16) | (0x8a14 >> 2),
722 (0x0e00 << 16) | (0x8a18 >> 2),
724 (0x0600 << 16) | (0x30a00 >> 2),
726 (0x0e00 << 16) | (0x8bf0 >> 2),
728 (0x0e00 << 16) | (0x8bcc >> 2),
730 (0x0e00 << 16) | (0x8b24 >> 2),
732 (0x0e00 << 16) | (0x30a04 >> 2),
734 (0x0600 << 16) | (0x30a10 >> 2),
736 (0x0600 << 16) | (0x30a14 >> 2),
738 (0x0600 << 16) | (0x30a18 >> 2),
740 (0x0600 << 16) | (0x30a2c >> 2),
742 (0x0e00 << 16) | (0xc700 >> 2),
744 (0x0e00 << 16) | (0xc704 >> 2),
746 (0x0e00 << 16) | (0xc708 >> 2),
748 (0x0e00 << 16) | (0xc768 >> 2),
750 (0x0400 << 16) | (0xc770 >> 2),
752 (0x0400 << 16) | (0xc774 >> 2),
754 (0x0400 << 16) | (0xc798 >> 2),
756 (0x0400 << 16) | (0xc79c >> 2),
758 (0x0e00 << 16) | (0x9100 >> 2),
760 (0x0e00 << 16) | (0x3c010 >> 2),
762 (0x0e00 << 16) | (0x8c00 >> 2),
764 (0x0e00 << 16) | (0x8c04 >> 2),
766 (0x0e00 << 16) | (0x8c20 >> 2),
768 (0x0e00 << 16) | (0x8c38 >> 2),
770 (0x0e00 << 16) | (0x8c3c >> 2),
772 (0x0e00 << 16) | (0xae00 >> 2),
774 (0x0e00 << 16) | (0x9604 >> 2),
776 (0x0e00 << 16) | (0xac08 >> 2),
778 (0x0e00 << 16) | (0xac0c >> 2),
780 (0x0e00 << 16) | (0xac10 >> 2),
782 (0x0e00 << 16) | (0xac14 >> 2),
784 (0x0e00 << 16) | (0xac58 >> 2),
786 (0x0e00 << 16) | (0xac68 >> 2),
788 (0x0e00 << 16) | (0xac6c >> 2),
790 (0x0e00 << 16) | (0xac70 >> 2),
792 (0x0e00 << 16) | (0xac74 >> 2),
794 (0x0e00 << 16) | (0xac78 >> 2),
796 (0x0e00 << 16) | (0xac7c >> 2),
798 (0x0e00 << 16) | (0xac80 >> 2),
800 (0x0e00 << 16) | (0xac84 >> 2),
802 (0x0e00 << 16) | (0xac88 >> 2),
804 (0x0e00 << 16) | (0xac8c >> 2),
806 (0x0e00 << 16) | (0x970c >> 2),
808 (0x0e00 << 16) | (0x9714 >> 2),
810 (0x0e00 << 16) | (0x9718 >> 2),
812 (0x0e00 << 16) | (0x971c >> 2),
814 (0x0e00 << 16) | (0x31068 >> 2),
816 (0x4e00 << 16) | (0x31068 >> 2),
818 (0x5e00 << 16) | (0x31068 >> 2),
820 (0x6e00 << 16) | (0x31068 >> 2),
822 (0x7e00 << 16) | (0x31068 >> 2),
824 (0x0e00 << 16) | (0xcd10 >> 2),
826 (0x0e00 << 16) | (0xcd14 >> 2),
828 (0x0e00 << 16) | (0x88b0 >> 2),
830 (0x0e00 << 16) | (0x88b4 >> 2),
832 (0x0e00 << 16) | (0x88b8 >> 2),
834 (0x0e00 << 16) | (0x88bc >> 2),
836 (0x0400 << 16) | (0x89c0 >> 2),
838 (0x0e00 << 16) | (0x88c4 >> 2),
840 (0x0e00 << 16) | (0x88c8 >> 2),
842 (0x0e00 << 16) | (0x88d0 >> 2),
844 (0x0e00 << 16) | (0x88d4 >> 2),
846 (0x0e00 << 16) | (0x88d8 >> 2),
848 (0x0e00 << 16) | (0x8980 >> 2),
850 (0x0e00 << 16) | (0x30938 >> 2),
852 (0x0e00 << 16) | (0x3093c >> 2),
854 (0x0e00 << 16) | (0x30940 >> 2),
856 (0x0e00 << 16) | (0x89a0 >> 2),
858 (0x0e00 << 16) | (0x30900 >> 2),
860 (0x0e00 << 16) | (0x30904 >> 2),
862 (0x0e00 << 16) | (0x89b4 >> 2),
864 (0x0e00 << 16) | (0x3e1fc >> 2),
866 (0x0e00 << 16) | (0x3c210 >> 2),
868 (0x0e00 << 16) | (0x3c214 >> 2),
870 (0x0e00 << 16) | (0x3c218 >> 2),
872 (0x0e00 << 16) | (0x8904 >> 2),
875 (0x0e00 << 16) | (0x8c28 >> 2),
876 (0x0e00 << 16) | (0x8c2c >> 2),
877 (0x0e00 << 16) | (0x8c30 >> 2),
878 (0x0e00 << 16) | (0x8c34 >> 2),
879 (0x0e00 << 16) | (0x9600 >> 2),
882 static u32
gfx_v7_0_get_csb_size(struct amdgpu_device
*adev
);
883 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device
*adev
, volatile u32
*buffer
);
884 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device
*adev
);
885 static void gfx_v7_0_init_pg(struct amdgpu_device
*adev
);
886 static void gfx_v7_0_get_cu_info(struct amdgpu_device
*adev
);
892 * gfx_v7_0_init_microcode - load ucode images from disk
894 * @adev: amdgpu_device pointer
896 * Use the firmware interface to load the ucode images into
897 * the driver (not loaded into hw).
898 * Returns 0 on success, error on failure.
900 static int gfx_v7_0_init_microcode(struct amdgpu_device
*adev
)
902 const char *chip_name
;
908 switch (adev
->asic_type
) {
910 chip_name
= "bonaire";
913 chip_name
= "hawaii";
916 chip_name
= "kaveri";
919 chip_name
= "kabini";
922 chip_name
= "mullins";
927 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_pfp.bin", chip_name
);
928 err
= request_firmware(&adev
->gfx
.pfp_fw
, fw_name
, adev
->dev
);
931 err
= amdgpu_ucode_validate(adev
->gfx
.pfp_fw
);
935 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_me.bin", chip_name
);
936 err
= request_firmware(&adev
->gfx
.me_fw
, fw_name
, adev
->dev
);
939 err
= amdgpu_ucode_validate(adev
->gfx
.me_fw
);
943 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_ce.bin", chip_name
);
944 err
= request_firmware(&adev
->gfx
.ce_fw
, fw_name
, adev
->dev
);
947 err
= amdgpu_ucode_validate(adev
->gfx
.ce_fw
);
951 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_mec.bin", chip_name
);
952 err
= request_firmware(&adev
->gfx
.mec_fw
, fw_name
, adev
->dev
);
955 err
= amdgpu_ucode_validate(adev
->gfx
.mec_fw
);
959 if (adev
->asic_type
== CHIP_KAVERI
) {
960 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_mec2.bin", chip_name
);
961 err
= request_firmware(&adev
->gfx
.mec2_fw
, fw_name
, adev
->dev
);
964 err
= amdgpu_ucode_validate(adev
->gfx
.mec2_fw
);
969 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_rlc.bin", chip_name
);
970 err
= request_firmware(&adev
->gfx
.rlc_fw
, fw_name
, adev
->dev
);
973 err
= amdgpu_ucode_validate(adev
->gfx
.rlc_fw
);
977 pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name
);
978 release_firmware(adev
->gfx
.pfp_fw
);
979 adev
->gfx
.pfp_fw
= NULL
;
980 release_firmware(adev
->gfx
.me_fw
);
981 adev
->gfx
.me_fw
= NULL
;
982 release_firmware(adev
->gfx
.ce_fw
);
983 adev
->gfx
.ce_fw
= NULL
;
984 release_firmware(adev
->gfx
.mec_fw
);
985 adev
->gfx
.mec_fw
= NULL
;
986 release_firmware(adev
->gfx
.mec2_fw
);
987 adev
->gfx
.mec2_fw
= NULL
;
988 release_firmware(adev
->gfx
.rlc_fw
);
989 adev
->gfx
.rlc_fw
= NULL
;
994 static void gfx_v7_0_free_microcode(struct amdgpu_device
*adev
)
996 release_firmware(adev
->gfx
.pfp_fw
);
997 adev
->gfx
.pfp_fw
= NULL
;
998 release_firmware(adev
->gfx
.me_fw
);
999 adev
->gfx
.me_fw
= NULL
;
1000 release_firmware(adev
->gfx
.ce_fw
);
1001 adev
->gfx
.ce_fw
= NULL
;
1002 release_firmware(adev
->gfx
.mec_fw
);
1003 adev
->gfx
.mec_fw
= NULL
;
1004 release_firmware(adev
->gfx
.mec2_fw
);
1005 adev
->gfx
.mec2_fw
= NULL
;
1006 release_firmware(adev
->gfx
.rlc_fw
);
1007 adev
->gfx
.rlc_fw
= NULL
;
1011 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
1013 * @adev: amdgpu_device pointer
1015 * Starting with SI, the tiling setup is done globally in a
1016 * set of 32 tiling modes. Rather than selecting each set of
1017 * parameters per surface as on older asics, we just select
1018 * which index in the tiling table we want to use, and the
1019 * surface uses those parameters (CIK).
1021 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device
*adev
)
1023 const u32 num_tile_mode_states
=
1024 ARRAY_SIZE(adev
->gfx
.config
.tile_mode_array
);
1025 const u32 num_secondary_tile_mode_states
=
1026 ARRAY_SIZE(adev
->gfx
.config
.macrotile_mode_array
);
1027 u32 reg_offset
, split_equal_to_row_size
;
1028 uint32_t *tile
, *macrotile
;
1030 tile
= adev
->gfx
.config
.tile_mode_array
;
1031 macrotile
= adev
->gfx
.config
.macrotile_mode_array
;
1033 switch (adev
->gfx
.config
.mem_row_size_in_kb
) {
1035 split_equal_to_row_size
= ADDR_SURF_TILE_SPLIT_1KB
;
1039 split_equal_to_row_size
= ADDR_SURF_TILE_SPLIT_2KB
;
1042 split_equal_to_row_size
= ADDR_SURF_TILE_SPLIT_4KB
;
1046 for (reg_offset
= 0; reg_offset
< num_tile_mode_states
; reg_offset
++)
1047 tile
[reg_offset
] = 0;
1048 for (reg_offset
= 0; reg_offset
< num_secondary_tile_mode_states
; reg_offset
++)
1049 macrotile
[reg_offset
] = 0;
1051 switch (adev
->asic_type
) {
1053 tile
[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1054 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1055 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B
) |
1056 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1057 tile
[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1058 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1059 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B
) |
1060 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1061 tile
[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1062 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1063 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1064 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1065 tile
[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1066 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1067 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B
) |
1068 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1069 tile
[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1070 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1071 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
) |
1072 TILE_SPLIT(split_equal_to_row_size
));
1073 tile
[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1074 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1075 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1076 tile
[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1077 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1078 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
) |
1079 TILE_SPLIT(split_equal_to_row_size
));
1080 tile
[7] = (TILE_SPLIT(split_equal_to_row_size
));
1081 tile
[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED
) |
1082 PIPE_CONFIG(ADDR_SURF_P4_16x16
));
1083 tile
[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1084 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1085 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
));
1086 tile
[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1087 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1088 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1089 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1090 tile
[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1091 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1092 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1093 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1094 tile
[12] = (TILE_SPLIT(split_equal_to_row_size
));
1095 tile
[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1096 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1097 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
));
1098 tile
[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1099 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1100 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1101 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1102 tile
[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1
) |
1103 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1104 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1105 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1106 tile
[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1107 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1108 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1109 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1110 tile
[17] = (TILE_SPLIT(split_equal_to_row_size
));
1111 tile
[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK
) |
1112 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1113 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1114 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1115 tile
[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK
) |
1116 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1117 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
));
1118 tile
[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK
) |
1119 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1120 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1121 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1122 tile
[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK
) |
1123 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1124 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1125 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1126 tile
[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK
) |
1127 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1128 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1129 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1130 tile
[23] = (TILE_SPLIT(split_equal_to_row_size
));
1131 tile
[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK
) |
1132 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1133 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1134 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1135 tile
[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK
) |
1136 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1137 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1138 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1139 tile
[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK
) |
1140 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1141 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1142 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1143 tile
[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1144 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1145 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
));
1146 tile
[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1147 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1148 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
) |
1149 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1150 tile
[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1151 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1152 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
) |
1153 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1154 tile
[30] = (TILE_SPLIT(split_equal_to_row_size
));
1156 macrotile
[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1159 NUM_BANKS(ADDR_SURF_16_BANK
));
1160 macrotile
[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1163 NUM_BANKS(ADDR_SURF_16_BANK
));
1164 macrotile
[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1167 NUM_BANKS(ADDR_SURF_16_BANK
));
1168 macrotile
[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1171 NUM_BANKS(ADDR_SURF_16_BANK
));
1172 macrotile
[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1175 NUM_BANKS(ADDR_SURF_16_BANK
));
1176 macrotile
[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1179 NUM_BANKS(ADDR_SURF_8_BANK
));
1180 macrotile
[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1183 NUM_BANKS(ADDR_SURF_4_BANK
));
1184 macrotile
[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2
) |
1185 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8
) |
1186 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1187 NUM_BANKS(ADDR_SURF_16_BANK
));
1188 macrotile
[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2
) |
1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1191 NUM_BANKS(ADDR_SURF_16_BANK
));
1192 macrotile
[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1193 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1194 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1195 NUM_BANKS(ADDR_SURF_16_BANK
));
1196 macrotile
[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1199 NUM_BANKS(ADDR_SURF_16_BANK
));
1200 macrotile
[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1201 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1202 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1203 NUM_BANKS(ADDR_SURF_16_BANK
));
1204 macrotile
[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1205 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1206 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1207 NUM_BANKS(ADDR_SURF_8_BANK
));
1208 macrotile
[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1209 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1210 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1211 NUM_BANKS(ADDR_SURF_4_BANK
));
1213 for (reg_offset
= 0; reg_offset
< num_tile_mode_states
; reg_offset
++)
1214 WREG32(mmGB_TILE_MODE0
+ reg_offset
, tile
[reg_offset
]);
1215 for (reg_offset
= 0; reg_offset
< num_secondary_tile_mode_states
; reg_offset
++)
1216 if (reg_offset
!= 7)
1217 WREG32(mmGB_MACROTILE_MODE0
+ reg_offset
, macrotile
[reg_offset
]);
1220 tile
[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1221 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1222 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B
) |
1223 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1224 tile
[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1225 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1226 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B
) |
1227 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1228 tile
[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1229 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1230 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1231 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1232 tile
[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1233 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1234 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B
) |
1235 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1236 tile
[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1237 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1238 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
) |
1239 TILE_SPLIT(split_equal_to_row_size
));
1240 tile
[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1241 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1242 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
) |
1243 TILE_SPLIT(split_equal_to_row_size
));
1244 tile
[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1245 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1246 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
) |
1247 TILE_SPLIT(split_equal_to_row_size
));
1248 tile
[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1249 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1250 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
) |
1251 TILE_SPLIT(split_equal_to_row_size
));
1252 tile
[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED
) |
1253 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
));
1254 tile
[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1255 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1256 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
));
1257 tile
[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1258 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1259 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1260 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1261 tile
[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1262 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1263 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1264 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1265 tile
[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1
) |
1266 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1267 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1268 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1269 tile
[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1270 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1271 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
));
1272 tile
[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1273 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1274 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1275 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1276 tile
[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1
) |
1277 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1278 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1279 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1280 tile
[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1281 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1282 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1283 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1284 tile
[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1285 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1286 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1287 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1288 tile
[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK
) |
1289 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1290 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1291 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1292 tile
[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK
) |
1293 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1294 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
));
1295 tile
[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK
) |
1296 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1297 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1298 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1299 tile
[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK
) |
1300 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1301 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1302 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1303 tile
[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK
) |
1304 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1305 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1306 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1307 tile
[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK
) |
1308 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1309 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1310 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1311 tile
[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK
) |
1312 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1313 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1314 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1315 tile
[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK
) |
1316 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1317 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1318 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1319 tile
[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK
) |
1320 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1321 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1322 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1323 tile
[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1324 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1325 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
));
1326 tile
[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1327 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1328 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
) |
1329 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1330 tile
[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1331 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1332 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
) |
1333 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1334 tile
[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1335 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1336 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
) |
1337 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1339 macrotile
[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1342 NUM_BANKS(ADDR_SURF_16_BANK
));
1343 macrotile
[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1346 NUM_BANKS(ADDR_SURF_16_BANK
));
1347 macrotile
[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1350 NUM_BANKS(ADDR_SURF_16_BANK
));
1351 macrotile
[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1354 NUM_BANKS(ADDR_SURF_16_BANK
));
1355 macrotile
[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1358 NUM_BANKS(ADDR_SURF_8_BANK
));
1359 macrotile
[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1362 NUM_BANKS(ADDR_SURF_4_BANK
));
1363 macrotile
[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1364 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1365 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1366 NUM_BANKS(ADDR_SURF_4_BANK
));
1367 macrotile
[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1370 NUM_BANKS(ADDR_SURF_16_BANK
));
1371 macrotile
[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1374 NUM_BANKS(ADDR_SURF_16_BANK
));
1375 macrotile
[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1376 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1377 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1378 NUM_BANKS(ADDR_SURF_16_BANK
));
1379 macrotile
[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1380 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1381 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1382 NUM_BANKS(ADDR_SURF_8_BANK
));
1383 macrotile
[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1384 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1385 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1386 NUM_BANKS(ADDR_SURF_16_BANK
));
1387 macrotile
[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1388 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1389 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1390 NUM_BANKS(ADDR_SURF_8_BANK
));
1391 macrotile
[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1392 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1393 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1394 NUM_BANKS(ADDR_SURF_4_BANK
));
1396 for (reg_offset
= 0; reg_offset
< num_tile_mode_states
; reg_offset
++)
1397 WREG32(mmGB_TILE_MODE0
+ reg_offset
, tile
[reg_offset
]);
1398 for (reg_offset
= 0; reg_offset
< num_secondary_tile_mode_states
; reg_offset
++)
1399 if (reg_offset
!= 7)
1400 WREG32(mmGB_MACROTILE_MODE0
+ reg_offset
, macrotile
[reg_offset
]);
1406 tile
[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1407 PIPE_CONFIG(ADDR_SURF_P2
) |
1408 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B
) |
1409 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1410 tile
[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1411 PIPE_CONFIG(ADDR_SURF_P2
) |
1412 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B
) |
1413 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1414 tile
[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1415 PIPE_CONFIG(ADDR_SURF_P2
) |
1416 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1417 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1418 tile
[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1419 PIPE_CONFIG(ADDR_SURF_P2
) |
1420 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B
) |
1421 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1422 tile
[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1423 PIPE_CONFIG(ADDR_SURF_P2
) |
1424 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
) |
1425 TILE_SPLIT(split_equal_to_row_size
));
1426 tile
[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1427 PIPE_CONFIG(ADDR_SURF_P2
) |
1428 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1429 tile
[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1430 PIPE_CONFIG(ADDR_SURF_P2
) |
1431 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
) |
1432 TILE_SPLIT(split_equal_to_row_size
));
1433 tile
[7] = (TILE_SPLIT(split_equal_to_row_size
));
1434 tile
[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED
) |
1435 PIPE_CONFIG(ADDR_SURF_P2
));
1436 tile
[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1437 PIPE_CONFIG(ADDR_SURF_P2
) |
1438 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
));
1439 tile
[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1440 PIPE_CONFIG(ADDR_SURF_P2
) |
1441 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1442 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1443 tile
[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1444 PIPE_CONFIG(ADDR_SURF_P2
) |
1445 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1446 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1447 tile
[12] = (TILE_SPLIT(split_equal_to_row_size
));
1448 tile
[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1449 PIPE_CONFIG(ADDR_SURF_P2
) |
1450 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
));
1451 tile
[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1452 PIPE_CONFIG(ADDR_SURF_P2
) |
1453 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1454 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1455 tile
[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1
) |
1456 PIPE_CONFIG(ADDR_SURF_P2
) |
1457 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1458 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1459 tile
[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1460 PIPE_CONFIG(ADDR_SURF_P2
) |
1461 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1462 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1463 tile
[17] = (TILE_SPLIT(split_equal_to_row_size
));
1464 tile
[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK
) |
1465 PIPE_CONFIG(ADDR_SURF_P2
) |
1466 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1467 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1468 tile
[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK
) |
1469 PIPE_CONFIG(ADDR_SURF_P2
) |
1470 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
));
1471 tile
[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK
) |
1472 PIPE_CONFIG(ADDR_SURF_P2
) |
1473 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1474 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1475 tile
[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK
) |
1476 PIPE_CONFIG(ADDR_SURF_P2
) |
1477 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1478 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1479 tile
[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK
) |
1480 PIPE_CONFIG(ADDR_SURF_P2
) |
1481 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1482 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1483 tile
[23] = (TILE_SPLIT(split_equal_to_row_size
));
1484 tile
[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK
) |
1485 PIPE_CONFIG(ADDR_SURF_P2
) |
1486 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1487 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1488 tile
[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK
) |
1489 PIPE_CONFIG(ADDR_SURF_P2
) |
1490 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1491 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1492 tile
[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK
) |
1493 PIPE_CONFIG(ADDR_SURF_P2
) |
1494 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1495 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1496 tile
[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1497 PIPE_CONFIG(ADDR_SURF_P2
) |
1498 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
));
1499 tile
[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1500 PIPE_CONFIG(ADDR_SURF_P2
) |
1501 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
) |
1502 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1503 tile
[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1504 PIPE_CONFIG(ADDR_SURF_P2
) |
1505 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
) |
1506 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1507 tile
[30] = (TILE_SPLIT(split_equal_to_row_size
));
1509 macrotile
[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1511 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1512 NUM_BANKS(ADDR_SURF_8_BANK
));
1513 macrotile
[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1516 NUM_BANKS(ADDR_SURF_8_BANK
));
1517 macrotile
[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1520 NUM_BANKS(ADDR_SURF_8_BANK
));
1521 macrotile
[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1524 NUM_BANKS(ADDR_SURF_8_BANK
));
1525 macrotile
[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1528 NUM_BANKS(ADDR_SURF_8_BANK
));
1529 macrotile
[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1532 NUM_BANKS(ADDR_SURF_8_BANK
));
1533 macrotile
[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1536 NUM_BANKS(ADDR_SURF_8_BANK
));
1537 macrotile
[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4
) |
1538 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8
) |
1539 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1540 NUM_BANKS(ADDR_SURF_16_BANK
));
1541 macrotile
[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4
) |
1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1544 NUM_BANKS(ADDR_SURF_16_BANK
));
1545 macrotile
[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2
) |
1546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1548 NUM_BANKS(ADDR_SURF_16_BANK
));
1549 macrotile
[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2
) |
1550 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1551 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1552 NUM_BANKS(ADDR_SURF_16_BANK
));
1553 macrotile
[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1556 NUM_BANKS(ADDR_SURF_16_BANK
));
1557 macrotile
[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1558 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1559 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1560 NUM_BANKS(ADDR_SURF_16_BANK
));
1561 macrotile
[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1562 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1563 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1564 NUM_BANKS(ADDR_SURF_8_BANK
));
1566 for (reg_offset
= 0; reg_offset
< num_tile_mode_states
; reg_offset
++)
1567 WREG32(mmGB_TILE_MODE0
+ reg_offset
, tile
[reg_offset
]);
1568 for (reg_offset
= 0; reg_offset
< num_secondary_tile_mode_states
; reg_offset
++)
1569 if (reg_offset
!= 7)
1570 WREG32(mmGB_MACROTILE_MODE0
+ reg_offset
, macrotile
[reg_offset
]);
1576 * gfx_v7_0_select_se_sh - select which SE, SH to address
1578 * @adev: amdgpu_device pointer
1579 * @se_num: shader engine to address
1580 * @sh_num: sh block to address
1582 * Select which SE, SH combinations to address. Certain
1583 * registers are instanced per SE or SH. 0xffffffff means
1584 * broadcast to all SEs or SHs (CIK).
1586 static void gfx_v7_0_select_se_sh(struct amdgpu_device
*adev
,
1587 u32 se_num
, u32 sh_num
, u32 instance
)
1591 if (instance
== 0xffffffff)
1592 data
= REG_SET_FIELD(0, GRBM_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
, 1);
1594 data
= REG_SET_FIELD(0, GRBM_GFX_INDEX
, INSTANCE_INDEX
, instance
);
1596 if ((se_num
== 0xffffffff) && (sh_num
== 0xffffffff))
1597 data
|= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK
|
1598 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK
;
1599 else if (se_num
== 0xffffffff)
1600 data
|= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK
|
1601 (sh_num
<< GRBM_GFX_INDEX__SH_INDEX__SHIFT
);
1602 else if (sh_num
== 0xffffffff)
1603 data
|= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK
|
1604 (se_num
<< GRBM_GFX_INDEX__SE_INDEX__SHIFT
);
1606 data
|= (sh_num
<< GRBM_GFX_INDEX__SH_INDEX__SHIFT
) |
1607 (se_num
<< GRBM_GFX_INDEX__SE_INDEX__SHIFT
);
1608 WREG32(mmGRBM_GFX_INDEX
, data
);
1612 * gfx_v7_0_create_bitmask - create a bitmask
1614 * @bit_width: length of the mask
1616 * create a variable length bit mask (CIK).
1617 * Returns the bitmask.
1619 static u32
gfx_v7_0_create_bitmask(u32 bit_width
)
1621 return (u32
)((1ULL << bit_width
) - 1);
1625 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
1627 * @adev: amdgpu_device pointer
1629 * Calculates the bitmask of enabled RBs (CIK).
1630 * Returns the enabled RB bitmask.
1632 static u32
gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device
*adev
)
1636 data
= RREG32(mmCC_RB_BACKEND_DISABLE
);
1637 data
|= RREG32(mmGC_USER_RB_BACKEND_DISABLE
);
1639 data
&= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK
;
1640 data
>>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT
;
1642 mask
= gfx_v7_0_create_bitmask(adev
->gfx
.config
.max_backends_per_se
/
1643 adev
->gfx
.config
.max_sh_per_se
);
1645 return (~data
) & mask
;
1649 gfx_v7_0_raster_config(struct amdgpu_device
*adev
, u32
*rconf
, u32
*rconf1
)
1651 switch (adev
->asic_type
) {
1653 *rconf
|= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
1654 SE_XSEL(1) | SE_YSEL(1);
1658 *rconf
|= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
1659 RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) |
1660 PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) |
1662 *rconf1
|= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
1666 *rconf
|= RB_MAP_PKR0(2);
1675 DRM_ERROR("unknown asic: 0x%x\n", adev
->asic_type
);
1681 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device
*adev
,
1682 u32 raster_config
, u32 raster_config_1
,
1683 unsigned rb_mask
, unsigned num_rb
)
1685 unsigned sh_per_se
= max_t(unsigned, adev
->gfx
.config
.max_sh_per_se
, 1);
1686 unsigned num_se
= max_t(unsigned, adev
->gfx
.config
.max_shader_engines
, 1);
1687 unsigned rb_per_pkr
= min_t(unsigned, num_rb
/ num_se
/ sh_per_se
, 2);
1688 unsigned rb_per_se
= num_rb
/ num_se
;
1689 unsigned se_mask
[4];
1692 se_mask
[0] = ((1 << rb_per_se
) - 1) & rb_mask
;
1693 se_mask
[1] = (se_mask
[0] << rb_per_se
) & rb_mask
;
1694 se_mask
[2] = (se_mask
[1] << rb_per_se
) & rb_mask
;
1695 se_mask
[3] = (se_mask
[2] << rb_per_se
) & rb_mask
;
1697 WARN_ON(!(num_se
== 1 || num_se
== 2 || num_se
== 4));
1698 WARN_ON(!(sh_per_se
== 1 || sh_per_se
== 2));
1699 WARN_ON(!(rb_per_pkr
== 1 || rb_per_pkr
== 2));
1701 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
1702 (!se_mask
[2] && !se_mask
[3]))) {
1703 raster_config_1
&= ~SE_PAIR_MAP_MASK
;
1705 if (!se_mask
[0] && !se_mask
[1]) {
1707 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3
);
1710 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0
);
1714 for (se
= 0; se
< num_se
; se
++) {
1715 unsigned raster_config_se
= raster_config
;
1716 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
1717 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
1718 int idx
= (se
/ 2) * 2;
1720 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
1721 raster_config_se
&= ~SE_MAP_MASK
;
1723 if (!se_mask
[idx
]) {
1724 raster_config_se
|= SE_MAP(RASTER_CONFIG_SE_MAP_3
);
1726 raster_config_se
|= SE_MAP(RASTER_CONFIG_SE_MAP_0
);
1730 pkr0_mask
&= rb_mask
;
1731 pkr1_mask
&= rb_mask
;
1732 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
1733 raster_config_se
&= ~PKR_MAP_MASK
;
1736 raster_config_se
|= PKR_MAP(RASTER_CONFIG_PKR_MAP_3
);
1738 raster_config_se
|= PKR_MAP(RASTER_CONFIG_PKR_MAP_0
);
1742 if (rb_per_se
>= 2) {
1743 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
1744 unsigned rb1_mask
= rb0_mask
<< 1;
1746 rb0_mask
&= rb_mask
;
1747 rb1_mask
&= rb_mask
;
1748 if (!rb0_mask
|| !rb1_mask
) {
1749 raster_config_se
&= ~RB_MAP_PKR0_MASK
;
1753 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3
);
1756 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0
);
1760 if (rb_per_se
> 2) {
1761 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
1762 rb1_mask
= rb0_mask
<< 1;
1763 rb0_mask
&= rb_mask
;
1764 rb1_mask
&= rb_mask
;
1765 if (!rb0_mask
|| !rb1_mask
) {
1766 raster_config_se
&= ~RB_MAP_PKR1_MASK
;
1770 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3
);
1773 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0
);
1779 /* GRBM_GFX_INDEX has a different offset on CI+ */
1780 gfx_v7_0_select_se_sh(adev
, se
, 0xffffffff, 0xffffffff);
1781 WREG32(mmPA_SC_RASTER_CONFIG
, raster_config_se
);
1782 WREG32(mmPA_SC_RASTER_CONFIG_1
, raster_config_1
);
1785 /* GRBM_GFX_INDEX has a different offset on CI+ */
1786 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
1790 * gfx_v7_0_setup_rb - setup the RBs on the asic
1792 * @adev: amdgpu_device pointer
1793 * @se_num: number of SEs (shader engines) for the asic
1794 * @sh_per_se: number of SH blocks per SE for the asic
1796 * Configures per-SE/SH RB registers (CIK).
1798 static void gfx_v7_0_setup_rb(struct amdgpu_device
*adev
)
1802 u32 raster_config
= 0, raster_config_1
= 0;
1804 u32 rb_bitmap_width_per_sh
= adev
->gfx
.config
.max_backends_per_se
/
1805 adev
->gfx
.config
.max_sh_per_se
;
1806 unsigned num_rb_pipes
;
1808 mutex_lock(&adev
->grbm_idx_mutex
);
1809 for (i
= 0; i
< adev
->gfx
.config
.max_shader_engines
; i
++) {
1810 for (j
= 0; j
< adev
->gfx
.config
.max_sh_per_se
; j
++) {
1811 gfx_v7_0_select_se_sh(adev
, i
, j
, 0xffffffff);
1812 data
= gfx_v7_0_get_rb_active_bitmap(adev
);
1813 active_rbs
|= data
<< ((i
* adev
->gfx
.config
.max_sh_per_se
+ j
) *
1814 rb_bitmap_width_per_sh
);
1817 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
1819 adev
->gfx
.config
.backend_enable_mask
= active_rbs
;
1820 adev
->gfx
.config
.num_rbs
= hweight32(active_rbs
);
1822 num_rb_pipes
= min_t(unsigned, adev
->gfx
.config
.max_backends_per_se
*
1823 adev
->gfx
.config
.max_shader_engines
, 16);
1825 gfx_v7_0_raster_config(adev
, &raster_config
, &raster_config_1
);
1827 if (!adev
->gfx
.config
.backend_enable_mask
||
1828 adev
->gfx
.config
.num_rbs
>= num_rb_pipes
) {
1829 WREG32(mmPA_SC_RASTER_CONFIG
, raster_config
);
1830 WREG32(mmPA_SC_RASTER_CONFIG_1
, raster_config_1
);
1832 gfx_v7_0_write_harvested_raster_configs(adev
, raster_config
, raster_config_1
,
1833 adev
->gfx
.config
.backend_enable_mask
,
1836 mutex_unlock(&adev
->grbm_idx_mutex
);
1840 * gmc_v7_0_init_compute_vmid - gart enable
1842 * @rdev: amdgpu_device pointer
1844 * Initialize compute vmid sh_mem registers
1847 #define DEFAULT_SH_MEM_BASES (0x6000)
1848 #define FIRST_COMPUTE_VMID (8)
1849 #define LAST_COMPUTE_VMID (16)
1850 static void gmc_v7_0_init_compute_vmid(struct amdgpu_device
*adev
)
1853 uint32_t sh_mem_config
;
1854 uint32_t sh_mem_bases
;
1857 * Configure apertures:
1858 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1859 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1860 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1862 sh_mem_bases
= DEFAULT_SH_MEM_BASES
| (DEFAULT_SH_MEM_BASES
<< 16);
1863 sh_mem_config
= SH_MEM_ALIGNMENT_MODE_UNALIGNED
<<
1864 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT
;
1865 sh_mem_config
|= MTYPE_NONCACHED
<< SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT
;
1866 mutex_lock(&adev
->srbm_mutex
);
1867 for (i
= FIRST_COMPUTE_VMID
; i
< LAST_COMPUTE_VMID
; i
++) {
1868 cik_srbm_select(adev
, 0, 0, 0, i
);
1869 /* CP and shaders */
1870 WREG32(mmSH_MEM_CONFIG
, sh_mem_config
);
1871 WREG32(mmSH_MEM_APE1_BASE
, 1);
1872 WREG32(mmSH_MEM_APE1_LIMIT
, 0);
1873 WREG32(mmSH_MEM_BASES
, sh_mem_bases
);
1875 cik_srbm_select(adev
, 0, 0, 0, 0);
1876 mutex_unlock(&adev
->srbm_mutex
);
1879 static void gfx_v7_0_config_init(struct amdgpu_device
*adev
)
1881 adev
->gfx
.config
.double_offchip_lds_buf
= 1;
1885 * gfx_v7_0_gpu_init - setup the 3D engine
1887 * @adev: amdgpu_device pointer
1889 * Configures the 3D engine and tiling configuration
1890 * registers so that the 3D engine is usable.
1892 static void gfx_v7_0_gpu_init(struct amdgpu_device
*adev
)
1894 u32 sh_mem_cfg
, sh_static_mem_cfg
, sh_mem_base
;
1898 WREG32(mmGRBM_CNTL
, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT
));
1900 WREG32(mmGB_ADDR_CONFIG
, adev
->gfx
.config
.gb_addr_config
);
1901 WREG32(mmHDP_ADDR_CONFIG
, adev
->gfx
.config
.gb_addr_config
);
1902 WREG32(mmDMIF_ADDR_CALC
, adev
->gfx
.config
.gb_addr_config
);
1904 gfx_v7_0_tiling_mode_table_init(adev
);
1906 gfx_v7_0_setup_rb(adev
);
1907 gfx_v7_0_get_cu_info(adev
);
1908 gfx_v7_0_config_init(adev
);
1910 /* set HW defaults for 3D engine */
1911 WREG32(mmCP_MEQ_THRESHOLDS
,
1912 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT
) |
1913 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT
));
1915 mutex_lock(&adev
->grbm_idx_mutex
);
1917 * making sure that the following register writes will be broadcasted
1918 * to all the shaders
1920 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
1922 /* XXX SH_MEM regs */
1923 /* where to put LDS, scratch, GPUVM in FSA64 space */
1924 sh_mem_cfg
= REG_SET_FIELD(0, SH_MEM_CONFIG
, ALIGNMENT_MODE
,
1925 SH_MEM_ALIGNMENT_MODE_UNALIGNED
);
1926 sh_mem_cfg
= REG_SET_FIELD(sh_mem_cfg
, SH_MEM_CONFIG
, DEFAULT_MTYPE
,
1928 sh_mem_cfg
= REG_SET_FIELD(sh_mem_cfg
, SH_MEM_CONFIG
, APE1_MTYPE
,
1930 sh_mem_cfg
= REG_SET_FIELD(sh_mem_cfg
, SH_MEM_CONFIG
, PRIVATE_ATC
, 0);
1932 sh_static_mem_cfg
= REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG
,
1934 sh_static_mem_cfg
= REG_SET_FIELD(sh_static_mem_cfg
, SH_STATIC_MEM_CONFIG
,
1936 sh_static_mem_cfg
= REG_SET_FIELD(sh_static_mem_cfg
, SH_STATIC_MEM_CONFIG
,
1939 mutex_lock(&adev
->srbm_mutex
);
1940 for (i
= 0; i
< adev
->vm_manager
.id_mgr
[0].num_ids
; i
++) {
1944 sh_mem_base
= adev
->mc
.shared_aperture_start
>> 48;
1945 cik_srbm_select(adev
, 0, 0, 0, i
);
1946 /* CP and shaders */
1947 WREG32(mmSH_MEM_CONFIG
, sh_mem_cfg
);
1948 WREG32(mmSH_MEM_APE1_BASE
, 1);
1949 WREG32(mmSH_MEM_APE1_LIMIT
, 0);
1950 WREG32(mmSH_MEM_BASES
, sh_mem_base
);
1951 WREG32(mmSH_STATIC_MEM_CONFIG
, sh_static_mem_cfg
);
1953 cik_srbm_select(adev
, 0, 0, 0, 0);
1954 mutex_unlock(&adev
->srbm_mutex
);
1956 gmc_v7_0_init_compute_vmid(adev
);
1958 WREG32(mmSX_DEBUG_1
, 0x20);
1960 WREG32(mmTA_CNTL_AUX
, 0x00010000);
1962 tmp
= RREG32(mmSPI_CONFIG_CNTL
);
1964 WREG32(mmSPI_CONFIG_CNTL
, tmp
);
1966 WREG32(mmSQ_CONFIG
, 1);
1968 WREG32(mmDB_DEBUG
, 0);
1970 tmp
= RREG32(mmDB_DEBUG2
) & ~0xf00fffff;
1972 WREG32(mmDB_DEBUG2
, tmp
);
1974 tmp
= RREG32(mmDB_DEBUG3
) & ~0x0002021c;
1976 WREG32(mmDB_DEBUG3
, tmp
);
1978 tmp
= RREG32(mmCB_HW_CONTROL
) & ~0x00010000;
1980 WREG32(mmCB_HW_CONTROL
, tmp
);
1982 WREG32(mmSPI_CONFIG_CNTL_1
, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT
));
1984 WREG32(mmPA_SC_FIFO_SIZE
,
1985 ((adev
->gfx
.config
.sc_prim_fifo_size_frontend
<< PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT
) |
1986 (adev
->gfx
.config
.sc_prim_fifo_size_backend
<< PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT
) |
1987 (adev
->gfx
.config
.sc_hiz_tile_fifo_size
<< PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT
) |
1988 (adev
->gfx
.config
.sc_earlyz_tile_fifo_size
<< PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT
)));
1990 WREG32(mmVGT_NUM_INSTANCES
, 1);
1992 WREG32(mmCP_PERFMON_CNTL
, 0);
1994 WREG32(mmSQ_CONFIG
, 0);
1996 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS
,
1997 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT
) |
1998 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT
)));
2000 WREG32(mmVGT_CACHE_INVALIDATION
,
2001 (VC_AND_TC
<< VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT
) |
2002 (ES_AND_GS_AUTO
<< VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT
));
2004 WREG32(mmVGT_GS_VERTEX_REUSE
, 16);
2005 WREG32(mmPA_SC_LINE_STIPPLE_STATE
, 0);
2007 WREG32(mmPA_CL_ENHANCE
, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK
|
2008 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT
));
2009 WREG32(mmPA_SC_ENHANCE
, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK
);
2011 tmp
= RREG32(mmSPI_ARB_PRIORITY
);
2012 tmp
= REG_SET_FIELD(tmp
, SPI_ARB_PRIORITY
, PIPE_ORDER_TS0
, 2);
2013 tmp
= REG_SET_FIELD(tmp
, SPI_ARB_PRIORITY
, PIPE_ORDER_TS1
, 2);
2014 tmp
= REG_SET_FIELD(tmp
, SPI_ARB_PRIORITY
, PIPE_ORDER_TS2
, 2);
2015 tmp
= REG_SET_FIELD(tmp
, SPI_ARB_PRIORITY
, PIPE_ORDER_TS3
, 2);
2016 WREG32(mmSPI_ARB_PRIORITY
, tmp
);
2018 mutex_unlock(&adev
->grbm_idx_mutex
);
2024 * GPU scratch registers helpers function.
2027 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
2029 * @adev: amdgpu_device pointer
2031 * Set up the number and offset of the CP scratch registers.
2032 * NOTE: use of CP scratch registers is a legacy inferface and
2033 * is not used by default on newer asics (r6xx+). On newer asics,
2034 * memory buffers are used for fences rather than scratch regs.
2036 static void gfx_v7_0_scratch_init(struct amdgpu_device
*adev
)
2038 adev
->gfx
.scratch
.num_reg
= 7;
2039 adev
->gfx
.scratch
.reg_base
= mmSCRATCH_REG0
;
2040 adev
->gfx
.scratch
.free_mask
= (1u << adev
->gfx
.scratch
.num_reg
) - 1;
2044 * gfx_v7_0_ring_test_ring - basic gfx ring test
2046 * @adev: amdgpu_device pointer
2047 * @ring: amdgpu_ring structure holding ring information
2049 * Allocate a scratch register and write to it using the gfx ring (CIK).
2050 * Provides a basic gfx ring test to verify that the ring is working.
2051 * Used by gfx_v7_0_cp_gfx_resume();
2052 * Returns 0 on success, error on failure.
2054 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring
*ring
)
2056 struct amdgpu_device
*adev
= ring
->adev
;
2062 r
= amdgpu_gfx_scratch_get(adev
, &scratch
);
2064 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r
);
2067 WREG32(scratch
, 0xCAFEDEAD);
2068 r
= amdgpu_ring_alloc(ring
, 3);
2070 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring
->idx
, r
);
2071 amdgpu_gfx_scratch_free(adev
, scratch
);
2074 amdgpu_ring_write(ring
, PACKET3(PACKET3_SET_UCONFIG_REG
, 1));
2075 amdgpu_ring_write(ring
, (scratch
- PACKET3_SET_UCONFIG_REG_START
));
2076 amdgpu_ring_write(ring
, 0xDEADBEEF);
2077 amdgpu_ring_commit(ring
);
2079 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
2080 tmp
= RREG32(scratch
);
2081 if (tmp
== 0xDEADBEEF)
2085 if (i
< adev
->usec_timeout
) {
2086 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring
->idx
, i
);
2088 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2089 ring
->idx
, scratch
, tmp
);
2092 amdgpu_gfx_scratch_free(adev
, scratch
);
2097 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
2099 * @adev: amdgpu_device pointer
2100 * @ridx: amdgpu ring index
2102 * Emits an hdp flush on the cp.
2104 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring
*ring
)
2107 int usepfp
= ring
->funcs
->type
== AMDGPU_RING_TYPE_COMPUTE
? 0 : 1;
2109 if (ring
->funcs
->type
== AMDGPU_RING_TYPE_COMPUTE
) {
2112 ref_and_mask
= GPU_HDP_FLUSH_DONE__CP2_MASK
<< ring
->pipe
;
2115 ref_and_mask
= GPU_HDP_FLUSH_DONE__CP6_MASK
<< ring
->pipe
;
2121 ref_and_mask
= GPU_HDP_FLUSH_DONE__CP0_MASK
;
2124 amdgpu_ring_write(ring
, PACKET3(PACKET3_WAIT_REG_MEM
, 5));
2125 amdgpu_ring_write(ring
, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2126 WAIT_REG_MEM_FUNCTION(3) | /* == */
2127 WAIT_REG_MEM_ENGINE(usepfp
))); /* pfp or me */
2128 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_REQ
);
2129 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_DONE
);
2130 amdgpu_ring_write(ring
, ref_and_mask
);
2131 amdgpu_ring_write(ring
, ref_and_mask
);
2132 amdgpu_ring_write(ring
, 0x20); /* poll interval */
2135 static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring
*ring
)
2137 amdgpu_ring_write(ring
, PACKET3(PACKET3_EVENT_WRITE
, 0));
2138 amdgpu_ring_write(ring
, EVENT_TYPE(VS_PARTIAL_FLUSH
) |
2141 amdgpu_ring_write(ring
, PACKET3(PACKET3_EVENT_WRITE
, 0));
2142 amdgpu_ring_write(ring
, EVENT_TYPE(VGT_FLUSH
) |
2148 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
2150 * @adev: amdgpu_device pointer
2151 * @ridx: amdgpu ring index
2153 * Emits an hdp invalidate on the cp.
2155 static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring
*ring
)
2157 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
2158 amdgpu_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(0) |
2159 WRITE_DATA_DST_SEL(0) |
2161 amdgpu_ring_write(ring
, mmHDP_DEBUG0
);
2162 amdgpu_ring_write(ring
, 0);
2163 amdgpu_ring_write(ring
, 1);
2167 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2169 * @adev: amdgpu_device pointer
2170 * @fence: amdgpu fence object
2172 * Emits a fence sequnce number on the gfx ring and flushes
2175 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring
*ring
, u64 addr
,
2176 u64 seq
, unsigned flags
)
2178 bool write64bit
= flags
& AMDGPU_FENCE_FLAG_64BIT
;
2179 bool int_sel
= flags
& AMDGPU_FENCE_FLAG_INT
;
2180 /* Workaround for cache flush problems. First send a dummy EOP
2181 * event down the pipe with seq one below.
2183 amdgpu_ring_write(ring
, PACKET3(PACKET3_EVENT_WRITE_EOP
, 4));
2184 amdgpu_ring_write(ring
, (EOP_TCL1_ACTION_EN
|
2186 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT
) |
2188 amdgpu_ring_write(ring
, addr
& 0xfffffffc);
2189 amdgpu_ring_write(ring
, (upper_32_bits(addr
) & 0xffff) |
2190 DATA_SEL(1) | INT_SEL(0));
2191 amdgpu_ring_write(ring
, lower_32_bits(seq
- 1));
2192 amdgpu_ring_write(ring
, upper_32_bits(seq
- 1));
2194 /* Then send the real EOP event down the pipe. */
2195 amdgpu_ring_write(ring
, PACKET3(PACKET3_EVENT_WRITE_EOP
, 4));
2196 amdgpu_ring_write(ring
, (EOP_TCL1_ACTION_EN
|
2198 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT
) |
2200 amdgpu_ring_write(ring
, addr
& 0xfffffffc);
2201 amdgpu_ring_write(ring
, (upper_32_bits(addr
) & 0xffff) |
2202 DATA_SEL(write64bit
? 2 : 1) | INT_SEL(int_sel
? 2 : 0));
2203 amdgpu_ring_write(ring
, lower_32_bits(seq
));
2204 amdgpu_ring_write(ring
, upper_32_bits(seq
));
2208 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2210 * @adev: amdgpu_device pointer
2211 * @fence: amdgpu fence object
2213 * Emits a fence sequnce number on the compute ring and flushes
2216 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring
*ring
,
2220 bool write64bit
= flags
& AMDGPU_FENCE_FLAG_64BIT
;
2221 bool int_sel
= flags
& AMDGPU_FENCE_FLAG_INT
;
2223 /* RELEASE_MEM - flush caches, send int */
2224 amdgpu_ring_write(ring
, PACKET3(PACKET3_RELEASE_MEM
, 5));
2225 amdgpu_ring_write(ring
, (EOP_TCL1_ACTION_EN
|
2227 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT
) |
2229 amdgpu_ring_write(ring
, DATA_SEL(write64bit
? 2 : 1) | INT_SEL(int_sel
? 2 : 0));
2230 amdgpu_ring_write(ring
, addr
& 0xfffffffc);
2231 amdgpu_ring_write(ring
, upper_32_bits(addr
));
2232 amdgpu_ring_write(ring
, lower_32_bits(seq
));
2233 amdgpu_ring_write(ring
, upper_32_bits(seq
));
2240 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2242 * @ring: amdgpu_ring structure holding ring information
2243 * @ib: amdgpu indirect buffer object
2245 * Emits an DE (drawing engine) or CE (constant engine) IB
2246 * on the gfx ring. IBs are usually generated by userspace
2247 * acceleration drivers and submitted to the kernel for
2248 * sheduling on the ring. This function schedules the IB
2249 * on the gfx ring for execution by the GPU.
2251 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring
*ring
,
2252 struct amdgpu_ib
*ib
,
2253 unsigned vm_id
, bool ctx_switch
)
2255 u32 header
, control
= 0;
2257 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2259 amdgpu_ring_write(ring
, PACKET3(PACKET3_SWITCH_BUFFER
, 0));
2260 amdgpu_ring_write(ring
, 0);
2263 if (ib
->flags
& AMDGPU_IB_FLAG_CE
)
2264 header
= PACKET3(PACKET3_INDIRECT_BUFFER_CONST
, 2);
2266 header
= PACKET3(PACKET3_INDIRECT_BUFFER
, 2);
2268 control
|= ib
->length_dw
| (vm_id
<< 24);
2270 amdgpu_ring_write(ring
, header
);
2271 amdgpu_ring_write(ring
,
2275 (ib
->gpu_addr
& 0xFFFFFFFC));
2276 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xFFFF);
2277 amdgpu_ring_write(ring
, control
);
2280 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring
*ring
,
2281 struct amdgpu_ib
*ib
,
2282 unsigned vm_id
, bool ctx_switch
)
2284 u32 control
= INDIRECT_BUFFER_VALID
| ib
->length_dw
| (vm_id
<< 24);
2286 amdgpu_ring_write(ring
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
2287 amdgpu_ring_write(ring
,
2291 (ib
->gpu_addr
& 0xFFFFFFFC));
2292 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xFFFF);
2293 amdgpu_ring_write(ring
, control
);
2296 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring
*ring
, uint32_t flags
)
2300 dw2
|= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2301 if (flags
& AMDGPU_HAVE_CTX_SWITCH
) {
2302 gfx_v7_0_ring_emit_vgt_flush(ring
);
2303 /* set load_global_config & load_global_uconfig */
2305 /* set load_cs_sh_regs */
2307 /* set load_per_context_state & load_gfx_sh_regs */
2311 amdgpu_ring_write(ring
, PACKET3(PACKET3_CONTEXT_CONTROL
, 1));
2312 amdgpu_ring_write(ring
, dw2
);
2313 amdgpu_ring_write(ring
, 0);
2317 * gfx_v7_0_ring_test_ib - basic ring IB test
2319 * @ring: amdgpu_ring structure holding ring information
2321 * Allocate an IB and execute it on the gfx ring (CIK).
2322 * Provides a basic gfx ring test to verify that IBs are working.
2323 * Returns 0 on success, error on failure.
2325 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring
*ring
, long timeout
)
2327 struct amdgpu_device
*adev
= ring
->adev
;
2328 struct amdgpu_ib ib
;
2329 struct dma_fence
*f
= NULL
;
2334 r
= amdgpu_gfx_scratch_get(adev
, &scratch
);
2336 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r
);
2339 WREG32(scratch
, 0xCAFEDEAD);
2340 memset(&ib
, 0, sizeof(ib
));
2341 r
= amdgpu_ib_get(adev
, NULL
, 256, &ib
);
2343 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r
);
2346 ib
.ptr
[0] = PACKET3(PACKET3_SET_UCONFIG_REG
, 1);
2347 ib
.ptr
[1] = ((scratch
- PACKET3_SET_UCONFIG_REG_START
));
2348 ib
.ptr
[2] = 0xDEADBEEF;
2351 r
= amdgpu_ib_schedule(ring
, 1, &ib
, NULL
, &f
);
2355 r
= dma_fence_wait_timeout(f
, false, timeout
);
2357 DRM_ERROR("amdgpu: IB test timed out\n");
2361 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r
);
2364 tmp
= RREG32(scratch
);
2365 if (tmp
== 0xDEADBEEF) {
2366 DRM_INFO("ib test on ring %d succeeded\n", ring
->idx
);
2369 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2375 amdgpu_ib_free(adev
, &ib
, NULL
);
2378 amdgpu_gfx_scratch_free(adev
, scratch
);
2384 * On CIK, gfx and compute now have independant command processors.
2387 * Gfx consists of a single ring and can process both gfx jobs and
2388 * compute jobs. The gfx CP consists of three microengines (ME):
2389 * PFP - Pre-Fetch Parser
2391 * CE - Constant Engine
2392 * The PFP and ME make up what is considered the Drawing Engine (DE).
2393 * The CE is an asynchronous engine used for updating buffer desciptors
2394 * used by the DE so that they can be loaded into cache in parallel
2395 * while the DE is processing state update packets.
2398 * The compute CP consists of two microengines (ME):
2399 * MEC1 - Compute MicroEngine 1
2400 * MEC2 - Compute MicroEngine 2
2401 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2402 * The queues are exposed to userspace and are programmed directly
2403 * by the compute runtime.
2406 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2408 * @adev: amdgpu_device pointer
2409 * @enable: enable or disable the MEs
2411 * Halts or unhalts the gfx MEs.
2413 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device
*adev
, bool enable
)
2418 WREG32(mmCP_ME_CNTL
, 0);
2420 WREG32(mmCP_ME_CNTL
, (CP_ME_CNTL__ME_HALT_MASK
| CP_ME_CNTL__PFP_HALT_MASK
| CP_ME_CNTL__CE_HALT_MASK
));
2421 for (i
= 0; i
< adev
->gfx
.num_gfx_rings
; i
++)
2422 adev
->gfx
.gfx_ring
[i
].ready
= false;
2428 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2430 * @adev: amdgpu_device pointer
2432 * Loads the gfx PFP, ME, and CE ucode.
2433 * Returns 0 for success, -EINVAL if the ucode is not available.
2435 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device
*adev
)
2437 const struct gfx_firmware_header_v1_0
*pfp_hdr
;
2438 const struct gfx_firmware_header_v1_0
*ce_hdr
;
2439 const struct gfx_firmware_header_v1_0
*me_hdr
;
2440 const __le32
*fw_data
;
2441 unsigned i
, fw_size
;
2443 if (!adev
->gfx
.me_fw
|| !adev
->gfx
.pfp_fw
|| !adev
->gfx
.ce_fw
)
2446 pfp_hdr
= (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.pfp_fw
->data
;
2447 ce_hdr
= (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.ce_fw
->data
;
2448 me_hdr
= (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.me_fw
->data
;
2450 amdgpu_ucode_print_gfx_hdr(&pfp_hdr
->header
);
2451 amdgpu_ucode_print_gfx_hdr(&ce_hdr
->header
);
2452 amdgpu_ucode_print_gfx_hdr(&me_hdr
->header
);
2453 adev
->gfx
.pfp_fw_version
= le32_to_cpu(pfp_hdr
->header
.ucode_version
);
2454 adev
->gfx
.ce_fw_version
= le32_to_cpu(ce_hdr
->header
.ucode_version
);
2455 adev
->gfx
.me_fw_version
= le32_to_cpu(me_hdr
->header
.ucode_version
);
2456 adev
->gfx
.me_feature_version
= le32_to_cpu(me_hdr
->ucode_feature_version
);
2457 adev
->gfx
.ce_feature_version
= le32_to_cpu(ce_hdr
->ucode_feature_version
);
2458 adev
->gfx
.pfp_feature_version
= le32_to_cpu(pfp_hdr
->ucode_feature_version
);
2460 gfx_v7_0_cp_gfx_enable(adev
, false);
2463 fw_data
= (const __le32
*)
2464 (adev
->gfx
.pfp_fw
->data
+
2465 le32_to_cpu(pfp_hdr
->header
.ucode_array_offset_bytes
));
2466 fw_size
= le32_to_cpu(pfp_hdr
->header
.ucode_size_bytes
) / 4;
2467 WREG32(mmCP_PFP_UCODE_ADDR
, 0);
2468 for (i
= 0; i
< fw_size
; i
++)
2469 WREG32(mmCP_PFP_UCODE_DATA
, le32_to_cpup(fw_data
++));
2470 WREG32(mmCP_PFP_UCODE_ADDR
, adev
->gfx
.pfp_fw_version
);
2473 fw_data
= (const __le32
*)
2474 (adev
->gfx
.ce_fw
->data
+
2475 le32_to_cpu(ce_hdr
->header
.ucode_array_offset_bytes
));
2476 fw_size
= le32_to_cpu(ce_hdr
->header
.ucode_size_bytes
) / 4;
2477 WREG32(mmCP_CE_UCODE_ADDR
, 0);
2478 for (i
= 0; i
< fw_size
; i
++)
2479 WREG32(mmCP_CE_UCODE_DATA
, le32_to_cpup(fw_data
++));
2480 WREG32(mmCP_CE_UCODE_ADDR
, adev
->gfx
.ce_fw_version
);
2483 fw_data
= (const __le32
*)
2484 (adev
->gfx
.me_fw
->data
+
2485 le32_to_cpu(me_hdr
->header
.ucode_array_offset_bytes
));
2486 fw_size
= le32_to_cpu(me_hdr
->header
.ucode_size_bytes
) / 4;
2487 WREG32(mmCP_ME_RAM_WADDR
, 0);
2488 for (i
= 0; i
< fw_size
; i
++)
2489 WREG32(mmCP_ME_RAM_DATA
, le32_to_cpup(fw_data
++));
2490 WREG32(mmCP_ME_RAM_WADDR
, adev
->gfx
.me_fw_version
);
2496 * gfx_v7_0_cp_gfx_start - start the gfx ring
2498 * @adev: amdgpu_device pointer
2500 * Enables the ring and loads the clear state context and other
2501 * packets required to init the ring.
2502 * Returns 0 for success, error for failure.
2504 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device
*adev
)
2506 struct amdgpu_ring
*ring
= &adev
->gfx
.gfx_ring
[0];
2507 const struct cs_section_def
*sect
= NULL
;
2508 const struct cs_extent_def
*ext
= NULL
;
2512 WREG32(mmCP_MAX_CONTEXT
, adev
->gfx
.config
.max_hw_contexts
- 1);
2513 WREG32(mmCP_ENDIAN_SWAP
, 0);
2514 WREG32(mmCP_DEVICE_ID
, 1);
2516 gfx_v7_0_cp_gfx_enable(adev
, true);
2518 r
= amdgpu_ring_alloc(ring
, gfx_v7_0_get_csb_size(adev
) + 8);
2520 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r
);
2524 /* init the CE partitions. CE only used for gfx on CIK */
2525 amdgpu_ring_write(ring
, PACKET3(PACKET3_SET_BASE
, 2));
2526 amdgpu_ring_write(ring
, PACKET3_BASE_INDEX(CE_PARTITION_BASE
));
2527 amdgpu_ring_write(ring
, 0x8000);
2528 amdgpu_ring_write(ring
, 0x8000);
2530 /* clear state buffer */
2531 amdgpu_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
2532 amdgpu_ring_write(ring
, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
);
2534 amdgpu_ring_write(ring
, PACKET3(PACKET3_CONTEXT_CONTROL
, 1));
2535 amdgpu_ring_write(ring
, 0x80000000);
2536 amdgpu_ring_write(ring
, 0x80000000);
2538 for (sect
= adev
->gfx
.rlc
.cs_data
; sect
->section
!= NULL
; ++sect
) {
2539 for (ext
= sect
->section
; ext
->extent
!= NULL
; ++ext
) {
2540 if (sect
->id
== SECT_CONTEXT
) {
2541 amdgpu_ring_write(ring
,
2542 PACKET3(PACKET3_SET_CONTEXT_REG
, ext
->reg_count
));
2543 amdgpu_ring_write(ring
, ext
->reg_index
- PACKET3_SET_CONTEXT_REG_START
);
2544 for (i
= 0; i
< ext
->reg_count
; i
++)
2545 amdgpu_ring_write(ring
, ext
->extent
[i
]);
2550 amdgpu_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 2));
2551 amdgpu_ring_write(ring
, mmPA_SC_RASTER_CONFIG
- PACKET3_SET_CONTEXT_REG_START
);
2552 switch (adev
->asic_type
) {
2554 amdgpu_ring_write(ring
, 0x16000012);
2555 amdgpu_ring_write(ring
, 0x00000000);
2558 amdgpu_ring_write(ring
, 0x00000000); /* XXX */
2559 amdgpu_ring_write(ring
, 0x00000000);
2563 amdgpu_ring_write(ring
, 0x00000000); /* XXX */
2564 amdgpu_ring_write(ring
, 0x00000000);
2567 amdgpu_ring_write(ring
, 0x3a00161a);
2568 amdgpu_ring_write(ring
, 0x0000002e);
2571 amdgpu_ring_write(ring
, 0x00000000);
2572 amdgpu_ring_write(ring
, 0x00000000);
2576 amdgpu_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
2577 amdgpu_ring_write(ring
, PACKET3_PREAMBLE_END_CLEAR_STATE
);
2579 amdgpu_ring_write(ring
, PACKET3(PACKET3_CLEAR_STATE
, 0));
2580 amdgpu_ring_write(ring
, 0);
2582 amdgpu_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 2));
2583 amdgpu_ring_write(ring
, 0x00000316);
2584 amdgpu_ring_write(ring
, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2585 amdgpu_ring_write(ring
, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2587 amdgpu_ring_commit(ring
);
2593 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2595 * @adev: amdgpu_device pointer
2597 * Program the location and size of the gfx ring buffer
2598 * and test it to make sure it's working.
2599 * Returns 0 for success, error for failure.
2601 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device
*adev
)
2603 struct amdgpu_ring
*ring
;
2606 u64 rb_addr
, rptr_addr
;
2609 WREG32(mmCP_SEM_WAIT_TIMER
, 0x0);
2610 if (adev
->asic_type
!= CHIP_HAWAII
)
2611 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL
, 0x0);
2613 /* Set the write pointer delay */
2614 WREG32(mmCP_RB_WPTR_DELAY
, 0);
2616 /* set the RB to use vmid 0 */
2617 WREG32(mmCP_RB_VMID
, 0);
2619 WREG32(mmSCRATCH_ADDR
, 0);
2621 /* ring 0 - compute and gfx */
2622 /* Set ring buffer size */
2623 ring
= &adev
->gfx
.gfx_ring
[0];
2624 rb_bufsz
= order_base_2(ring
->ring_size
/ 8);
2625 tmp
= (order_base_2(AMDGPU_GPU_PAGE_SIZE
/8) << 8) | rb_bufsz
;
2627 tmp
|= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT
;
2629 WREG32(mmCP_RB0_CNTL
, tmp
);
2631 /* Initialize the ring buffer's read and write pointers */
2632 WREG32(mmCP_RB0_CNTL
, tmp
| CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK
);
2634 WREG32(mmCP_RB0_WPTR
, lower_32_bits(ring
->wptr
));
2636 /* set the wb address wether it's enabled or not */
2637 rptr_addr
= adev
->wb
.gpu_addr
+ (ring
->rptr_offs
* 4);
2638 WREG32(mmCP_RB0_RPTR_ADDR
, lower_32_bits(rptr_addr
));
2639 WREG32(mmCP_RB0_RPTR_ADDR_HI
, upper_32_bits(rptr_addr
) & 0xFF);
2641 /* scratch register shadowing is no longer supported */
2642 WREG32(mmSCRATCH_UMSK
, 0);
2645 WREG32(mmCP_RB0_CNTL
, tmp
);
2647 rb_addr
= ring
->gpu_addr
>> 8;
2648 WREG32(mmCP_RB0_BASE
, rb_addr
);
2649 WREG32(mmCP_RB0_BASE_HI
, upper_32_bits(rb_addr
));
2651 /* start the ring */
2652 gfx_v7_0_cp_gfx_start(adev
);
2654 r
= amdgpu_ring_test_ring(ring
);
2656 ring
->ready
= false;
2663 static u64
gfx_v7_0_ring_get_rptr(struct amdgpu_ring
*ring
)
2665 return ring
->adev
->wb
.wb
[ring
->rptr_offs
];
2668 static u64
gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring
*ring
)
2670 struct amdgpu_device
*adev
= ring
->adev
;
2672 return RREG32(mmCP_RB0_WPTR
);
2675 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring
*ring
)
2677 struct amdgpu_device
*adev
= ring
->adev
;
2679 WREG32(mmCP_RB0_WPTR
, lower_32_bits(ring
->wptr
));
2680 (void)RREG32(mmCP_RB0_WPTR
);
2683 static u64
gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring
*ring
)
2685 /* XXX check if swapping is necessary on BE */
2686 return ring
->adev
->wb
.wb
[ring
->wptr_offs
];
2689 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring
*ring
)
2691 struct amdgpu_device
*adev
= ring
->adev
;
2693 /* XXX check if swapping is necessary on BE */
2694 adev
->wb
.wb
[ring
->wptr_offs
] = lower_32_bits(ring
->wptr
);
2695 WDOORBELL32(ring
->doorbell_index
, lower_32_bits(ring
->wptr
));
2699 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2701 * @adev: amdgpu_device pointer
2702 * @enable: enable or disable the MEs
2704 * Halts or unhalts the compute MEs.
2706 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device
*adev
, bool enable
)
2711 WREG32(mmCP_MEC_CNTL
, 0);
2713 WREG32(mmCP_MEC_CNTL
, (CP_MEC_CNTL__MEC_ME1_HALT_MASK
| CP_MEC_CNTL__MEC_ME2_HALT_MASK
));
2714 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++)
2715 adev
->gfx
.compute_ring
[i
].ready
= false;
2721 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2723 * @adev: amdgpu_device pointer
2725 * Loads the compute MEC1&2 ucode.
2726 * Returns 0 for success, -EINVAL if the ucode is not available.
2728 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device
*adev
)
2730 const struct gfx_firmware_header_v1_0
*mec_hdr
;
2731 const __le32
*fw_data
;
2732 unsigned i
, fw_size
;
2734 if (!adev
->gfx
.mec_fw
)
2737 mec_hdr
= (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.mec_fw
->data
;
2738 amdgpu_ucode_print_gfx_hdr(&mec_hdr
->header
);
2739 adev
->gfx
.mec_fw_version
= le32_to_cpu(mec_hdr
->header
.ucode_version
);
2740 adev
->gfx
.mec_feature_version
= le32_to_cpu(
2741 mec_hdr
->ucode_feature_version
);
2743 gfx_v7_0_cp_compute_enable(adev
, false);
2746 fw_data
= (const __le32
*)
2747 (adev
->gfx
.mec_fw
->data
+
2748 le32_to_cpu(mec_hdr
->header
.ucode_array_offset_bytes
));
2749 fw_size
= le32_to_cpu(mec_hdr
->header
.ucode_size_bytes
) / 4;
2750 WREG32(mmCP_MEC_ME1_UCODE_ADDR
, 0);
2751 for (i
= 0; i
< fw_size
; i
++)
2752 WREG32(mmCP_MEC_ME1_UCODE_DATA
, le32_to_cpup(fw_data
++));
2753 WREG32(mmCP_MEC_ME1_UCODE_ADDR
, 0);
2755 if (adev
->asic_type
== CHIP_KAVERI
) {
2756 const struct gfx_firmware_header_v1_0
*mec2_hdr
;
2758 if (!adev
->gfx
.mec2_fw
)
2761 mec2_hdr
= (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.mec2_fw
->data
;
2762 amdgpu_ucode_print_gfx_hdr(&mec2_hdr
->header
);
2763 adev
->gfx
.mec2_fw_version
= le32_to_cpu(mec2_hdr
->header
.ucode_version
);
2764 adev
->gfx
.mec2_feature_version
= le32_to_cpu(
2765 mec2_hdr
->ucode_feature_version
);
2768 fw_data
= (const __le32
*)
2769 (adev
->gfx
.mec2_fw
->data
+
2770 le32_to_cpu(mec2_hdr
->header
.ucode_array_offset_bytes
));
2771 fw_size
= le32_to_cpu(mec2_hdr
->header
.ucode_size_bytes
) / 4;
2772 WREG32(mmCP_MEC_ME2_UCODE_ADDR
, 0);
2773 for (i
= 0; i
< fw_size
; i
++)
2774 WREG32(mmCP_MEC_ME2_UCODE_DATA
, le32_to_cpup(fw_data
++));
2775 WREG32(mmCP_MEC_ME2_UCODE_ADDR
, 0);
2782 * gfx_v7_0_cp_compute_fini - stop the compute queues
2784 * @adev: amdgpu_device pointer
2786 * Stop the compute queues and tear down the driver queue
2789 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device
*adev
)
2793 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++) {
2794 struct amdgpu_ring
*ring
= &adev
->gfx
.compute_ring
[i
];
2796 if (ring
->mqd_obj
) {
2797 r
= amdgpu_bo_reserve(ring
->mqd_obj
, true);
2798 if (unlikely(r
!= 0))
2799 dev_warn(adev
->dev
, "(%d) reserve MQD bo failed\n", r
);
2801 amdgpu_bo_unpin(ring
->mqd_obj
);
2802 amdgpu_bo_unreserve(ring
->mqd_obj
);
2804 amdgpu_bo_unref(&ring
->mqd_obj
);
2805 ring
->mqd_obj
= NULL
;
2810 static void gfx_v7_0_mec_fini(struct amdgpu_device
*adev
)
2814 if (adev
->gfx
.mec
.hpd_eop_obj
) {
2815 r
= amdgpu_bo_reserve(adev
->gfx
.mec
.hpd_eop_obj
, true);
2816 if (unlikely(r
!= 0))
2817 dev_warn(adev
->dev
, "(%d) reserve HPD EOP bo failed\n", r
);
2818 amdgpu_bo_unpin(adev
->gfx
.mec
.hpd_eop_obj
);
2819 amdgpu_bo_unreserve(adev
->gfx
.mec
.hpd_eop_obj
);
2821 amdgpu_bo_unref(&adev
->gfx
.mec
.hpd_eop_obj
);
2822 adev
->gfx
.mec
.hpd_eop_obj
= NULL
;
2826 static int gfx_v7_0_mec_init(struct amdgpu_device
*adev
)
2832 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
2833 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
2834 * Nonetheless, we assign only 1 pipe because all other pipes will
2837 adev
->gfx
.mec
.num_mec
= 1;
2838 adev
->gfx
.mec
.num_pipe
= 1;
2839 adev
->gfx
.mec
.num_queue
= adev
->gfx
.mec
.num_mec
* adev
->gfx
.mec
.num_pipe
* 8;
2841 if (adev
->gfx
.mec
.hpd_eop_obj
== NULL
) {
2842 r
= amdgpu_bo_create(adev
,
2843 adev
->gfx
.mec
.num_mec
* adev
->gfx
.mec
.num_pipe
* GFX7_MEC_HPD_SIZE
* 2,
2845 AMDGPU_GEM_DOMAIN_GTT
, 0, NULL
, NULL
,
2846 &adev
->gfx
.mec
.hpd_eop_obj
);
2848 dev_warn(adev
->dev
, "(%d) create HDP EOP bo failed\n", r
);
2853 r
= amdgpu_bo_reserve(adev
->gfx
.mec
.hpd_eop_obj
, false);
2854 if (unlikely(r
!= 0)) {
2855 gfx_v7_0_mec_fini(adev
);
2858 r
= amdgpu_bo_pin(adev
->gfx
.mec
.hpd_eop_obj
, AMDGPU_GEM_DOMAIN_GTT
,
2859 &adev
->gfx
.mec
.hpd_eop_gpu_addr
);
2861 dev_warn(adev
->dev
, "(%d) pin HDP EOP bo failed\n", r
);
2862 gfx_v7_0_mec_fini(adev
);
2865 r
= amdgpu_bo_kmap(adev
->gfx
.mec
.hpd_eop_obj
, (void **)&hpd
);
2867 dev_warn(adev
->dev
, "(%d) map HDP EOP bo failed\n", r
);
2868 gfx_v7_0_mec_fini(adev
);
2872 /* clear memory. Not sure if this is required or not */
2873 memset(hpd
, 0, adev
->gfx
.mec
.num_mec
* adev
->gfx
.mec
.num_pipe
* GFX7_MEC_HPD_SIZE
* 2);
2875 amdgpu_bo_kunmap(adev
->gfx
.mec
.hpd_eop_obj
);
2876 amdgpu_bo_unreserve(adev
->gfx
.mec
.hpd_eop_obj
);
2881 struct hqd_registers
2883 u32 cp_mqd_base_addr
;
2884 u32 cp_mqd_base_addr_hi
;
2887 u32 cp_hqd_persistent_state
;
2888 u32 cp_hqd_pipe_priority
;
2889 u32 cp_hqd_queue_priority
;
2892 u32 cp_hqd_pq_base_hi
;
2894 u32 cp_hqd_pq_rptr_report_addr
;
2895 u32 cp_hqd_pq_rptr_report_addr_hi
;
2896 u32 cp_hqd_pq_wptr_poll_addr
;
2897 u32 cp_hqd_pq_wptr_poll_addr_hi
;
2898 u32 cp_hqd_pq_doorbell_control
;
2900 u32 cp_hqd_pq_control
;
2901 u32 cp_hqd_ib_base_addr
;
2902 u32 cp_hqd_ib_base_addr_hi
;
2904 u32 cp_hqd_ib_control
;
2905 u32 cp_hqd_iq_timer
;
2907 u32 cp_hqd_dequeue_request
;
2908 u32 cp_hqd_dma_offload
;
2909 u32 cp_hqd_sema_cmd
;
2910 u32 cp_hqd_msg_type
;
2911 u32 cp_hqd_atomic0_preop_lo
;
2912 u32 cp_hqd_atomic0_preop_hi
;
2913 u32 cp_hqd_atomic1_preop_lo
;
2914 u32 cp_hqd_atomic1_preop_hi
;
2915 u32 cp_hqd_hq_scheduler0
;
2916 u32 cp_hqd_hq_scheduler1
;
2920 static void gfx_v7_0_compute_pipe_init(struct amdgpu_device
*adev
, int me
, int pipe
)
2924 size_t eop_offset
= me
* pipe
* GFX7_MEC_HPD_SIZE
* 2;
2926 mutex_lock(&adev
->srbm_mutex
);
2927 eop_gpu_addr
= adev
->gfx
.mec
.hpd_eop_gpu_addr
+ eop_offset
;
2929 cik_srbm_select(adev
, me
, pipe
, 0, 0);
2931 /* write the EOP addr */
2932 WREG32(mmCP_HPD_EOP_BASE_ADDR
, eop_gpu_addr
>> 8);
2933 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI
, upper_32_bits(eop_gpu_addr
) >> 8);
2935 /* set the VMID assigned */
2936 WREG32(mmCP_HPD_EOP_VMID
, 0);
2938 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2939 tmp
= RREG32(mmCP_HPD_EOP_CONTROL
);
2940 tmp
&= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK
;
2941 tmp
|= order_base_2(GFX7_MEC_HPD_SIZE
/ 8);
2942 WREG32(mmCP_HPD_EOP_CONTROL
, tmp
);
2944 cik_srbm_select(adev
, 0, 0, 0, 0);
2945 mutex_unlock(&adev
->srbm_mutex
);
2948 static int gfx_v7_0_mqd_deactivate(struct amdgpu_device
*adev
)
2952 /* disable the queue if it's active */
2953 if (RREG32(mmCP_HQD_ACTIVE
) & 1) {
2954 WREG32(mmCP_HQD_DEQUEUE_REQUEST
, 1);
2955 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
2956 if (!(RREG32(mmCP_HQD_ACTIVE
) & 1))
2961 if (i
== adev
->usec_timeout
)
2964 WREG32(mmCP_HQD_DEQUEUE_REQUEST
, 0);
2965 WREG32(mmCP_HQD_PQ_RPTR
, 0);
2966 WREG32(mmCP_HQD_PQ_WPTR
, 0);
2972 static void gfx_v7_0_mqd_init(struct amdgpu_device
*adev
,
2973 struct cik_mqd
*mqd
,
2974 uint64_t mqd_gpu_addr
,
2975 struct amdgpu_ring
*ring
)
2980 /* init the mqd struct */
2981 memset(mqd
, 0, sizeof(struct cik_mqd
));
2983 mqd
->header
= 0xC0310800;
2984 mqd
->compute_static_thread_mgmt_se0
= 0xffffffff;
2985 mqd
->compute_static_thread_mgmt_se1
= 0xffffffff;
2986 mqd
->compute_static_thread_mgmt_se2
= 0xffffffff;
2987 mqd
->compute_static_thread_mgmt_se3
= 0xffffffff;
2989 /* enable doorbell? */
2990 mqd
->cp_hqd_pq_doorbell_control
=
2991 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL
);
2992 if (ring
->use_doorbell
)
2993 mqd
->cp_hqd_pq_doorbell_control
|= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK
;
2995 mqd
->cp_hqd_pq_doorbell_control
&= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK
;
2997 /* set the pointer to the MQD */
2998 mqd
->cp_mqd_base_addr_lo
= mqd_gpu_addr
& 0xfffffffc;
2999 mqd
->cp_mqd_base_addr_hi
= upper_32_bits(mqd_gpu_addr
);
3001 /* set MQD vmid to 0 */
3002 mqd
->cp_mqd_control
= RREG32(mmCP_MQD_CONTROL
);
3003 mqd
->cp_mqd_control
&= ~CP_MQD_CONTROL__VMID_MASK
;
3005 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3006 hqd_gpu_addr
= ring
->gpu_addr
>> 8;
3007 mqd
->cp_hqd_pq_base_lo
= hqd_gpu_addr
;
3008 mqd
->cp_hqd_pq_base_hi
= upper_32_bits(hqd_gpu_addr
);
3010 /* set up the HQD, this is similar to CP_RB0_CNTL */
3011 mqd
->cp_hqd_pq_control
= RREG32(mmCP_HQD_PQ_CONTROL
);
3012 mqd
->cp_hqd_pq_control
&=
3013 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK
|
3014 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK
);
3016 mqd
->cp_hqd_pq_control
|=
3017 order_base_2(ring
->ring_size
/ 8);
3018 mqd
->cp_hqd_pq_control
|=
3019 (order_base_2(AMDGPU_GPU_PAGE_SIZE
/8) << 8);
3021 mqd
->cp_hqd_pq_control
|=
3022 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT
;
3024 mqd
->cp_hqd_pq_control
&=
3025 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK
|
3026 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK
|
3027 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK
);
3028 mqd
->cp_hqd_pq_control
|=
3029 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK
|
3030 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK
; /* assuming kernel queue control */
3032 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3033 wb_gpu_addr
= adev
->wb
.gpu_addr
+ (ring
->wptr_offs
* 4);
3034 mqd
->cp_hqd_pq_wptr_poll_addr_lo
= wb_gpu_addr
& 0xfffffffc;
3035 mqd
->cp_hqd_pq_wptr_poll_addr_hi
= upper_32_bits(wb_gpu_addr
) & 0xffff;
3037 /* set the wb address wether it's enabled or not */
3038 wb_gpu_addr
= adev
->wb
.gpu_addr
+ (ring
->rptr_offs
* 4);
3039 mqd
->cp_hqd_pq_rptr_report_addr_lo
= wb_gpu_addr
& 0xfffffffc;
3040 mqd
->cp_hqd_pq_rptr_report_addr_hi
=
3041 upper_32_bits(wb_gpu_addr
) & 0xffff;
3043 /* enable the doorbell if requested */
3044 if (ring
->use_doorbell
) {
3045 mqd
->cp_hqd_pq_doorbell_control
=
3046 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL
);
3047 mqd
->cp_hqd_pq_doorbell_control
&=
3048 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK
;
3049 mqd
->cp_hqd_pq_doorbell_control
|=
3050 (ring
->doorbell_index
<<
3051 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT
);
3052 mqd
->cp_hqd_pq_doorbell_control
|=
3053 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK
;
3054 mqd
->cp_hqd_pq_doorbell_control
&=
3055 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK
|
3056 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK
);
3059 mqd
->cp_hqd_pq_doorbell_control
= 0;
3062 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3064 mqd
->cp_hqd_pq_wptr
= lower_32_bits(ring
->wptr
);
3065 mqd
->cp_hqd_pq_rptr
= RREG32(mmCP_HQD_PQ_RPTR
);
3067 /* set the vmid for the queue */
3068 mqd
->cp_hqd_vmid
= 0;
3071 mqd
->cp_hqd_ib_control
= RREG32(mmCP_HQD_IB_CONTROL
);
3072 mqd
->cp_hqd_ib_base_addr_lo
= RREG32(mmCP_HQD_IB_BASE_ADDR
);
3073 mqd
->cp_hqd_ib_base_addr_hi
= RREG32(mmCP_HQD_IB_BASE_ADDR_HI
);
3074 mqd
->cp_hqd_ib_rptr
= RREG32(mmCP_HQD_IB_RPTR
);
3075 mqd
->cp_hqd_persistent_state
= RREG32(mmCP_HQD_PERSISTENT_STATE
);
3076 mqd
->cp_hqd_sema_cmd
= RREG32(mmCP_HQD_SEMA_CMD
);
3077 mqd
->cp_hqd_msg_type
= RREG32(mmCP_HQD_MSG_TYPE
);
3078 mqd
->cp_hqd_atomic0_preop_lo
= RREG32(mmCP_HQD_ATOMIC0_PREOP_LO
);
3079 mqd
->cp_hqd_atomic0_preop_hi
= RREG32(mmCP_HQD_ATOMIC0_PREOP_HI
);
3080 mqd
->cp_hqd_atomic1_preop_lo
= RREG32(mmCP_HQD_ATOMIC1_PREOP_LO
);
3081 mqd
->cp_hqd_atomic1_preop_hi
= RREG32(mmCP_HQD_ATOMIC1_PREOP_HI
);
3082 mqd
->cp_hqd_pq_rptr
= RREG32(mmCP_HQD_PQ_RPTR
);
3083 mqd
->cp_hqd_quantum
= RREG32(mmCP_HQD_QUANTUM
);
3084 mqd
->cp_hqd_pipe_priority
= RREG32(mmCP_HQD_PIPE_PRIORITY
);
3085 mqd
->cp_hqd_queue_priority
= RREG32(mmCP_HQD_QUEUE_PRIORITY
);
3086 mqd
->cp_hqd_iq_rptr
= RREG32(mmCP_HQD_IQ_RPTR
);
3088 /* activate the queue */
3089 mqd
->cp_hqd_active
= 1;
3092 int gfx_v7_0_mqd_commit(struct amdgpu_device
*adev
, struct cik_mqd
*mqd
)
3096 /* disable wptr polling */
3097 tmp
= RREG32(mmCP_PQ_WPTR_POLL_CNTL
);
3098 tmp
= REG_SET_FIELD(tmp
, CP_PQ_WPTR_POLL_CNTL
, EN
, 0);
3099 WREG32(mmCP_PQ_WPTR_POLL_CNTL
, tmp
);
3101 /* program MQD field to HW */
3102 WREG32(mmCP_MQD_BASE_ADDR
, mqd
->cp_mqd_base_addr_lo
);
3103 WREG32(mmCP_MQD_BASE_ADDR_HI
, mqd
->cp_mqd_base_addr_hi
);
3104 WREG32(mmCP_MQD_CONTROL
, mqd
->cp_mqd_control
);
3105 WREG32(mmCP_HQD_PQ_BASE
, mqd
->cp_hqd_pq_base_lo
);
3106 WREG32(mmCP_HQD_PQ_BASE_HI
, mqd
->cp_hqd_pq_base_hi
);
3107 WREG32(mmCP_HQD_PQ_CONTROL
, mqd
->cp_hqd_pq_control
);
3108 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR
, mqd
->cp_hqd_pq_wptr_poll_addr_lo
);
3109 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI
, mqd
->cp_hqd_pq_wptr_poll_addr_hi
);
3110 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR
, mqd
->cp_hqd_pq_rptr_report_addr_lo
);
3111 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI
, mqd
->cp_hqd_pq_rptr_report_addr_hi
);
3112 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL
, mqd
->cp_hqd_pq_doorbell_control
);
3113 WREG32(mmCP_HQD_PQ_WPTR
, mqd
->cp_hqd_pq_wptr
);
3114 WREG32(mmCP_HQD_VMID
, mqd
->cp_hqd_vmid
);
3116 WREG32(mmCP_HQD_IB_CONTROL
, mqd
->cp_hqd_ib_control
);
3117 WREG32(mmCP_HQD_IB_BASE_ADDR
, mqd
->cp_hqd_ib_base_addr_lo
);
3118 WREG32(mmCP_HQD_IB_BASE_ADDR_HI
, mqd
->cp_hqd_ib_base_addr_hi
);
3119 WREG32(mmCP_HQD_IB_RPTR
, mqd
->cp_hqd_ib_rptr
);
3120 WREG32(mmCP_HQD_PERSISTENT_STATE
, mqd
->cp_hqd_persistent_state
);
3121 WREG32(mmCP_HQD_SEMA_CMD
, mqd
->cp_hqd_sema_cmd
);
3122 WREG32(mmCP_HQD_MSG_TYPE
, mqd
->cp_hqd_msg_type
);
3123 WREG32(mmCP_HQD_ATOMIC0_PREOP_LO
, mqd
->cp_hqd_atomic0_preop_lo
);
3124 WREG32(mmCP_HQD_ATOMIC0_PREOP_HI
, mqd
->cp_hqd_atomic0_preop_hi
);
3125 WREG32(mmCP_HQD_ATOMIC1_PREOP_LO
, mqd
->cp_hqd_atomic1_preop_lo
);
3126 WREG32(mmCP_HQD_ATOMIC1_PREOP_HI
, mqd
->cp_hqd_atomic1_preop_hi
);
3127 WREG32(mmCP_HQD_PQ_RPTR
, mqd
->cp_hqd_pq_rptr
);
3128 WREG32(mmCP_HQD_QUANTUM
, mqd
->cp_hqd_quantum
);
3129 WREG32(mmCP_HQD_PIPE_PRIORITY
, mqd
->cp_hqd_pipe_priority
);
3130 WREG32(mmCP_HQD_QUEUE_PRIORITY
, mqd
->cp_hqd_queue_priority
);
3131 WREG32(mmCP_HQD_IQ_RPTR
, mqd
->cp_hqd_iq_rptr
);
3133 /* activate the HQD */
3134 WREG32(mmCP_HQD_ACTIVE
, mqd
->cp_hqd_active
);
3139 static int gfx_v7_0_compute_queue_init(struct amdgpu_device
*adev
, int ring_id
)
3143 struct cik_mqd
*mqd
;
3144 struct amdgpu_ring
*ring
= &adev
->gfx
.compute_ring
[ring_id
];
3146 if (ring
->mqd_obj
== NULL
) {
3147 r
= amdgpu_bo_create(adev
,
3148 sizeof(struct cik_mqd
),
3150 AMDGPU_GEM_DOMAIN_GTT
, 0, NULL
, NULL
,
3153 dev_warn(adev
->dev
, "(%d) create MQD bo failed\n", r
);
3158 r
= amdgpu_bo_reserve(ring
->mqd_obj
, false);
3159 if (unlikely(r
!= 0))
3162 r
= amdgpu_bo_pin(ring
->mqd_obj
, AMDGPU_GEM_DOMAIN_GTT
,
3165 dev_warn(adev
->dev
, "(%d) pin MQD bo failed\n", r
);
3168 r
= amdgpu_bo_kmap(ring
->mqd_obj
, (void **)&mqd
);
3170 dev_warn(adev
->dev
, "(%d) map MQD bo failed\n", r
);
3174 mutex_lock(&adev
->srbm_mutex
);
3175 cik_srbm_select(adev
, ring
->me
, ring
->pipe
, ring
->queue
, 0);
3177 gfx_v7_0_mqd_init(adev
, mqd
, mqd_gpu_addr
, ring
);
3178 gfx_v7_0_mqd_deactivate(adev
);
3179 gfx_v7_0_mqd_commit(adev
, mqd
);
3181 cik_srbm_select(adev
, 0, 0, 0, 0);
3182 mutex_unlock(&adev
->srbm_mutex
);
3184 amdgpu_bo_kunmap(ring
->mqd_obj
);
3186 amdgpu_bo_unreserve(ring
->mqd_obj
);
3192 * gfx_v7_0_cp_compute_resume - setup the compute queue registers
3194 * @adev: amdgpu_device pointer
3196 * Program the compute queues and test them to make sure they
3198 * Returns 0 for success, error for failure.
3200 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device
*adev
)
3204 struct amdgpu_ring
*ring
;
3206 /* fix up chicken bits */
3207 tmp
= RREG32(mmCP_CPF_DEBUG
);
3209 WREG32(mmCP_CPF_DEBUG
, tmp
);
3211 /* init the pipes */
3212 for (i
= 0; i
< adev
->gfx
.mec
.num_mec
; i
++)
3213 for (j
= 0; j
< adev
->gfx
.mec
.num_pipe
; j
++)
3214 gfx_v7_0_compute_pipe_init(adev
, i
, j
);
3216 /* init the queues */
3217 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++) {
3218 r
= gfx_v7_0_compute_queue_init(adev
, i
);
3220 gfx_v7_0_cp_compute_fini(adev
);
3225 gfx_v7_0_cp_compute_enable(adev
, true);
3227 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++) {
3228 ring
= &adev
->gfx
.compute_ring
[i
];
3230 r
= amdgpu_ring_test_ring(ring
);
3232 ring
->ready
= false;
3238 static void gfx_v7_0_cp_enable(struct amdgpu_device
*adev
, bool enable
)
3240 gfx_v7_0_cp_gfx_enable(adev
, enable
);
3241 gfx_v7_0_cp_compute_enable(adev
, enable
);
3244 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device
*adev
)
3248 r
= gfx_v7_0_cp_gfx_load_microcode(adev
);
3251 r
= gfx_v7_0_cp_compute_load_microcode(adev
);
3258 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device
*adev
,
3261 u32 tmp
= RREG32(mmCP_INT_CNTL_RING0
);
3264 tmp
|= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK
|
3265 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK
);
3267 tmp
&= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK
|
3268 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK
);
3269 WREG32(mmCP_INT_CNTL_RING0
, tmp
);
3272 static int gfx_v7_0_cp_resume(struct amdgpu_device
*adev
)
3276 gfx_v7_0_enable_gui_idle_interrupt(adev
, false);
3278 r
= gfx_v7_0_cp_load_microcode(adev
);
3282 r
= gfx_v7_0_cp_gfx_resume(adev
);
3285 r
= gfx_v7_0_cp_compute_resume(adev
);
3289 gfx_v7_0_enable_gui_idle_interrupt(adev
, true);
3295 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3297 * @ring: the ring to emmit the commands to
3299 * Sync the command pipeline with the PFP. E.g. wait for everything
3302 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring
*ring
)
3304 int usepfp
= (ring
->funcs
->type
== AMDGPU_RING_TYPE_GFX
);
3305 uint32_t seq
= ring
->fence_drv
.sync_seq
;
3306 uint64_t addr
= ring
->fence_drv
.gpu_addr
;
3308 amdgpu_ring_write(ring
, PACKET3(PACKET3_WAIT_REG_MEM
, 5));
3309 amdgpu_ring_write(ring
, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3310 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3311 WAIT_REG_MEM_ENGINE(usepfp
))); /* pfp or me */
3312 amdgpu_ring_write(ring
, addr
& 0xfffffffc);
3313 amdgpu_ring_write(ring
, upper_32_bits(addr
) & 0xffffffff);
3314 amdgpu_ring_write(ring
, seq
);
3315 amdgpu_ring_write(ring
, 0xffffffff);
3316 amdgpu_ring_write(ring
, 4); /* poll interval */
3319 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3320 amdgpu_ring_write(ring
, PACKET3(PACKET3_SWITCH_BUFFER
, 0));
3321 amdgpu_ring_write(ring
, 0);
3322 amdgpu_ring_write(ring
, PACKET3(PACKET3_SWITCH_BUFFER
, 0));
3323 amdgpu_ring_write(ring
, 0);
3329 * VMID 0 is the physical GPU addresses as used by the kernel.
3330 * VMIDs 1-15 are used for userspace clients and are handled
3331 * by the amdgpu vm/hsa code.
3334 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3336 * @adev: amdgpu_device pointer
3338 * Update the page table base and flush the VM TLB
3339 * using the CP (CIK).
3341 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring
*ring
,
3342 unsigned vm_id
, uint64_t pd_addr
)
3344 int usepfp
= (ring
->funcs
->type
== AMDGPU_RING_TYPE_GFX
);
3346 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
3347 amdgpu_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(usepfp
) |
3348 WRITE_DATA_DST_SEL(0)));
3350 amdgpu_ring_write(ring
,
3351 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ vm_id
));
3353 amdgpu_ring_write(ring
,
3354 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ vm_id
- 8));
3356 amdgpu_ring_write(ring
, 0);
3357 amdgpu_ring_write(ring
, pd_addr
>> 12);
3359 /* bits 0-15 are the VM contexts0-15 */
3360 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
3361 amdgpu_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(0) |
3362 WRITE_DATA_DST_SEL(0)));
3363 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
);
3364 amdgpu_ring_write(ring
, 0);
3365 amdgpu_ring_write(ring
, 1 << vm_id
);
3367 /* wait for the invalidate to complete */
3368 amdgpu_ring_write(ring
, PACKET3(PACKET3_WAIT_REG_MEM
, 5));
3369 amdgpu_ring_write(ring
, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3370 WAIT_REG_MEM_FUNCTION(0) | /* always */
3371 WAIT_REG_MEM_ENGINE(0))); /* me */
3372 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
);
3373 amdgpu_ring_write(ring
, 0);
3374 amdgpu_ring_write(ring
, 0); /* ref */
3375 amdgpu_ring_write(ring
, 0); /* mask */
3376 amdgpu_ring_write(ring
, 0x20); /* poll interval */
3378 /* compute doesn't have PFP */
3380 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3381 amdgpu_ring_write(ring
, PACKET3(PACKET3_PFP_SYNC_ME
, 0));
3382 amdgpu_ring_write(ring
, 0x0);
3384 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3385 amdgpu_ring_write(ring
, PACKET3(PACKET3_SWITCH_BUFFER
, 0));
3386 amdgpu_ring_write(ring
, 0);
3387 amdgpu_ring_write(ring
, PACKET3(PACKET3_SWITCH_BUFFER
, 0));
3388 amdgpu_ring_write(ring
, 0);
3394 * The RLC is a multi-purpose microengine that handles a
3395 * variety of functions.
3397 static void gfx_v7_0_rlc_fini(struct amdgpu_device
*adev
)
3401 /* save restore block */
3402 if (adev
->gfx
.rlc
.save_restore_obj
) {
3403 r
= amdgpu_bo_reserve(adev
->gfx
.rlc
.save_restore_obj
, true);
3404 if (unlikely(r
!= 0))
3405 dev_warn(adev
->dev
, "(%d) reserve RLC sr bo failed\n", r
);
3406 amdgpu_bo_unpin(adev
->gfx
.rlc
.save_restore_obj
);
3407 amdgpu_bo_unreserve(adev
->gfx
.rlc
.save_restore_obj
);
3409 amdgpu_bo_unref(&adev
->gfx
.rlc
.save_restore_obj
);
3410 adev
->gfx
.rlc
.save_restore_obj
= NULL
;
3413 /* clear state block */
3414 if (adev
->gfx
.rlc
.clear_state_obj
) {
3415 r
= amdgpu_bo_reserve(adev
->gfx
.rlc
.clear_state_obj
, true);
3416 if (unlikely(r
!= 0))
3417 dev_warn(adev
->dev
, "(%d) reserve RLC c bo failed\n", r
);
3418 amdgpu_bo_unpin(adev
->gfx
.rlc
.clear_state_obj
);
3419 amdgpu_bo_unreserve(adev
->gfx
.rlc
.clear_state_obj
);
3421 amdgpu_bo_unref(&adev
->gfx
.rlc
.clear_state_obj
);
3422 adev
->gfx
.rlc
.clear_state_obj
= NULL
;
3425 /* clear state block */
3426 if (adev
->gfx
.rlc
.cp_table_obj
) {
3427 r
= amdgpu_bo_reserve(adev
->gfx
.rlc
.cp_table_obj
, true);
3428 if (unlikely(r
!= 0))
3429 dev_warn(adev
->dev
, "(%d) reserve RLC cp table bo failed\n", r
);
3430 amdgpu_bo_unpin(adev
->gfx
.rlc
.cp_table_obj
);
3431 amdgpu_bo_unreserve(adev
->gfx
.rlc
.cp_table_obj
);
3433 amdgpu_bo_unref(&adev
->gfx
.rlc
.cp_table_obj
);
3434 adev
->gfx
.rlc
.cp_table_obj
= NULL
;
3438 static int gfx_v7_0_rlc_init(struct amdgpu_device
*adev
)
3441 volatile u32
*dst_ptr
;
3443 const struct cs_section_def
*cs_data
;
3446 /* allocate rlc buffers */
3447 if (adev
->flags
& AMD_IS_APU
) {
3448 if (adev
->asic_type
== CHIP_KAVERI
) {
3449 adev
->gfx
.rlc
.reg_list
= spectre_rlc_save_restore_register_list
;
3450 adev
->gfx
.rlc
.reg_list_size
=
3451 (u32
)ARRAY_SIZE(spectre_rlc_save_restore_register_list
);
3453 adev
->gfx
.rlc
.reg_list
= kalindi_rlc_save_restore_register_list
;
3454 adev
->gfx
.rlc
.reg_list_size
=
3455 (u32
)ARRAY_SIZE(kalindi_rlc_save_restore_register_list
);
3458 adev
->gfx
.rlc
.cs_data
= ci_cs_data
;
3459 adev
->gfx
.rlc
.cp_table_size
= ALIGN(CP_ME_TABLE_SIZE
* 5 * 4, 2048); /* CP JT */
3460 adev
->gfx
.rlc
.cp_table_size
+= 64 * 1024; /* GDS */
3462 src_ptr
= adev
->gfx
.rlc
.reg_list
;
3463 dws
= adev
->gfx
.rlc
.reg_list_size
;
3464 dws
+= (5 * 16) + 48 + 48 + 64;
3466 cs_data
= adev
->gfx
.rlc
.cs_data
;
3469 /* save restore block */
3470 if (adev
->gfx
.rlc
.save_restore_obj
== NULL
) {
3471 r
= amdgpu_bo_create(adev
, dws
* 4, PAGE_SIZE
, true,
3472 AMDGPU_GEM_DOMAIN_VRAM
,
3473 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
|
3474 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
,
3476 &adev
->gfx
.rlc
.save_restore_obj
);
3478 dev_warn(adev
->dev
, "(%d) create RLC sr bo failed\n", r
);
3483 r
= amdgpu_bo_reserve(adev
->gfx
.rlc
.save_restore_obj
, false);
3484 if (unlikely(r
!= 0)) {
3485 gfx_v7_0_rlc_fini(adev
);
3488 r
= amdgpu_bo_pin(adev
->gfx
.rlc
.save_restore_obj
, AMDGPU_GEM_DOMAIN_VRAM
,
3489 &adev
->gfx
.rlc
.save_restore_gpu_addr
);
3491 amdgpu_bo_unreserve(adev
->gfx
.rlc
.save_restore_obj
);
3492 dev_warn(adev
->dev
, "(%d) pin RLC sr bo failed\n", r
);
3493 gfx_v7_0_rlc_fini(adev
);
3497 r
= amdgpu_bo_kmap(adev
->gfx
.rlc
.save_restore_obj
, (void **)&adev
->gfx
.rlc
.sr_ptr
);
3499 dev_warn(adev
->dev
, "(%d) map RLC sr bo failed\n", r
);
3500 gfx_v7_0_rlc_fini(adev
);
3503 /* write the sr buffer */
3504 dst_ptr
= adev
->gfx
.rlc
.sr_ptr
;
3505 for (i
= 0; i
< adev
->gfx
.rlc
.reg_list_size
; i
++)
3506 dst_ptr
[i
] = cpu_to_le32(src_ptr
[i
]);
3507 amdgpu_bo_kunmap(adev
->gfx
.rlc
.save_restore_obj
);
3508 amdgpu_bo_unreserve(adev
->gfx
.rlc
.save_restore_obj
);
3512 /* clear state block */
3513 adev
->gfx
.rlc
.clear_state_size
= dws
= gfx_v7_0_get_csb_size(adev
);
3515 if (adev
->gfx
.rlc
.clear_state_obj
== NULL
) {
3516 r
= amdgpu_bo_create(adev
, dws
* 4, PAGE_SIZE
, true,
3517 AMDGPU_GEM_DOMAIN_VRAM
,
3518 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
|
3519 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
,
3521 &adev
->gfx
.rlc
.clear_state_obj
);
3523 dev_warn(adev
->dev
, "(%d) create RLC c bo failed\n", r
);
3524 gfx_v7_0_rlc_fini(adev
);
3528 r
= amdgpu_bo_reserve(adev
->gfx
.rlc
.clear_state_obj
, false);
3529 if (unlikely(r
!= 0)) {
3530 gfx_v7_0_rlc_fini(adev
);
3533 r
= amdgpu_bo_pin(adev
->gfx
.rlc
.clear_state_obj
, AMDGPU_GEM_DOMAIN_VRAM
,
3534 &adev
->gfx
.rlc
.clear_state_gpu_addr
);
3536 amdgpu_bo_unreserve(adev
->gfx
.rlc
.clear_state_obj
);
3537 dev_warn(adev
->dev
, "(%d) pin RLC c bo failed\n", r
);
3538 gfx_v7_0_rlc_fini(adev
);
3542 r
= amdgpu_bo_kmap(adev
->gfx
.rlc
.clear_state_obj
, (void **)&adev
->gfx
.rlc
.cs_ptr
);
3544 dev_warn(adev
->dev
, "(%d) map RLC c bo failed\n", r
);
3545 gfx_v7_0_rlc_fini(adev
);
3548 /* set up the cs buffer */
3549 dst_ptr
= adev
->gfx
.rlc
.cs_ptr
;
3550 gfx_v7_0_get_csb_buffer(adev
, dst_ptr
);
3551 amdgpu_bo_kunmap(adev
->gfx
.rlc
.clear_state_obj
);
3552 amdgpu_bo_unreserve(adev
->gfx
.rlc
.clear_state_obj
);
3555 if (adev
->gfx
.rlc
.cp_table_size
) {
3556 if (adev
->gfx
.rlc
.cp_table_obj
== NULL
) {
3557 r
= amdgpu_bo_create(adev
, adev
->gfx
.rlc
.cp_table_size
, PAGE_SIZE
, true,
3558 AMDGPU_GEM_DOMAIN_VRAM
,
3559 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
|
3560 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
,
3562 &adev
->gfx
.rlc
.cp_table_obj
);
3564 dev_warn(adev
->dev
, "(%d) create RLC cp table bo failed\n", r
);
3565 gfx_v7_0_rlc_fini(adev
);
3570 r
= amdgpu_bo_reserve(adev
->gfx
.rlc
.cp_table_obj
, false);
3571 if (unlikely(r
!= 0)) {
3572 dev_warn(adev
->dev
, "(%d) reserve RLC cp table bo failed\n", r
);
3573 gfx_v7_0_rlc_fini(adev
);
3576 r
= amdgpu_bo_pin(adev
->gfx
.rlc
.cp_table_obj
, AMDGPU_GEM_DOMAIN_VRAM
,
3577 &adev
->gfx
.rlc
.cp_table_gpu_addr
);
3579 amdgpu_bo_unreserve(adev
->gfx
.rlc
.cp_table_obj
);
3580 dev_warn(adev
->dev
, "(%d) pin RLC cp_table bo failed\n", r
);
3581 gfx_v7_0_rlc_fini(adev
);
3584 r
= amdgpu_bo_kmap(adev
->gfx
.rlc
.cp_table_obj
, (void **)&adev
->gfx
.rlc
.cp_table_ptr
);
3586 dev_warn(adev
->dev
, "(%d) map RLC cp table bo failed\n", r
);
3587 gfx_v7_0_rlc_fini(adev
);
3591 gfx_v7_0_init_cp_pg_table(adev
);
3593 amdgpu_bo_kunmap(adev
->gfx
.rlc
.cp_table_obj
);
3594 amdgpu_bo_unreserve(adev
->gfx
.rlc
.cp_table_obj
);
3601 static void gfx_v7_0_enable_lbpw(struct amdgpu_device
*adev
, bool enable
)
3605 tmp
= RREG32(mmRLC_LB_CNTL
);
3607 tmp
|= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK
;
3609 tmp
&= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK
;
3610 WREG32(mmRLC_LB_CNTL
, tmp
);
3613 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device
*adev
)
3618 mutex_lock(&adev
->grbm_idx_mutex
);
3619 for (i
= 0; i
< adev
->gfx
.config
.max_shader_engines
; i
++) {
3620 for (j
= 0; j
< adev
->gfx
.config
.max_sh_per_se
; j
++) {
3621 gfx_v7_0_select_se_sh(adev
, i
, j
, 0xffffffff);
3622 for (k
= 0; k
< adev
->usec_timeout
; k
++) {
3623 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY
) == 0)
3629 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
3630 mutex_unlock(&adev
->grbm_idx_mutex
);
3632 mask
= RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK
|
3633 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK
|
3634 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK
|
3635 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK
;
3636 for (k
= 0; k
< adev
->usec_timeout
; k
++) {
3637 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY
) & mask
) == 0)
3643 static void gfx_v7_0_update_rlc(struct amdgpu_device
*adev
, u32 rlc
)
3647 tmp
= RREG32(mmRLC_CNTL
);
3649 WREG32(mmRLC_CNTL
, rlc
);
3652 static u32
gfx_v7_0_halt_rlc(struct amdgpu_device
*adev
)
3656 orig
= data
= RREG32(mmRLC_CNTL
);
3658 if (data
& RLC_CNTL__RLC_ENABLE_F32_MASK
) {
3661 data
&= ~RLC_CNTL__RLC_ENABLE_F32_MASK
;
3662 WREG32(mmRLC_CNTL
, data
);
3664 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
3665 if ((RREG32(mmRLC_GPM_STAT
) & RLC_GPM_STAT__RLC_BUSY_MASK
) == 0)
3670 gfx_v7_0_wait_for_rlc_serdes(adev
);
3676 static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device
*adev
)
3680 tmp
= 0x1 | (1 << 1);
3681 WREG32(mmRLC_GPR_REG2
, tmp
);
3683 mask
= RLC_GPM_STAT__GFX_POWER_STATUS_MASK
|
3684 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK
;
3685 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
3686 if ((RREG32(mmRLC_GPM_STAT
) & mask
) == mask
)
3691 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
3692 if ((RREG32(mmRLC_GPR_REG2
) & 0x1) == 0)
3698 static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device
*adev
)
3702 tmp
= 0x1 | (0 << 1);
3703 WREG32(mmRLC_GPR_REG2
, tmp
);
3707 * gfx_v7_0_rlc_stop - stop the RLC ME
3709 * @adev: amdgpu_device pointer
3711 * Halt the RLC ME (MicroEngine) (CIK).
3713 static void gfx_v7_0_rlc_stop(struct amdgpu_device
*adev
)
3715 WREG32(mmRLC_CNTL
, 0);
3717 gfx_v7_0_enable_gui_idle_interrupt(adev
, false);
3719 gfx_v7_0_wait_for_rlc_serdes(adev
);
3723 * gfx_v7_0_rlc_start - start the RLC ME
3725 * @adev: amdgpu_device pointer
3727 * Unhalt the RLC ME (MicroEngine) (CIK).
3729 static void gfx_v7_0_rlc_start(struct amdgpu_device
*adev
)
3731 WREG32(mmRLC_CNTL
, RLC_CNTL__RLC_ENABLE_F32_MASK
);
3733 gfx_v7_0_enable_gui_idle_interrupt(adev
, true);
3738 static void gfx_v7_0_rlc_reset(struct amdgpu_device
*adev
)
3740 u32 tmp
= RREG32(mmGRBM_SOFT_RESET
);
3742 tmp
|= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK
;
3743 WREG32(mmGRBM_SOFT_RESET
, tmp
);
3745 tmp
&= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK
;
3746 WREG32(mmGRBM_SOFT_RESET
, tmp
);
3751 * gfx_v7_0_rlc_resume - setup the RLC hw
3753 * @adev: amdgpu_device pointer
3755 * Initialize the RLC registers, load the ucode,
3756 * and start the RLC (CIK).
3757 * Returns 0 for success, -EINVAL if the ucode is not available.
3759 static int gfx_v7_0_rlc_resume(struct amdgpu_device
*adev
)
3761 const struct rlc_firmware_header_v1_0
*hdr
;
3762 const __le32
*fw_data
;
3763 unsigned i
, fw_size
;
3766 if (!adev
->gfx
.rlc_fw
)
3769 hdr
= (const struct rlc_firmware_header_v1_0
*)adev
->gfx
.rlc_fw
->data
;
3770 amdgpu_ucode_print_rlc_hdr(&hdr
->header
);
3771 adev
->gfx
.rlc_fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
3772 adev
->gfx
.rlc_feature_version
= le32_to_cpu(
3773 hdr
->ucode_feature_version
);
3775 gfx_v7_0_rlc_stop(adev
);
3778 tmp
= RREG32(mmRLC_CGCG_CGLS_CTRL
) & 0xfffffffc;
3779 WREG32(mmRLC_CGCG_CGLS_CTRL
, tmp
);
3781 gfx_v7_0_rlc_reset(adev
);
3783 gfx_v7_0_init_pg(adev
);
3785 WREG32(mmRLC_LB_CNTR_INIT
, 0);
3786 WREG32(mmRLC_LB_CNTR_MAX
, 0x00008000);
3788 mutex_lock(&adev
->grbm_idx_mutex
);
3789 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
3790 WREG32(mmRLC_LB_INIT_CU_MASK
, 0xffffffff);
3791 WREG32(mmRLC_LB_PARAMS
, 0x00600408);
3792 WREG32(mmRLC_LB_CNTL
, 0x80000004);
3793 mutex_unlock(&adev
->grbm_idx_mutex
);
3795 WREG32(mmRLC_MC_CNTL
, 0);
3796 WREG32(mmRLC_UCODE_CNTL
, 0);
3798 fw_data
= (const __le32
*)
3799 (adev
->gfx
.rlc_fw
->data
+ le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
3800 fw_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
3801 WREG32(mmRLC_GPM_UCODE_ADDR
, 0);
3802 for (i
= 0; i
< fw_size
; i
++)
3803 WREG32(mmRLC_GPM_UCODE_DATA
, le32_to_cpup(fw_data
++));
3804 WREG32(mmRLC_GPM_UCODE_ADDR
, adev
->gfx
.rlc_fw_version
);
3806 /* XXX - find out what chips support lbpw */
3807 gfx_v7_0_enable_lbpw(adev
, false);
3809 if (adev
->asic_type
== CHIP_BONAIRE
)
3810 WREG32(mmRLC_DRIVER_CPDMA_STATUS
, 0);
3812 gfx_v7_0_rlc_start(adev
);
3817 static void gfx_v7_0_enable_cgcg(struct amdgpu_device
*adev
, bool enable
)
3819 u32 data
, orig
, tmp
, tmp2
;
3821 orig
= data
= RREG32(mmRLC_CGCG_CGLS_CTRL
);
3823 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_CGCG
)) {
3824 gfx_v7_0_enable_gui_idle_interrupt(adev
, true);
3826 tmp
= gfx_v7_0_halt_rlc(adev
);
3828 mutex_lock(&adev
->grbm_idx_mutex
);
3829 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
3830 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK
, 0xffffffff);
3831 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK
, 0xffffffff);
3832 tmp2
= RLC_SERDES_WR_CTRL__BPM_ADDR_MASK
|
3833 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK
|
3834 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK
;
3835 WREG32(mmRLC_SERDES_WR_CTRL
, tmp2
);
3836 mutex_unlock(&adev
->grbm_idx_mutex
);
3838 gfx_v7_0_update_rlc(adev
, tmp
);
3840 data
|= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK
| RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK
;
3842 WREG32(mmRLC_CGCG_CGLS_CTRL
, data
);
3845 gfx_v7_0_enable_gui_idle_interrupt(adev
, false);
3847 RREG32(mmCB_CGTT_SCLK_CTRL
);
3848 RREG32(mmCB_CGTT_SCLK_CTRL
);
3849 RREG32(mmCB_CGTT_SCLK_CTRL
);
3850 RREG32(mmCB_CGTT_SCLK_CTRL
);
3852 data
&= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK
| RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK
);
3854 WREG32(mmRLC_CGCG_CGLS_CTRL
, data
);
3856 gfx_v7_0_enable_gui_idle_interrupt(adev
, true);
3860 static void gfx_v7_0_enable_mgcg(struct amdgpu_device
*adev
, bool enable
)
3862 u32 data
, orig
, tmp
= 0;
3864 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_MGCG
)) {
3865 if (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_MGLS
) {
3866 if (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_CP_LS
) {
3867 orig
= data
= RREG32(mmCP_MEM_SLP_CNTL
);
3868 data
|= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
;
3870 WREG32(mmCP_MEM_SLP_CNTL
, data
);
3874 orig
= data
= RREG32(mmRLC_CGTT_MGCG_OVERRIDE
);
3878 WREG32(mmRLC_CGTT_MGCG_OVERRIDE
, data
);
3880 tmp
= gfx_v7_0_halt_rlc(adev
);
3882 mutex_lock(&adev
->grbm_idx_mutex
);
3883 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
3884 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK
, 0xffffffff);
3885 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK
, 0xffffffff);
3886 data
= RLC_SERDES_WR_CTRL__BPM_ADDR_MASK
|
3887 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK
;
3888 WREG32(mmRLC_SERDES_WR_CTRL
, data
);
3889 mutex_unlock(&adev
->grbm_idx_mutex
);
3891 gfx_v7_0_update_rlc(adev
, tmp
);
3893 if (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_CGTS
) {
3894 orig
= data
= RREG32(mmCGTS_SM_CTRL_REG
);
3895 data
&= ~CGTS_SM_CTRL_REG__SM_MODE_MASK
;
3896 data
|= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT
);
3897 data
|= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK
;
3898 data
&= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK
;
3899 if ((adev
->cg_flags
& AMD_CG_SUPPORT_GFX_MGLS
) &&
3900 (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_CGTS_LS
))
3901 data
&= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK
;
3902 data
&= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK
;
3903 data
|= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK
;
3904 data
|= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT
);
3906 WREG32(mmCGTS_SM_CTRL_REG
, data
);
3909 orig
= data
= RREG32(mmRLC_CGTT_MGCG_OVERRIDE
);
3912 WREG32(mmRLC_CGTT_MGCG_OVERRIDE
, data
);
3914 data
= RREG32(mmRLC_MEM_SLP_CNTL
);
3915 if (data
& RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK
) {
3916 data
&= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK
;
3917 WREG32(mmRLC_MEM_SLP_CNTL
, data
);
3920 data
= RREG32(mmCP_MEM_SLP_CNTL
);
3921 if (data
& CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
) {
3922 data
&= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
;
3923 WREG32(mmCP_MEM_SLP_CNTL
, data
);
3926 orig
= data
= RREG32(mmCGTS_SM_CTRL_REG
);
3927 data
|= CGTS_SM_CTRL_REG__OVERRIDE_MASK
| CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK
;
3929 WREG32(mmCGTS_SM_CTRL_REG
, data
);
3931 tmp
= gfx_v7_0_halt_rlc(adev
);
3933 mutex_lock(&adev
->grbm_idx_mutex
);
3934 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
3935 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK
, 0xffffffff);
3936 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK
, 0xffffffff);
3937 data
= RLC_SERDES_WR_CTRL__BPM_ADDR_MASK
| RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK
;
3938 WREG32(mmRLC_SERDES_WR_CTRL
, data
);
3939 mutex_unlock(&adev
->grbm_idx_mutex
);
3941 gfx_v7_0_update_rlc(adev
, tmp
);
3945 static void gfx_v7_0_update_cg(struct amdgpu_device
*adev
,
3948 gfx_v7_0_enable_gui_idle_interrupt(adev
, false);
3949 /* order matters! */
3951 gfx_v7_0_enable_mgcg(adev
, true);
3952 gfx_v7_0_enable_cgcg(adev
, true);
3954 gfx_v7_0_enable_cgcg(adev
, false);
3955 gfx_v7_0_enable_mgcg(adev
, false);
3957 gfx_v7_0_enable_gui_idle_interrupt(adev
, true);
3960 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device
*adev
,
3965 orig
= data
= RREG32(mmRLC_PG_CNTL
);
3966 if (enable
&& (adev
->pg_flags
& AMD_PG_SUPPORT_RLC_SMU_HS
))
3967 data
|= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK
;
3969 data
&= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK
;
3971 WREG32(mmRLC_PG_CNTL
, data
);
3974 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device
*adev
,
3979 orig
= data
= RREG32(mmRLC_PG_CNTL
);
3980 if (enable
&& (adev
->pg_flags
& AMD_PG_SUPPORT_RLC_SMU_HS
))
3981 data
|= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK
;
3983 data
&= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK
;
3985 WREG32(mmRLC_PG_CNTL
, data
);
3988 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device
*adev
, bool enable
)
3992 orig
= data
= RREG32(mmRLC_PG_CNTL
);
3993 if (enable
&& (adev
->pg_flags
& AMD_PG_SUPPORT_CP
))
3998 WREG32(mmRLC_PG_CNTL
, data
);
4001 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device
*adev
, bool enable
)
4005 orig
= data
= RREG32(mmRLC_PG_CNTL
);
4006 if (enable
&& (adev
->pg_flags
& AMD_PG_SUPPORT_GDS
))
4011 WREG32(mmRLC_PG_CNTL
, data
);
4014 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device
*adev
)
4016 const __le32
*fw_data
;
4017 volatile u32
*dst_ptr
;
4018 int me
, i
, max_me
= 4;
4020 u32 table_offset
, table_size
;
4022 if (adev
->asic_type
== CHIP_KAVERI
)
4025 if (adev
->gfx
.rlc
.cp_table_ptr
== NULL
)
4028 /* write the cp table buffer */
4029 dst_ptr
= adev
->gfx
.rlc
.cp_table_ptr
;
4030 for (me
= 0; me
< max_me
; me
++) {
4032 const struct gfx_firmware_header_v1_0
*hdr
=
4033 (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.ce_fw
->data
;
4034 fw_data
= (const __le32
*)
4035 (adev
->gfx
.ce_fw
->data
+
4036 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
4037 table_offset
= le32_to_cpu(hdr
->jt_offset
);
4038 table_size
= le32_to_cpu(hdr
->jt_size
);
4039 } else if (me
== 1) {
4040 const struct gfx_firmware_header_v1_0
*hdr
=
4041 (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.pfp_fw
->data
;
4042 fw_data
= (const __le32
*)
4043 (adev
->gfx
.pfp_fw
->data
+
4044 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
4045 table_offset
= le32_to_cpu(hdr
->jt_offset
);
4046 table_size
= le32_to_cpu(hdr
->jt_size
);
4047 } else if (me
== 2) {
4048 const struct gfx_firmware_header_v1_0
*hdr
=
4049 (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.me_fw
->data
;
4050 fw_data
= (const __le32
*)
4051 (adev
->gfx
.me_fw
->data
+
4052 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
4053 table_offset
= le32_to_cpu(hdr
->jt_offset
);
4054 table_size
= le32_to_cpu(hdr
->jt_size
);
4055 } else if (me
== 3) {
4056 const struct gfx_firmware_header_v1_0
*hdr
=
4057 (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.mec_fw
->data
;
4058 fw_data
= (const __le32
*)
4059 (adev
->gfx
.mec_fw
->data
+
4060 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
4061 table_offset
= le32_to_cpu(hdr
->jt_offset
);
4062 table_size
= le32_to_cpu(hdr
->jt_size
);
4064 const struct gfx_firmware_header_v1_0
*hdr
=
4065 (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.mec2_fw
->data
;
4066 fw_data
= (const __le32
*)
4067 (adev
->gfx
.mec2_fw
->data
+
4068 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
4069 table_offset
= le32_to_cpu(hdr
->jt_offset
);
4070 table_size
= le32_to_cpu(hdr
->jt_size
);
4073 for (i
= 0; i
< table_size
; i
++) {
4074 dst_ptr
[bo_offset
+ i
] =
4075 cpu_to_le32(le32_to_cpu(fw_data
[table_offset
+ i
]));
4078 bo_offset
+= table_size
;
4082 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device
*adev
,
4087 if (enable
&& (adev
->pg_flags
& AMD_PG_SUPPORT_GFX_PG
)) {
4088 orig
= data
= RREG32(mmRLC_PG_CNTL
);
4089 data
|= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK
;
4091 WREG32(mmRLC_PG_CNTL
, data
);
4093 orig
= data
= RREG32(mmRLC_AUTO_PG_CTRL
);
4094 data
|= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK
;
4096 WREG32(mmRLC_AUTO_PG_CTRL
, data
);
4098 orig
= data
= RREG32(mmRLC_PG_CNTL
);
4099 data
&= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK
;
4101 WREG32(mmRLC_PG_CNTL
, data
);
4103 orig
= data
= RREG32(mmRLC_AUTO_PG_CTRL
);
4104 data
&= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK
;
4106 WREG32(mmRLC_AUTO_PG_CTRL
, data
);
4108 data
= RREG32(mmDB_RENDER_CONTROL
);
4112 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device
*adev
,
4120 data
= bitmap
<< GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT
;
4121 data
&= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK
;
4123 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG
, data
);
4126 static u32
gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device
*adev
)
4130 data
= RREG32(mmCC_GC_SHADER_ARRAY_CONFIG
);
4131 data
|= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG
);
4133 data
&= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK
;
4134 data
>>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT
;
4136 mask
= gfx_v7_0_create_bitmask(adev
->gfx
.config
.max_cu_per_sh
);
4138 return (~data
) & mask
;
4141 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device
*adev
)
4145 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK
, adev
->gfx
.cu_info
.ao_cu_mask
);
4147 tmp
= RREG32(mmRLC_MAX_PG_CU
);
4148 tmp
&= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK
;
4149 tmp
|= (adev
->gfx
.cu_info
.number
<< RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT
);
4150 WREG32(mmRLC_MAX_PG_CU
, tmp
);
4153 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device
*adev
,
4158 orig
= data
= RREG32(mmRLC_PG_CNTL
);
4159 if (enable
&& (adev
->pg_flags
& AMD_PG_SUPPORT_GFX_SMG
))
4160 data
|= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK
;
4162 data
&= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK
;
4164 WREG32(mmRLC_PG_CNTL
, data
);
4167 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device
*adev
,
4172 orig
= data
= RREG32(mmRLC_PG_CNTL
);
4173 if (enable
&& (adev
->pg_flags
& AMD_PG_SUPPORT_GFX_DMG
))
4174 data
|= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK
;
4176 data
&= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK
;
4178 WREG32(mmRLC_PG_CNTL
, data
);
4181 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
4182 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
4184 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device
*adev
)
4189 if (adev
->gfx
.rlc
.cs_data
) {
4190 WREG32(mmRLC_GPM_SCRATCH_ADDR
, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET
);
4191 WREG32(mmRLC_GPM_SCRATCH_DATA
, upper_32_bits(adev
->gfx
.rlc
.clear_state_gpu_addr
));
4192 WREG32(mmRLC_GPM_SCRATCH_DATA
, lower_32_bits(adev
->gfx
.rlc
.clear_state_gpu_addr
));
4193 WREG32(mmRLC_GPM_SCRATCH_DATA
, adev
->gfx
.rlc
.clear_state_size
);
4195 WREG32(mmRLC_GPM_SCRATCH_ADDR
, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET
);
4196 for (i
= 0; i
< 3; i
++)
4197 WREG32(mmRLC_GPM_SCRATCH_DATA
, 0);
4199 if (adev
->gfx
.rlc
.reg_list
) {
4200 WREG32(mmRLC_GPM_SCRATCH_ADDR
, RLC_SAVE_AND_RESTORE_STARTING_OFFSET
);
4201 for (i
= 0; i
< adev
->gfx
.rlc
.reg_list_size
; i
++)
4202 WREG32(mmRLC_GPM_SCRATCH_DATA
, adev
->gfx
.rlc
.reg_list
[i
]);
4205 orig
= data
= RREG32(mmRLC_PG_CNTL
);
4206 data
|= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK
;
4208 WREG32(mmRLC_PG_CNTL
, data
);
4210 WREG32(mmRLC_SAVE_AND_RESTORE_BASE
, adev
->gfx
.rlc
.save_restore_gpu_addr
>> 8);
4211 WREG32(mmRLC_JUMP_TABLE_RESTORE
, adev
->gfx
.rlc
.cp_table_gpu_addr
>> 8);
4213 data
= RREG32(mmCP_RB_WPTR_POLL_CNTL
);
4214 data
&= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK
;
4215 data
|= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT
);
4216 WREG32(mmCP_RB_WPTR_POLL_CNTL
, data
);
4219 WREG32(mmRLC_PG_DELAY
, data
);
4221 data
= RREG32(mmRLC_PG_DELAY_2
);
4224 WREG32(mmRLC_PG_DELAY_2
, data
);
4226 data
= RREG32(mmRLC_AUTO_PG_CTRL
);
4227 data
&= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK
;
4228 data
|= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT
);
4229 WREG32(mmRLC_AUTO_PG_CTRL
, data
);
4233 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device
*adev
, bool enable
)
4235 gfx_v7_0_enable_gfx_cgpg(adev
, enable
);
4236 gfx_v7_0_enable_gfx_static_mgpg(adev
, enable
);
4237 gfx_v7_0_enable_gfx_dynamic_mgpg(adev
, enable
);
4240 static u32
gfx_v7_0_get_csb_size(struct amdgpu_device
*adev
)
4243 const struct cs_section_def
*sect
= NULL
;
4244 const struct cs_extent_def
*ext
= NULL
;
4246 if (adev
->gfx
.rlc
.cs_data
== NULL
)
4249 /* begin clear state */
4251 /* context control state */
4254 for (sect
= adev
->gfx
.rlc
.cs_data
; sect
->section
!= NULL
; ++sect
) {
4255 for (ext
= sect
->section
; ext
->extent
!= NULL
; ++ext
) {
4256 if (sect
->id
== SECT_CONTEXT
)
4257 count
+= 2 + ext
->reg_count
;
4262 /* pa_sc_raster_config/pa_sc_raster_config1 */
4264 /* end clear state */
4272 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device
*adev
,
4273 volatile u32
*buffer
)
4276 const struct cs_section_def
*sect
= NULL
;
4277 const struct cs_extent_def
*ext
= NULL
;
4279 if (adev
->gfx
.rlc
.cs_data
== NULL
)
4284 buffer
[count
++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
4285 buffer
[count
++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
);
4287 buffer
[count
++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL
, 1));
4288 buffer
[count
++] = cpu_to_le32(0x80000000);
4289 buffer
[count
++] = cpu_to_le32(0x80000000);
4291 for (sect
= adev
->gfx
.rlc
.cs_data
; sect
->section
!= NULL
; ++sect
) {
4292 for (ext
= sect
->section
; ext
->extent
!= NULL
; ++ext
) {
4293 if (sect
->id
== SECT_CONTEXT
) {
4295 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG
, ext
->reg_count
));
4296 buffer
[count
++] = cpu_to_le32(ext
->reg_index
- PACKET3_SET_CONTEXT_REG_START
);
4297 for (i
= 0; i
< ext
->reg_count
; i
++)
4298 buffer
[count
++] = cpu_to_le32(ext
->extent
[i
]);
4305 buffer
[count
++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG
, 2));
4306 buffer
[count
++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG
- PACKET3_SET_CONTEXT_REG_START
);
4307 switch (adev
->asic_type
) {
4309 buffer
[count
++] = cpu_to_le32(0x16000012);
4310 buffer
[count
++] = cpu_to_le32(0x00000000);
4313 buffer
[count
++] = cpu_to_le32(0x00000000); /* XXX */
4314 buffer
[count
++] = cpu_to_le32(0x00000000);
4318 buffer
[count
++] = cpu_to_le32(0x00000000); /* XXX */
4319 buffer
[count
++] = cpu_to_le32(0x00000000);
4322 buffer
[count
++] = cpu_to_le32(0x3a00161a);
4323 buffer
[count
++] = cpu_to_le32(0x0000002e);
4326 buffer
[count
++] = cpu_to_le32(0x00000000);
4327 buffer
[count
++] = cpu_to_le32(0x00000000);
4331 buffer
[count
++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
4332 buffer
[count
++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE
);
4334 buffer
[count
++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE
, 0));
4335 buffer
[count
++] = cpu_to_le32(0);
4338 static void gfx_v7_0_init_pg(struct amdgpu_device
*adev
)
4340 if (adev
->pg_flags
& (AMD_PG_SUPPORT_GFX_PG
|
4341 AMD_PG_SUPPORT_GFX_SMG
|
4342 AMD_PG_SUPPORT_GFX_DMG
|
4344 AMD_PG_SUPPORT_GDS
|
4345 AMD_PG_SUPPORT_RLC_SMU_HS
)) {
4346 gfx_v7_0_enable_sclk_slowdown_on_pu(adev
, true);
4347 gfx_v7_0_enable_sclk_slowdown_on_pd(adev
, true);
4348 if (adev
->pg_flags
& AMD_PG_SUPPORT_GFX_PG
) {
4349 gfx_v7_0_init_gfx_cgpg(adev
);
4350 gfx_v7_0_enable_cp_pg(adev
, true);
4351 gfx_v7_0_enable_gds_pg(adev
, true);
4353 gfx_v7_0_init_ao_cu_mask(adev
);
4354 gfx_v7_0_update_gfx_pg(adev
, true);
4358 static void gfx_v7_0_fini_pg(struct amdgpu_device
*adev
)
4360 if (adev
->pg_flags
& (AMD_PG_SUPPORT_GFX_PG
|
4361 AMD_PG_SUPPORT_GFX_SMG
|
4362 AMD_PG_SUPPORT_GFX_DMG
|
4364 AMD_PG_SUPPORT_GDS
|
4365 AMD_PG_SUPPORT_RLC_SMU_HS
)) {
4366 gfx_v7_0_update_gfx_pg(adev
, false);
4367 if (adev
->pg_flags
& AMD_PG_SUPPORT_GFX_PG
) {
4368 gfx_v7_0_enable_cp_pg(adev
, false);
4369 gfx_v7_0_enable_gds_pg(adev
, false);
4375 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4377 * @adev: amdgpu_device pointer
4379 * Fetches a GPU clock counter snapshot (SI).
4380 * Returns the 64 bit clock counter snapshot.
4382 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device
*adev
)
4386 mutex_lock(&adev
->gfx
.gpu_clock_mutex
);
4387 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT
, 1);
4388 clock
= (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB
) |
4389 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB
) << 32ULL);
4390 mutex_unlock(&adev
->gfx
.gpu_clock_mutex
);
4394 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring
*ring
,
4396 uint32_t gds_base
, uint32_t gds_size
,
4397 uint32_t gws_base
, uint32_t gws_size
,
4398 uint32_t oa_base
, uint32_t oa_size
)
4400 gds_base
= gds_base
>> AMDGPU_GDS_SHIFT
;
4401 gds_size
= gds_size
>> AMDGPU_GDS_SHIFT
;
4403 gws_base
= gws_base
>> AMDGPU_GWS_SHIFT
;
4404 gws_size
= gws_size
>> AMDGPU_GWS_SHIFT
;
4406 oa_base
= oa_base
>> AMDGPU_OA_SHIFT
;
4407 oa_size
= oa_size
>> AMDGPU_OA_SHIFT
;
4410 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
4411 amdgpu_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(0) |
4412 WRITE_DATA_DST_SEL(0)));
4413 amdgpu_ring_write(ring
, amdgpu_gds_reg_offset
[vmid
].mem_base
);
4414 amdgpu_ring_write(ring
, 0);
4415 amdgpu_ring_write(ring
, gds_base
);
4418 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
4419 amdgpu_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(0) |
4420 WRITE_DATA_DST_SEL(0)));
4421 amdgpu_ring_write(ring
, amdgpu_gds_reg_offset
[vmid
].mem_size
);
4422 amdgpu_ring_write(ring
, 0);
4423 amdgpu_ring_write(ring
, gds_size
);
4426 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
4427 amdgpu_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(0) |
4428 WRITE_DATA_DST_SEL(0)));
4429 amdgpu_ring_write(ring
, amdgpu_gds_reg_offset
[vmid
].gws
);
4430 amdgpu_ring_write(ring
, 0);
4431 amdgpu_ring_write(ring
, gws_size
<< GDS_GWS_VMID0__SIZE__SHIFT
| gws_base
);
4434 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
4435 amdgpu_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(0) |
4436 WRITE_DATA_DST_SEL(0)));
4437 amdgpu_ring_write(ring
, amdgpu_gds_reg_offset
[vmid
].oa
);
4438 amdgpu_ring_write(ring
, 0);
4439 amdgpu_ring_write(ring
, (1 << (oa_size
+ oa_base
)) - (1 << oa_base
));
4442 static uint32_t wave_read_ind(struct amdgpu_device
*adev
, uint32_t simd
, uint32_t wave
, uint32_t address
)
4444 WREG32(mmSQ_IND_INDEX
,
4445 (wave
<< SQ_IND_INDEX__WAVE_ID__SHIFT
) |
4446 (simd
<< SQ_IND_INDEX__SIMD_ID__SHIFT
) |
4447 (address
<< SQ_IND_INDEX__INDEX__SHIFT
) |
4448 (SQ_IND_INDEX__FORCE_READ_MASK
));
4449 return RREG32(mmSQ_IND_DATA
);
4452 static void wave_read_regs(struct amdgpu_device
*adev
, uint32_t simd
,
4453 uint32_t wave
, uint32_t thread
,
4454 uint32_t regno
, uint32_t num
, uint32_t *out
)
4456 WREG32(mmSQ_IND_INDEX
,
4457 (wave
<< SQ_IND_INDEX__WAVE_ID__SHIFT
) |
4458 (simd
<< SQ_IND_INDEX__SIMD_ID__SHIFT
) |
4459 (regno
<< SQ_IND_INDEX__INDEX__SHIFT
) |
4460 (thread
<< SQ_IND_INDEX__THREAD_ID__SHIFT
) |
4461 (SQ_IND_INDEX__FORCE_READ_MASK
) |
4462 (SQ_IND_INDEX__AUTO_INCR_MASK
));
4464 *(out
++) = RREG32(mmSQ_IND_DATA
);
4467 static void gfx_v7_0_read_wave_data(struct amdgpu_device
*adev
, uint32_t simd
, uint32_t wave
, uint32_t *dst
, int *no_fields
)
4469 /* type 0 wave data */
4470 dst
[(*no_fields
)++] = 0;
4471 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_STATUS
);
4472 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_PC_LO
);
4473 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_PC_HI
);
4474 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_EXEC_LO
);
4475 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_EXEC_HI
);
4476 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_HW_ID
);
4477 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_INST_DW0
);
4478 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_INST_DW1
);
4479 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_GPR_ALLOC
);
4480 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_LDS_ALLOC
);
4481 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_TRAPSTS
);
4482 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_IB_STS
);
4483 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_TBA_LO
);
4484 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_TBA_HI
);
4485 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_TMA_LO
);
4486 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_TMA_HI
);
4487 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_IB_DBG0
);
4488 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_M0
);
4491 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device
*adev
, uint32_t simd
,
4492 uint32_t wave
, uint32_t start
,
4493 uint32_t size
, uint32_t *dst
)
4496 adev
, simd
, wave
, 0,
4497 start
+ SQIND_WAVE_SGPRS_OFFSET
, size
, dst
);
4500 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs
= {
4501 .get_gpu_clock_counter
= &gfx_v7_0_get_gpu_clock_counter
,
4502 .select_se_sh
= &gfx_v7_0_select_se_sh
,
4503 .read_wave_data
= &gfx_v7_0_read_wave_data
,
4504 .read_wave_sgprs
= &gfx_v7_0_read_wave_sgprs
,
4507 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs
= {
4508 .enter_safe_mode
= gfx_v7_0_enter_rlc_safe_mode
,
4509 .exit_safe_mode
= gfx_v7_0_exit_rlc_safe_mode
4512 static int gfx_v7_0_early_init(void *handle
)
4514 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4516 adev
->gfx
.num_gfx_rings
= GFX7_NUM_GFX_RINGS
;
4517 adev
->gfx
.num_compute_rings
= GFX7_NUM_COMPUTE_RINGS
;
4518 adev
->gfx
.funcs
= &gfx_v7_0_gfx_funcs
;
4519 adev
->gfx
.rlc
.funcs
= &gfx_v7_0_rlc_funcs
;
4520 gfx_v7_0_set_ring_funcs(adev
);
4521 gfx_v7_0_set_irq_funcs(adev
);
4522 gfx_v7_0_set_gds_init(adev
);
4527 static int gfx_v7_0_late_init(void *handle
)
4529 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4532 r
= amdgpu_irq_get(adev
, &adev
->gfx
.priv_reg_irq
, 0);
4536 r
= amdgpu_irq_get(adev
, &adev
->gfx
.priv_inst_irq
, 0);
4543 static void gfx_v7_0_gpu_early_init(struct amdgpu_device
*adev
)
4546 u32 mc_shared_chmap
, mc_arb_ramcfg
;
4547 u32 dimm00_addr_map
, dimm01_addr_map
, dimm10_addr_map
, dimm11_addr_map
;
4550 switch (adev
->asic_type
) {
4552 adev
->gfx
.config
.max_shader_engines
= 2;
4553 adev
->gfx
.config
.max_tile_pipes
= 4;
4554 adev
->gfx
.config
.max_cu_per_sh
= 7;
4555 adev
->gfx
.config
.max_sh_per_se
= 1;
4556 adev
->gfx
.config
.max_backends_per_se
= 2;
4557 adev
->gfx
.config
.max_texture_channel_caches
= 4;
4558 adev
->gfx
.config
.max_gprs
= 256;
4559 adev
->gfx
.config
.max_gs_threads
= 32;
4560 adev
->gfx
.config
.max_hw_contexts
= 8;
4562 adev
->gfx
.config
.sc_prim_fifo_size_frontend
= 0x20;
4563 adev
->gfx
.config
.sc_prim_fifo_size_backend
= 0x100;
4564 adev
->gfx
.config
.sc_hiz_tile_fifo_size
= 0x30;
4565 adev
->gfx
.config
.sc_earlyz_tile_fifo_size
= 0x130;
4566 gb_addr_config
= BONAIRE_GB_ADDR_CONFIG_GOLDEN
;
4569 adev
->gfx
.config
.max_shader_engines
= 4;
4570 adev
->gfx
.config
.max_tile_pipes
= 16;
4571 adev
->gfx
.config
.max_cu_per_sh
= 11;
4572 adev
->gfx
.config
.max_sh_per_se
= 1;
4573 adev
->gfx
.config
.max_backends_per_se
= 4;
4574 adev
->gfx
.config
.max_texture_channel_caches
= 16;
4575 adev
->gfx
.config
.max_gprs
= 256;
4576 adev
->gfx
.config
.max_gs_threads
= 32;
4577 adev
->gfx
.config
.max_hw_contexts
= 8;
4579 adev
->gfx
.config
.sc_prim_fifo_size_frontend
= 0x20;
4580 adev
->gfx
.config
.sc_prim_fifo_size_backend
= 0x100;
4581 adev
->gfx
.config
.sc_hiz_tile_fifo_size
= 0x30;
4582 adev
->gfx
.config
.sc_earlyz_tile_fifo_size
= 0x130;
4583 gb_addr_config
= HAWAII_GB_ADDR_CONFIG_GOLDEN
;
4586 adev
->gfx
.config
.max_shader_engines
= 1;
4587 adev
->gfx
.config
.max_tile_pipes
= 4;
4588 if ((adev
->pdev
->device
== 0x1304) ||
4589 (adev
->pdev
->device
== 0x1305) ||
4590 (adev
->pdev
->device
== 0x130C) ||
4591 (adev
->pdev
->device
== 0x130F) ||
4592 (adev
->pdev
->device
== 0x1310) ||
4593 (adev
->pdev
->device
== 0x1311) ||
4594 (adev
->pdev
->device
== 0x131C)) {
4595 adev
->gfx
.config
.max_cu_per_sh
= 8;
4596 adev
->gfx
.config
.max_backends_per_se
= 2;
4597 } else if ((adev
->pdev
->device
== 0x1309) ||
4598 (adev
->pdev
->device
== 0x130A) ||
4599 (adev
->pdev
->device
== 0x130D) ||
4600 (adev
->pdev
->device
== 0x1313) ||
4601 (adev
->pdev
->device
== 0x131D)) {
4602 adev
->gfx
.config
.max_cu_per_sh
= 6;
4603 adev
->gfx
.config
.max_backends_per_se
= 2;
4604 } else if ((adev
->pdev
->device
== 0x1306) ||
4605 (adev
->pdev
->device
== 0x1307) ||
4606 (adev
->pdev
->device
== 0x130B) ||
4607 (adev
->pdev
->device
== 0x130E) ||
4608 (adev
->pdev
->device
== 0x1315) ||
4609 (adev
->pdev
->device
== 0x131B)) {
4610 adev
->gfx
.config
.max_cu_per_sh
= 4;
4611 adev
->gfx
.config
.max_backends_per_se
= 1;
4613 adev
->gfx
.config
.max_cu_per_sh
= 3;
4614 adev
->gfx
.config
.max_backends_per_se
= 1;
4616 adev
->gfx
.config
.max_sh_per_se
= 1;
4617 adev
->gfx
.config
.max_texture_channel_caches
= 4;
4618 adev
->gfx
.config
.max_gprs
= 256;
4619 adev
->gfx
.config
.max_gs_threads
= 16;
4620 adev
->gfx
.config
.max_hw_contexts
= 8;
4622 adev
->gfx
.config
.sc_prim_fifo_size_frontend
= 0x20;
4623 adev
->gfx
.config
.sc_prim_fifo_size_backend
= 0x100;
4624 adev
->gfx
.config
.sc_hiz_tile_fifo_size
= 0x30;
4625 adev
->gfx
.config
.sc_earlyz_tile_fifo_size
= 0x130;
4626 gb_addr_config
= BONAIRE_GB_ADDR_CONFIG_GOLDEN
;
4631 adev
->gfx
.config
.max_shader_engines
= 1;
4632 adev
->gfx
.config
.max_tile_pipes
= 2;
4633 adev
->gfx
.config
.max_cu_per_sh
= 2;
4634 adev
->gfx
.config
.max_sh_per_se
= 1;
4635 adev
->gfx
.config
.max_backends_per_se
= 1;
4636 adev
->gfx
.config
.max_texture_channel_caches
= 2;
4637 adev
->gfx
.config
.max_gprs
= 256;
4638 adev
->gfx
.config
.max_gs_threads
= 16;
4639 adev
->gfx
.config
.max_hw_contexts
= 8;
4641 adev
->gfx
.config
.sc_prim_fifo_size_frontend
= 0x20;
4642 adev
->gfx
.config
.sc_prim_fifo_size_backend
= 0x100;
4643 adev
->gfx
.config
.sc_hiz_tile_fifo_size
= 0x30;
4644 adev
->gfx
.config
.sc_earlyz_tile_fifo_size
= 0x130;
4645 gb_addr_config
= BONAIRE_GB_ADDR_CONFIG_GOLDEN
;
4649 mc_shared_chmap
= RREG32(mmMC_SHARED_CHMAP
);
4650 adev
->gfx
.config
.mc_arb_ramcfg
= RREG32(mmMC_ARB_RAMCFG
);
4651 mc_arb_ramcfg
= adev
->gfx
.config
.mc_arb_ramcfg
;
4653 adev
->gfx
.config
.num_tile_pipes
= adev
->gfx
.config
.max_tile_pipes
;
4654 adev
->gfx
.config
.mem_max_burst_length_bytes
= 256;
4655 if (adev
->flags
& AMD_IS_APU
) {
4656 /* Get memory bank mapping mode. */
4657 tmp
= RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING
);
4658 dimm00_addr_map
= REG_GET_FIELD(tmp
, MC_FUS_DRAM0_BANK_ADDR_MAPPING
, DIMM0ADDRMAP
);
4659 dimm01_addr_map
= REG_GET_FIELD(tmp
, MC_FUS_DRAM0_BANK_ADDR_MAPPING
, DIMM1ADDRMAP
);
4661 tmp
= RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING
);
4662 dimm10_addr_map
= REG_GET_FIELD(tmp
, MC_FUS_DRAM1_BANK_ADDR_MAPPING
, DIMM0ADDRMAP
);
4663 dimm11_addr_map
= REG_GET_FIELD(tmp
, MC_FUS_DRAM1_BANK_ADDR_MAPPING
, DIMM1ADDRMAP
);
4665 /* Validate settings in case only one DIMM installed. */
4666 if ((dimm00_addr_map
== 0) || (dimm00_addr_map
== 3) || (dimm00_addr_map
== 4) || (dimm00_addr_map
> 12))
4667 dimm00_addr_map
= 0;
4668 if ((dimm01_addr_map
== 0) || (dimm01_addr_map
== 3) || (dimm01_addr_map
== 4) || (dimm01_addr_map
> 12))
4669 dimm01_addr_map
= 0;
4670 if ((dimm10_addr_map
== 0) || (dimm10_addr_map
== 3) || (dimm10_addr_map
== 4) || (dimm10_addr_map
> 12))
4671 dimm10_addr_map
= 0;
4672 if ((dimm11_addr_map
== 0) || (dimm11_addr_map
== 3) || (dimm11_addr_map
== 4) || (dimm11_addr_map
> 12))
4673 dimm11_addr_map
= 0;
4675 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4676 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4677 if ((dimm00_addr_map
== 11) || (dimm01_addr_map
== 11) || (dimm10_addr_map
== 11) || (dimm11_addr_map
== 11))
4678 adev
->gfx
.config
.mem_row_size_in_kb
= 2;
4680 adev
->gfx
.config
.mem_row_size_in_kb
= 1;
4682 tmp
= (mc_arb_ramcfg
& MC_ARB_RAMCFG__NOOFCOLS_MASK
) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT
;
4683 adev
->gfx
.config
.mem_row_size_in_kb
= (4 * (1 << (8 + tmp
))) / 1024;
4684 if (adev
->gfx
.config
.mem_row_size_in_kb
> 4)
4685 adev
->gfx
.config
.mem_row_size_in_kb
= 4;
4687 /* XXX use MC settings? */
4688 adev
->gfx
.config
.shader_engine_tile_size
= 32;
4689 adev
->gfx
.config
.num_gpus
= 1;
4690 adev
->gfx
.config
.multi_gpu_tile_size
= 64;
4692 /* fix up row size */
4693 gb_addr_config
&= ~GB_ADDR_CONFIG__ROW_SIZE_MASK
;
4694 switch (adev
->gfx
.config
.mem_row_size_in_kb
) {
4697 gb_addr_config
|= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT
);
4700 gb_addr_config
|= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT
);
4703 gb_addr_config
|= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT
);
4706 adev
->gfx
.config
.gb_addr_config
= gb_addr_config
;
4709 static int gfx_v7_0_sw_init(void *handle
)
4711 struct amdgpu_ring
*ring
;
4712 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4716 r
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_LEGACY
, 181, &adev
->gfx
.eop_irq
);
4720 /* Privileged reg */
4721 r
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_LEGACY
, 184,
4722 &adev
->gfx
.priv_reg_irq
);
4726 /* Privileged inst */
4727 r
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_LEGACY
, 185,
4728 &adev
->gfx
.priv_inst_irq
);
4732 gfx_v7_0_scratch_init(adev
);
4734 r
= gfx_v7_0_init_microcode(adev
);
4736 DRM_ERROR("Failed to load gfx firmware!\n");
4740 r
= gfx_v7_0_rlc_init(adev
);
4742 DRM_ERROR("Failed to init rlc BOs!\n");
4746 /* allocate mec buffers */
4747 r
= gfx_v7_0_mec_init(adev
);
4749 DRM_ERROR("Failed to init MEC BOs!\n");
4753 for (i
= 0; i
< adev
->gfx
.num_gfx_rings
; i
++) {
4754 ring
= &adev
->gfx
.gfx_ring
[i
];
4755 ring
->ring_obj
= NULL
;
4756 sprintf(ring
->name
, "gfx");
4757 r
= amdgpu_ring_init(adev
, ring
, 1024,
4758 &adev
->gfx
.eop_irq
, AMDGPU_CP_IRQ_GFX_EOP
);
4763 /* set up the compute queues */
4764 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++) {
4767 /* max 32 queues per MEC */
4768 if ((i
>= 32) || (i
>= AMDGPU_MAX_COMPUTE_RINGS
)) {
4769 DRM_ERROR("Too many (%d) compute rings!\n", i
);
4772 ring
= &adev
->gfx
.compute_ring
[i
];
4773 ring
->ring_obj
= NULL
;
4774 ring
->use_doorbell
= true;
4775 ring
->doorbell_index
= AMDGPU_DOORBELL_MEC_RING0
+ i
;
4776 ring
->me
= 1; /* first MEC */
4778 ring
->queue
= i
% 8;
4779 sprintf(ring
->name
, "comp_%d.%d.%d", ring
->me
, ring
->pipe
, ring
->queue
);
4780 irq_type
= AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
+ ring
->pipe
;
4781 /* type-2 packets are deprecated on MEC, use type-3 instead */
4782 r
= amdgpu_ring_init(adev
, ring
, 1024,
4783 &adev
->gfx
.eop_irq
, irq_type
);
4788 /* reserve GDS, GWS and OA resource for gfx */
4789 r
= amdgpu_bo_create_kernel(adev
, adev
->gds
.mem
.gfx_partition_size
,
4790 PAGE_SIZE
, AMDGPU_GEM_DOMAIN_GDS
,
4791 &adev
->gds
.gds_gfx_bo
, NULL
, NULL
);
4795 r
= amdgpu_bo_create_kernel(adev
, adev
->gds
.gws
.gfx_partition_size
,
4796 PAGE_SIZE
, AMDGPU_GEM_DOMAIN_GWS
,
4797 &adev
->gds
.gws_gfx_bo
, NULL
, NULL
);
4801 r
= amdgpu_bo_create_kernel(adev
, adev
->gds
.oa
.gfx_partition_size
,
4802 PAGE_SIZE
, AMDGPU_GEM_DOMAIN_OA
,
4803 &adev
->gds
.oa_gfx_bo
, NULL
, NULL
);
4807 adev
->gfx
.ce_ram_size
= 0x8000;
4809 gfx_v7_0_gpu_early_init(adev
);
4814 static int gfx_v7_0_sw_fini(void *handle
)
4817 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4819 amdgpu_bo_free_kernel(&adev
->gds
.oa_gfx_bo
, NULL
, NULL
);
4820 amdgpu_bo_free_kernel(&adev
->gds
.gws_gfx_bo
, NULL
, NULL
);
4821 amdgpu_bo_free_kernel(&adev
->gds
.gds_gfx_bo
, NULL
, NULL
);
4823 for (i
= 0; i
< adev
->gfx
.num_gfx_rings
; i
++)
4824 amdgpu_ring_fini(&adev
->gfx
.gfx_ring
[i
]);
4825 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++)
4826 amdgpu_ring_fini(&adev
->gfx
.compute_ring
[i
]);
4828 gfx_v7_0_cp_compute_fini(adev
);
4829 gfx_v7_0_rlc_fini(adev
);
4830 gfx_v7_0_mec_fini(adev
);
4831 gfx_v7_0_free_microcode(adev
);
4836 static int gfx_v7_0_hw_init(void *handle
)
4839 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4841 gfx_v7_0_gpu_init(adev
);
4844 r
= gfx_v7_0_rlc_resume(adev
);
4848 r
= gfx_v7_0_cp_resume(adev
);
4855 static int gfx_v7_0_hw_fini(void *handle
)
4857 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4859 amdgpu_irq_put(adev
, &adev
->gfx
.priv_reg_irq
, 0);
4860 amdgpu_irq_put(adev
, &adev
->gfx
.priv_inst_irq
, 0);
4861 gfx_v7_0_cp_enable(adev
, false);
4862 gfx_v7_0_rlc_stop(adev
);
4863 gfx_v7_0_fini_pg(adev
);
4868 static int gfx_v7_0_suspend(void *handle
)
4870 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4872 return gfx_v7_0_hw_fini(adev
);
4875 static int gfx_v7_0_resume(void *handle
)
4877 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4879 return gfx_v7_0_hw_init(adev
);
4882 static bool gfx_v7_0_is_idle(void *handle
)
4884 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4886 if (RREG32(mmGRBM_STATUS
) & GRBM_STATUS__GUI_ACTIVE_MASK
)
4892 static int gfx_v7_0_wait_for_idle(void *handle
)
4896 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4898 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
4899 /* read MC_STATUS */
4900 tmp
= RREG32(mmGRBM_STATUS
) & GRBM_STATUS__GUI_ACTIVE_MASK
;
4909 static int gfx_v7_0_soft_reset(void *handle
)
4911 u32 grbm_soft_reset
= 0, srbm_soft_reset
= 0;
4913 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4916 tmp
= RREG32(mmGRBM_STATUS
);
4917 if (tmp
& (GRBM_STATUS__PA_BUSY_MASK
| GRBM_STATUS__SC_BUSY_MASK
|
4918 GRBM_STATUS__BCI_BUSY_MASK
| GRBM_STATUS__SX_BUSY_MASK
|
4919 GRBM_STATUS__TA_BUSY_MASK
| GRBM_STATUS__VGT_BUSY_MASK
|
4920 GRBM_STATUS__DB_BUSY_MASK
| GRBM_STATUS__CB_BUSY_MASK
|
4921 GRBM_STATUS__GDS_BUSY_MASK
| GRBM_STATUS__SPI_BUSY_MASK
|
4922 GRBM_STATUS__IA_BUSY_MASK
| GRBM_STATUS__IA_BUSY_NO_DMA_MASK
))
4923 grbm_soft_reset
|= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK
|
4924 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK
;
4926 if (tmp
& (GRBM_STATUS__CP_BUSY_MASK
| GRBM_STATUS__CP_COHERENCY_BUSY_MASK
)) {
4927 grbm_soft_reset
|= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK
;
4928 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK
;
4932 tmp
= RREG32(mmGRBM_STATUS2
);
4933 if (tmp
& GRBM_STATUS2__RLC_BUSY_MASK
)
4934 grbm_soft_reset
|= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK
;
4937 tmp
= RREG32(mmSRBM_STATUS
);
4938 if (tmp
& SRBM_STATUS__GRBM_RQ_PENDING_MASK
)
4939 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK
;
4941 if (grbm_soft_reset
|| srbm_soft_reset
) {
4943 gfx_v7_0_fini_pg(adev
);
4944 gfx_v7_0_update_cg(adev
, false);
4947 gfx_v7_0_rlc_stop(adev
);
4949 /* Disable GFX parsing/prefetching */
4950 WREG32(mmCP_ME_CNTL
, CP_ME_CNTL__ME_HALT_MASK
| CP_ME_CNTL__PFP_HALT_MASK
| CP_ME_CNTL__CE_HALT_MASK
);
4952 /* Disable MEC parsing/prefetching */
4953 WREG32(mmCP_MEC_CNTL
, CP_MEC_CNTL__MEC_ME1_HALT_MASK
| CP_MEC_CNTL__MEC_ME2_HALT_MASK
);
4955 if (grbm_soft_reset
) {
4956 tmp
= RREG32(mmGRBM_SOFT_RESET
);
4957 tmp
|= grbm_soft_reset
;
4958 dev_info(adev
->dev
, "GRBM_SOFT_RESET=0x%08X\n", tmp
);
4959 WREG32(mmGRBM_SOFT_RESET
, tmp
);
4960 tmp
= RREG32(mmGRBM_SOFT_RESET
);
4964 tmp
&= ~grbm_soft_reset
;
4965 WREG32(mmGRBM_SOFT_RESET
, tmp
);
4966 tmp
= RREG32(mmGRBM_SOFT_RESET
);
4969 if (srbm_soft_reset
) {
4970 tmp
= RREG32(mmSRBM_SOFT_RESET
);
4971 tmp
|= srbm_soft_reset
;
4972 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
4973 WREG32(mmSRBM_SOFT_RESET
, tmp
);
4974 tmp
= RREG32(mmSRBM_SOFT_RESET
);
4978 tmp
&= ~srbm_soft_reset
;
4979 WREG32(mmSRBM_SOFT_RESET
, tmp
);
4980 tmp
= RREG32(mmSRBM_SOFT_RESET
);
4982 /* Wait a little for things to settle down */
4988 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device
*adev
,
4989 enum amdgpu_interrupt_state state
)
4994 case AMDGPU_IRQ_STATE_DISABLE
:
4995 cp_int_cntl
= RREG32(mmCP_INT_CNTL_RING0
);
4996 cp_int_cntl
&= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK
;
4997 WREG32(mmCP_INT_CNTL_RING0
, cp_int_cntl
);
4999 case AMDGPU_IRQ_STATE_ENABLE
:
5000 cp_int_cntl
= RREG32(mmCP_INT_CNTL_RING0
);
5001 cp_int_cntl
|= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK
;
5002 WREG32(mmCP_INT_CNTL_RING0
, cp_int_cntl
);
5009 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device
*adev
,
5011 enum amdgpu_interrupt_state state
)
5013 u32 mec_int_cntl
, mec_int_cntl_reg
;
5016 * amdgpu controls only pipe 0 of MEC1. That's why this function only
5017 * handles the setting of interrupts for this specific pipe. All other
5018 * pipes' interrupts are set by amdkfd.
5024 mec_int_cntl_reg
= mmCP_ME1_PIPE0_INT_CNTL
;
5027 DRM_DEBUG("invalid pipe %d\n", pipe
);
5031 DRM_DEBUG("invalid me %d\n", me
);
5036 case AMDGPU_IRQ_STATE_DISABLE
:
5037 mec_int_cntl
= RREG32(mec_int_cntl_reg
);
5038 mec_int_cntl
&= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK
;
5039 WREG32(mec_int_cntl_reg
, mec_int_cntl
);
5041 case AMDGPU_IRQ_STATE_ENABLE
:
5042 mec_int_cntl
= RREG32(mec_int_cntl_reg
);
5043 mec_int_cntl
|= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK
;
5044 WREG32(mec_int_cntl_reg
, mec_int_cntl
);
5051 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device
*adev
,
5052 struct amdgpu_irq_src
*src
,
5054 enum amdgpu_interrupt_state state
)
5059 case AMDGPU_IRQ_STATE_DISABLE
:
5060 cp_int_cntl
= RREG32(mmCP_INT_CNTL_RING0
);
5061 cp_int_cntl
&= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK
;
5062 WREG32(mmCP_INT_CNTL_RING0
, cp_int_cntl
);
5064 case AMDGPU_IRQ_STATE_ENABLE
:
5065 cp_int_cntl
= RREG32(mmCP_INT_CNTL_RING0
);
5066 cp_int_cntl
|= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK
;
5067 WREG32(mmCP_INT_CNTL_RING0
, cp_int_cntl
);
5076 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device
*adev
,
5077 struct amdgpu_irq_src
*src
,
5079 enum amdgpu_interrupt_state state
)
5084 case AMDGPU_IRQ_STATE_DISABLE
:
5085 cp_int_cntl
= RREG32(mmCP_INT_CNTL_RING0
);
5086 cp_int_cntl
&= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK
;
5087 WREG32(mmCP_INT_CNTL_RING0
, cp_int_cntl
);
5089 case AMDGPU_IRQ_STATE_ENABLE
:
5090 cp_int_cntl
= RREG32(mmCP_INT_CNTL_RING0
);
5091 cp_int_cntl
|= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK
;
5092 WREG32(mmCP_INT_CNTL_RING0
, cp_int_cntl
);
5101 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device
*adev
,
5102 struct amdgpu_irq_src
*src
,
5104 enum amdgpu_interrupt_state state
)
5107 case AMDGPU_CP_IRQ_GFX_EOP
:
5108 gfx_v7_0_set_gfx_eop_interrupt_state(adev
, state
);
5110 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
:
5111 gfx_v7_0_set_compute_eop_interrupt_state(adev
, 1, 0, state
);
5113 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP
:
5114 gfx_v7_0_set_compute_eop_interrupt_state(adev
, 1, 1, state
);
5116 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP
:
5117 gfx_v7_0_set_compute_eop_interrupt_state(adev
, 1, 2, state
);
5119 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP
:
5120 gfx_v7_0_set_compute_eop_interrupt_state(adev
, 1, 3, state
);
5122 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP
:
5123 gfx_v7_0_set_compute_eop_interrupt_state(adev
, 2, 0, state
);
5125 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP
:
5126 gfx_v7_0_set_compute_eop_interrupt_state(adev
, 2, 1, state
);
5128 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP
:
5129 gfx_v7_0_set_compute_eop_interrupt_state(adev
, 2, 2, state
);
5131 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP
:
5132 gfx_v7_0_set_compute_eop_interrupt_state(adev
, 2, 3, state
);
5140 static int gfx_v7_0_eop_irq(struct amdgpu_device
*adev
,
5141 struct amdgpu_irq_src
*source
,
5142 struct amdgpu_iv_entry
*entry
)
5145 struct amdgpu_ring
*ring
;
5148 DRM_DEBUG("IH: CP EOP\n");
5149 me_id
= (entry
->ring_id
& 0x0c) >> 2;
5150 pipe_id
= (entry
->ring_id
& 0x03) >> 0;
5153 amdgpu_fence_process(&adev
->gfx
.gfx_ring
[0]);
5157 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++) {
5158 ring
= &adev
->gfx
.compute_ring
[i
];
5159 if ((ring
->me
== me_id
) && (ring
->pipe
== pipe_id
))
5160 amdgpu_fence_process(ring
);
5167 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device
*adev
,
5168 struct amdgpu_irq_src
*source
,
5169 struct amdgpu_iv_entry
*entry
)
5171 DRM_ERROR("Illegal register access in command stream\n");
5172 schedule_work(&adev
->reset_work
);
5176 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device
*adev
,
5177 struct amdgpu_irq_src
*source
,
5178 struct amdgpu_iv_entry
*entry
)
5180 DRM_ERROR("Illegal instruction in command stream\n");
5181 // XXX soft reset the gfx block only
5182 schedule_work(&adev
->reset_work
);
5186 static int gfx_v7_0_set_clockgating_state(void *handle
,
5187 enum amd_clockgating_state state
)
5190 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
5192 if (state
== AMD_CG_STATE_GATE
)
5195 gfx_v7_0_enable_gui_idle_interrupt(adev
, false);
5196 /* order matters! */
5198 gfx_v7_0_enable_mgcg(adev
, true);
5199 gfx_v7_0_enable_cgcg(adev
, true);
5201 gfx_v7_0_enable_cgcg(adev
, false);
5202 gfx_v7_0_enable_mgcg(adev
, false);
5204 gfx_v7_0_enable_gui_idle_interrupt(adev
, true);
5209 static int gfx_v7_0_set_powergating_state(void *handle
,
5210 enum amd_powergating_state state
)
5213 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
5215 if (state
== AMD_PG_STATE_GATE
)
5218 if (adev
->pg_flags
& (AMD_PG_SUPPORT_GFX_PG
|
5219 AMD_PG_SUPPORT_GFX_SMG
|
5220 AMD_PG_SUPPORT_GFX_DMG
|
5222 AMD_PG_SUPPORT_GDS
|
5223 AMD_PG_SUPPORT_RLC_SMU_HS
)) {
5224 gfx_v7_0_update_gfx_pg(adev
, gate
);
5225 if (adev
->pg_flags
& AMD_PG_SUPPORT_GFX_PG
) {
5226 gfx_v7_0_enable_cp_pg(adev
, gate
);
5227 gfx_v7_0_enable_gds_pg(adev
, gate
);
5234 static const struct amd_ip_funcs gfx_v7_0_ip_funcs
= {
5236 .early_init
= gfx_v7_0_early_init
,
5237 .late_init
= gfx_v7_0_late_init
,
5238 .sw_init
= gfx_v7_0_sw_init
,
5239 .sw_fini
= gfx_v7_0_sw_fini
,
5240 .hw_init
= gfx_v7_0_hw_init
,
5241 .hw_fini
= gfx_v7_0_hw_fini
,
5242 .suspend
= gfx_v7_0_suspend
,
5243 .resume
= gfx_v7_0_resume
,
5244 .is_idle
= gfx_v7_0_is_idle
,
5245 .wait_for_idle
= gfx_v7_0_wait_for_idle
,
5246 .soft_reset
= gfx_v7_0_soft_reset
,
5247 .set_clockgating_state
= gfx_v7_0_set_clockgating_state
,
5248 .set_powergating_state
= gfx_v7_0_set_powergating_state
,
5251 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx
= {
5252 .type
= AMDGPU_RING_TYPE_GFX
,
5254 .nop
= PACKET3(PACKET3_NOP
, 0x3FFF),
5255 .support_64bit_ptrs
= false,
5256 .get_rptr
= gfx_v7_0_ring_get_rptr
,
5257 .get_wptr
= gfx_v7_0_ring_get_wptr_gfx
,
5258 .set_wptr
= gfx_v7_0_ring_set_wptr_gfx
,
5260 20 + /* gfx_v7_0_ring_emit_gds_switch */
5261 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5262 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
5263 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
5264 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
5265 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
5266 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
5267 .emit_ib_size
= 4, /* gfx_v7_0_ring_emit_ib_gfx */
5268 .emit_ib
= gfx_v7_0_ring_emit_ib_gfx
,
5269 .emit_fence
= gfx_v7_0_ring_emit_fence_gfx
,
5270 .emit_pipeline_sync
= gfx_v7_0_ring_emit_pipeline_sync
,
5271 .emit_vm_flush
= gfx_v7_0_ring_emit_vm_flush
,
5272 .emit_gds_switch
= gfx_v7_0_ring_emit_gds_switch
,
5273 .emit_hdp_flush
= gfx_v7_0_ring_emit_hdp_flush
,
5274 .emit_hdp_invalidate
= gfx_v7_0_ring_emit_hdp_invalidate
,
5275 .test_ring
= gfx_v7_0_ring_test_ring
,
5276 .test_ib
= gfx_v7_0_ring_test_ib
,
5277 .insert_nop
= amdgpu_ring_insert_nop
,
5278 .pad_ib
= amdgpu_ring_generic_pad_ib
,
5279 .emit_cntxcntl
= gfx_v7_ring_emit_cntxcntl
,
5282 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute
= {
5283 .type
= AMDGPU_RING_TYPE_COMPUTE
,
5285 .nop
= PACKET3(PACKET3_NOP
, 0x3FFF),
5286 .support_64bit_ptrs
= false,
5287 .get_rptr
= gfx_v7_0_ring_get_rptr
,
5288 .get_wptr
= gfx_v7_0_ring_get_wptr_compute
,
5289 .set_wptr
= gfx_v7_0_ring_set_wptr_compute
,
5291 20 + /* gfx_v7_0_ring_emit_gds_switch */
5292 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5293 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
5294 7 + /* gfx_v7_0_ring_emit_pipeline_sync */
5295 17 + /* gfx_v7_0_ring_emit_vm_flush */
5296 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
5297 .emit_ib_size
= 4, /* gfx_v7_0_ring_emit_ib_compute */
5298 .emit_ib
= gfx_v7_0_ring_emit_ib_compute
,
5299 .emit_fence
= gfx_v7_0_ring_emit_fence_compute
,
5300 .emit_pipeline_sync
= gfx_v7_0_ring_emit_pipeline_sync
,
5301 .emit_vm_flush
= gfx_v7_0_ring_emit_vm_flush
,
5302 .emit_gds_switch
= gfx_v7_0_ring_emit_gds_switch
,
5303 .emit_hdp_flush
= gfx_v7_0_ring_emit_hdp_flush
,
5304 .emit_hdp_invalidate
= gfx_v7_0_ring_emit_hdp_invalidate
,
5305 .test_ring
= gfx_v7_0_ring_test_ring
,
5306 .test_ib
= gfx_v7_0_ring_test_ib
,
5307 .insert_nop
= amdgpu_ring_insert_nop
,
5308 .pad_ib
= amdgpu_ring_generic_pad_ib
,
5311 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device
*adev
)
5315 for (i
= 0; i
< adev
->gfx
.num_gfx_rings
; i
++)
5316 adev
->gfx
.gfx_ring
[i
].funcs
= &gfx_v7_0_ring_funcs_gfx
;
5317 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++)
5318 adev
->gfx
.compute_ring
[i
].funcs
= &gfx_v7_0_ring_funcs_compute
;
5321 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs
= {
5322 .set
= gfx_v7_0_set_eop_interrupt_state
,
5323 .process
= gfx_v7_0_eop_irq
,
5326 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs
= {
5327 .set
= gfx_v7_0_set_priv_reg_fault_state
,
5328 .process
= gfx_v7_0_priv_reg_irq
,
5331 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs
= {
5332 .set
= gfx_v7_0_set_priv_inst_fault_state
,
5333 .process
= gfx_v7_0_priv_inst_irq
,
5336 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device
*adev
)
5338 adev
->gfx
.eop_irq
.num_types
= AMDGPU_CP_IRQ_LAST
;
5339 adev
->gfx
.eop_irq
.funcs
= &gfx_v7_0_eop_irq_funcs
;
5341 adev
->gfx
.priv_reg_irq
.num_types
= 1;
5342 adev
->gfx
.priv_reg_irq
.funcs
= &gfx_v7_0_priv_reg_irq_funcs
;
5344 adev
->gfx
.priv_inst_irq
.num_types
= 1;
5345 adev
->gfx
.priv_inst_irq
.funcs
= &gfx_v7_0_priv_inst_irq_funcs
;
5348 static void gfx_v7_0_set_gds_init(struct amdgpu_device
*adev
)
5350 /* init asci gds info */
5351 adev
->gds
.mem
.total_size
= RREG32(mmGDS_VMID0_SIZE
);
5352 adev
->gds
.gws
.total_size
= 64;
5353 adev
->gds
.oa
.total_size
= 16;
5355 if (adev
->gds
.mem
.total_size
== 64 * 1024) {
5356 adev
->gds
.mem
.gfx_partition_size
= 4096;
5357 adev
->gds
.mem
.cs_partition_size
= 4096;
5359 adev
->gds
.gws
.gfx_partition_size
= 4;
5360 adev
->gds
.gws
.cs_partition_size
= 4;
5362 adev
->gds
.oa
.gfx_partition_size
= 4;
5363 adev
->gds
.oa
.cs_partition_size
= 1;
5365 adev
->gds
.mem
.gfx_partition_size
= 1024;
5366 adev
->gds
.mem
.cs_partition_size
= 1024;
5368 adev
->gds
.gws
.gfx_partition_size
= 16;
5369 adev
->gds
.gws
.cs_partition_size
= 16;
5371 adev
->gds
.oa
.gfx_partition_size
= 4;
5372 adev
->gds
.oa
.cs_partition_size
= 4;
5377 static void gfx_v7_0_get_cu_info(struct amdgpu_device
*adev
)
5379 int i
, j
, k
, counter
, active_cu_number
= 0;
5380 u32 mask
, bitmap
, ao_bitmap
, ao_cu_mask
= 0;
5381 struct amdgpu_cu_info
*cu_info
= &adev
->gfx
.cu_info
;
5382 unsigned disable_masks
[4 * 2];
5385 if (adev
->flags
& AMD_IS_APU
)
5388 ao_cu_num
= adev
->gfx
.config
.max_cu_per_sh
;
5390 memset(cu_info
, 0, sizeof(*cu_info
));
5392 amdgpu_gfx_parse_disable_cu(disable_masks
, 4, 2);
5394 mutex_lock(&adev
->grbm_idx_mutex
);
5395 for (i
= 0; i
< adev
->gfx
.config
.max_shader_engines
; i
++) {
5396 for (j
= 0; j
< adev
->gfx
.config
.max_sh_per_se
; j
++) {
5400 gfx_v7_0_select_se_sh(adev
, i
, j
, 0xffffffff);
5402 gfx_v7_0_set_user_cu_inactive_bitmap(
5403 adev
, disable_masks
[i
* 2 + j
]);
5404 bitmap
= gfx_v7_0_get_cu_active_bitmap(adev
);
5405 cu_info
->bitmap
[i
][j
] = bitmap
;
5407 for (k
= 0; k
< adev
->gfx
.config
.max_cu_per_sh
; k
++) {
5408 if (bitmap
& mask
) {
5409 if (counter
< ao_cu_num
)
5415 active_cu_number
+= counter
;
5416 ao_cu_mask
|= (ao_bitmap
<< (i
* 16 + j
* 8));
5419 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
5420 mutex_unlock(&adev
->grbm_idx_mutex
);
5422 cu_info
->number
= active_cu_number
;
5423 cu_info
->ao_cu_mask
= ao_cu_mask
;
5426 const struct amdgpu_ip_block_version gfx_v7_0_ip_block
=
5428 .type
= AMD_IP_BLOCK_TYPE_GFX
,
5432 .funcs
= &gfx_v7_0_ip_funcs
,
5435 const struct amdgpu_ip_block_version gfx_v7_1_ip_block
=
5437 .type
= AMD_IP_BLOCK_TYPE_GFX
,
5441 .funcs
= &gfx_v7_0_ip_funcs
,
5444 const struct amdgpu_ip_block_version gfx_v7_2_ip_block
=
5446 .type
= AMD_IP_BLOCK_TYPE_GFX
,
5450 .funcs
= &gfx_v7_0_ip_funcs
,
5453 const struct amdgpu_ip_block_version gfx_v7_3_ip_block
=
5455 .type
= AMD_IP_BLOCK_TYPE_GFX
,
5459 .funcs
= &gfx_v7_0_ip_funcs
,