2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
26 #include "amdgpu_ih.h"
27 #include "amdgpu_gfx.h"
30 #include "cik_structs.h"
32 #include "amdgpu_ucode.h"
33 #include "clearstate_ci.h"
35 #include "dce/dce_8_0_d.h"
36 #include "dce/dce_8_0_sh_mask.h"
38 #include "bif/bif_4_1_d.h"
39 #include "bif/bif_4_1_sh_mask.h"
41 #include "gca/gfx_7_0_d.h"
42 #include "gca/gfx_7_2_enum.h"
43 #include "gca/gfx_7_2_sh_mask.h"
45 #include "gmc/gmc_7_0_d.h"
46 #include "gmc/gmc_7_0_sh_mask.h"
48 #include "oss/oss_2_0_d.h"
49 #include "oss/oss_2_0_sh_mask.h"
51 #define GFX7_NUM_GFX_RINGS 1
52 #define GFX7_MEC_HPD_SIZE 2048
54 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device
*adev
);
55 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device
*adev
);
56 static void gfx_v7_0_set_gds_init(struct amdgpu_device
*adev
);
58 MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
59 MODULE_FIRMWARE("radeon/bonaire_me.bin");
60 MODULE_FIRMWARE("radeon/bonaire_ce.bin");
61 MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
62 MODULE_FIRMWARE("radeon/bonaire_mec.bin");
64 MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
65 MODULE_FIRMWARE("radeon/hawaii_me.bin");
66 MODULE_FIRMWARE("radeon/hawaii_ce.bin");
67 MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
68 MODULE_FIRMWARE("radeon/hawaii_mec.bin");
70 MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
71 MODULE_FIRMWARE("radeon/kaveri_me.bin");
72 MODULE_FIRMWARE("radeon/kaveri_ce.bin");
73 MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
74 MODULE_FIRMWARE("radeon/kaveri_mec.bin");
75 MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
77 MODULE_FIRMWARE("radeon/kabini_pfp.bin");
78 MODULE_FIRMWARE("radeon/kabini_me.bin");
79 MODULE_FIRMWARE("radeon/kabini_ce.bin");
80 MODULE_FIRMWARE("radeon/kabini_rlc.bin");
81 MODULE_FIRMWARE("radeon/kabini_mec.bin");
83 MODULE_FIRMWARE("radeon/mullins_pfp.bin");
84 MODULE_FIRMWARE("radeon/mullins_me.bin");
85 MODULE_FIRMWARE("radeon/mullins_ce.bin");
86 MODULE_FIRMWARE("radeon/mullins_rlc.bin");
87 MODULE_FIRMWARE("radeon/mullins_mec.bin");
89 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset
[] =
91 {mmGDS_VMID0_BASE
, mmGDS_VMID0_SIZE
, mmGDS_GWS_VMID0
, mmGDS_OA_VMID0
},
92 {mmGDS_VMID1_BASE
, mmGDS_VMID1_SIZE
, mmGDS_GWS_VMID1
, mmGDS_OA_VMID1
},
93 {mmGDS_VMID2_BASE
, mmGDS_VMID2_SIZE
, mmGDS_GWS_VMID2
, mmGDS_OA_VMID2
},
94 {mmGDS_VMID3_BASE
, mmGDS_VMID3_SIZE
, mmGDS_GWS_VMID3
, mmGDS_OA_VMID3
},
95 {mmGDS_VMID4_BASE
, mmGDS_VMID4_SIZE
, mmGDS_GWS_VMID4
, mmGDS_OA_VMID4
},
96 {mmGDS_VMID5_BASE
, mmGDS_VMID5_SIZE
, mmGDS_GWS_VMID5
, mmGDS_OA_VMID5
},
97 {mmGDS_VMID6_BASE
, mmGDS_VMID6_SIZE
, mmGDS_GWS_VMID6
, mmGDS_OA_VMID6
},
98 {mmGDS_VMID7_BASE
, mmGDS_VMID7_SIZE
, mmGDS_GWS_VMID7
, mmGDS_OA_VMID7
},
99 {mmGDS_VMID8_BASE
, mmGDS_VMID8_SIZE
, mmGDS_GWS_VMID8
, mmGDS_OA_VMID8
},
100 {mmGDS_VMID9_BASE
, mmGDS_VMID9_SIZE
, mmGDS_GWS_VMID9
, mmGDS_OA_VMID9
},
101 {mmGDS_VMID10_BASE
, mmGDS_VMID10_SIZE
, mmGDS_GWS_VMID10
, mmGDS_OA_VMID10
},
102 {mmGDS_VMID11_BASE
, mmGDS_VMID11_SIZE
, mmGDS_GWS_VMID11
, mmGDS_OA_VMID11
},
103 {mmGDS_VMID12_BASE
, mmGDS_VMID12_SIZE
, mmGDS_GWS_VMID12
, mmGDS_OA_VMID12
},
104 {mmGDS_VMID13_BASE
, mmGDS_VMID13_SIZE
, mmGDS_GWS_VMID13
, mmGDS_OA_VMID13
},
105 {mmGDS_VMID14_BASE
, mmGDS_VMID14_SIZE
, mmGDS_GWS_VMID14
, mmGDS_OA_VMID14
},
106 {mmGDS_VMID15_BASE
, mmGDS_VMID15_SIZE
, mmGDS_GWS_VMID15
, mmGDS_OA_VMID15
}
109 static const u32 spectre_rlc_save_restore_register_list
[] =
111 (0x0e00 << 16) | (0xc12c >> 2),
113 (0x0e00 << 16) | (0xc140 >> 2),
115 (0x0e00 << 16) | (0xc150 >> 2),
117 (0x0e00 << 16) | (0xc15c >> 2),
119 (0x0e00 << 16) | (0xc168 >> 2),
121 (0x0e00 << 16) | (0xc170 >> 2),
123 (0x0e00 << 16) | (0xc178 >> 2),
125 (0x0e00 << 16) | (0xc204 >> 2),
127 (0x0e00 << 16) | (0xc2b4 >> 2),
129 (0x0e00 << 16) | (0xc2b8 >> 2),
131 (0x0e00 << 16) | (0xc2bc >> 2),
133 (0x0e00 << 16) | (0xc2c0 >> 2),
135 (0x0e00 << 16) | (0x8228 >> 2),
137 (0x0e00 << 16) | (0x829c >> 2),
139 (0x0e00 << 16) | (0x869c >> 2),
141 (0x0600 << 16) | (0x98f4 >> 2),
143 (0x0e00 << 16) | (0x98f8 >> 2),
145 (0x0e00 << 16) | (0x9900 >> 2),
147 (0x0e00 << 16) | (0xc260 >> 2),
149 (0x0e00 << 16) | (0x90e8 >> 2),
151 (0x0e00 << 16) | (0x3c000 >> 2),
153 (0x0e00 << 16) | (0x3c00c >> 2),
155 (0x0e00 << 16) | (0x8c1c >> 2),
157 (0x0e00 << 16) | (0x9700 >> 2),
159 (0x0e00 << 16) | (0xcd20 >> 2),
161 (0x4e00 << 16) | (0xcd20 >> 2),
163 (0x5e00 << 16) | (0xcd20 >> 2),
165 (0x6e00 << 16) | (0xcd20 >> 2),
167 (0x7e00 << 16) | (0xcd20 >> 2),
169 (0x8e00 << 16) | (0xcd20 >> 2),
171 (0x9e00 << 16) | (0xcd20 >> 2),
173 (0xae00 << 16) | (0xcd20 >> 2),
175 (0xbe00 << 16) | (0xcd20 >> 2),
177 (0x0e00 << 16) | (0x89bc >> 2),
179 (0x0e00 << 16) | (0x8900 >> 2),
182 (0x0e00 << 16) | (0xc130 >> 2),
184 (0x0e00 << 16) | (0xc134 >> 2),
186 (0x0e00 << 16) | (0xc1fc >> 2),
188 (0x0e00 << 16) | (0xc208 >> 2),
190 (0x0e00 << 16) | (0xc264 >> 2),
192 (0x0e00 << 16) | (0xc268 >> 2),
194 (0x0e00 << 16) | (0xc26c >> 2),
196 (0x0e00 << 16) | (0xc270 >> 2),
198 (0x0e00 << 16) | (0xc274 >> 2),
200 (0x0e00 << 16) | (0xc278 >> 2),
202 (0x0e00 << 16) | (0xc27c >> 2),
204 (0x0e00 << 16) | (0xc280 >> 2),
206 (0x0e00 << 16) | (0xc284 >> 2),
208 (0x0e00 << 16) | (0xc288 >> 2),
210 (0x0e00 << 16) | (0xc28c >> 2),
212 (0x0e00 << 16) | (0xc290 >> 2),
214 (0x0e00 << 16) | (0xc294 >> 2),
216 (0x0e00 << 16) | (0xc298 >> 2),
218 (0x0e00 << 16) | (0xc29c >> 2),
220 (0x0e00 << 16) | (0xc2a0 >> 2),
222 (0x0e00 << 16) | (0xc2a4 >> 2),
224 (0x0e00 << 16) | (0xc2a8 >> 2),
226 (0x0e00 << 16) | (0xc2ac >> 2),
228 (0x0e00 << 16) | (0xc2b0 >> 2),
230 (0x0e00 << 16) | (0x301d0 >> 2),
232 (0x0e00 << 16) | (0x30238 >> 2),
234 (0x0e00 << 16) | (0x30250 >> 2),
236 (0x0e00 << 16) | (0x30254 >> 2),
238 (0x0e00 << 16) | (0x30258 >> 2),
240 (0x0e00 << 16) | (0x3025c >> 2),
242 (0x4e00 << 16) | (0xc900 >> 2),
244 (0x5e00 << 16) | (0xc900 >> 2),
246 (0x6e00 << 16) | (0xc900 >> 2),
248 (0x7e00 << 16) | (0xc900 >> 2),
250 (0x8e00 << 16) | (0xc900 >> 2),
252 (0x9e00 << 16) | (0xc900 >> 2),
254 (0xae00 << 16) | (0xc900 >> 2),
256 (0xbe00 << 16) | (0xc900 >> 2),
258 (0x4e00 << 16) | (0xc904 >> 2),
260 (0x5e00 << 16) | (0xc904 >> 2),
262 (0x6e00 << 16) | (0xc904 >> 2),
264 (0x7e00 << 16) | (0xc904 >> 2),
266 (0x8e00 << 16) | (0xc904 >> 2),
268 (0x9e00 << 16) | (0xc904 >> 2),
270 (0xae00 << 16) | (0xc904 >> 2),
272 (0xbe00 << 16) | (0xc904 >> 2),
274 (0x4e00 << 16) | (0xc908 >> 2),
276 (0x5e00 << 16) | (0xc908 >> 2),
278 (0x6e00 << 16) | (0xc908 >> 2),
280 (0x7e00 << 16) | (0xc908 >> 2),
282 (0x8e00 << 16) | (0xc908 >> 2),
284 (0x9e00 << 16) | (0xc908 >> 2),
286 (0xae00 << 16) | (0xc908 >> 2),
288 (0xbe00 << 16) | (0xc908 >> 2),
290 (0x4e00 << 16) | (0xc90c >> 2),
292 (0x5e00 << 16) | (0xc90c >> 2),
294 (0x6e00 << 16) | (0xc90c >> 2),
296 (0x7e00 << 16) | (0xc90c >> 2),
298 (0x8e00 << 16) | (0xc90c >> 2),
300 (0x9e00 << 16) | (0xc90c >> 2),
302 (0xae00 << 16) | (0xc90c >> 2),
304 (0xbe00 << 16) | (0xc90c >> 2),
306 (0x4e00 << 16) | (0xc910 >> 2),
308 (0x5e00 << 16) | (0xc910 >> 2),
310 (0x6e00 << 16) | (0xc910 >> 2),
312 (0x7e00 << 16) | (0xc910 >> 2),
314 (0x8e00 << 16) | (0xc910 >> 2),
316 (0x9e00 << 16) | (0xc910 >> 2),
318 (0xae00 << 16) | (0xc910 >> 2),
320 (0xbe00 << 16) | (0xc910 >> 2),
322 (0x0e00 << 16) | (0xc99c >> 2),
324 (0x0e00 << 16) | (0x9834 >> 2),
326 (0x0000 << 16) | (0x30f00 >> 2),
328 (0x0001 << 16) | (0x30f00 >> 2),
330 (0x0000 << 16) | (0x30f04 >> 2),
332 (0x0001 << 16) | (0x30f04 >> 2),
334 (0x0000 << 16) | (0x30f08 >> 2),
336 (0x0001 << 16) | (0x30f08 >> 2),
338 (0x0000 << 16) | (0x30f0c >> 2),
340 (0x0001 << 16) | (0x30f0c >> 2),
342 (0x0600 << 16) | (0x9b7c >> 2),
344 (0x0e00 << 16) | (0x8a14 >> 2),
346 (0x0e00 << 16) | (0x8a18 >> 2),
348 (0x0600 << 16) | (0x30a00 >> 2),
350 (0x0e00 << 16) | (0x8bf0 >> 2),
352 (0x0e00 << 16) | (0x8bcc >> 2),
354 (0x0e00 << 16) | (0x8b24 >> 2),
356 (0x0e00 << 16) | (0x30a04 >> 2),
358 (0x0600 << 16) | (0x30a10 >> 2),
360 (0x0600 << 16) | (0x30a14 >> 2),
362 (0x0600 << 16) | (0x30a18 >> 2),
364 (0x0600 << 16) | (0x30a2c >> 2),
366 (0x0e00 << 16) | (0xc700 >> 2),
368 (0x0e00 << 16) | (0xc704 >> 2),
370 (0x0e00 << 16) | (0xc708 >> 2),
372 (0x0e00 << 16) | (0xc768 >> 2),
374 (0x0400 << 16) | (0xc770 >> 2),
376 (0x0400 << 16) | (0xc774 >> 2),
378 (0x0400 << 16) | (0xc778 >> 2),
380 (0x0400 << 16) | (0xc77c >> 2),
382 (0x0400 << 16) | (0xc780 >> 2),
384 (0x0400 << 16) | (0xc784 >> 2),
386 (0x0400 << 16) | (0xc788 >> 2),
388 (0x0400 << 16) | (0xc78c >> 2),
390 (0x0400 << 16) | (0xc798 >> 2),
392 (0x0400 << 16) | (0xc79c >> 2),
394 (0x0400 << 16) | (0xc7a0 >> 2),
396 (0x0400 << 16) | (0xc7a4 >> 2),
398 (0x0400 << 16) | (0xc7a8 >> 2),
400 (0x0400 << 16) | (0xc7ac >> 2),
402 (0x0400 << 16) | (0xc7b0 >> 2),
404 (0x0400 << 16) | (0xc7b4 >> 2),
406 (0x0e00 << 16) | (0x9100 >> 2),
408 (0x0e00 << 16) | (0x3c010 >> 2),
410 (0x0e00 << 16) | (0x92a8 >> 2),
412 (0x0e00 << 16) | (0x92ac >> 2),
414 (0x0e00 << 16) | (0x92b4 >> 2),
416 (0x0e00 << 16) | (0x92b8 >> 2),
418 (0x0e00 << 16) | (0x92bc >> 2),
420 (0x0e00 << 16) | (0x92c0 >> 2),
422 (0x0e00 << 16) | (0x92c4 >> 2),
424 (0x0e00 << 16) | (0x92c8 >> 2),
426 (0x0e00 << 16) | (0x92cc >> 2),
428 (0x0e00 << 16) | (0x92d0 >> 2),
430 (0x0e00 << 16) | (0x8c00 >> 2),
432 (0x0e00 << 16) | (0x8c04 >> 2),
434 (0x0e00 << 16) | (0x8c20 >> 2),
436 (0x0e00 << 16) | (0x8c38 >> 2),
438 (0x0e00 << 16) | (0x8c3c >> 2),
440 (0x0e00 << 16) | (0xae00 >> 2),
442 (0x0e00 << 16) | (0x9604 >> 2),
444 (0x0e00 << 16) | (0xac08 >> 2),
446 (0x0e00 << 16) | (0xac0c >> 2),
448 (0x0e00 << 16) | (0xac10 >> 2),
450 (0x0e00 << 16) | (0xac14 >> 2),
452 (0x0e00 << 16) | (0xac58 >> 2),
454 (0x0e00 << 16) | (0xac68 >> 2),
456 (0x0e00 << 16) | (0xac6c >> 2),
458 (0x0e00 << 16) | (0xac70 >> 2),
460 (0x0e00 << 16) | (0xac74 >> 2),
462 (0x0e00 << 16) | (0xac78 >> 2),
464 (0x0e00 << 16) | (0xac7c >> 2),
466 (0x0e00 << 16) | (0xac80 >> 2),
468 (0x0e00 << 16) | (0xac84 >> 2),
470 (0x0e00 << 16) | (0xac88 >> 2),
472 (0x0e00 << 16) | (0xac8c >> 2),
474 (0x0e00 << 16) | (0x970c >> 2),
476 (0x0e00 << 16) | (0x9714 >> 2),
478 (0x0e00 << 16) | (0x9718 >> 2),
480 (0x0e00 << 16) | (0x971c >> 2),
482 (0x0e00 << 16) | (0x31068 >> 2),
484 (0x4e00 << 16) | (0x31068 >> 2),
486 (0x5e00 << 16) | (0x31068 >> 2),
488 (0x6e00 << 16) | (0x31068 >> 2),
490 (0x7e00 << 16) | (0x31068 >> 2),
492 (0x8e00 << 16) | (0x31068 >> 2),
494 (0x9e00 << 16) | (0x31068 >> 2),
496 (0xae00 << 16) | (0x31068 >> 2),
498 (0xbe00 << 16) | (0x31068 >> 2),
500 (0x0e00 << 16) | (0xcd10 >> 2),
502 (0x0e00 << 16) | (0xcd14 >> 2),
504 (0x0e00 << 16) | (0x88b0 >> 2),
506 (0x0e00 << 16) | (0x88b4 >> 2),
508 (0x0e00 << 16) | (0x88b8 >> 2),
510 (0x0e00 << 16) | (0x88bc >> 2),
512 (0x0400 << 16) | (0x89c0 >> 2),
514 (0x0e00 << 16) | (0x88c4 >> 2),
516 (0x0e00 << 16) | (0x88c8 >> 2),
518 (0x0e00 << 16) | (0x88d0 >> 2),
520 (0x0e00 << 16) | (0x88d4 >> 2),
522 (0x0e00 << 16) | (0x88d8 >> 2),
524 (0x0e00 << 16) | (0x8980 >> 2),
526 (0x0e00 << 16) | (0x30938 >> 2),
528 (0x0e00 << 16) | (0x3093c >> 2),
530 (0x0e00 << 16) | (0x30940 >> 2),
532 (0x0e00 << 16) | (0x89a0 >> 2),
534 (0x0e00 << 16) | (0x30900 >> 2),
536 (0x0e00 << 16) | (0x30904 >> 2),
538 (0x0e00 << 16) | (0x89b4 >> 2),
540 (0x0e00 << 16) | (0x3c210 >> 2),
542 (0x0e00 << 16) | (0x3c214 >> 2),
544 (0x0e00 << 16) | (0x3c218 >> 2),
546 (0x0e00 << 16) | (0x8904 >> 2),
549 (0x0e00 << 16) | (0x8c28 >> 2),
550 (0x0e00 << 16) | (0x8c2c >> 2),
551 (0x0e00 << 16) | (0x8c30 >> 2),
552 (0x0e00 << 16) | (0x8c34 >> 2),
553 (0x0e00 << 16) | (0x9600 >> 2),
556 static const u32 kalindi_rlc_save_restore_register_list
[] =
558 (0x0e00 << 16) | (0xc12c >> 2),
560 (0x0e00 << 16) | (0xc140 >> 2),
562 (0x0e00 << 16) | (0xc150 >> 2),
564 (0x0e00 << 16) | (0xc15c >> 2),
566 (0x0e00 << 16) | (0xc168 >> 2),
568 (0x0e00 << 16) | (0xc170 >> 2),
570 (0x0e00 << 16) | (0xc204 >> 2),
572 (0x0e00 << 16) | (0xc2b4 >> 2),
574 (0x0e00 << 16) | (0xc2b8 >> 2),
576 (0x0e00 << 16) | (0xc2bc >> 2),
578 (0x0e00 << 16) | (0xc2c0 >> 2),
580 (0x0e00 << 16) | (0x8228 >> 2),
582 (0x0e00 << 16) | (0x829c >> 2),
584 (0x0e00 << 16) | (0x869c >> 2),
586 (0x0600 << 16) | (0x98f4 >> 2),
588 (0x0e00 << 16) | (0x98f8 >> 2),
590 (0x0e00 << 16) | (0x9900 >> 2),
592 (0x0e00 << 16) | (0xc260 >> 2),
594 (0x0e00 << 16) | (0x90e8 >> 2),
596 (0x0e00 << 16) | (0x3c000 >> 2),
598 (0x0e00 << 16) | (0x3c00c >> 2),
600 (0x0e00 << 16) | (0x8c1c >> 2),
602 (0x0e00 << 16) | (0x9700 >> 2),
604 (0x0e00 << 16) | (0xcd20 >> 2),
606 (0x4e00 << 16) | (0xcd20 >> 2),
608 (0x5e00 << 16) | (0xcd20 >> 2),
610 (0x6e00 << 16) | (0xcd20 >> 2),
612 (0x7e00 << 16) | (0xcd20 >> 2),
614 (0x0e00 << 16) | (0x89bc >> 2),
616 (0x0e00 << 16) | (0x8900 >> 2),
619 (0x0e00 << 16) | (0xc130 >> 2),
621 (0x0e00 << 16) | (0xc134 >> 2),
623 (0x0e00 << 16) | (0xc1fc >> 2),
625 (0x0e00 << 16) | (0xc208 >> 2),
627 (0x0e00 << 16) | (0xc264 >> 2),
629 (0x0e00 << 16) | (0xc268 >> 2),
631 (0x0e00 << 16) | (0xc26c >> 2),
633 (0x0e00 << 16) | (0xc270 >> 2),
635 (0x0e00 << 16) | (0xc274 >> 2),
637 (0x0e00 << 16) | (0xc28c >> 2),
639 (0x0e00 << 16) | (0xc290 >> 2),
641 (0x0e00 << 16) | (0xc294 >> 2),
643 (0x0e00 << 16) | (0xc298 >> 2),
645 (0x0e00 << 16) | (0xc2a0 >> 2),
647 (0x0e00 << 16) | (0xc2a4 >> 2),
649 (0x0e00 << 16) | (0xc2a8 >> 2),
651 (0x0e00 << 16) | (0xc2ac >> 2),
653 (0x0e00 << 16) | (0x301d0 >> 2),
655 (0x0e00 << 16) | (0x30238 >> 2),
657 (0x0e00 << 16) | (0x30250 >> 2),
659 (0x0e00 << 16) | (0x30254 >> 2),
661 (0x0e00 << 16) | (0x30258 >> 2),
663 (0x0e00 << 16) | (0x3025c >> 2),
665 (0x4e00 << 16) | (0xc900 >> 2),
667 (0x5e00 << 16) | (0xc900 >> 2),
669 (0x6e00 << 16) | (0xc900 >> 2),
671 (0x7e00 << 16) | (0xc900 >> 2),
673 (0x4e00 << 16) | (0xc904 >> 2),
675 (0x5e00 << 16) | (0xc904 >> 2),
677 (0x6e00 << 16) | (0xc904 >> 2),
679 (0x7e00 << 16) | (0xc904 >> 2),
681 (0x4e00 << 16) | (0xc908 >> 2),
683 (0x5e00 << 16) | (0xc908 >> 2),
685 (0x6e00 << 16) | (0xc908 >> 2),
687 (0x7e00 << 16) | (0xc908 >> 2),
689 (0x4e00 << 16) | (0xc90c >> 2),
691 (0x5e00 << 16) | (0xc90c >> 2),
693 (0x6e00 << 16) | (0xc90c >> 2),
695 (0x7e00 << 16) | (0xc90c >> 2),
697 (0x4e00 << 16) | (0xc910 >> 2),
699 (0x5e00 << 16) | (0xc910 >> 2),
701 (0x6e00 << 16) | (0xc910 >> 2),
703 (0x7e00 << 16) | (0xc910 >> 2),
705 (0x0e00 << 16) | (0xc99c >> 2),
707 (0x0e00 << 16) | (0x9834 >> 2),
709 (0x0000 << 16) | (0x30f00 >> 2),
711 (0x0000 << 16) | (0x30f04 >> 2),
713 (0x0000 << 16) | (0x30f08 >> 2),
715 (0x0000 << 16) | (0x30f0c >> 2),
717 (0x0600 << 16) | (0x9b7c >> 2),
719 (0x0e00 << 16) | (0x8a14 >> 2),
721 (0x0e00 << 16) | (0x8a18 >> 2),
723 (0x0600 << 16) | (0x30a00 >> 2),
725 (0x0e00 << 16) | (0x8bf0 >> 2),
727 (0x0e00 << 16) | (0x8bcc >> 2),
729 (0x0e00 << 16) | (0x8b24 >> 2),
731 (0x0e00 << 16) | (0x30a04 >> 2),
733 (0x0600 << 16) | (0x30a10 >> 2),
735 (0x0600 << 16) | (0x30a14 >> 2),
737 (0x0600 << 16) | (0x30a18 >> 2),
739 (0x0600 << 16) | (0x30a2c >> 2),
741 (0x0e00 << 16) | (0xc700 >> 2),
743 (0x0e00 << 16) | (0xc704 >> 2),
745 (0x0e00 << 16) | (0xc708 >> 2),
747 (0x0e00 << 16) | (0xc768 >> 2),
749 (0x0400 << 16) | (0xc770 >> 2),
751 (0x0400 << 16) | (0xc774 >> 2),
753 (0x0400 << 16) | (0xc798 >> 2),
755 (0x0400 << 16) | (0xc79c >> 2),
757 (0x0e00 << 16) | (0x9100 >> 2),
759 (0x0e00 << 16) | (0x3c010 >> 2),
761 (0x0e00 << 16) | (0x8c00 >> 2),
763 (0x0e00 << 16) | (0x8c04 >> 2),
765 (0x0e00 << 16) | (0x8c20 >> 2),
767 (0x0e00 << 16) | (0x8c38 >> 2),
769 (0x0e00 << 16) | (0x8c3c >> 2),
771 (0x0e00 << 16) | (0xae00 >> 2),
773 (0x0e00 << 16) | (0x9604 >> 2),
775 (0x0e00 << 16) | (0xac08 >> 2),
777 (0x0e00 << 16) | (0xac0c >> 2),
779 (0x0e00 << 16) | (0xac10 >> 2),
781 (0x0e00 << 16) | (0xac14 >> 2),
783 (0x0e00 << 16) | (0xac58 >> 2),
785 (0x0e00 << 16) | (0xac68 >> 2),
787 (0x0e00 << 16) | (0xac6c >> 2),
789 (0x0e00 << 16) | (0xac70 >> 2),
791 (0x0e00 << 16) | (0xac74 >> 2),
793 (0x0e00 << 16) | (0xac78 >> 2),
795 (0x0e00 << 16) | (0xac7c >> 2),
797 (0x0e00 << 16) | (0xac80 >> 2),
799 (0x0e00 << 16) | (0xac84 >> 2),
801 (0x0e00 << 16) | (0xac88 >> 2),
803 (0x0e00 << 16) | (0xac8c >> 2),
805 (0x0e00 << 16) | (0x970c >> 2),
807 (0x0e00 << 16) | (0x9714 >> 2),
809 (0x0e00 << 16) | (0x9718 >> 2),
811 (0x0e00 << 16) | (0x971c >> 2),
813 (0x0e00 << 16) | (0x31068 >> 2),
815 (0x4e00 << 16) | (0x31068 >> 2),
817 (0x5e00 << 16) | (0x31068 >> 2),
819 (0x6e00 << 16) | (0x31068 >> 2),
821 (0x7e00 << 16) | (0x31068 >> 2),
823 (0x0e00 << 16) | (0xcd10 >> 2),
825 (0x0e00 << 16) | (0xcd14 >> 2),
827 (0x0e00 << 16) | (0x88b0 >> 2),
829 (0x0e00 << 16) | (0x88b4 >> 2),
831 (0x0e00 << 16) | (0x88b8 >> 2),
833 (0x0e00 << 16) | (0x88bc >> 2),
835 (0x0400 << 16) | (0x89c0 >> 2),
837 (0x0e00 << 16) | (0x88c4 >> 2),
839 (0x0e00 << 16) | (0x88c8 >> 2),
841 (0x0e00 << 16) | (0x88d0 >> 2),
843 (0x0e00 << 16) | (0x88d4 >> 2),
845 (0x0e00 << 16) | (0x88d8 >> 2),
847 (0x0e00 << 16) | (0x8980 >> 2),
849 (0x0e00 << 16) | (0x30938 >> 2),
851 (0x0e00 << 16) | (0x3093c >> 2),
853 (0x0e00 << 16) | (0x30940 >> 2),
855 (0x0e00 << 16) | (0x89a0 >> 2),
857 (0x0e00 << 16) | (0x30900 >> 2),
859 (0x0e00 << 16) | (0x30904 >> 2),
861 (0x0e00 << 16) | (0x89b4 >> 2),
863 (0x0e00 << 16) | (0x3e1fc >> 2),
865 (0x0e00 << 16) | (0x3c210 >> 2),
867 (0x0e00 << 16) | (0x3c214 >> 2),
869 (0x0e00 << 16) | (0x3c218 >> 2),
871 (0x0e00 << 16) | (0x8904 >> 2),
874 (0x0e00 << 16) | (0x8c28 >> 2),
875 (0x0e00 << 16) | (0x8c2c >> 2),
876 (0x0e00 << 16) | (0x8c30 >> 2),
877 (0x0e00 << 16) | (0x8c34 >> 2),
878 (0x0e00 << 16) | (0x9600 >> 2),
881 static u32
gfx_v7_0_get_csb_size(struct amdgpu_device
*adev
);
882 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device
*adev
, volatile u32
*buffer
);
883 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device
*adev
);
884 static void gfx_v7_0_init_pg(struct amdgpu_device
*adev
);
885 static void gfx_v7_0_get_cu_info(struct amdgpu_device
*adev
);
891 * gfx_v7_0_init_microcode - load ucode images from disk
893 * @adev: amdgpu_device pointer
895 * Use the firmware interface to load the ucode images into
896 * the driver (not loaded into hw).
897 * Returns 0 on success, error on failure.
899 static int gfx_v7_0_init_microcode(struct amdgpu_device
*adev
)
901 const char *chip_name
;
907 switch (adev
->asic_type
) {
909 chip_name
= "bonaire";
912 chip_name
= "hawaii";
915 chip_name
= "kaveri";
918 chip_name
= "kabini";
921 chip_name
= "mullins";
926 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_pfp.bin", chip_name
);
927 err
= request_firmware(&adev
->gfx
.pfp_fw
, fw_name
, adev
->dev
);
930 err
= amdgpu_ucode_validate(adev
->gfx
.pfp_fw
);
934 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_me.bin", chip_name
);
935 err
= request_firmware(&adev
->gfx
.me_fw
, fw_name
, adev
->dev
);
938 err
= amdgpu_ucode_validate(adev
->gfx
.me_fw
);
942 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_ce.bin", chip_name
);
943 err
= request_firmware(&adev
->gfx
.ce_fw
, fw_name
, adev
->dev
);
946 err
= amdgpu_ucode_validate(adev
->gfx
.ce_fw
);
950 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_mec.bin", chip_name
);
951 err
= request_firmware(&adev
->gfx
.mec_fw
, fw_name
, adev
->dev
);
954 err
= amdgpu_ucode_validate(adev
->gfx
.mec_fw
);
958 if (adev
->asic_type
== CHIP_KAVERI
) {
959 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_mec2.bin", chip_name
);
960 err
= request_firmware(&adev
->gfx
.mec2_fw
, fw_name
, adev
->dev
);
963 err
= amdgpu_ucode_validate(adev
->gfx
.mec2_fw
);
968 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_rlc.bin", chip_name
);
969 err
= request_firmware(&adev
->gfx
.rlc_fw
, fw_name
, adev
->dev
);
972 err
= amdgpu_ucode_validate(adev
->gfx
.rlc_fw
);
976 pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name
);
977 release_firmware(adev
->gfx
.pfp_fw
);
978 adev
->gfx
.pfp_fw
= NULL
;
979 release_firmware(adev
->gfx
.me_fw
);
980 adev
->gfx
.me_fw
= NULL
;
981 release_firmware(adev
->gfx
.ce_fw
);
982 adev
->gfx
.ce_fw
= NULL
;
983 release_firmware(adev
->gfx
.mec_fw
);
984 adev
->gfx
.mec_fw
= NULL
;
985 release_firmware(adev
->gfx
.mec2_fw
);
986 adev
->gfx
.mec2_fw
= NULL
;
987 release_firmware(adev
->gfx
.rlc_fw
);
988 adev
->gfx
.rlc_fw
= NULL
;
993 static void gfx_v7_0_free_microcode(struct amdgpu_device
*adev
)
995 release_firmware(adev
->gfx
.pfp_fw
);
996 adev
->gfx
.pfp_fw
= NULL
;
997 release_firmware(adev
->gfx
.me_fw
);
998 adev
->gfx
.me_fw
= NULL
;
999 release_firmware(adev
->gfx
.ce_fw
);
1000 adev
->gfx
.ce_fw
= NULL
;
1001 release_firmware(adev
->gfx
.mec_fw
);
1002 adev
->gfx
.mec_fw
= NULL
;
1003 release_firmware(adev
->gfx
.mec2_fw
);
1004 adev
->gfx
.mec2_fw
= NULL
;
1005 release_firmware(adev
->gfx
.rlc_fw
);
1006 adev
->gfx
.rlc_fw
= NULL
;
1010 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
1012 * @adev: amdgpu_device pointer
1014 * Starting with SI, the tiling setup is done globally in a
1015 * set of 32 tiling modes. Rather than selecting each set of
1016 * parameters per surface as on older asics, we just select
1017 * which index in the tiling table we want to use, and the
1018 * surface uses those parameters (CIK).
1020 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device
*adev
)
1022 const u32 num_tile_mode_states
=
1023 ARRAY_SIZE(adev
->gfx
.config
.tile_mode_array
);
1024 const u32 num_secondary_tile_mode_states
=
1025 ARRAY_SIZE(adev
->gfx
.config
.macrotile_mode_array
);
1026 u32 reg_offset
, split_equal_to_row_size
;
1027 uint32_t *tile
, *macrotile
;
1029 tile
= adev
->gfx
.config
.tile_mode_array
;
1030 macrotile
= adev
->gfx
.config
.macrotile_mode_array
;
1032 switch (adev
->gfx
.config
.mem_row_size_in_kb
) {
1034 split_equal_to_row_size
= ADDR_SURF_TILE_SPLIT_1KB
;
1038 split_equal_to_row_size
= ADDR_SURF_TILE_SPLIT_2KB
;
1041 split_equal_to_row_size
= ADDR_SURF_TILE_SPLIT_4KB
;
1045 for (reg_offset
= 0; reg_offset
< num_tile_mode_states
; reg_offset
++)
1046 tile
[reg_offset
] = 0;
1047 for (reg_offset
= 0; reg_offset
< num_secondary_tile_mode_states
; reg_offset
++)
1048 macrotile
[reg_offset
] = 0;
1050 switch (adev
->asic_type
) {
1052 tile
[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1053 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1054 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B
) |
1055 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1056 tile
[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1057 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1058 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B
) |
1059 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1060 tile
[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1061 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1062 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1063 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1064 tile
[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1065 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1066 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B
) |
1067 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1068 tile
[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1069 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1070 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
) |
1071 TILE_SPLIT(split_equal_to_row_size
));
1072 tile
[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1073 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1074 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1075 tile
[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1076 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1077 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
) |
1078 TILE_SPLIT(split_equal_to_row_size
));
1079 tile
[7] = (TILE_SPLIT(split_equal_to_row_size
));
1080 tile
[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED
) |
1081 PIPE_CONFIG(ADDR_SURF_P4_16x16
));
1082 tile
[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1083 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1084 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
));
1085 tile
[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1086 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1087 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1088 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1089 tile
[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1090 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1091 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1092 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1093 tile
[12] = (TILE_SPLIT(split_equal_to_row_size
));
1094 tile
[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1095 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1096 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
));
1097 tile
[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1098 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1099 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1100 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1101 tile
[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1
) |
1102 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1103 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1104 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1105 tile
[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1106 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1107 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1108 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1109 tile
[17] = (TILE_SPLIT(split_equal_to_row_size
));
1110 tile
[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK
) |
1111 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1112 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1113 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1114 tile
[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK
) |
1115 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1116 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
));
1117 tile
[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK
) |
1118 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1119 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1120 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1121 tile
[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK
) |
1122 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1123 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1124 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1125 tile
[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK
) |
1126 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1127 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1128 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1129 tile
[23] = (TILE_SPLIT(split_equal_to_row_size
));
1130 tile
[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK
) |
1131 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1132 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1133 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1134 tile
[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK
) |
1135 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1136 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1137 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1138 tile
[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK
) |
1139 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1140 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1141 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1142 tile
[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1143 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1144 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
));
1145 tile
[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1146 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1147 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
) |
1148 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1149 tile
[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1150 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1151 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
) |
1152 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1153 tile
[30] = (TILE_SPLIT(split_equal_to_row_size
));
1155 macrotile
[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1156 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1157 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1158 NUM_BANKS(ADDR_SURF_16_BANK
));
1159 macrotile
[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1160 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1161 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1162 NUM_BANKS(ADDR_SURF_16_BANK
));
1163 macrotile
[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1164 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1165 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1166 NUM_BANKS(ADDR_SURF_16_BANK
));
1167 macrotile
[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1168 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1169 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1170 NUM_BANKS(ADDR_SURF_16_BANK
));
1171 macrotile
[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1172 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1173 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1174 NUM_BANKS(ADDR_SURF_16_BANK
));
1175 macrotile
[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1176 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1177 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1178 NUM_BANKS(ADDR_SURF_8_BANK
));
1179 macrotile
[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1180 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1181 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1182 NUM_BANKS(ADDR_SURF_4_BANK
));
1183 macrotile
[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2
) |
1184 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8
) |
1185 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1186 NUM_BANKS(ADDR_SURF_16_BANK
));
1187 macrotile
[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2
) |
1188 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1189 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1190 NUM_BANKS(ADDR_SURF_16_BANK
));
1191 macrotile
[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1192 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1193 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1194 NUM_BANKS(ADDR_SURF_16_BANK
));
1195 macrotile
[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1196 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1197 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1198 NUM_BANKS(ADDR_SURF_16_BANK
));
1199 macrotile
[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1200 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1201 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1202 NUM_BANKS(ADDR_SURF_16_BANK
));
1203 macrotile
[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1204 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1205 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1206 NUM_BANKS(ADDR_SURF_8_BANK
));
1207 macrotile
[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1208 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1209 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1210 NUM_BANKS(ADDR_SURF_4_BANK
));
1212 for (reg_offset
= 0; reg_offset
< num_tile_mode_states
; reg_offset
++)
1213 WREG32(mmGB_TILE_MODE0
+ reg_offset
, tile
[reg_offset
]);
1214 for (reg_offset
= 0; reg_offset
< num_secondary_tile_mode_states
; reg_offset
++)
1215 if (reg_offset
!= 7)
1216 WREG32(mmGB_MACROTILE_MODE0
+ reg_offset
, macrotile
[reg_offset
]);
1219 tile
[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1220 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1221 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B
) |
1222 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1223 tile
[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1224 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1225 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B
) |
1226 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1227 tile
[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1228 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1229 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1230 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1231 tile
[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1232 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1233 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B
) |
1234 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1235 tile
[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1236 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1237 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
) |
1238 TILE_SPLIT(split_equal_to_row_size
));
1239 tile
[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1240 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1241 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
) |
1242 TILE_SPLIT(split_equal_to_row_size
));
1243 tile
[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1244 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1245 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
) |
1246 TILE_SPLIT(split_equal_to_row_size
));
1247 tile
[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1248 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1249 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
) |
1250 TILE_SPLIT(split_equal_to_row_size
));
1251 tile
[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED
) |
1252 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
));
1253 tile
[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1254 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1255 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
));
1256 tile
[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1257 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1258 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1259 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1260 tile
[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1261 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1262 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1263 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1264 tile
[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1
) |
1265 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1266 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1267 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1268 tile
[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1269 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1270 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
));
1271 tile
[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1272 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1273 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1274 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1275 tile
[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1
) |
1276 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1277 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1278 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1279 tile
[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1280 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1281 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1282 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1283 tile
[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1284 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1285 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1286 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1287 tile
[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK
) |
1288 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1289 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1290 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1291 tile
[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK
) |
1292 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1293 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
));
1294 tile
[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK
) |
1295 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1296 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1297 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1298 tile
[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK
) |
1299 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1300 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1301 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1302 tile
[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK
) |
1303 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1304 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1305 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1306 tile
[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK
) |
1307 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1308 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1309 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1310 tile
[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK
) |
1311 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1312 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1313 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1314 tile
[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK
) |
1315 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1316 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1317 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1318 tile
[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK
) |
1319 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1320 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1321 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1322 tile
[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1323 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1324 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
));
1325 tile
[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1326 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1327 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
) |
1328 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1329 tile
[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1330 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16
) |
1331 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
) |
1332 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1333 tile
[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1334 PIPE_CONFIG(ADDR_SURF_P4_16x16
) |
1335 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
) |
1336 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1338 macrotile
[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1339 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1340 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1341 NUM_BANKS(ADDR_SURF_16_BANK
));
1342 macrotile
[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1343 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1344 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1345 NUM_BANKS(ADDR_SURF_16_BANK
));
1346 macrotile
[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1347 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1348 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1349 NUM_BANKS(ADDR_SURF_16_BANK
));
1350 macrotile
[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1351 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1352 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1353 NUM_BANKS(ADDR_SURF_16_BANK
));
1354 macrotile
[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1355 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1356 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1357 NUM_BANKS(ADDR_SURF_8_BANK
));
1358 macrotile
[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1359 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1360 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1361 NUM_BANKS(ADDR_SURF_4_BANK
));
1362 macrotile
[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1363 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1364 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1365 NUM_BANKS(ADDR_SURF_4_BANK
));
1366 macrotile
[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1367 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1368 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1369 NUM_BANKS(ADDR_SURF_16_BANK
));
1370 macrotile
[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1371 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1372 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1373 NUM_BANKS(ADDR_SURF_16_BANK
));
1374 macrotile
[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1375 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1376 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1377 NUM_BANKS(ADDR_SURF_16_BANK
));
1378 macrotile
[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1379 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1380 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1381 NUM_BANKS(ADDR_SURF_8_BANK
));
1382 macrotile
[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1383 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1384 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1385 NUM_BANKS(ADDR_SURF_16_BANK
));
1386 macrotile
[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1387 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1388 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1389 NUM_BANKS(ADDR_SURF_8_BANK
));
1390 macrotile
[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1391 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1392 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
) |
1393 NUM_BANKS(ADDR_SURF_4_BANK
));
1395 for (reg_offset
= 0; reg_offset
< num_tile_mode_states
; reg_offset
++)
1396 WREG32(mmGB_TILE_MODE0
+ reg_offset
, tile
[reg_offset
]);
1397 for (reg_offset
= 0; reg_offset
< num_secondary_tile_mode_states
; reg_offset
++)
1398 if (reg_offset
!= 7)
1399 WREG32(mmGB_MACROTILE_MODE0
+ reg_offset
, macrotile
[reg_offset
]);
1405 tile
[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1406 PIPE_CONFIG(ADDR_SURF_P2
) |
1407 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B
) |
1408 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1409 tile
[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1410 PIPE_CONFIG(ADDR_SURF_P2
) |
1411 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B
) |
1412 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1413 tile
[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1414 PIPE_CONFIG(ADDR_SURF_P2
) |
1415 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1416 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1417 tile
[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1418 PIPE_CONFIG(ADDR_SURF_P2
) |
1419 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B
) |
1420 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1421 tile
[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1422 PIPE_CONFIG(ADDR_SURF_P2
) |
1423 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
) |
1424 TILE_SPLIT(split_equal_to_row_size
));
1425 tile
[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1426 PIPE_CONFIG(ADDR_SURF_P2
) |
1427 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
));
1428 tile
[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1429 PIPE_CONFIG(ADDR_SURF_P2
) |
1430 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING
) |
1431 TILE_SPLIT(split_equal_to_row_size
));
1432 tile
[7] = (TILE_SPLIT(split_equal_to_row_size
));
1433 tile
[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED
) |
1434 PIPE_CONFIG(ADDR_SURF_P2
));
1435 tile
[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1436 PIPE_CONFIG(ADDR_SURF_P2
) |
1437 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
));
1438 tile
[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1439 PIPE_CONFIG(ADDR_SURF_P2
) |
1440 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1441 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1442 tile
[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1443 PIPE_CONFIG(ADDR_SURF_P2
) |
1444 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1445 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1446 tile
[12] = (TILE_SPLIT(split_equal_to_row_size
));
1447 tile
[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1448 PIPE_CONFIG(ADDR_SURF_P2
) |
1449 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
));
1450 tile
[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1451 PIPE_CONFIG(ADDR_SURF_P2
) |
1452 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1453 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1454 tile
[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1
) |
1455 PIPE_CONFIG(ADDR_SURF_P2
) |
1456 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1457 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1458 tile
[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1459 PIPE_CONFIG(ADDR_SURF_P2
) |
1460 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1461 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1462 tile
[17] = (TILE_SPLIT(split_equal_to_row_size
));
1463 tile
[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK
) |
1464 PIPE_CONFIG(ADDR_SURF_P2
) |
1465 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1466 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1467 tile
[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK
) |
1468 PIPE_CONFIG(ADDR_SURF_P2
) |
1469 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
));
1470 tile
[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK
) |
1471 PIPE_CONFIG(ADDR_SURF_P2
) |
1472 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1473 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1474 tile
[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK
) |
1475 PIPE_CONFIG(ADDR_SURF_P2
) |
1476 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1477 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1478 tile
[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK
) |
1479 PIPE_CONFIG(ADDR_SURF_P2
) |
1480 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1481 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1482 tile
[23] = (TILE_SPLIT(split_equal_to_row_size
));
1483 tile
[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK
) |
1484 PIPE_CONFIG(ADDR_SURF_P2
) |
1485 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING
) |
1486 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1487 tile
[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK
) |
1488 PIPE_CONFIG(ADDR_SURF_P2
) |
1489 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1490 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1491 tile
[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK
) |
1492 PIPE_CONFIG(ADDR_SURF_P2
) |
1493 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING
) |
1494 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1
));
1495 tile
[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1496 PIPE_CONFIG(ADDR_SURF_P2
) |
1497 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
));
1498 tile
[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1499 PIPE_CONFIG(ADDR_SURF_P2
) |
1500 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
) |
1501 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2
));
1502 tile
[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1
) |
1503 PIPE_CONFIG(ADDR_SURF_P2
) |
1504 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING
) |
1505 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8
));
1506 tile
[30] = (TILE_SPLIT(split_equal_to_row_size
));
1508 macrotile
[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1509 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1510 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1511 NUM_BANKS(ADDR_SURF_8_BANK
));
1512 macrotile
[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1513 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1514 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1515 NUM_BANKS(ADDR_SURF_8_BANK
));
1516 macrotile
[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1517 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1518 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1519 NUM_BANKS(ADDR_SURF_8_BANK
));
1520 macrotile
[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1521 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1522 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1523 NUM_BANKS(ADDR_SURF_8_BANK
));
1524 macrotile
[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1525 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1526 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1527 NUM_BANKS(ADDR_SURF_8_BANK
));
1528 macrotile
[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1529 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1530 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1531 NUM_BANKS(ADDR_SURF_8_BANK
));
1532 macrotile
[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1533 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1534 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1535 NUM_BANKS(ADDR_SURF_8_BANK
));
1536 macrotile
[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4
) |
1537 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8
) |
1538 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1539 NUM_BANKS(ADDR_SURF_16_BANK
));
1540 macrotile
[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4
) |
1541 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1542 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1543 NUM_BANKS(ADDR_SURF_16_BANK
));
1544 macrotile
[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2
) |
1545 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1546 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1547 NUM_BANKS(ADDR_SURF_16_BANK
));
1548 macrotile
[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2
) |
1549 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1550 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1551 NUM_BANKS(ADDR_SURF_16_BANK
));
1552 macrotile
[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1553 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1554 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1555 NUM_BANKS(ADDR_SURF_16_BANK
));
1556 macrotile
[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1557 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1558 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
) |
1559 NUM_BANKS(ADDR_SURF_16_BANK
));
1560 macrotile
[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1561 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1562 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
) |
1563 NUM_BANKS(ADDR_SURF_8_BANK
));
1565 for (reg_offset
= 0; reg_offset
< num_tile_mode_states
; reg_offset
++)
1566 WREG32(mmGB_TILE_MODE0
+ reg_offset
, tile
[reg_offset
]);
1567 for (reg_offset
= 0; reg_offset
< num_secondary_tile_mode_states
; reg_offset
++)
1568 if (reg_offset
!= 7)
1569 WREG32(mmGB_MACROTILE_MODE0
+ reg_offset
, macrotile
[reg_offset
]);
1575 * gfx_v7_0_select_se_sh - select which SE, SH to address
1577 * @adev: amdgpu_device pointer
1578 * @se_num: shader engine to address
1579 * @sh_num: sh block to address
1581 * Select which SE, SH combinations to address. Certain
1582 * registers are instanced per SE or SH. 0xffffffff means
1583 * broadcast to all SEs or SHs (CIK).
1585 static void gfx_v7_0_select_se_sh(struct amdgpu_device
*adev
,
1586 u32 se_num
, u32 sh_num
, u32 instance
)
1590 if (instance
== 0xffffffff)
1591 data
= REG_SET_FIELD(0, GRBM_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
, 1);
1593 data
= REG_SET_FIELD(0, GRBM_GFX_INDEX
, INSTANCE_INDEX
, instance
);
1595 if ((se_num
== 0xffffffff) && (sh_num
== 0xffffffff))
1596 data
|= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK
|
1597 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK
;
1598 else if (se_num
== 0xffffffff)
1599 data
|= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK
|
1600 (sh_num
<< GRBM_GFX_INDEX__SH_INDEX__SHIFT
);
1601 else if (sh_num
== 0xffffffff)
1602 data
|= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK
|
1603 (se_num
<< GRBM_GFX_INDEX__SE_INDEX__SHIFT
);
1605 data
|= (sh_num
<< GRBM_GFX_INDEX__SH_INDEX__SHIFT
) |
1606 (se_num
<< GRBM_GFX_INDEX__SE_INDEX__SHIFT
);
1607 WREG32(mmGRBM_GFX_INDEX
, data
);
1611 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
1613 * @adev: amdgpu_device pointer
1615 * Calculates the bitmask of enabled RBs (CIK).
1616 * Returns the enabled RB bitmask.
1618 static u32
gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device
*adev
)
1622 data
= RREG32(mmCC_RB_BACKEND_DISABLE
);
1623 data
|= RREG32(mmGC_USER_RB_BACKEND_DISABLE
);
1625 data
&= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK
;
1626 data
>>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT
;
1628 mask
= amdgpu_gfx_create_bitmask(adev
->gfx
.config
.max_backends_per_se
/
1629 adev
->gfx
.config
.max_sh_per_se
);
1631 return (~data
) & mask
;
1635 gfx_v7_0_raster_config(struct amdgpu_device
*adev
, u32
*rconf
, u32
*rconf1
)
1637 switch (adev
->asic_type
) {
1639 *rconf
|= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
1640 SE_XSEL(1) | SE_YSEL(1);
1644 *rconf
|= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
1645 RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) |
1646 PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) |
1648 *rconf1
|= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
1652 *rconf
|= RB_MAP_PKR0(2);
1661 DRM_ERROR("unknown asic: 0x%x\n", adev
->asic_type
);
1667 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device
*adev
,
1668 u32 raster_config
, u32 raster_config_1
,
1669 unsigned rb_mask
, unsigned num_rb
)
1671 unsigned sh_per_se
= max_t(unsigned, adev
->gfx
.config
.max_sh_per_se
, 1);
1672 unsigned num_se
= max_t(unsigned, adev
->gfx
.config
.max_shader_engines
, 1);
1673 unsigned rb_per_pkr
= min_t(unsigned, num_rb
/ num_se
/ sh_per_se
, 2);
1674 unsigned rb_per_se
= num_rb
/ num_se
;
1675 unsigned se_mask
[4];
1678 se_mask
[0] = ((1 << rb_per_se
) - 1) & rb_mask
;
1679 se_mask
[1] = (se_mask
[0] << rb_per_se
) & rb_mask
;
1680 se_mask
[2] = (se_mask
[1] << rb_per_se
) & rb_mask
;
1681 se_mask
[3] = (se_mask
[2] << rb_per_se
) & rb_mask
;
1683 WARN_ON(!(num_se
== 1 || num_se
== 2 || num_se
== 4));
1684 WARN_ON(!(sh_per_se
== 1 || sh_per_se
== 2));
1685 WARN_ON(!(rb_per_pkr
== 1 || rb_per_pkr
== 2));
1687 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
1688 (!se_mask
[2] && !se_mask
[3]))) {
1689 raster_config_1
&= ~SE_PAIR_MAP_MASK
;
1691 if (!se_mask
[0] && !se_mask
[1]) {
1693 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3
);
1696 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0
);
1700 for (se
= 0; se
< num_se
; se
++) {
1701 unsigned raster_config_se
= raster_config
;
1702 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
1703 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
1704 int idx
= (se
/ 2) * 2;
1706 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
1707 raster_config_se
&= ~SE_MAP_MASK
;
1709 if (!se_mask
[idx
]) {
1710 raster_config_se
|= SE_MAP(RASTER_CONFIG_SE_MAP_3
);
1712 raster_config_se
|= SE_MAP(RASTER_CONFIG_SE_MAP_0
);
1716 pkr0_mask
&= rb_mask
;
1717 pkr1_mask
&= rb_mask
;
1718 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
1719 raster_config_se
&= ~PKR_MAP_MASK
;
1722 raster_config_se
|= PKR_MAP(RASTER_CONFIG_PKR_MAP_3
);
1724 raster_config_se
|= PKR_MAP(RASTER_CONFIG_PKR_MAP_0
);
1728 if (rb_per_se
>= 2) {
1729 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
1730 unsigned rb1_mask
= rb0_mask
<< 1;
1732 rb0_mask
&= rb_mask
;
1733 rb1_mask
&= rb_mask
;
1734 if (!rb0_mask
|| !rb1_mask
) {
1735 raster_config_se
&= ~RB_MAP_PKR0_MASK
;
1739 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3
);
1742 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0
);
1746 if (rb_per_se
> 2) {
1747 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
1748 rb1_mask
= rb0_mask
<< 1;
1749 rb0_mask
&= rb_mask
;
1750 rb1_mask
&= rb_mask
;
1751 if (!rb0_mask
|| !rb1_mask
) {
1752 raster_config_se
&= ~RB_MAP_PKR1_MASK
;
1756 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3
);
1759 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0
);
1765 /* GRBM_GFX_INDEX has a different offset on CI+ */
1766 gfx_v7_0_select_se_sh(adev
, se
, 0xffffffff, 0xffffffff);
1767 WREG32(mmPA_SC_RASTER_CONFIG
, raster_config_se
);
1768 WREG32(mmPA_SC_RASTER_CONFIG_1
, raster_config_1
);
1771 /* GRBM_GFX_INDEX has a different offset on CI+ */
1772 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
1776 * gfx_v7_0_setup_rb - setup the RBs on the asic
1778 * @adev: amdgpu_device pointer
1779 * @se_num: number of SEs (shader engines) for the asic
1780 * @sh_per_se: number of SH blocks per SE for the asic
1782 * Configures per-SE/SH RB registers (CIK).
1784 static void gfx_v7_0_setup_rb(struct amdgpu_device
*adev
)
1788 u32 raster_config
= 0, raster_config_1
= 0;
1790 u32 rb_bitmap_width_per_sh
= adev
->gfx
.config
.max_backends_per_se
/
1791 adev
->gfx
.config
.max_sh_per_se
;
1792 unsigned num_rb_pipes
;
1794 mutex_lock(&adev
->grbm_idx_mutex
);
1795 for (i
= 0; i
< adev
->gfx
.config
.max_shader_engines
; i
++) {
1796 for (j
= 0; j
< adev
->gfx
.config
.max_sh_per_se
; j
++) {
1797 gfx_v7_0_select_se_sh(adev
, i
, j
, 0xffffffff);
1798 data
= gfx_v7_0_get_rb_active_bitmap(adev
);
1799 active_rbs
|= data
<< ((i
* adev
->gfx
.config
.max_sh_per_se
+ j
) *
1800 rb_bitmap_width_per_sh
);
1803 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
1805 adev
->gfx
.config
.backend_enable_mask
= active_rbs
;
1806 adev
->gfx
.config
.num_rbs
= hweight32(active_rbs
);
1808 num_rb_pipes
= min_t(unsigned, adev
->gfx
.config
.max_backends_per_se
*
1809 adev
->gfx
.config
.max_shader_engines
, 16);
1811 gfx_v7_0_raster_config(adev
, &raster_config
, &raster_config_1
);
1813 if (!adev
->gfx
.config
.backend_enable_mask
||
1814 adev
->gfx
.config
.num_rbs
>= num_rb_pipes
) {
1815 WREG32(mmPA_SC_RASTER_CONFIG
, raster_config
);
1816 WREG32(mmPA_SC_RASTER_CONFIG_1
, raster_config_1
);
1818 gfx_v7_0_write_harvested_raster_configs(adev
, raster_config
, raster_config_1
,
1819 adev
->gfx
.config
.backend_enable_mask
,
1823 /* cache the values for userspace */
1824 for (i
= 0; i
< adev
->gfx
.config
.max_shader_engines
; i
++) {
1825 for (j
= 0; j
< adev
->gfx
.config
.max_sh_per_se
; j
++) {
1826 gfx_v7_0_select_se_sh(adev
, i
, j
, 0xffffffff);
1827 adev
->gfx
.config
.rb_config
[i
][j
].rb_backend_disable
=
1828 RREG32(mmCC_RB_BACKEND_DISABLE
);
1829 adev
->gfx
.config
.rb_config
[i
][j
].user_rb_backend_disable
=
1830 RREG32(mmGC_USER_RB_BACKEND_DISABLE
);
1831 adev
->gfx
.config
.rb_config
[i
][j
].raster_config
=
1832 RREG32(mmPA_SC_RASTER_CONFIG
);
1833 adev
->gfx
.config
.rb_config
[i
][j
].raster_config_1
=
1834 RREG32(mmPA_SC_RASTER_CONFIG_1
);
1837 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
1838 mutex_unlock(&adev
->grbm_idx_mutex
);
1842 * gfx_v7_0_init_compute_vmid - gart enable
1844 * @adev: amdgpu_device pointer
1846 * Initialize compute vmid sh_mem registers
1849 #define DEFAULT_SH_MEM_BASES (0x6000)
1850 #define FIRST_COMPUTE_VMID (8)
1851 #define LAST_COMPUTE_VMID (16)
1852 static void gfx_v7_0_init_compute_vmid(struct amdgpu_device
*adev
)
1855 uint32_t sh_mem_config
;
1856 uint32_t sh_mem_bases
;
1859 * Configure apertures:
1860 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1861 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1862 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1864 sh_mem_bases
= DEFAULT_SH_MEM_BASES
| (DEFAULT_SH_MEM_BASES
<< 16);
1865 sh_mem_config
= SH_MEM_ALIGNMENT_MODE_UNALIGNED
<<
1866 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT
;
1867 sh_mem_config
|= MTYPE_NONCACHED
<< SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT
;
1868 mutex_lock(&adev
->srbm_mutex
);
1869 for (i
= FIRST_COMPUTE_VMID
; i
< LAST_COMPUTE_VMID
; i
++) {
1870 cik_srbm_select(adev
, 0, 0, 0, i
);
1871 /* CP and shaders */
1872 WREG32(mmSH_MEM_CONFIG
, sh_mem_config
);
1873 WREG32(mmSH_MEM_APE1_BASE
, 1);
1874 WREG32(mmSH_MEM_APE1_LIMIT
, 0);
1875 WREG32(mmSH_MEM_BASES
, sh_mem_bases
);
1877 cik_srbm_select(adev
, 0, 0, 0, 0);
1878 mutex_unlock(&adev
->srbm_mutex
);
1881 static void gfx_v7_0_config_init(struct amdgpu_device
*adev
)
1883 adev
->gfx
.config
.double_offchip_lds_buf
= 1;
1887 * gfx_v7_0_gpu_init - setup the 3D engine
1889 * @adev: amdgpu_device pointer
1891 * Configures the 3D engine and tiling configuration
1892 * registers so that the 3D engine is usable.
1894 static void gfx_v7_0_gpu_init(struct amdgpu_device
*adev
)
1896 u32 sh_mem_cfg
, sh_static_mem_cfg
, sh_mem_base
;
1900 WREG32(mmGRBM_CNTL
, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT
));
1902 WREG32(mmGB_ADDR_CONFIG
, adev
->gfx
.config
.gb_addr_config
);
1903 WREG32(mmHDP_ADDR_CONFIG
, adev
->gfx
.config
.gb_addr_config
);
1904 WREG32(mmDMIF_ADDR_CALC
, adev
->gfx
.config
.gb_addr_config
);
1906 gfx_v7_0_tiling_mode_table_init(adev
);
1908 gfx_v7_0_setup_rb(adev
);
1909 gfx_v7_0_get_cu_info(adev
);
1910 gfx_v7_0_config_init(adev
);
1912 /* set HW defaults for 3D engine */
1913 WREG32(mmCP_MEQ_THRESHOLDS
,
1914 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT
) |
1915 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT
));
1917 mutex_lock(&adev
->grbm_idx_mutex
);
1919 * making sure that the following register writes will be broadcasted
1920 * to all the shaders
1922 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
1924 /* XXX SH_MEM regs */
1925 /* where to put LDS, scratch, GPUVM in FSA64 space */
1926 sh_mem_cfg
= REG_SET_FIELD(0, SH_MEM_CONFIG
, ALIGNMENT_MODE
,
1927 SH_MEM_ALIGNMENT_MODE_UNALIGNED
);
1928 sh_mem_cfg
= REG_SET_FIELD(sh_mem_cfg
, SH_MEM_CONFIG
, DEFAULT_MTYPE
,
1930 sh_mem_cfg
= REG_SET_FIELD(sh_mem_cfg
, SH_MEM_CONFIG
, APE1_MTYPE
,
1932 sh_mem_cfg
= REG_SET_FIELD(sh_mem_cfg
, SH_MEM_CONFIG
, PRIVATE_ATC
, 0);
1934 sh_static_mem_cfg
= REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG
,
1936 sh_static_mem_cfg
= REG_SET_FIELD(sh_static_mem_cfg
, SH_STATIC_MEM_CONFIG
,
1938 sh_static_mem_cfg
= REG_SET_FIELD(sh_static_mem_cfg
, SH_STATIC_MEM_CONFIG
,
1940 WREG32(mmSH_STATIC_MEM_CONFIG
, sh_static_mem_cfg
);
1942 mutex_lock(&adev
->srbm_mutex
);
1943 for (i
= 0; i
< adev
->vm_manager
.id_mgr
[0].num_ids
; i
++) {
1947 sh_mem_base
= adev
->mc
.shared_aperture_start
>> 48;
1948 cik_srbm_select(adev
, 0, 0, 0, i
);
1949 /* CP and shaders */
1950 WREG32(mmSH_MEM_CONFIG
, sh_mem_cfg
);
1951 WREG32(mmSH_MEM_APE1_BASE
, 1);
1952 WREG32(mmSH_MEM_APE1_LIMIT
, 0);
1953 WREG32(mmSH_MEM_BASES
, sh_mem_base
);
1955 cik_srbm_select(adev
, 0, 0, 0, 0);
1956 mutex_unlock(&adev
->srbm_mutex
);
1958 gfx_v7_0_init_compute_vmid(adev
);
1960 WREG32(mmSX_DEBUG_1
, 0x20);
1962 WREG32(mmTA_CNTL_AUX
, 0x00010000);
1964 tmp
= RREG32(mmSPI_CONFIG_CNTL
);
1966 WREG32(mmSPI_CONFIG_CNTL
, tmp
);
1968 WREG32(mmSQ_CONFIG
, 1);
1970 WREG32(mmDB_DEBUG
, 0);
1972 tmp
= RREG32(mmDB_DEBUG2
) & ~0xf00fffff;
1974 WREG32(mmDB_DEBUG2
, tmp
);
1976 tmp
= RREG32(mmDB_DEBUG3
) & ~0x0002021c;
1978 WREG32(mmDB_DEBUG3
, tmp
);
1980 tmp
= RREG32(mmCB_HW_CONTROL
) & ~0x00010000;
1982 WREG32(mmCB_HW_CONTROL
, tmp
);
1984 WREG32(mmSPI_CONFIG_CNTL_1
, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT
));
1986 WREG32(mmPA_SC_FIFO_SIZE
,
1987 ((adev
->gfx
.config
.sc_prim_fifo_size_frontend
<< PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT
) |
1988 (adev
->gfx
.config
.sc_prim_fifo_size_backend
<< PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT
) |
1989 (adev
->gfx
.config
.sc_hiz_tile_fifo_size
<< PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT
) |
1990 (adev
->gfx
.config
.sc_earlyz_tile_fifo_size
<< PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT
)));
1992 WREG32(mmVGT_NUM_INSTANCES
, 1);
1994 WREG32(mmCP_PERFMON_CNTL
, 0);
1996 WREG32(mmSQ_CONFIG
, 0);
1998 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS
,
1999 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT
) |
2000 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT
)));
2002 WREG32(mmVGT_CACHE_INVALIDATION
,
2003 (VC_AND_TC
<< VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT
) |
2004 (ES_AND_GS_AUTO
<< VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT
));
2006 WREG32(mmVGT_GS_VERTEX_REUSE
, 16);
2007 WREG32(mmPA_SC_LINE_STIPPLE_STATE
, 0);
2009 WREG32(mmPA_CL_ENHANCE
, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK
|
2010 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT
));
2011 WREG32(mmPA_SC_ENHANCE
, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK
);
2013 tmp
= RREG32(mmSPI_ARB_PRIORITY
);
2014 tmp
= REG_SET_FIELD(tmp
, SPI_ARB_PRIORITY
, PIPE_ORDER_TS0
, 2);
2015 tmp
= REG_SET_FIELD(tmp
, SPI_ARB_PRIORITY
, PIPE_ORDER_TS1
, 2);
2016 tmp
= REG_SET_FIELD(tmp
, SPI_ARB_PRIORITY
, PIPE_ORDER_TS2
, 2);
2017 tmp
= REG_SET_FIELD(tmp
, SPI_ARB_PRIORITY
, PIPE_ORDER_TS3
, 2);
2018 WREG32(mmSPI_ARB_PRIORITY
, tmp
);
2020 mutex_unlock(&adev
->grbm_idx_mutex
);
2026 * GPU scratch registers helpers function.
2029 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
2031 * @adev: amdgpu_device pointer
2033 * Set up the number and offset of the CP scratch registers.
2034 * NOTE: use of CP scratch registers is a legacy inferface and
2035 * is not used by default on newer asics (r6xx+). On newer asics,
2036 * memory buffers are used for fences rather than scratch regs.
2038 static void gfx_v7_0_scratch_init(struct amdgpu_device
*adev
)
2040 adev
->gfx
.scratch
.num_reg
= 8;
2041 adev
->gfx
.scratch
.reg_base
= mmSCRATCH_REG0
;
2042 adev
->gfx
.scratch
.free_mask
= (1u << adev
->gfx
.scratch
.num_reg
) - 1;
2046 * gfx_v7_0_ring_test_ring - basic gfx ring test
2048 * @adev: amdgpu_device pointer
2049 * @ring: amdgpu_ring structure holding ring information
2051 * Allocate a scratch register and write to it using the gfx ring (CIK).
2052 * Provides a basic gfx ring test to verify that the ring is working.
2053 * Used by gfx_v7_0_cp_gfx_resume();
2054 * Returns 0 on success, error on failure.
2056 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring
*ring
)
2058 struct amdgpu_device
*adev
= ring
->adev
;
2064 r
= amdgpu_gfx_scratch_get(adev
, &scratch
);
2066 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r
);
2069 WREG32(scratch
, 0xCAFEDEAD);
2070 r
= amdgpu_ring_alloc(ring
, 3);
2072 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring
->idx
, r
);
2073 amdgpu_gfx_scratch_free(adev
, scratch
);
2076 amdgpu_ring_write(ring
, PACKET3(PACKET3_SET_UCONFIG_REG
, 1));
2077 amdgpu_ring_write(ring
, (scratch
- PACKET3_SET_UCONFIG_REG_START
));
2078 amdgpu_ring_write(ring
, 0xDEADBEEF);
2079 amdgpu_ring_commit(ring
);
2081 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
2082 tmp
= RREG32(scratch
);
2083 if (tmp
== 0xDEADBEEF)
2087 if (i
< adev
->usec_timeout
) {
2088 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring
->idx
, i
);
2090 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2091 ring
->idx
, scratch
, tmp
);
2094 amdgpu_gfx_scratch_free(adev
, scratch
);
2099 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
2101 * @adev: amdgpu_device pointer
2102 * @ridx: amdgpu ring index
2104 * Emits an hdp flush on the cp.
2106 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring
*ring
)
2109 int usepfp
= ring
->funcs
->type
== AMDGPU_RING_TYPE_COMPUTE
? 0 : 1;
2111 if (ring
->funcs
->type
== AMDGPU_RING_TYPE_COMPUTE
) {
2114 ref_and_mask
= GPU_HDP_FLUSH_DONE__CP2_MASK
<< ring
->pipe
;
2117 ref_and_mask
= GPU_HDP_FLUSH_DONE__CP6_MASK
<< ring
->pipe
;
2123 ref_and_mask
= GPU_HDP_FLUSH_DONE__CP0_MASK
;
2126 amdgpu_ring_write(ring
, PACKET3(PACKET3_WAIT_REG_MEM
, 5));
2127 amdgpu_ring_write(ring
, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2128 WAIT_REG_MEM_FUNCTION(3) | /* == */
2129 WAIT_REG_MEM_ENGINE(usepfp
))); /* pfp or me */
2130 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_REQ
);
2131 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_DONE
);
2132 amdgpu_ring_write(ring
, ref_and_mask
);
2133 amdgpu_ring_write(ring
, ref_and_mask
);
2134 amdgpu_ring_write(ring
, 0x20); /* poll interval */
2137 static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring
*ring
)
2139 amdgpu_ring_write(ring
, PACKET3(PACKET3_EVENT_WRITE
, 0));
2140 amdgpu_ring_write(ring
, EVENT_TYPE(VS_PARTIAL_FLUSH
) |
2143 amdgpu_ring_write(ring
, PACKET3(PACKET3_EVENT_WRITE
, 0));
2144 amdgpu_ring_write(ring
, EVENT_TYPE(VGT_FLUSH
) |
2150 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
2152 * @adev: amdgpu_device pointer
2153 * @ridx: amdgpu ring index
2155 * Emits an hdp invalidate on the cp.
2157 static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring
*ring
)
2159 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
2160 amdgpu_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(0) |
2161 WRITE_DATA_DST_SEL(0) |
2163 amdgpu_ring_write(ring
, mmHDP_DEBUG0
);
2164 amdgpu_ring_write(ring
, 0);
2165 amdgpu_ring_write(ring
, 1);
2169 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2171 * @adev: amdgpu_device pointer
2172 * @fence: amdgpu fence object
2174 * Emits a fence sequnce number on the gfx ring and flushes
2177 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring
*ring
, u64 addr
,
2178 u64 seq
, unsigned flags
)
2180 bool write64bit
= flags
& AMDGPU_FENCE_FLAG_64BIT
;
2181 bool int_sel
= flags
& AMDGPU_FENCE_FLAG_INT
;
2182 /* Workaround for cache flush problems. First send a dummy EOP
2183 * event down the pipe with seq one below.
2185 amdgpu_ring_write(ring
, PACKET3(PACKET3_EVENT_WRITE_EOP
, 4));
2186 amdgpu_ring_write(ring
, (EOP_TCL1_ACTION_EN
|
2188 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT
) |
2190 amdgpu_ring_write(ring
, addr
& 0xfffffffc);
2191 amdgpu_ring_write(ring
, (upper_32_bits(addr
) & 0xffff) |
2192 DATA_SEL(1) | INT_SEL(0));
2193 amdgpu_ring_write(ring
, lower_32_bits(seq
- 1));
2194 amdgpu_ring_write(ring
, upper_32_bits(seq
- 1));
2196 /* Then send the real EOP event down the pipe. */
2197 amdgpu_ring_write(ring
, PACKET3(PACKET3_EVENT_WRITE_EOP
, 4));
2198 amdgpu_ring_write(ring
, (EOP_TCL1_ACTION_EN
|
2200 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT
) |
2202 amdgpu_ring_write(ring
, addr
& 0xfffffffc);
2203 amdgpu_ring_write(ring
, (upper_32_bits(addr
) & 0xffff) |
2204 DATA_SEL(write64bit
? 2 : 1) | INT_SEL(int_sel
? 2 : 0));
2205 amdgpu_ring_write(ring
, lower_32_bits(seq
));
2206 amdgpu_ring_write(ring
, upper_32_bits(seq
));
2210 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2212 * @adev: amdgpu_device pointer
2213 * @fence: amdgpu fence object
2215 * Emits a fence sequnce number on the compute ring and flushes
2218 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring
*ring
,
2222 bool write64bit
= flags
& AMDGPU_FENCE_FLAG_64BIT
;
2223 bool int_sel
= flags
& AMDGPU_FENCE_FLAG_INT
;
2225 /* RELEASE_MEM - flush caches, send int */
2226 amdgpu_ring_write(ring
, PACKET3(PACKET3_RELEASE_MEM
, 5));
2227 amdgpu_ring_write(ring
, (EOP_TCL1_ACTION_EN
|
2229 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT
) |
2231 amdgpu_ring_write(ring
, DATA_SEL(write64bit
? 2 : 1) | INT_SEL(int_sel
? 2 : 0));
2232 amdgpu_ring_write(ring
, addr
& 0xfffffffc);
2233 amdgpu_ring_write(ring
, upper_32_bits(addr
));
2234 amdgpu_ring_write(ring
, lower_32_bits(seq
));
2235 amdgpu_ring_write(ring
, upper_32_bits(seq
));
2242 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2244 * @ring: amdgpu_ring structure holding ring information
2245 * @ib: amdgpu indirect buffer object
2247 * Emits an DE (drawing engine) or CE (constant engine) IB
2248 * on the gfx ring. IBs are usually generated by userspace
2249 * acceleration drivers and submitted to the kernel for
2250 * sheduling on the ring. This function schedules the IB
2251 * on the gfx ring for execution by the GPU.
2253 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring
*ring
,
2254 struct amdgpu_ib
*ib
,
2255 unsigned vm_id
, bool ctx_switch
)
2257 u32 header
, control
= 0;
2259 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2261 amdgpu_ring_write(ring
, PACKET3(PACKET3_SWITCH_BUFFER
, 0));
2262 amdgpu_ring_write(ring
, 0);
2265 if (ib
->flags
& AMDGPU_IB_FLAG_CE
)
2266 header
= PACKET3(PACKET3_INDIRECT_BUFFER_CONST
, 2);
2268 header
= PACKET3(PACKET3_INDIRECT_BUFFER
, 2);
2270 control
|= ib
->length_dw
| (vm_id
<< 24);
2272 amdgpu_ring_write(ring
, header
);
2273 amdgpu_ring_write(ring
,
2277 (ib
->gpu_addr
& 0xFFFFFFFC));
2278 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xFFFF);
2279 amdgpu_ring_write(ring
, control
);
2282 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring
*ring
,
2283 struct amdgpu_ib
*ib
,
2284 unsigned vm_id
, bool ctx_switch
)
2286 u32 control
= INDIRECT_BUFFER_VALID
| ib
->length_dw
| (vm_id
<< 24);
2288 amdgpu_ring_write(ring
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
2289 amdgpu_ring_write(ring
,
2293 (ib
->gpu_addr
& 0xFFFFFFFC));
2294 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xFFFF);
2295 amdgpu_ring_write(ring
, control
);
2298 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring
*ring
, uint32_t flags
)
2302 dw2
|= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2303 if (flags
& AMDGPU_HAVE_CTX_SWITCH
) {
2304 gfx_v7_0_ring_emit_vgt_flush(ring
);
2305 /* set load_global_config & load_global_uconfig */
2307 /* set load_cs_sh_regs */
2309 /* set load_per_context_state & load_gfx_sh_regs */
2313 amdgpu_ring_write(ring
, PACKET3(PACKET3_CONTEXT_CONTROL
, 1));
2314 amdgpu_ring_write(ring
, dw2
);
2315 amdgpu_ring_write(ring
, 0);
2319 * gfx_v7_0_ring_test_ib - basic ring IB test
2321 * @ring: amdgpu_ring structure holding ring information
2323 * Allocate an IB and execute it on the gfx ring (CIK).
2324 * Provides a basic gfx ring test to verify that IBs are working.
2325 * Returns 0 on success, error on failure.
2327 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring
*ring
, long timeout
)
2329 struct amdgpu_device
*adev
= ring
->adev
;
2330 struct amdgpu_ib ib
;
2331 struct dma_fence
*f
= NULL
;
2336 r
= amdgpu_gfx_scratch_get(adev
, &scratch
);
2338 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r
);
2341 WREG32(scratch
, 0xCAFEDEAD);
2342 memset(&ib
, 0, sizeof(ib
));
2343 r
= amdgpu_ib_get(adev
, NULL
, 256, &ib
);
2345 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r
);
2348 ib
.ptr
[0] = PACKET3(PACKET3_SET_UCONFIG_REG
, 1);
2349 ib
.ptr
[1] = ((scratch
- PACKET3_SET_UCONFIG_REG_START
));
2350 ib
.ptr
[2] = 0xDEADBEEF;
2353 r
= amdgpu_ib_schedule(ring
, 1, &ib
, NULL
, &f
);
2357 r
= dma_fence_wait_timeout(f
, false, timeout
);
2359 DRM_ERROR("amdgpu: IB test timed out\n");
2363 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r
);
2366 tmp
= RREG32(scratch
);
2367 if (tmp
== 0xDEADBEEF) {
2368 DRM_INFO("ib test on ring %d succeeded\n", ring
->idx
);
2371 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2377 amdgpu_ib_free(adev
, &ib
, NULL
);
2380 amdgpu_gfx_scratch_free(adev
, scratch
);
2386 * On CIK, gfx and compute now have independant command processors.
2389 * Gfx consists of a single ring and can process both gfx jobs and
2390 * compute jobs. The gfx CP consists of three microengines (ME):
2391 * PFP - Pre-Fetch Parser
2393 * CE - Constant Engine
2394 * The PFP and ME make up what is considered the Drawing Engine (DE).
2395 * The CE is an asynchronous engine used for updating buffer desciptors
2396 * used by the DE so that they can be loaded into cache in parallel
2397 * while the DE is processing state update packets.
2400 * The compute CP consists of two microengines (ME):
2401 * MEC1 - Compute MicroEngine 1
2402 * MEC2 - Compute MicroEngine 2
2403 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2404 * The queues are exposed to userspace and are programmed directly
2405 * by the compute runtime.
2408 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2410 * @adev: amdgpu_device pointer
2411 * @enable: enable or disable the MEs
2413 * Halts or unhalts the gfx MEs.
2415 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device
*adev
, bool enable
)
2420 WREG32(mmCP_ME_CNTL
, 0);
2422 WREG32(mmCP_ME_CNTL
, (CP_ME_CNTL__ME_HALT_MASK
| CP_ME_CNTL__PFP_HALT_MASK
| CP_ME_CNTL__CE_HALT_MASK
));
2423 for (i
= 0; i
< adev
->gfx
.num_gfx_rings
; i
++)
2424 adev
->gfx
.gfx_ring
[i
].ready
= false;
2430 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2432 * @adev: amdgpu_device pointer
2434 * Loads the gfx PFP, ME, and CE ucode.
2435 * Returns 0 for success, -EINVAL if the ucode is not available.
2437 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device
*adev
)
2439 const struct gfx_firmware_header_v1_0
*pfp_hdr
;
2440 const struct gfx_firmware_header_v1_0
*ce_hdr
;
2441 const struct gfx_firmware_header_v1_0
*me_hdr
;
2442 const __le32
*fw_data
;
2443 unsigned i
, fw_size
;
2445 if (!adev
->gfx
.me_fw
|| !adev
->gfx
.pfp_fw
|| !adev
->gfx
.ce_fw
)
2448 pfp_hdr
= (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.pfp_fw
->data
;
2449 ce_hdr
= (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.ce_fw
->data
;
2450 me_hdr
= (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.me_fw
->data
;
2452 amdgpu_ucode_print_gfx_hdr(&pfp_hdr
->header
);
2453 amdgpu_ucode_print_gfx_hdr(&ce_hdr
->header
);
2454 amdgpu_ucode_print_gfx_hdr(&me_hdr
->header
);
2455 adev
->gfx
.pfp_fw_version
= le32_to_cpu(pfp_hdr
->header
.ucode_version
);
2456 adev
->gfx
.ce_fw_version
= le32_to_cpu(ce_hdr
->header
.ucode_version
);
2457 adev
->gfx
.me_fw_version
= le32_to_cpu(me_hdr
->header
.ucode_version
);
2458 adev
->gfx
.me_feature_version
= le32_to_cpu(me_hdr
->ucode_feature_version
);
2459 adev
->gfx
.ce_feature_version
= le32_to_cpu(ce_hdr
->ucode_feature_version
);
2460 adev
->gfx
.pfp_feature_version
= le32_to_cpu(pfp_hdr
->ucode_feature_version
);
2462 gfx_v7_0_cp_gfx_enable(adev
, false);
2465 fw_data
= (const __le32
*)
2466 (adev
->gfx
.pfp_fw
->data
+
2467 le32_to_cpu(pfp_hdr
->header
.ucode_array_offset_bytes
));
2468 fw_size
= le32_to_cpu(pfp_hdr
->header
.ucode_size_bytes
) / 4;
2469 WREG32(mmCP_PFP_UCODE_ADDR
, 0);
2470 for (i
= 0; i
< fw_size
; i
++)
2471 WREG32(mmCP_PFP_UCODE_DATA
, le32_to_cpup(fw_data
++));
2472 WREG32(mmCP_PFP_UCODE_ADDR
, adev
->gfx
.pfp_fw_version
);
2475 fw_data
= (const __le32
*)
2476 (adev
->gfx
.ce_fw
->data
+
2477 le32_to_cpu(ce_hdr
->header
.ucode_array_offset_bytes
));
2478 fw_size
= le32_to_cpu(ce_hdr
->header
.ucode_size_bytes
) / 4;
2479 WREG32(mmCP_CE_UCODE_ADDR
, 0);
2480 for (i
= 0; i
< fw_size
; i
++)
2481 WREG32(mmCP_CE_UCODE_DATA
, le32_to_cpup(fw_data
++));
2482 WREG32(mmCP_CE_UCODE_ADDR
, adev
->gfx
.ce_fw_version
);
2485 fw_data
= (const __le32
*)
2486 (adev
->gfx
.me_fw
->data
+
2487 le32_to_cpu(me_hdr
->header
.ucode_array_offset_bytes
));
2488 fw_size
= le32_to_cpu(me_hdr
->header
.ucode_size_bytes
) / 4;
2489 WREG32(mmCP_ME_RAM_WADDR
, 0);
2490 for (i
= 0; i
< fw_size
; i
++)
2491 WREG32(mmCP_ME_RAM_DATA
, le32_to_cpup(fw_data
++));
2492 WREG32(mmCP_ME_RAM_WADDR
, adev
->gfx
.me_fw_version
);
2498 * gfx_v7_0_cp_gfx_start - start the gfx ring
2500 * @adev: amdgpu_device pointer
2502 * Enables the ring and loads the clear state context and other
2503 * packets required to init the ring.
2504 * Returns 0 for success, error for failure.
2506 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device
*adev
)
2508 struct amdgpu_ring
*ring
= &adev
->gfx
.gfx_ring
[0];
2509 const struct cs_section_def
*sect
= NULL
;
2510 const struct cs_extent_def
*ext
= NULL
;
2514 WREG32(mmCP_MAX_CONTEXT
, adev
->gfx
.config
.max_hw_contexts
- 1);
2515 WREG32(mmCP_ENDIAN_SWAP
, 0);
2516 WREG32(mmCP_DEVICE_ID
, 1);
2518 gfx_v7_0_cp_gfx_enable(adev
, true);
2520 r
= amdgpu_ring_alloc(ring
, gfx_v7_0_get_csb_size(adev
) + 8);
2522 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r
);
2526 /* init the CE partitions. CE only used for gfx on CIK */
2527 amdgpu_ring_write(ring
, PACKET3(PACKET3_SET_BASE
, 2));
2528 amdgpu_ring_write(ring
, PACKET3_BASE_INDEX(CE_PARTITION_BASE
));
2529 amdgpu_ring_write(ring
, 0x8000);
2530 amdgpu_ring_write(ring
, 0x8000);
2532 /* clear state buffer */
2533 amdgpu_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
2534 amdgpu_ring_write(ring
, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
);
2536 amdgpu_ring_write(ring
, PACKET3(PACKET3_CONTEXT_CONTROL
, 1));
2537 amdgpu_ring_write(ring
, 0x80000000);
2538 amdgpu_ring_write(ring
, 0x80000000);
2540 for (sect
= adev
->gfx
.rlc
.cs_data
; sect
->section
!= NULL
; ++sect
) {
2541 for (ext
= sect
->section
; ext
->extent
!= NULL
; ++ext
) {
2542 if (sect
->id
== SECT_CONTEXT
) {
2543 amdgpu_ring_write(ring
,
2544 PACKET3(PACKET3_SET_CONTEXT_REG
, ext
->reg_count
));
2545 amdgpu_ring_write(ring
, ext
->reg_index
- PACKET3_SET_CONTEXT_REG_START
);
2546 for (i
= 0; i
< ext
->reg_count
; i
++)
2547 amdgpu_ring_write(ring
, ext
->extent
[i
]);
2552 amdgpu_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 2));
2553 amdgpu_ring_write(ring
, mmPA_SC_RASTER_CONFIG
- PACKET3_SET_CONTEXT_REG_START
);
2554 switch (adev
->asic_type
) {
2556 amdgpu_ring_write(ring
, 0x16000012);
2557 amdgpu_ring_write(ring
, 0x00000000);
2560 amdgpu_ring_write(ring
, 0x00000000); /* XXX */
2561 amdgpu_ring_write(ring
, 0x00000000);
2565 amdgpu_ring_write(ring
, 0x00000000); /* XXX */
2566 amdgpu_ring_write(ring
, 0x00000000);
2569 amdgpu_ring_write(ring
, 0x3a00161a);
2570 amdgpu_ring_write(ring
, 0x0000002e);
2573 amdgpu_ring_write(ring
, 0x00000000);
2574 amdgpu_ring_write(ring
, 0x00000000);
2578 amdgpu_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
2579 amdgpu_ring_write(ring
, PACKET3_PREAMBLE_END_CLEAR_STATE
);
2581 amdgpu_ring_write(ring
, PACKET3(PACKET3_CLEAR_STATE
, 0));
2582 amdgpu_ring_write(ring
, 0);
2584 amdgpu_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 2));
2585 amdgpu_ring_write(ring
, 0x00000316);
2586 amdgpu_ring_write(ring
, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2587 amdgpu_ring_write(ring
, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2589 amdgpu_ring_commit(ring
);
2595 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2597 * @adev: amdgpu_device pointer
2599 * Program the location and size of the gfx ring buffer
2600 * and test it to make sure it's working.
2601 * Returns 0 for success, error for failure.
2603 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device
*adev
)
2605 struct amdgpu_ring
*ring
;
2608 u64 rb_addr
, rptr_addr
;
2611 WREG32(mmCP_SEM_WAIT_TIMER
, 0x0);
2612 if (adev
->asic_type
!= CHIP_HAWAII
)
2613 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL
, 0x0);
2615 /* Set the write pointer delay */
2616 WREG32(mmCP_RB_WPTR_DELAY
, 0);
2618 /* set the RB to use vmid 0 */
2619 WREG32(mmCP_RB_VMID
, 0);
2621 WREG32(mmSCRATCH_ADDR
, 0);
2623 /* ring 0 - compute and gfx */
2624 /* Set ring buffer size */
2625 ring
= &adev
->gfx
.gfx_ring
[0];
2626 rb_bufsz
= order_base_2(ring
->ring_size
/ 8);
2627 tmp
= (order_base_2(AMDGPU_GPU_PAGE_SIZE
/8) << 8) | rb_bufsz
;
2629 tmp
|= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT
;
2631 WREG32(mmCP_RB0_CNTL
, tmp
);
2633 /* Initialize the ring buffer's read and write pointers */
2634 WREG32(mmCP_RB0_CNTL
, tmp
| CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK
);
2636 WREG32(mmCP_RB0_WPTR
, lower_32_bits(ring
->wptr
));
2638 /* set the wb address wether it's enabled or not */
2639 rptr_addr
= adev
->wb
.gpu_addr
+ (ring
->rptr_offs
* 4);
2640 WREG32(mmCP_RB0_RPTR_ADDR
, lower_32_bits(rptr_addr
));
2641 WREG32(mmCP_RB0_RPTR_ADDR_HI
, upper_32_bits(rptr_addr
) & 0xFF);
2643 /* scratch register shadowing is no longer supported */
2644 WREG32(mmSCRATCH_UMSK
, 0);
2647 WREG32(mmCP_RB0_CNTL
, tmp
);
2649 rb_addr
= ring
->gpu_addr
>> 8;
2650 WREG32(mmCP_RB0_BASE
, rb_addr
);
2651 WREG32(mmCP_RB0_BASE_HI
, upper_32_bits(rb_addr
));
2653 /* start the ring */
2654 gfx_v7_0_cp_gfx_start(adev
);
2656 r
= amdgpu_ring_test_ring(ring
);
2658 ring
->ready
= false;
2665 static u64
gfx_v7_0_ring_get_rptr(struct amdgpu_ring
*ring
)
2667 return ring
->adev
->wb
.wb
[ring
->rptr_offs
];
2670 static u64
gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring
*ring
)
2672 struct amdgpu_device
*adev
= ring
->adev
;
2674 return RREG32(mmCP_RB0_WPTR
);
2677 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring
*ring
)
2679 struct amdgpu_device
*adev
= ring
->adev
;
2681 WREG32(mmCP_RB0_WPTR
, lower_32_bits(ring
->wptr
));
2682 (void)RREG32(mmCP_RB0_WPTR
);
2685 static u64
gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring
*ring
)
2687 /* XXX check if swapping is necessary on BE */
2688 return ring
->adev
->wb
.wb
[ring
->wptr_offs
];
2691 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring
*ring
)
2693 struct amdgpu_device
*adev
= ring
->adev
;
2695 /* XXX check if swapping is necessary on BE */
2696 adev
->wb
.wb
[ring
->wptr_offs
] = lower_32_bits(ring
->wptr
);
2697 WDOORBELL32(ring
->doorbell_index
, lower_32_bits(ring
->wptr
));
2701 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2703 * @adev: amdgpu_device pointer
2704 * @enable: enable or disable the MEs
2706 * Halts or unhalts the compute MEs.
2708 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device
*adev
, bool enable
)
2713 WREG32(mmCP_MEC_CNTL
, 0);
2715 WREG32(mmCP_MEC_CNTL
, (CP_MEC_CNTL__MEC_ME1_HALT_MASK
| CP_MEC_CNTL__MEC_ME2_HALT_MASK
));
2716 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++)
2717 adev
->gfx
.compute_ring
[i
].ready
= false;
2723 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2725 * @adev: amdgpu_device pointer
2727 * Loads the compute MEC1&2 ucode.
2728 * Returns 0 for success, -EINVAL if the ucode is not available.
2730 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device
*adev
)
2732 const struct gfx_firmware_header_v1_0
*mec_hdr
;
2733 const __le32
*fw_data
;
2734 unsigned i
, fw_size
;
2736 if (!adev
->gfx
.mec_fw
)
2739 mec_hdr
= (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.mec_fw
->data
;
2740 amdgpu_ucode_print_gfx_hdr(&mec_hdr
->header
);
2741 adev
->gfx
.mec_fw_version
= le32_to_cpu(mec_hdr
->header
.ucode_version
);
2742 adev
->gfx
.mec_feature_version
= le32_to_cpu(
2743 mec_hdr
->ucode_feature_version
);
2745 gfx_v7_0_cp_compute_enable(adev
, false);
2748 fw_data
= (const __le32
*)
2749 (adev
->gfx
.mec_fw
->data
+
2750 le32_to_cpu(mec_hdr
->header
.ucode_array_offset_bytes
));
2751 fw_size
= le32_to_cpu(mec_hdr
->header
.ucode_size_bytes
) / 4;
2752 WREG32(mmCP_MEC_ME1_UCODE_ADDR
, 0);
2753 for (i
= 0; i
< fw_size
; i
++)
2754 WREG32(mmCP_MEC_ME1_UCODE_DATA
, le32_to_cpup(fw_data
++));
2755 WREG32(mmCP_MEC_ME1_UCODE_ADDR
, 0);
2757 if (adev
->asic_type
== CHIP_KAVERI
) {
2758 const struct gfx_firmware_header_v1_0
*mec2_hdr
;
2760 if (!adev
->gfx
.mec2_fw
)
2763 mec2_hdr
= (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.mec2_fw
->data
;
2764 amdgpu_ucode_print_gfx_hdr(&mec2_hdr
->header
);
2765 adev
->gfx
.mec2_fw_version
= le32_to_cpu(mec2_hdr
->header
.ucode_version
);
2766 adev
->gfx
.mec2_feature_version
= le32_to_cpu(
2767 mec2_hdr
->ucode_feature_version
);
2770 fw_data
= (const __le32
*)
2771 (adev
->gfx
.mec2_fw
->data
+
2772 le32_to_cpu(mec2_hdr
->header
.ucode_array_offset_bytes
));
2773 fw_size
= le32_to_cpu(mec2_hdr
->header
.ucode_size_bytes
) / 4;
2774 WREG32(mmCP_MEC_ME2_UCODE_ADDR
, 0);
2775 for (i
= 0; i
< fw_size
; i
++)
2776 WREG32(mmCP_MEC_ME2_UCODE_DATA
, le32_to_cpup(fw_data
++));
2777 WREG32(mmCP_MEC_ME2_UCODE_ADDR
, 0);
2784 * gfx_v7_0_cp_compute_fini - stop the compute queues
2786 * @adev: amdgpu_device pointer
2788 * Stop the compute queues and tear down the driver queue
2791 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device
*adev
)
2795 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++) {
2796 struct amdgpu_ring
*ring
= &adev
->gfx
.compute_ring
[i
];
2798 amdgpu_bo_free_kernel(&ring
->mqd_obj
, NULL
, NULL
);
2802 static void gfx_v7_0_mec_fini(struct amdgpu_device
*adev
)
2804 amdgpu_bo_free_kernel(&adev
->gfx
.mec
.hpd_eop_obj
, NULL
, NULL
);
2807 static int gfx_v7_0_mec_init(struct amdgpu_device
*adev
)
2811 size_t mec_hpd_size
;
2813 bitmap_zero(adev
->gfx
.mec
.queue_bitmap
, AMDGPU_MAX_COMPUTE_QUEUES
);
2815 /* take ownership of the relevant compute queues */
2816 amdgpu_gfx_compute_queue_acquire(adev
);
2818 /* allocate space for ALL pipes (even the ones we don't own) */
2819 mec_hpd_size
= adev
->gfx
.mec
.num_mec
* adev
->gfx
.mec
.num_pipe_per_mec
2820 * GFX7_MEC_HPD_SIZE
* 2;
2822 r
= amdgpu_bo_create_reserved(adev
, mec_hpd_size
, PAGE_SIZE
,
2823 AMDGPU_GEM_DOMAIN_GTT
,
2824 &adev
->gfx
.mec
.hpd_eop_obj
,
2825 &adev
->gfx
.mec
.hpd_eop_gpu_addr
,
2828 dev_warn(adev
->dev
, "(%d) create, pin or map of HDP EOP bo failed\n", r
);
2829 gfx_v7_0_mec_fini(adev
);
2833 /* clear memory. Not sure if this is required or not */
2834 memset(hpd
, 0, mec_hpd_size
);
2836 amdgpu_bo_kunmap(adev
->gfx
.mec
.hpd_eop_obj
);
2837 amdgpu_bo_unreserve(adev
->gfx
.mec
.hpd_eop_obj
);
2842 struct hqd_registers
2844 u32 cp_mqd_base_addr
;
2845 u32 cp_mqd_base_addr_hi
;
2848 u32 cp_hqd_persistent_state
;
2849 u32 cp_hqd_pipe_priority
;
2850 u32 cp_hqd_queue_priority
;
2853 u32 cp_hqd_pq_base_hi
;
2855 u32 cp_hqd_pq_rptr_report_addr
;
2856 u32 cp_hqd_pq_rptr_report_addr_hi
;
2857 u32 cp_hqd_pq_wptr_poll_addr
;
2858 u32 cp_hqd_pq_wptr_poll_addr_hi
;
2859 u32 cp_hqd_pq_doorbell_control
;
2861 u32 cp_hqd_pq_control
;
2862 u32 cp_hqd_ib_base_addr
;
2863 u32 cp_hqd_ib_base_addr_hi
;
2865 u32 cp_hqd_ib_control
;
2866 u32 cp_hqd_iq_timer
;
2868 u32 cp_hqd_dequeue_request
;
2869 u32 cp_hqd_dma_offload
;
2870 u32 cp_hqd_sema_cmd
;
2871 u32 cp_hqd_msg_type
;
2872 u32 cp_hqd_atomic0_preop_lo
;
2873 u32 cp_hqd_atomic0_preop_hi
;
2874 u32 cp_hqd_atomic1_preop_lo
;
2875 u32 cp_hqd_atomic1_preop_hi
;
2876 u32 cp_hqd_hq_scheduler0
;
2877 u32 cp_hqd_hq_scheduler1
;
2881 static void gfx_v7_0_compute_pipe_init(struct amdgpu_device
*adev
,
2886 size_t eop_offset
= (mec
* adev
->gfx
.mec
.num_pipe_per_mec
+ pipe
)
2887 * GFX7_MEC_HPD_SIZE
* 2;
2889 mutex_lock(&adev
->srbm_mutex
);
2890 eop_gpu_addr
= adev
->gfx
.mec
.hpd_eop_gpu_addr
+ eop_offset
;
2892 cik_srbm_select(adev
, mec
+ 1, pipe
, 0, 0);
2894 /* write the EOP addr */
2895 WREG32(mmCP_HPD_EOP_BASE_ADDR
, eop_gpu_addr
>> 8);
2896 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI
, upper_32_bits(eop_gpu_addr
) >> 8);
2898 /* set the VMID assigned */
2899 WREG32(mmCP_HPD_EOP_VMID
, 0);
2901 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2902 tmp
= RREG32(mmCP_HPD_EOP_CONTROL
);
2903 tmp
&= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK
;
2904 tmp
|= order_base_2(GFX7_MEC_HPD_SIZE
/ 8);
2905 WREG32(mmCP_HPD_EOP_CONTROL
, tmp
);
2907 cik_srbm_select(adev
, 0, 0, 0, 0);
2908 mutex_unlock(&adev
->srbm_mutex
);
2911 static int gfx_v7_0_mqd_deactivate(struct amdgpu_device
*adev
)
2915 /* disable the queue if it's active */
2916 if (RREG32(mmCP_HQD_ACTIVE
) & 1) {
2917 WREG32(mmCP_HQD_DEQUEUE_REQUEST
, 1);
2918 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
2919 if (!(RREG32(mmCP_HQD_ACTIVE
) & 1))
2924 if (i
== adev
->usec_timeout
)
2927 WREG32(mmCP_HQD_DEQUEUE_REQUEST
, 0);
2928 WREG32(mmCP_HQD_PQ_RPTR
, 0);
2929 WREG32(mmCP_HQD_PQ_WPTR
, 0);
2935 static void gfx_v7_0_mqd_init(struct amdgpu_device
*adev
,
2936 struct cik_mqd
*mqd
,
2937 uint64_t mqd_gpu_addr
,
2938 struct amdgpu_ring
*ring
)
2943 /* init the mqd struct */
2944 memset(mqd
, 0, sizeof(struct cik_mqd
));
2946 mqd
->header
= 0xC0310800;
2947 mqd
->compute_static_thread_mgmt_se0
= 0xffffffff;
2948 mqd
->compute_static_thread_mgmt_se1
= 0xffffffff;
2949 mqd
->compute_static_thread_mgmt_se2
= 0xffffffff;
2950 mqd
->compute_static_thread_mgmt_se3
= 0xffffffff;
2952 /* enable doorbell? */
2953 mqd
->cp_hqd_pq_doorbell_control
=
2954 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL
);
2955 if (ring
->use_doorbell
)
2956 mqd
->cp_hqd_pq_doorbell_control
|= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK
;
2958 mqd
->cp_hqd_pq_doorbell_control
&= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK
;
2960 /* set the pointer to the MQD */
2961 mqd
->cp_mqd_base_addr_lo
= mqd_gpu_addr
& 0xfffffffc;
2962 mqd
->cp_mqd_base_addr_hi
= upper_32_bits(mqd_gpu_addr
);
2964 /* set MQD vmid to 0 */
2965 mqd
->cp_mqd_control
= RREG32(mmCP_MQD_CONTROL
);
2966 mqd
->cp_mqd_control
&= ~CP_MQD_CONTROL__VMID_MASK
;
2968 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2969 hqd_gpu_addr
= ring
->gpu_addr
>> 8;
2970 mqd
->cp_hqd_pq_base_lo
= hqd_gpu_addr
;
2971 mqd
->cp_hqd_pq_base_hi
= upper_32_bits(hqd_gpu_addr
);
2973 /* set up the HQD, this is similar to CP_RB0_CNTL */
2974 mqd
->cp_hqd_pq_control
= RREG32(mmCP_HQD_PQ_CONTROL
);
2975 mqd
->cp_hqd_pq_control
&=
2976 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK
|
2977 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK
);
2979 mqd
->cp_hqd_pq_control
|=
2980 order_base_2(ring
->ring_size
/ 8);
2981 mqd
->cp_hqd_pq_control
|=
2982 (order_base_2(AMDGPU_GPU_PAGE_SIZE
/8) << 8);
2984 mqd
->cp_hqd_pq_control
|=
2985 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT
;
2987 mqd
->cp_hqd_pq_control
&=
2988 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK
|
2989 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK
|
2990 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK
);
2991 mqd
->cp_hqd_pq_control
|=
2992 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK
|
2993 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK
; /* assuming kernel queue control */
2995 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2996 wb_gpu_addr
= adev
->wb
.gpu_addr
+ (ring
->wptr_offs
* 4);
2997 mqd
->cp_hqd_pq_wptr_poll_addr_lo
= wb_gpu_addr
& 0xfffffffc;
2998 mqd
->cp_hqd_pq_wptr_poll_addr_hi
= upper_32_bits(wb_gpu_addr
) & 0xffff;
3000 /* set the wb address wether it's enabled or not */
3001 wb_gpu_addr
= adev
->wb
.gpu_addr
+ (ring
->rptr_offs
* 4);
3002 mqd
->cp_hqd_pq_rptr_report_addr_lo
= wb_gpu_addr
& 0xfffffffc;
3003 mqd
->cp_hqd_pq_rptr_report_addr_hi
=
3004 upper_32_bits(wb_gpu_addr
) & 0xffff;
3006 /* enable the doorbell if requested */
3007 if (ring
->use_doorbell
) {
3008 mqd
->cp_hqd_pq_doorbell_control
=
3009 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL
);
3010 mqd
->cp_hqd_pq_doorbell_control
&=
3011 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK
;
3012 mqd
->cp_hqd_pq_doorbell_control
|=
3013 (ring
->doorbell_index
<<
3014 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT
);
3015 mqd
->cp_hqd_pq_doorbell_control
|=
3016 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK
;
3017 mqd
->cp_hqd_pq_doorbell_control
&=
3018 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK
|
3019 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK
);
3022 mqd
->cp_hqd_pq_doorbell_control
= 0;
3025 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3027 mqd
->cp_hqd_pq_wptr
= lower_32_bits(ring
->wptr
);
3028 mqd
->cp_hqd_pq_rptr
= RREG32(mmCP_HQD_PQ_RPTR
);
3030 /* set the vmid for the queue */
3031 mqd
->cp_hqd_vmid
= 0;
3034 mqd
->cp_hqd_ib_control
= RREG32(mmCP_HQD_IB_CONTROL
);
3035 mqd
->cp_hqd_ib_base_addr_lo
= RREG32(mmCP_HQD_IB_BASE_ADDR
);
3036 mqd
->cp_hqd_ib_base_addr_hi
= RREG32(mmCP_HQD_IB_BASE_ADDR_HI
);
3037 mqd
->cp_hqd_ib_rptr
= RREG32(mmCP_HQD_IB_RPTR
);
3038 mqd
->cp_hqd_persistent_state
= RREG32(mmCP_HQD_PERSISTENT_STATE
);
3039 mqd
->cp_hqd_sema_cmd
= RREG32(mmCP_HQD_SEMA_CMD
);
3040 mqd
->cp_hqd_msg_type
= RREG32(mmCP_HQD_MSG_TYPE
);
3041 mqd
->cp_hqd_atomic0_preop_lo
= RREG32(mmCP_HQD_ATOMIC0_PREOP_LO
);
3042 mqd
->cp_hqd_atomic0_preop_hi
= RREG32(mmCP_HQD_ATOMIC0_PREOP_HI
);
3043 mqd
->cp_hqd_atomic1_preop_lo
= RREG32(mmCP_HQD_ATOMIC1_PREOP_LO
);
3044 mqd
->cp_hqd_atomic1_preop_hi
= RREG32(mmCP_HQD_ATOMIC1_PREOP_HI
);
3045 mqd
->cp_hqd_pq_rptr
= RREG32(mmCP_HQD_PQ_RPTR
);
3046 mqd
->cp_hqd_quantum
= RREG32(mmCP_HQD_QUANTUM
);
3047 mqd
->cp_hqd_pipe_priority
= RREG32(mmCP_HQD_PIPE_PRIORITY
);
3048 mqd
->cp_hqd_queue_priority
= RREG32(mmCP_HQD_QUEUE_PRIORITY
);
3049 mqd
->cp_hqd_iq_rptr
= RREG32(mmCP_HQD_IQ_RPTR
);
3051 /* activate the queue */
3052 mqd
->cp_hqd_active
= 1;
3055 int gfx_v7_0_mqd_commit(struct amdgpu_device
*adev
, struct cik_mqd
*mqd
)
3061 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_MQD_CONTROL */
3062 mqd_data
= &mqd
->cp_mqd_base_addr_lo
;
3064 /* disable wptr polling */
3065 tmp
= RREG32(mmCP_PQ_WPTR_POLL_CNTL
);
3066 tmp
= REG_SET_FIELD(tmp
, CP_PQ_WPTR_POLL_CNTL
, EN
, 0);
3067 WREG32(mmCP_PQ_WPTR_POLL_CNTL
, tmp
);
3069 /* program all HQD registers */
3070 for (mqd_reg
= mmCP_HQD_VMID
; mqd_reg
<= mmCP_MQD_CONTROL
; mqd_reg
++)
3071 WREG32(mqd_reg
, mqd_data
[mqd_reg
- mmCP_MQD_BASE_ADDR
]);
3073 /* activate the HQD */
3074 for (mqd_reg
= mmCP_MQD_BASE_ADDR
; mqd_reg
<= mmCP_HQD_ACTIVE
; mqd_reg
++)
3075 WREG32(mqd_reg
, mqd_data
[mqd_reg
- mmCP_MQD_BASE_ADDR
]);
3080 static int gfx_v7_0_compute_queue_init(struct amdgpu_device
*adev
, int ring_id
)
3084 struct cik_mqd
*mqd
;
3085 struct amdgpu_ring
*ring
= &adev
->gfx
.compute_ring
[ring_id
];
3087 r
= amdgpu_bo_create_reserved(adev
, sizeof(struct cik_mqd
), PAGE_SIZE
,
3088 AMDGPU_GEM_DOMAIN_GTT
, &ring
->mqd_obj
,
3089 &mqd_gpu_addr
, (void **)&mqd
);
3091 dev_warn(adev
->dev
, "(%d) create MQD bo failed\n", r
);
3095 mutex_lock(&adev
->srbm_mutex
);
3096 cik_srbm_select(adev
, ring
->me
, ring
->pipe
, ring
->queue
, 0);
3098 gfx_v7_0_mqd_init(adev
, mqd
, mqd_gpu_addr
, ring
);
3099 gfx_v7_0_mqd_deactivate(adev
);
3100 gfx_v7_0_mqd_commit(adev
, mqd
);
3102 cik_srbm_select(adev
, 0, 0, 0, 0);
3103 mutex_unlock(&adev
->srbm_mutex
);
3105 amdgpu_bo_kunmap(ring
->mqd_obj
);
3106 amdgpu_bo_unreserve(ring
->mqd_obj
);
3111 * gfx_v7_0_cp_compute_resume - setup the compute queue registers
3113 * @adev: amdgpu_device pointer
3115 * Program the compute queues and test them to make sure they
3117 * Returns 0 for success, error for failure.
3119 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device
*adev
)
3123 struct amdgpu_ring
*ring
;
3125 /* fix up chicken bits */
3126 tmp
= RREG32(mmCP_CPF_DEBUG
);
3128 WREG32(mmCP_CPF_DEBUG
, tmp
);
3130 /* init all pipes (even the ones we don't own) */
3131 for (i
= 0; i
< adev
->gfx
.mec
.num_mec
; i
++)
3132 for (j
= 0; j
< adev
->gfx
.mec
.num_pipe_per_mec
; j
++)
3133 gfx_v7_0_compute_pipe_init(adev
, i
, j
);
3135 /* init the queues */
3136 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++) {
3137 r
= gfx_v7_0_compute_queue_init(adev
, i
);
3139 gfx_v7_0_cp_compute_fini(adev
);
3144 gfx_v7_0_cp_compute_enable(adev
, true);
3146 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++) {
3147 ring
= &adev
->gfx
.compute_ring
[i
];
3149 r
= amdgpu_ring_test_ring(ring
);
3151 ring
->ready
= false;
3157 static void gfx_v7_0_cp_enable(struct amdgpu_device
*adev
, bool enable
)
3159 gfx_v7_0_cp_gfx_enable(adev
, enable
);
3160 gfx_v7_0_cp_compute_enable(adev
, enable
);
3163 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device
*adev
)
3167 r
= gfx_v7_0_cp_gfx_load_microcode(adev
);
3170 r
= gfx_v7_0_cp_compute_load_microcode(adev
);
3177 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device
*adev
,
3180 u32 tmp
= RREG32(mmCP_INT_CNTL_RING0
);
3183 tmp
|= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK
|
3184 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK
);
3186 tmp
&= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK
|
3187 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK
);
3188 WREG32(mmCP_INT_CNTL_RING0
, tmp
);
3191 static int gfx_v7_0_cp_resume(struct amdgpu_device
*adev
)
3195 gfx_v7_0_enable_gui_idle_interrupt(adev
, false);
3197 r
= gfx_v7_0_cp_load_microcode(adev
);
3201 r
= gfx_v7_0_cp_gfx_resume(adev
);
3204 r
= gfx_v7_0_cp_compute_resume(adev
);
3208 gfx_v7_0_enable_gui_idle_interrupt(adev
, true);
3214 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3216 * @ring: the ring to emmit the commands to
3218 * Sync the command pipeline with the PFP. E.g. wait for everything
3221 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring
*ring
)
3223 int usepfp
= (ring
->funcs
->type
== AMDGPU_RING_TYPE_GFX
);
3224 uint32_t seq
= ring
->fence_drv
.sync_seq
;
3225 uint64_t addr
= ring
->fence_drv
.gpu_addr
;
3227 amdgpu_ring_write(ring
, PACKET3(PACKET3_WAIT_REG_MEM
, 5));
3228 amdgpu_ring_write(ring
, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3229 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3230 WAIT_REG_MEM_ENGINE(usepfp
))); /* pfp or me */
3231 amdgpu_ring_write(ring
, addr
& 0xfffffffc);
3232 amdgpu_ring_write(ring
, upper_32_bits(addr
) & 0xffffffff);
3233 amdgpu_ring_write(ring
, seq
);
3234 amdgpu_ring_write(ring
, 0xffffffff);
3235 amdgpu_ring_write(ring
, 4); /* poll interval */
3238 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3239 amdgpu_ring_write(ring
, PACKET3(PACKET3_SWITCH_BUFFER
, 0));
3240 amdgpu_ring_write(ring
, 0);
3241 amdgpu_ring_write(ring
, PACKET3(PACKET3_SWITCH_BUFFER
, 0));
3242 amdgpu_ring_write(ring
, 0);
3248 * VMID 0 is the physical GPU addresses as used by the kernel.
3249 * VMIDs 1-15 are used for userspace clients and are handled
3250 * by the amdgpu vm/hsa code.
3253 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3255 * @adev: amdgpu_device pointer
3257 * Update the page table base and flush the VM TLB
3258 * using the CP (CIK).
3260 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring
*ring
,
3261 unsigned vm_id
, uint64_t pd_addr
)
3263 int usepfp
= (ring
->funcs
->type
== AMDGPU_RING_TYPE_GFX
);
3265 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
3266 amdgpu_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(usepfp
) |
3267 WRITE_DATA_DST_SEL(0)));
3269 amdgpu_ring_write(ring
,
3270 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ vm_id
));
3272 amdgpu_ring_write(ring
,
3273 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ vm_id
- 8));
3275 amdgpu_ring_write(ring
, 0);
3276 amdgpu_ring_write(ring
, pd_addr
>> 12);
3278 /* bits 0-15 are the VM contexts0-15 */
3279 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
3280 amdgpu_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(0) |
3281 WRITE_DATA_DST_SEL(0)));
3282 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
);
3283 amdgpu_ring_write(ring
, 0);
3284 amdgpu_ring_write(ring
, 1 << vm_id
);
3286 /* wait for the invalidate to complete */
3287 amdgpu_ring_write(ring
, PACKET3(PACKET3_WAIT_REG_MEM
, 5));
3288 amdgpu_ring_write(ring
, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3289 WAIT_REG_MEM_FUNCTION(0) | /* always */
3290 WAIT_REG_MEM_ENGINE(0))); /* me */
3291 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
);
3292 amdgpu_ring_write(ring
, 0);
3293 amdgpu_ring_write(ring
, 0); /* ref */
3294 amdgpu_ring_write(ring
, 0); /* mask */
3295 amdgpu_ring_write(ring
, 0x20); /* poll interval */
3297 /* compute doesn't have PFP */
3299 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3300 amdgpu_ring_write(ring
, PACKET3(PACKET3_PFP_SYNC_ME
, 0));
3301 amdgpu_ring_write(ring
, 0x0);
3303 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3304 amdgpu_ring_write(ring
, PACKET3(PACKET3_SWITCH_BUFFER
, 0));
3305 amdgpu_ring_write(ring
, 0);
3306 amdgpu_ring_write(ring
, PACKET3(PACKET3_SWITCH_BUFFER
, 0));
3307 amdgpu_ring_write(ring
, 0);
3313 * The RLC is a multi-purpose microengine that handles a
3314 * variety of functions.
3316 static void gfx_v7_0_rlc_fini(struct amdgpu_device
*adev
)
3318 amdgpu_bo_free_kernel(&adev
->gfx
.rlc
.save_restore_obj
, NULL
, NULL
);
3319 amdgpu_bo_free_kernel(&adev
->gfx
.rlc
.clear_state_obj
, NULL
, NULL
);
3320 amdgpu_bo_free_kernel(&adev
->gfx
.rlc
.cp_table_obj
, NULL
, NULL
);
3323 static int gfx_v7_0_rlc_init(struct amdgpu_device
*adev
)
3326 volatile u32
*dst_ptr
;
3328 const struct cs_section_def
*cs_data
;
3331 /* allocate rlc buffers */
3332 if (adev
->flags
& AMD_IS_APU
) {
3333 if (adev
->asic_type
== CHIP_KAVERI
) {
3334 adev
->gfx
.rlc
.reg_list
= spectre_rlc_save_restore_register_list
;
3335 adev
->gfx
.rlc
.reg_list_size
=
3336 (u32
)ARRAY_SIZE(spectre_rlc_save_restore_register_list
);
3338 adev
->gfx
.rlc
.reg_list
= kalindi_rlc_save_restore_register_list
;
3339 adev
->gfx
.rlc
.reg_list_size
=
3340 (u32
)ARRAY_SIZE(kalindi_rlc_save_restore_register_list
);
3343 adev
->gfx
.rlc
.cs_data
= ci_cs_data
;
3344 adev
->gfx
.rlc
.cp_table_size
= ALIGN(CP_ME_TABLE_SIZE
* 5 * 4, 2048); /* CP JT */
3345 adev
->gfx
.rlc
.cp_table_size
+= 64 * 1024; /* GDS */
3347 src_ptr
= adev
->gfx
.rlc
.reg_list
;
3348 dws
= adev
->gfx
.rlc
.reg_list_size
;
3349 dws
+= (5 * 16) + 48 + 48 + 64;
3351 cs_data
= adev
->gfx
.rlc
.cs_data
;
3354 /* save restore block */
3355 r
= amdgpu_bo_create_reserved(adev
, dws
* 4, PAGE_SIZE
,
3356 AMDGPU_GEM_DOMAIN_VRAM
,
3357 &adev
->gfx
.rlc
.save_restore_obj
,
3358 &adev
->gfx
.rlc
.save_restore_gpu_addr
,
3359 (void **)&adev
->gfx
.rlc
.sr_ptr
);
3361 dev_warn(adev
->dev
, "(%d) create, pin or map of RLC sr bo failed\n", r
);
3362 gfx_v7_0_rlc_fini(adev
);
3366 /* write the sr buffer */
3367 dst_ptr
= adev
->gfx
.rlc
.sr_ptr
;
3368 for (i
= 0; i
< adev
->gfx
.rlc
.reg_list_size
; i
++)
3369 dst_ptr
[i
] = cpu_to_le32(src_ptr
[i
]);
3370 amdgpu_bo_kunmap(adev
->gfx
.rlc
.save_restore_obj
);
3371 amdgpu_bo_unreserve(adev
->gfx
.rlc
.save_restore_obj
);
3375 /* clear state block */
3376 adev
->gfx
.rlc
.clear_state_size
= dws
= gfx_v7_0_get_csb_size(adev
);
3378 r
= amdgpu_bo_create_reserved(adev
, dws
* 4, PAGE_SIZE
,
3379 AMDGPU_GEM_DOMAIN_VRAM
,
3380 &adev
->gfx
.rlc
.clear_state_obj
,
3381 &adev
->gfx
.rlc
.clear_state_gpu_addr
,
3382 (void **)&adev
->gfx
.rlc
.cs_ptr
);
3384 dev_warn(adev
->dev
, "(%d) create RLC c bo failed\n", r
);
3385 gfx_v7_0_rlc_fini(adev
);
3389 /* set up the cs buffer */
3390 dst_ptr
= adev
->gfx
.rlc
.cs_ptr
;
3391 gfx_v7_0_get_csb_buffer(adev
, dst_ptr
);
3392 amdgpu_bo_kunmap(adev
->gfx
.rlc
.clear_state_obj
);
3393 amdgpu_bo_unreserve(adev
->gfx
.rlc
.clear_state_obj
);
3396 if (adev
->gfx
.rlc
.cp_table_size
) {
3398 r
= amdgpu_bo_create_reserved(adev
, adev
->gfx
.rlc
.cp_table_size
,
3399 PAGE_SIZE
, AMDGPU_GEM_DOMAIN_VRAM
,
3400 &adev
->gfx
.rlc
.cp_table_obj
,
3401 &adev
->gfx
.rlc
.cp_table_gpu_addr
,
3402 (void **)&adev
->gfx
.rlc
.cp_table_ptr
);
3404 dev_warn(adev
->dev
, "(%d) create RLC cp table bo failed\n", r
);
3405 gfx_v7_0_rlc_fini(adev
);
3409 gfx_v7_0_init_cp_pg_table(adev
);
3411 amdgpu_bo_kunmap(adev
->gfx
.rlc
.cp_table_obj
);
3412 amdgpu_bo_unreserve(adev
->gfx
.rlc
.cp_table_obj
);
3419 static void gfx_v7_0_enable_lbpw(struct amdgpu_device
*adev
, bool enable
)
3423 tmp
= RREG32(mmRLC_LB_CNTL
);
3425 tmp
|= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK
;
3427 tmp
&= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK
;
3428 WREG32(mmRLC_LB_CNTL
, tmp
);
3431 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device
*adev
)
3436 mutex_lock(&adev
->grbm_idx_mutex
);
3437 for (i
= 0; i
< adev
->gfx
.config
.max_shader_engines
; i
++) {
3438 for (j
= 0; j
< adev
->gfx
.config
.max_sh_per_se
; j
++) {
3439 gfx_v7_0_select_se_sh(adev
, i
, j
, 0xffffffff);
3440 for (k
= 0; k
< adev
->usec_timeout
; k
++) {
3441 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY
) == 0)
3447 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
3448 mutex_unlock(&adev
->grbm_idx_mutex
);
3450 mask
= RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK
|
3451 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK
|
3452 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK
|
3453 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK
;
3454 for (k
= 0; k
< adev
->usec_timeout
; k
++) {
3455 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY
) & mask
) == 0)
3461 static void gfx_v7_0_update_rlc(struct amdgpu_device
*adev
, u32 rlc
)
3465 tmp
= RREG32(mmRLC_CNTL
);
3467 WREG32(mmRLC_CNTL
, rlc
);
3470 static u32
gfx_v7_0_halt_rlc(struct amdgpu_device
*adev
)
3474 orig
= data
= RREG32(mmRLC_CNTL
);
3476 if (data
& RLC_CNTL__RLC_ENABLE_F32_MASK
) {
3479 data
&= ~RLC_CNTL__RLC_ENABLE_F32_MASK
;
3480 WREG32(mmRLC_CNTL
, data
);
3482 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
3483 if ((RREG32(mmRLC_GPM_STAT
) & RLC_GPM_STAT__RLC_BUSY_MASK
) == 0)
3488 gfx_v7_0_wait_for_rlc_serdes(adev
);
3494 static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device
*adev
)
3498 tmp
= 0x1 | (1 << 1);
3499 WREG32(mmRLC_GPR_REG2
, tmp
);
3501 mask
= RLC_GPM_STAT__GFX_POWER_STATUS_MASK
|
3502 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK
;
3503 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
3504 if ((RREG32(mmRLC_GPM_STAT
) & mask
) == mask
)
3509 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
3510 if ((RREG32(mmRLC_GPR_REG2
) & 0x1) == 0)
3516 static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device
*adev
)
3520 tmp
= 0x1 | (0 << 1);
3521 WREG32(mmRLC_GPR_REG2
, tmp
);
3525 * gfx_v7_0_rlc_stop - stop the RLC ME
3527 * @adev: amdgpu_device pointer
3529 * Halt the RLC ME (MicroEngine) (CIK).
3531 static void gfx_v7_0_rlc_stop(struct amdgpu_device
*adev
)
3533 WREG32(mmRLC_CNTL
, 0);
3535 gfx_v7_0_enable_gui_idle_interrupt(adev
, false);
3537 gfx_v7_0_wait_for_rlc_serdes(adev
);
3541 * gfx_v7_0_rlc_start - start the RLC ME
3543 * @adev: amdgpu_device pointer
3545 * Unhalt the RLC ME (MicroEngine) (CIK).
3547 static void gfx_v7_0_rlc_start(struct amdgpu_device
*adev
)
3549 WREG32(mmRLC_CNTL
, RLC_CNTL__RLC_ENABLE_F32_MASK
);
3551 gfx_v7_0_enable_gui_idle_interrupt(adev
, true);
3556 static void gfx_v7_0_rlc_reset(struct amdgpu_device
*adev
)
3558 u32 tmp
= RREG32(mmGRBM_SOFT_RESET
);
3560 tmp
|= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK
;
3561 WREG32(mmGRBM_SOFT_RESET
, tmp
);
3563 tmp
&= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK
;
3564 WREG32(mmGRBM_SOFT_RESET
, tmp
);
3569 * gfx_v7_0_rlc_resume - setup the RLC hw
3571 * @adev: amdgpu_device pointer
3573 * Initialize the RLC registers, load the ucode,
3574 * and start the RLC (CIK).
3575 * Returns 0 for success, -EINVAL if the ucode is not available.
3577 static int gfx_v7_0_rlc_resume(struct amdgpu_device
*adev
)
3579 const struct rlc_firmware_header_v1_0
*hdr
;
3580 const __le32
*fw_data
;
3581 unsigned i
, fw_size
;
3584 if (!adev
->gfx
.rlc_fw
)
3587 hdr
= (const struct rlc_firmware_header_v1_0
*)adev
->gfx
.rlc_fw
->data
;
3588 amdgpu_ucode_print_rlc_hdr(&hdr
->header
);
3589 adev
->gfx
.rlc_fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
3590 adev
->gfx
.rlc_feature_version
= le32_to_cpu(
3591 hdr
->ucode_feature_version
);
3593 gfx_v7_0_rlc_stop(adev
);
3596 tmp
= RREG32(mmRLC_CGCG_CGLS_CTRL
) & 0xfffffffc;
3597 WREG32(mmRLC_CGCG_CGLS_CTRL
, tmp
);
3599 gfx_v7_0_rlc_reset(adev
);
3601 gfx_v7_0_init_pg(adev
);
3603 WREG32(mmRLC_LB_CNTR_INIT
, 0);
3604 WREG32(mmRLC_LB_CNTR_MAX
, 0x00008000);
3606 mutex_lock(&adev
->grbm_idx_mutex
);
3607 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
3608 WREG32(mmRLC_LB_INIT_CU_MASK
, 0xffffffff);
3609 WREG32(mmRLC_LB_PARAMS
, 0x00600408);
3610 WREG32(mmRLC_LB_CNTL
, 0x80000004);
3611 mutex_unlock(&adev
->grbm_idx_mutex
);
3613 WREG32(mmRLC_MC_CNTL
, 0);
3614 WREG32(mmRLC_UCODE_CNTL
, 0);
3616 fw_data
= (const __le32
*)
3617 (adev
->gfx
.rlc_fw
->data
+ le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
3618 fw_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
3619 WREG32(mmRLC_GPM_UCODE_ADDR
, 0);
3620 for (i
= 0; i
< fw_size
; i
++)
3621 WREG32(mmRLC_GPM_UCODE_DATA
, le32_to_cpup(fw_data
++));
3622 WREG32(mmRLC_GPM_UCODE_ADDR
, adev
->gfx
.rlc_fw_version
);
3624 /* XXX - find out what chips support lbpw */
3625 gfx_v7_0_enable_lbpw(adev
, false);
3627 if (adev
->asic_type
== CHIP_BONAIRE
)
3628 WREG32(mmRLC_DRIVER_CPDMA_STATUS
, 0);
3630 gfx_v7_0_rlc_start(adev
);
3635 static void gfx_v7_0_enable_cgcg(struct amdgpu_device
*adev
, bool enable
)
3637 u32 data
, orig
, tmp
, tmp2
;
3639 orig
= data
= RREG32(mmRLC_CGCG_CGLS_CTRL
);
3641 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_CGCG
)) {
3642 gfx_v7_0_enable_gui_idle_interrupt(adev
, true);
3644 tmp
= gfx_v7_0_halt_rlc(adev
);
3646 mutex_lock(&adev
->grbm_idx_mutex
);
3647 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
3648 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK
, 0xffffffff);
3649 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK
, 0xffffffff);
3650 tmp2
= RLC_SERDES_WR_CTRL__BPM_ADDR_MASK
|
3651 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK
|
3652 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK
;
3653 WREG32(mmRLC_SERDES_WR_CTRL
, tmp2
);
3654 mutex_unlock(&adev
->grbm_idx_mutex
);
3656 gfx_v7_0_update_rlc(adev
, tmp
);
3658 data
|= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK
| RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK
;
3660 WREG32(mmRLC_CGCG_CGLS_CTRL
, data
);
3663 gfx_v7_0_enable_gui_idle_interrupt(adev
, false);
3665 RREG32(mmCB_CGTT_SCLK_CTRL
);
3666 RREG32(mmCB_CGTT_SCLK_CTRL
);
3667 RREG32(mmCB_CGTT_SCLK_CTRL
);
3668 RREG32(mmCB_CGTT_SCLK_CTRL
);
3670 data
&= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK
| RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK
);
3672 WREG32(mmRLC_CGCG_CGLS_CTRL
, data
);
3674 gfx_v7_0_enable_gui_idle_interrupt(adev
, true);
3678 static void gfx_v7_0_enable_mgcg(struct amdgpu_device
*adev
, bool enable
)
3680 u32 data
, orig
, tmp
= 0;
3682 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_MGCG
)) {
3683 if (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_MGLS
) {
3684 if (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_CP_LS
) {
3685 orig
= data
= RREG32(mmCP_MEM_SLP_CNTL
);
3686 data
|= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
;
3688 WREG32(mmCP_MEM_SLP_CNTL
, data
);
3692 orig
= data
= RREG32(mmRLC_CGTT_MGCG_OVERRIDE
);
3696 WREG32(mmRLC_CGTT_MGCG_OVERRIDE
, data
);
3698 tmp
= gfx_v7_0_halt_rlc(adev
);
3700 mutex_lock(&adev
->grbm_idx_mutex
);
3701 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
3702 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK
, 0xffffffff);
3703 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK
, 0xffffffff);
3704 data
= RLC_SERDES_WR_CTRL__BPM_ADDR_MASK
|
3705 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK
;
3706 WREG32(mmRLC_SERDES_WR_CTRL
, data
);
3707 mutex_unlock(&adev
->grbm_idx_mutex
);
3709 gfx_v7_0_update_rlc(adev
, tmp
);
3711 if (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_CGTS
) {
3712 orig
= data
= RREG32(mmCGTS_SM_CTRL_REG
);
3713 data
&= ~CGTS_SM_CTRL_REG__SM_MODE_MASK
;
3714 data
|= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT
);
3715 data
|= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK
;
3716 data
&= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK
;
3717 if ((adev
->cg_flags
& AMD_CG_SUPPORT_GFX_MGLS
) &&
3718 (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_CGTS_LS
))
3719 data
&= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK
;
3720 data
&= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK
;
3721 data
|= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK
;
3722 data
|= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT
);
3724 WREG32(mmCGTS_SM_CTRL_REG
, data
);
3727 orig
= data
= RREG32(mmRLC_CGTT_MGCG_OVERRIDE
);
3730 WREG32(mmRLC_CGTT_MGCG_OVERRIDE
, data
);
3732 data
= RREG32(mmRLC_MEM_SLP_CNTL
);
3733 if (data
& RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK
) {
3734 data
&= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK
;
3735 WREG32(mmRLC_MEM_SLP_CNTL
, data
);
3738 data
= RREG32(mmCP_MEM_SLP_CNTL
);
3739 if (data
& CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
) {
3740 data
&= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
;
3741 WREG32(mmCP_MEM_SLP_CNTL
, data
);
3744 orig
= data
= RREG32(mmCGTS_SM_CTRL_REG
);
3745 data
|= CGTS_SM_CTRL_REG__OVERRIDE_MASK
| CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK
;
3747 WREG32(mmCGTS_SM_CTRL_REG
, data
);
3749 tmp
= gfx_v7_0_halt_rlc(adev
);
3751 mutex_lock(&adev
->grbm_idx_mutex
);
3752 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
3753 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK
, 0xffffffff);
3754 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK
, 0xffffffff);
3755 data
= RLC_SERDES_WR_CTRL__BPM_ADDR_MASK
| RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK
;
3756 WREG32(mmRLC_SERDES_WR_CTRL
, data
);
3757 mutex_unlock(&adev
->grbm_idx_mutex
);
3759 gfx_v7_0_update_rlc(adev
, tmp
);
3763 static void gfx_v7_0_update_cg(struct amdgpu_device
*adev
,
3766 gfx_v7_0_enable_gui_idle_interrupt(adev
, false);
3767 /* order matters! */
3769 gfx_v7_0_enable_mgcg(adev
, true);
3770 gfx_v7_0_enable_cgcg(adev
, true);
3772 gfx_v7_0_enable_cgcg(adev
, false);
3773 gfx_v7_0_enable_mgcg(adev
, false);
3775 gfx_v7_0_enable_gui_idle_interrupt(adev
, true);
3778 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device
*adev
,
3783 orig
= data
= RREG32(mmRLC_PG_CNTL
);
3784 if (enable
&& (adev
->pg_flags
& AMD_PG_SUPPORT_RLC_SMU_HS
))
3785 data
|= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK
;
3787 data
&= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK
;
3789 WREG32(mmRLC_PG_CNTL
, data
);
3792 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device
*adev
,
3797 orig
= data
= RREG32(mmRLC_PG_CNTL
);
3798 if (enable
&& (adev
->pg_flags
& AMD_PG_SUPPORT_RLC_SMU_HS
))
3799 data
|= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK
;
3801 data
&= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK
;
3803 WREG32(mmRLC_PG_CNTL
, data
);
3806 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device
*adev
, bool enable
)
3810 orig
= data
= RREG32(mmRLC_PG_CNTL
);
3811 if (enable
&& (adev
->pg_flags
& AMD_PG_SUPPORT_CP
))
3816 WREG32(mmRLC_PG_CNTL
, data
);
3819 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device
*adev
, bool enable
)
3823 orig
= data
= RREG32(mmRLC_PG_CNTL
);
3824 if (enable
&& (adev
->pg_flags
& AMD_PG_SUPPORT_GDS
))
3829 WREG32(mmRLC_PG_CNTL
, data
);
3832 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device
*adev
)
3834 const __le32
*fw_data
;
3835 volatile u32
*dst_ptr
;
3836 int me
, i
, max_me
= 4;
3838 u32 table_offset
, table_size
;
3840 if (adev
->asic_type
== CHIP_KAVERI
)
3843 if (adev
->gfx
.rlc
.cp_table_ptr
== NULL
)
3846 /* write the cp table buffer */
3847 dst_ptr
= adev
->gfx
.rlc
.cp_table_ptr
;
3848 for (me
= 0; me
< max_me
; me
++) {
3850 const struct gfx_firmware_header_v1_0
*hdr
=
3851 (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.ce_fw
->data
;
3852 fw_data
= (const __le32
*)
3853 (adev
->gfx
.ce_fw
->data
+
3854 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
3855 table_offset
= le32_to_cpu(hdr
->jt_offset
);
3856 table_size
= le32_to_cpu(hdr
->jt_size
);
3857 } else if (me
== 1) {
3858 const struct gfx_firmware_header_v1_0
*hdr
=
3859 (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.pfp_fw
->data
;
3860 fw_data
= (const __le32
*)
3861 (adev
->gfx
.pfp_fw
->data
+
3862 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
3863 table_offset
= le32_to_cpu(hdr
->jt_offset
);
3864 table_size
= le32_to_cpu(hdr
->jt_size
);
3865 } else if (me
== 2) {
3866 const struct gfx_firmware_header_v1_0
*hdr
=
3867 (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.me_fw
->data
;
3868 fw_data
= (const __le32
*)
3869 (adev
->gfx
.me_fw
->data
+
3870 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
3871 table_offset
= le32_to_cpu(hdr
->jt_offset
);
3872 table_size
= le32_to_cpu(hdr
->jt_size
);
3873 } else if (me
== 3) {
3874 const struct gfx_firmware_header_v1_0
*hdr
=
3875 (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.mec_fw
->data
;
3876 fw_data
= (const __le32
*)
3877 (adev
->gfx
.mec_fw
->data
+
3878 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
3879 table_offset
= le32_to_cpu(hdr
->jt_offset
);
3880 table_size
= le32_to_cpu(hdr
->jt_size
);
3882 const struct gfx_firmware_header_v1_0
*hdr
=
3883 (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.mec2_fw
->data
;
3884 fw_data
= (const __le32
*)
3885 (adev
->gfx
.mec2_fw
->data
+
3886 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
3887 table_offset
= le32_to_cpu(hdr
->jt_offset
);
3888 table_size
= le32_to_cpu(hdr
->jt_size
);
3891 for (i
= 0; i
< table_size
; i
++) {
3892 dst_ptr
[bo_offset
+ i
] =
3893 cpu_to_le32(le32_to_cpu(fw_data
[table_offset
+ i
]));
3896 bo_offset
+= table_size
;
3900 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device
*adev
,
3905 if (enable
&& (adev
->pg_flags
& AMD_PG_SUPPORT_GFX_PG
)) {
3906 orig
= data
= RREG32(mmRLC_PG_CNTL
);
3907 data
|= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK
;
3909 WREG32(mmRLC_PG_CNTL
, data
);
3911 orig
= data
= RREG32(mmRLC_AUTO_PG_CTRL
);
3912 data
|= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK
;
3914 WREG32(mmRLC_AUTO_PG_CTRL
, data
);
3916 orig
= data
= RREG32(mmRLC_PG_CNTL
);
3917 data
&= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK
;
3919 WREG32(mmRLC_PG_CNTL
, data
);
3921 orig
= data
= RREG32(mmRLC_AUTO_PG_CTRL
);
3922 data
&= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK
;
3924 WREG32(mmRLC_AUTO_PG_CTRL
, data
);
3926 data
= RREG32(mmDB_RENDER_CONTROL
);
3930 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device
*adev
,
3938 data
= bitmap
<< GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT
;
3939 data
&= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK
;
3941 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG
, data
);
3944 static u32
gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device
*adev
)
3948 data
= RREG32(mmCC_GC_SHADER_ARRAY_CONFIG
);
3949 data
|= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG
);
3951 data
&= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK
;
3952 data
>>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT
;
3954 mask
= amdgpu_gfx_create_bitmask(adev
->gfx
.config
.max_cu_per_sh
);
3956 return (~data
) & mask
;
3959 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device
*adev
)
3963 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK
, adev
->gfx
.cu_info
.ao_cu_mask
);
3965 tmp
= RREG32(mmRLC_MAX_PG_CU
);
3966 tmp
&= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK
;
3967 tmp
|= (adev
->gfx
.cu_info
.number
<< RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT
);
3968 WREG32(mmRLC_MAX_PG_CU
, tmp
);
3971 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device
*adev
,
3976 orig
= data
= RREG32(mmRLC_PG_CNTL
);
3977 if (enable
&& (adev
->pg_flags
& AMD_PG_SUPPORT_GFX_SMG
))
3978 data
|= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK
;
3980 data
&= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK
;
3982 WREG32(mmRLC_PG_CNTL
, data
);
3985 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device
*adev
,
3990 orig
= data
= RREG32(mmRLC_PG_CNTL
);
3991 if (enable
&& (adev
->pg_flags
& AMD_PG_SUPPORT_GFX_DMG
))
3992 data
|= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK
;
3994 data
&= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK
;
3996 WREG32(mmRLC_PG_CNTL
, data
);
3999 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
4000 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
4002 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device
*adev
)
4007 if (adev
->gfx
.rlc
.cs_data
) {
4008 WREG32(mmRLC_GPM_SCRATCH_ADDR
, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET
);
4009 WREG32(mmRLC_GPM_SCRATCH_DATA
, upper_32_bits(adev
->gfx
.rlc
.clear_state_gpu_addr
));
4010 WREG32(mmRLC_GPM_SCRATCH_DATA
, lower_32_bits(adev
->gfx
.rlc
.clear_state_gpu_addr
));
4011 WREG32(mmRLC_GPM_SCRATCH_DATA
, adev
->gfx
.rlc
.clear_state_size
);
4013 WREG32(mmRLC_GPM_SCRATCH_ADDR
, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET
);
4014 for (i
= 0; i
< 3; i
++)
4015 WREG32(mmRLC_GPM_SCRATCH_DATA
, 0);
4017 if (adev
->gfx
.rlc
.reg_list
) {
4018 WREG32(mmRLC_GPM_SCRATCH_ADDR
, RLC_SAVE_AND_RESTORE_STARTING_OFFSET
);
4019 for (i
= 0; i
< adev
->gfx
.rlc
.reg_list_size
; i
++)
4020 WREG32(mmRLC_GPM_SCRATCH_DATA
, adev
->gfx
.rlc
.reg_list
[i
]);
4023 orig
= data
= RREG32(mmRLC_PG_CNTL
);
4024 data
|= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK
;
4026 WREG32(mmRLC_PG_CNTL
, data
);
4028 WREG32(mmRLC_SAVE_AND_RESTORE_BASE
, adev
->gfx
.rlc
.save_restore_gpu_addr
>> 8);
4029 WREG32(mmRLC_JUMP_TABLE_RESTORE
, adev
->gfx
.rlc
.cp_table_gpu_addr
>> 8);
4031 data
= RREG32(mmCP_RB_WPTR_POLL_CNTL
);
4032 data
&= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK
;
4033 data
|= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT
);
4034 WREG32(mmCP_RB_WPTR_POLL_CNTL
, data
);
4037 WREG32(mmRLC_PG_DELAY
, data
);
4039 data
= RREG32(mmRLC_PG_DELAY_2
);
4042 WREG32(mmRLC_PG_DELAY_2
, data
);
4044 data
= RREG32(mmRLC_AUTO_PG_CTRL
);
4045 data
&= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK
;
4046 data
|= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT
);
4047 WREG32(mmRLC_AUTO_PG_CTRL
, data
);
4051 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device
*adev
, bool enable
)
4053 gfx_v7_0_enable_gfx_cgpg(adev
, enable
);
4054 gfx_v7_0_enable_gfx_static_mgpg(adev
, enable
);
4055 gfx_v7_0_enable_gfx_dynamic_mgpg(adev
, enable
);
4058 static u32
gfx_v7_0_get_csb_size(struct amdgpu_device
*adev
)
4061 const struct cs_section_def
*sect
= NULL
;
4062 const struct cs_extent_def
*ext
= NULL
;
4064 if (adev
->gfx
.rlc
.cs_data
== NULL
)
4067 /* begin clear state */
4069 /* context control state */
4072 for (sect
= adev
->gfx
.rlc
.cs_data
; sect
->section
!= NULL
; ++sect
) {
4073 for (ext
= sect
->section
; ext
->extent
!= NULL
; ++ext
) {
4074 if (sect
->id
== SECT_CONTEXT
)
4075 count
+= 2 + ext
->reg_count
;
4080 /* pa_sc_raster_config/pa_sc_raster_config1 */
4082 /* end clear state */
4090 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device
*adev
,
4091 volatile u32
*buffer
)
4094 const struct cs_section_def
*sect
= NULL
;
4095 const struct cs_extent_def
*ext
= NULL
;
4097 if (adev
->gfx
.rlc
.cs_data
== NULL
)
4102 buffer
[count
++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
4103 buffer
[count
++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
);
4105 buffer
[count
++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL
, 1));
4106 buffer
[count
++] = cpu_to_le32(0x80000000);
4107 buffer
[count
++] = cpu_to_le32(0x80000000);
4109 for (sect
= adev
->gfx
.rlc
.cs_data
; sect
->section
!= NULL
; ++sect
) {
4110 for (ext
= sect
->section
; ext
->extent
!= NULL
; ++ext
) {
4111 if (sect
->id
== SECT_CONTEXT
) {
4113 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG
, ext
->reg_count
));
4114 buffer
[count
++] = cpu_to_le32(ext
->reg_index
- PACKET3_SET_CONTEXT_REG_START
);
4115 for (i
= 0; i
< ext
->reg_count
; i
++)
4116 buffer
[count
++] = cpu_to_le32(ext
->extent
[i
]);
4123 buffer
[count
++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG
, 2));
4124 buffer
[count
++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG
- PACKET3_SET_CONTEXT_REG_START
);
4125 switch (adev
->asic_type
) {
4127 buffer
[count
++] = cpu_to_le32(0x16000012);
4128 buffer
[count
++] = cpu_to_le32(0x00000000);
4131 buffer
[count
++] = cpu_to_le32(0x00000000); /* XXX */
4132 buffer
[count
++] = cpu_to_le32(0x00000000);
4136 buffer
[count
++] = cpu_to_le32(0x00000000); /* XXX */
4137 buffer
[count
++] = cpu_to_le32(0x00000000);
4140 buffer
[count
++] = cpu_to_le32(0x3a00161a);
4141 buffer
[count
++] = cpu_to_le32(0x0000002e);
4144 buffer
[count
++] = cpu_to_le32(0x00000000);
4145 buffer
[count
++] = cpu_to_le32(0x00000000);
4149 buffer
[count
++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
4150 buffer
[count
++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE
);
4152 buffer
[count
++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE
, 0));
4153 buffer
[count
++] = cpu_to_le32(0);
4156 static void gfx_v7_0_init_pg(struct amdgpu_device
*adev
)
4158 if (adev
->pg_flags
& (AMD_PG_SUPPORT_GFX_PG
|
4159 AMD_PG_SUPPORT_GFX_SMG
|
4160 AMD_PG_SUPPORT_GFX_DMG
|
4162 AMD_PG_SUPPORT_GDS
|
4163 AMD_PG_SUPPORT_RLC_SMU_HS
)) {
4164 gfx_v7_0_enable_sclk_slowdown_on_pu(adev
, true);
4165 gfx_v7_0_enable_sclk_slowdown_on_pd(adev
, true);
4166 if (adev
->pg_flags
& AMD_PG_SUPPORT_GFX_PG
) {
4167 gfx_v7_0_init_gfx_cgpg(adev
);
4168 gfx_v7_0_enable_cp_pg(adev
, true);
4169 gfx_v7_0_enable_gds_pg(adev
, true);
4171 gfx_v7_0_init_ao_cu_mask(adev
);
4172 gfx_v7_0_update_gfx_pg(adev
, true);
4176 static void gfx_v7_0_fini_pg(struct amdgpu_device
*adev
)
4178 if (adev
->pg_flags
& (AMD_PG_SUPPORT_GFX_PG
|
4179 AMD_PG_SUPPORT_GFX_SMG
|
4180 AMD_PG_SUPPORT_GFX_DMG
|
4182 AMD_PG_SUPPORT_GDS
|
4183 AMD_PG_SUPPORT_RLC_SMU_HS
)) {
4184 gfx_v7_0_update_gfx_pg(adev
, false);
4185 if (adev
->pg_flags
& AMD_PG_SUPPORT_GFX_PG
) {
4186 gfx_v7_0_enable_cp_pg(adev
, false);
4187 gfx_v7_0_enable_gds_pg(adev
, false);
4193 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4195 * @adev: amdgpu_device pointer
4197 * Fetches a GPU clock counter snapshot (SI).
4198 * Returns the 64 bit clock counter snapshot.
4200 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device
*adev
)
4204 mutex_lock(&adev
->gfx
.gpu_clock_mutex
);
4205 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT
, 1);
4206 clock
= (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB
) |
4207 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB
) << 32ULL);
4208 mutex_unlock(&adev
->gfx
.gpu_clock_mutex
);
4212 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring
*ring
,
4214 uint32_t gds_base
, uint32_t gds_size
,
4215 uint32_t gws_base
, uint32_t gws_size
,
4216 uint32_t oa_base
, uint32_t oa_size
)
4218 gds_base
= gds_base
>> AMDGPU_GDS_SHIFT
;
4219 gds_size
= gds_size
>> AMDGPU_GDS_SHIFT
;
4221 gws_base
= gws_base
>> AMDGPU_GWS_SHIFT
;
4222 gws_size
= gws_size
>> AMDGPU_GWS_SHIFT
;
4224 oa_base
= oa_base
>> AMDGPU_OA_SHIFT
;
4225 oa_size
= oa_size
>> AMDGPU_OA_SHIFT
;
4228 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
4229 amdgpu_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(0) |
4230 WRITE_DATA_DST_SEL(0)));
4231 amdgpu_ring_write(ring
, amdgpu_gds_reg_offset
[vmid
].mem_base
);
4232 amdgpu_ring_write(ring
, 0);
4233 amdgpu_ring_write(ring
, gds_base
);
4236 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
4237 amdgpu_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(0) |
4238 WRITE_DATA_DST_SEL(0)));
4239 amdgpu_ring_write(ring
, amdgpu_gds_reg_offset
[vmid
].mem_size
);
4240 amdgpu_ring_write(ring
, 0);
4241 amdgpu_ring_write(ring
, gds_size
);
4244 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
4245 amdgpu_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(0) |
4246 WRITE_DATA_DST_SEL(0)));
4247 amdgpu_ring_write(ring
, amdgpu_gds_reg_offset
[vmid
].gws
);
4248 amdgpu_ring_write(ring
, 0);
4249 amdgpu_ring_write(ring
, gws_size
<< GDS_GWS_VMID0__SIZE__SHIFT
| gws_base
);
4252 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
4253 amdgpu_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(0) |
4254 WRITE_DATA_DST_SEL(0)));
4255 amdgpu_ring_write(ring
, amdgpu_gds_reg_offset
[vmid
].oa
);
4256 amdgpu_ring_write(ring
, 0);
4257 amdgpu_ring_write(ring
, (1 << (oa_size
+ oa_base
)) - (1 << oa_base
));
4260 static uint32_t wave_read_ind(struct amdgpu_device
*adev
, uint32_t simd
, uint32_t wave
, uint32_t address
)
4262 WREG32(mmSQ_IND_INDEX
,
4263 (wave
<< SQ_IND_INDEX__WAVE_ID__SHIFT
) |
4264 (simd
<< SQ_IND_INDEX__SIMD_ID__SHIFT
) |
4265 (address
<< SQ_IND_INDEX__INDEX__SHIFT
) |
4266 (SQ_IND_INDEX__FORCE_READ_MASK
));
4267 return RREG32(mmSQ_IND_DATA
);
4270 static void wave_read_regs(struct amdgpu_device
*adev
, uint32_t simd
,
4271 uint32_t wave
, uint32_t thread
,
4272 uint32_t regno
, uint32_t num
, uint32_t *out
)
4274 WREG32(mmSQ_IND_INDEX
,
4275 (wave
<< SQ_IND_INDEX__WAVE_ID__SHIFT
) |
4276 (simd
<< SQ_IND_INDEX__SIMD_ID__SHIFT
) |
4277 (regno
<< SQ_IND_INDEX__INDEX__SHIFT
) |
4278 (thread
<< SQ_IND_INDEX__THREAD_ID__SHIFT
) |
4279 (SQ_IND_INDEX__FORCE_READ_MASK
) |
4280 (SQ_IND_INDEX__AUTO_INCR_MASK
));
4282 *(out
++) = RREG32(mmSQ_IND_DATA
);
4285 static void gfx_v7_0_read_wave_data(struct amdgpu_device
*adev
, uint32_t simd
, uint32_t wave
, uint32_t *dst
, int *no_fields
)
4287 /* type 0 wave data */
4288 dst
[(*no_fields
)++] = 0;
4289 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_STATUS
);
4290 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_PC_LO
);
4291 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_PC_HI
);
4292 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_EXEC_LO
);
4293 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_EXEC_HI
);
4294 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_HW_ID
);
4295 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_INST_DW0
);
4296 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_INST_DW1
);
4297 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_GPR_ALLOC
);
4298 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_LDS_ALLOC
);
4299 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_TRAPSTS
);
4300 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_IB_STS
);
4301 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_TBA_LO
);
4302 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_TBA_HI
);
4303 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_TMA_LO
);
4304 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_TMA_HI
);
4305 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_IB_DBG0
);
4306 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_M0
);
4309 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device
*adev
, uint32_t simd
,
4310 uint32_t wave
, uint32_t start
,
4311 uint32_t size
, uint32_t *dst
)
4314 adev
, simd
, wave
, 0,
4315 start
+ SQIND_WAVE_SGPRS_OFFSET
, size
, dst
);
4318 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs
= {
4319 .get_gpu_clock_counter
= &gfx_v7_0_get_gpu_clock_counter
,
4320 .select_se_sh
= &gfx_v7_0_select_se_sh
,
4321 .read_wave_data
= &gfx_v7_0_read_wave_data
,
4322 .read_wave_sgprs
= &gfx_v7_0_read_wave_sgprs
,
4325 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs
= {
4326 .enter_safe_mode
= gfx_v7_0_enter_rlc_safe_mode
,
4327 .exit_safe_mode
= gfx_v7_0_exit_rlc_safe_mode
4330 static int gfx_v7_0_early_init(void *handle
)
4332 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4334 adev
->gfx
.num_gfx_rings
= GFX7_NUM_GFX_RINGS
;
4335 adev
->gfx
.num_compute_rings
= AMDGPU_MAX_COMPUTE_RINGS
;
4336 adev
->gfx
.funcs
= &gfx_v7_0_gfx_funcs
;
4337 adev
->gfx
.rlc
.funcs
= &gfx_v7_0_rlc_funcs
;
4338 gfx_v7_0_set_ring_funcs(adev
);
4339 gfx_v7_0_set_irq_funcs(adev
);
4340 gfx_v7_0_set_gds_init(adev
);
4345 static int gfx_v7_0_late_init(void *handle
)
4347 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4350 r
= amdgpu_irq_get(adev
, &adev
->gfx
.priv_reg_irq
, 0);
4354 r
= amdgpu_irq_get(adev
, &adev
->gfx
.priv_inst_irq
, 0);
4361 static void gfx_v7_0_gpu_early_init(struct amdgpu_device
*adev
)
4364 u32 mc_shared_chmap
, mc_arb_ramcfg
;
4365 u32 dimm00_addr_map
, dimm01_addr_map
, dimm10_addr_map
, dimm11_addr_map
;
4368 switch (adev
->asic_type
) {
4370 adev
->gfx
.config
.max_shader_engines
= 2;
4371 adev
->gfx
.config
.max_tile_pipes
= 4;
4372 adev
->gfx
.config
.max_cu_per_sh
= 7;
4373 adev
->gfx
.config
.max_sh_per_se
= 1;
4374 adev
->gfx
.config
.max_backends_per_se
= 2;
4375 adev
->gfx
.config
.max_texture_channel_caches
= 4;
4376 adev
->gfx
.config
.max_gprs
= 256;
4377 adev
->gfx
.config
.max_gs_threads
= 32;
4378 adev
->gfx
.config
.max_hw_contexts
= 8;
4380 adev
->gfx
.config
.sc_prim_fifo_size_frontend
= 0x20;
4381 adev
->gfx
.config
.sc_prim_fifo_size_backend
= 0x100;
4382 adev
->gfx
.config
.sc_hiz_tile_fifo_size
= 0x30;
4383 adev
->gfx
.config
.sc_earlyz_tile_fifo_size
= 0x130;
4384 gb_addr_config
= BONAIRE_GB_ADDR_CONFIG_GOLDEN
;
4387 adev
->gfx
.config
.max_shader_engines
= 4;
4388 adev
->gfx
.config
.max_tile_pipes
= 16;
4389 adev
->gfx
.config
.max_cu_per_sh
= 11;
4390 adev
->gfx
.config
.max_sh_per_se
= 1;
4391 adev
->gfx
.config
.max_backends_per_se
= 4;
4392 adev
->gfx
.config
.max_texture_channel_caches
= 16;
4393 adev
->gfx
.config
.max_gprs
= 256;
4394 adev
->gfx
.config
.max_gs_threads
= 32;
4395 adev
->gfx
.config
.max_hw_contexts
= 8;
4397 adev
->gfx
.config
.sc_prim_fifo_size_frontend
= 0x20;
4398 adev
->gfx
.config
.sc_prim_fifo_size_backend
= 0x100;
4399 adev
->gfx
.config
.sc_hiz_tile_fifo_size
= 0x30;
4400 adev
->gfx
.config
.sc_earlyz_tile_fifo_size
= 0x130;
4401 gb_addr_config
= HAWAII_GB_ADDR_CONFIG_GOLDEN
;
4404 adev
->gfx
.config
.max_shader_engines
= 1;
4405 adev
->gfx
.config
.max_tile_pipes
= 4;
4406 if ((adev
->pdev
->device
== 0x1304) ||
4407 (adev
->pdev
->device
== 0x1305) ||
4408 (adev
->pdev
->device
== 0x130C) ||
4409 (adev
->pdev
->device
== 0x130F) ||
4410 (adev
->pdev
->device
== 0x1310) ||
4411 (adev
->pdev
->device
== 0x1311) ||
4412 (adev
->pdev
->device
== 0x131C)) {
4413 adev
->gfx
.config
.max_cu_per_sh
= 8;
4414 adev
->gfx
.config
.max_backends_per_se
= 2;
4415 } else if ((adev
->pdev
->device
== 0x1309) ||
4416 (adev
->pdev
->device
== 0x130A) ||
4417 (adev
->pdev
->device
== 0x130D) ||
4418 (adev
->pdev
->device
== 0x1313) ||
4419 (adev
->pdev
->device
== 0x131D)) {
4420 adev
->gfx
.config
.max_cu_per_sh
= 6;
4421 adev
->gfx
.config
.max_backends_per_se
= 2;
4422 } else if ((adev
->pdev
->device
== 0x1306) ||
4423 (adev
->pdev
->device
== 0x1307) ||
4424 (adev
->pdev
->device
== 0x130B) ||
4425 (adev
->pdev
->device
== 0x130E) ||
4426 (adev
->pdev
->device
== 0x1315) ||
4427 (adev
->pdev
->device
== 0x131B)) {
4428 adev
->gfx
.config
.max_cu_per_sh
= 4;
4429 adev
->gfx
.config
.max_backends_per_se
= 1;
4431 adev
->gfx
.config
.max_cu_per_sh
= 3;
4432 adev
->gfx
.config
.max_backends_per_se
= 1;
4434 adev
->gfx
.config
.max_sh_per_se
= 1;
4435 adev
->gfx
.config
.max_texture_channel_caches
= 4;
4436 adev
->gfx
.config
.max_gprs
= 256;
4437 adev
->gfx
.config
.max_gs_threads
= 16;
4438 adev
->gfx
.config
.max_hw_contexts
= 8;
4440 adev
->gfx
.config
.sc_prim_fifo_size_frontend
= 0x20;
4441 adev
->gfx
.config
.sc_prim_fifo_size_backend
= 0x100;
4442 adev
->gfx
.config
.sc_hiz_tile_fifo_size
= 0x30;
4443 adev
->gfx
.config
.sc_earlyz_tile_fifo_size
= 0x130;
4444 gb_addr_config
= BONAIRE_GB_ADDR_CONFIG_GOLDEN
;
4449 adev
->gfx
.config
.max_shader_engines
= 1;
4450 adev
->gfx
.config
.max_tile_pipes
= 2;
4451 adev
->gfx
.config
.max_cu_per_sh
= 2;
4452 adev
->gfx
.config
.max_sh_per_se
= 1;
4453 adev
->gfx
.config
.max_backends_per_se
= 1;
4454 adev
->gfx
.config
.max_texture_channel_caches
= 2;
4455 adev
->gfx
.config
.max_gprs
= 256;
4456 adev
->gfx
.config
.max_gs_threads
= 16;
4457 adev
->gfx
.config
.max_hw_contexts
= 8;
4459 adev
->gfx
.config
.sc_prim_fifo_size_frontend
= 0x20;
4460 adev
->gfx
.config
.sc_prim_fifo_size_backend
= 0x100;
4461 adev
->gfx
.config
.sc_hiz_tile_fifo_size
= 0x30;
4462 adev
->gfx
.config
.sc_earlyz_tile_fifo_size
= 0x130;
4463 gb_addr_config
= BONAIRE_GB_ADDR_CONFIG_GOLDEN
;
4467 mc_shared_chmap
= RREG32(mmMC_SHARED_CHMAP
);
4468 adev
->gfx
.config
.mc_arb_ramcfg
= RREG32(mmMC_ARB_RAMCFG
);
4469 mc_arb_ramcfg
= adev
->gfx
.config
.mc_arb_ramcfg
;
4471 adev
->gfx
.config
.num_tile_pipes
= adev
->gfx
.config
.max_tile_pipes
;
4472 adev
->gfx
.config
.mem_max_burst_length_bytes
= 256;
4473 if (adev
->flags
& AMD_IS_APU
) {
4474 /* Get memory bank mapping mode. */
4475 tmp
= RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING
);
4476 dimm00_addr_map
= REG_GET_FIELD(tmp
, MC_FUS_DRAM0_BANK_ADDR_MAPPING
, DIMM0ADDRMAP
);
4477 dimm01_addr_map
= REG_GET_FIELD(tmp
, MC_FUS_DRAM0_BANK_ADDR_MAPPING
, DIMM1ADDRMAP
);
4479 tmp
= RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING
);
4480 dimm10_addr_map
= REG_GET_FIELD(tmp
, MC_FUS_DRAM1_BANK_ADDR_MAPPING
, DIMM0ADDRMAP
);
4481 dimm11_addr_map
= REG_GET_FIELD(tmp
, MC_FUS_DRAM1_BANK_ADDR_MAPPING
, DIMM1ADDRMAP
);
4483 /* Validate settings in case only one DIMM installed. */
4484 if ((dimm00_addr_map
== 0) || (dimm00_addr_map
== 3) || (dimm00_addr_map
== 4) || (dimm00_addr_map
> 12))
4485 dimm00_addr_map
= 0;
4486 if ((dimm01_addr_map
== 0) || (dimm01_addr_map
== 3) || (dimm01_addr_map
== 4) || (dimm01_addr_map
> 12))
4487 dimm01_addr_map
= 0;
4488 if ((dimm10_addr_map
== 0) || (dimm10_addr_map
== 3) || (dimm10_addr_map
== 4) || (dimm10_addr_map
> 12))
4489 dimm10_addr_map
= 0;
4490 if ((dimm11_addr_map
== 0) || (dimm11_addr_map
== 3) || (dimm11_addr_map
== 4) || (dimm11_addr_map
> 12))
4491 dimm11_addr_map
= 0;
4493 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4494 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4495 if ((dimm00_addr_map
== 11) || (dimm01_addr_map
== 11) || (dimm10_addr_map
== 11) || (dimm11_addr_map
== 11))
4496 adev
->gfx
.config
.mem_row_size_in_kb
= 2;
4498 adev
->gfx
.config
.mem_row_size_in_kb
= 1;
4500 tmp
= (mc_arb_ramcfg
& MC_ARB_RAMCFG__NOOFCOLS_MASK
) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT
;
4501 adev
->gfx
.config
.mem_row_size_in_kb
= (4 * (1 << (8 + tmp
))) / 1024;
4502 if (adev
->gfx
.config
.mem_row_size_in_kb
> 4)
4503 adev
->gfx
.config
.mem_row_size_in_kb
= 4;
4505 /* XXX use MC settings? */
4506 adev
->gfx
.config
.shader_engine_tile_size
= 32;
4507 adev
->gfx
.config
.num_gpus
= 1;
4508 adev
->gfx
.config
.multi_gpu_tile_size
= 64;
4510 /* fix up row size */
4511 gb_addr_config
&= ~GB_ADDR_CONFIG__ROW_SIZE_MASK
;
4512 switch (adev
->gfx
.config
.mem_row_size_in_kb
) {
4515 gb_addr_config
|= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT
);
4518 gb_addr_config
|= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT
);
4521 gb_addr_config
|= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT
);
4524 adev
->gfx
.config
.gb_addr_config
= gb_addr_config
;
4527 static int gfx_v7_0_compute_ring_init(struct amdgpu_device
*adev
, int ring_id
,
4528 int mec
, int pipe
, int queue
)
4532 struct amdgpu_ring
*ring
= &adev
->gfx
.compute_ring
[ring_id
];
4537 ring
->queue
= queue
;
4539 ring
->ring_obj
= NULL
;
4540 ring
->use_doorbell
= true;
4541 ring
->doorbell_index
= AMDGPU_DOORBELL_MEC_RING0
+ ring_id
;
4542 sprintf(ring
->name
, "comp_%d.%d.%d", ring
->me
, ring
->pipe
, ring
->queue
);
4544 irq_type
= AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4545 + ((ring
->me
- 1) * adev
->gfx
.mec
.num_pipe_per_mec
)
4548 /* type-2 packets are deprecated on MEC, use type-3 instead */
4549 r
= amdgpu_ring_init(adev
, ring
, 1024,
4550 &adev
->gfx
.eop_irq
, irq_type
);
4558 static int gfx_v7_0_sw_init(void *handle
)
4560 struct amdgpu_ring
*ring
;
4561 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4562 int i
, j
, k
, r
, ring_id
;
4564 switch (adev
->asic_type
) {
4566 adev
->gfx
.mec
.num_mec
= 2;
4573 adev
->gfx
.mec
.num_mec
= 1;
4576 adev
->gfx
.mec
.num_pipe_per_mec
= 4;
4577 adev
->gfx
.mec
.num_queue_per_pipe
= 8;
4580 r
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_LEGACY
, 181, &adev
->gfx
.eop_irq
);
4584 /* Privileged reg */
4585 r
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_LEGACY
, 184,
4586 &adev
->gfx
.priv_reg_irq
);
4590 /* Privileged inst */
4591 r
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_LEGACY
, 185,
4592 &adev
->gfx
.priv_inst_irq
);
4596 gfx_v7_0_scratch_init(adev
);
4598 r
= gfx_v7_0_init_microcode(adev
);
4600 DRM_ERROR("Failed to load gfx firmware!\n");
4604 r
= gfx_v7_0_rlc_init(adev
);
4606 DRM_ERROR("Failed to init rlc BOs!\n");
4610 /* allocate mec buffers */
4611 r
= gfx_v7_0_mec_init(adev
);
4613 DRM_ERROR("Failed to init MEC BOs!\n");
4617 for (i
= 0; i
< adev
->gfx
.num_gfx_rings
; i
++) {
4618 ring
= &adev
->gfx
.gfx_ring
[i
];
4619 ring
->ring_obj
= NULL
;
4620 sprintf(ring
->name
, "gfx");
4621 r
= amdgpu_ring_init(adev
, ring
, 1024,
4622 &adev
->gfx
.eop_irq
, AMDGPU_CP_IRQ_GFX_EOP
);
4627 /* set up the compute queues - allocate horizontally across pipes */
4629 for (i
= 0; i
< adev
->gfx
.mec
.num_mec
; ++i
) {
4630 for (j
= 0; j
< adev
->gfx
.mec
.num_queue_per_pipe
; j
++) {
4631 for (k
= 0; k
< adev
->gfx
.mec
.num_pipe_per_mec
; k
++) {
4632 if (!amdgpu_gfx_is_mec_queue_enabled(adev
, i
, k
, j
))
4635 r
= gfx_v7_0_compute_ring_init(adev
,
4646 /* reserve GDS, GWS and OA resource for gfx */
4647 r
= amdgpu_bo_create_kernel(adev
, adev
->gds
.mem
.gfx_partition_size
,
4648 PAGE_SIZE
, AMDGPU_GEM_DOMAIN_GDS
,
4649 &adev
->gds
.gds_gfx_bo
, NULL
, NULL
);
4653 r
= amdgpu_bo_create_kernel(adev
, adev
->gds
.gws
.gfx_partition_size
,
4654 PAGE_SIZE
, AMDGPU_GEM_DOMAIN_GWS
,
4655 &adev
->gds
.gws_gfx_bo
, NULL
, NULL
);
4659 r
= amdgpu_bo_create_kernel(adev
, adev
->gds
.oa
.gfx_partition_size
,
4660 PAGE_SIZE
, AMDGPU_GEM_DOMAIN_OA
,
4661 &adev
->gds
.oa_gfx_bo
, NULL
, NULL
);
4665 adev
->gfx
.ce_ram_size
= 0x8000;
4667 gfx_v7_0_gpu_early_init(adev
);
4672 static int gfx_v7_0_sw_fini(void *handle
)
4675 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4677 amdgpu_bo_free_kernel(&adev
->gds
.oa_gfx_bo
, NULL
, NULL
);
4678 amdgpu_bo_free_kernel(&adev
->gds
.gws_gfx_bo
, NULL
, NULL
);
4679 amdgpu_bo_free_kernel(&adev
->gds
.gds_gfx_bo
, NULL
, NULL
);
4681 for (i
= 0; i
< adev
->gfx
.num_gfx_rings
; i
++)
4682 amdgpu_ring_fini(&adev
->gfx
.gfx_ring
[i
]);
4683 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++)
4684 amdgpu_ring_fini(&adev
->gfx
.compute_ring
[i
]);
4686 gfx_v7_0_cp_compute_fini(adev
);
4687 gfx_v7_0_rlc_fini(adev
);
4688 gfx_v7_0_mec_fini(adev
);
4689 amdgpu_bo_free_kernel(&adev
->gfx
.rlc
.clear_state_obj
,
4690 &adev
->gfx
.rlc
.clear_state_gpu_addr
,
4691 (void **)&adev
->gfx
.rlc
.cs_ptr
);
4692 if (adev
->gfx
.rlc
.cp_table_size
) {
4693 amdgpu_bo_free_kernel(&adev
->gfx
.rlc
.cp_table_obj
,
4694 &adev
->gfx
.rlc
.cp_table_gpu_addr
,
4695 (void **)&adev
->gfx
.rlc
.cp_table_ptr
);
4697 gfx_v7_0_free_microcode(adev
);
4702 static int gfx_v7_0_hw_init(void *handle
)
4705 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4707 gfx_v7_0_gpu_init(adev
);
4710 r
= gfx_v7_0_rlc_resume(adev
);
4714 r
= gfx_v7_0_cp_resume(adev
);
4721 static int gfx_v7_0_hw_fini(void *handle
)
4723 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4725 amdgpu_irq_put(adev
, &adev
->gfx
.priv_reg_irq
, 0);
4726 amdgpu_irq_put(adev
, &adev
->gfx
.priv_inst_irq
, 0);
4727 gfx_v7_0_cp_enable(adev
, false);
4728 gfx_v7_0_rlc_stop(adev
);
4729 gfx_v7_0_fini_pg(adev
);
4734 static int gfx_v7_0_suspend(void *handle
)
4736 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4738 return gfx_v7_0_hw_fini(adev
);
4741 static int gfx_v7_0_resume(void *handle
)
4743 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4745 return gfx_v7_0_hw_init(adev
);
4748 static bool gfx_v7_0_is_idle(void *handle
)
4750 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4752 if (RREG32(mmGRBM_STATUS
) & GRBM_STATUS__GUI_ACTIVE_MASK
)
4758 static int gfx_v7_0_wait_for_idle(void *handle
)
4762 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4764 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
4765 /* read MC_STATUS */
4766 tmp
= RREG32(mmGRBM_STATUS
) & GRBM_STATUS__GUI_ACTIVE_MASK
;
4775 static int gfx_v7_0_soft_reset(void *handle
)
4777 u32 grbm_soft_reset
= 0, srbm_soft_reset
= 0;
4779 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4782 tmp
= RREG32(mmGRBM_STATUS
);
4783 if (tmp
& (GRBM_STATUS__PA_BUSY_MASK
| GRBM_STATUS__SC_BUSY_MASK
|
4784 GRBM_STATUS__BCI_BUSY_MASK
| GRBM_STATUS__SX_BUSY_MASK
|
4785 GRBM_STATUS__TA_BUSY_MASK
| GRBM_STATUS__VGT_BUSY_MASK
|
4786 GRBM_STATUS__DB_BUSY_MASK
| GRBM_STATUS__CB_BUSY_MASK
|
4787 GRBM_STATUS__GDS_BUSY_MASK
| GRBM_STATUS__SPI_BUSY_MASK
|
4788 GRBM_STATUS__IA_BUSY_MASK
| GRBM_STATUS__IA_BUSY_NO_DMA_MASK
))
4789 grbm_soft_reset
|= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK
|
4790 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK
;
4792 if (tmp
& (GRBM_STATUS__CP_BUSY_MASK
| GRBM_STATUS__CP_COHERENCY_BUSY_MASK
)) {
4793 grbm_soft_reset
|= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK
;
4794 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK
;
4798 tmp
= RREG32(mmGRBM_STATUS2
);
4799 if (tmp
& GRBM_STATUS2__RLC_BUSY_MASK
)
4800 grbm_soft_reset
|= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK
;
4803 tmp
= RREG32(mmSRBM_STATUS
);
4804 if (tmp
& SRBM_STATUS__GRBM_RQ_PENDING_MASK
)
4805 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK
;
4807 if (grbm_soft_reset
|| srbm_soft_reset
) {
4809 gfx_v7_0_fini_pg(adev
);
4810 gfx_v7_0_update_cg(adev
, false);
4813 gfx_v7_0_rlc_stop(adev
);
4815 /* Disable GFX parsing/prefetching */
4816 WREG32(mmCP_ME_CNTL
, CP_ME_CNTL__ME_HALT_MASK
| CP_ME_CNTL__PFP_HALT_MASK
| CP_ME_CNTL__CE_HALT_MASK
);
4818 /* Disable MEC parsing/prefetching */
4819 WREG32(mmCP_MEC_CNTL
, CP_MEC_CNTL__MEC_ME1_HALT_MASK
| CP_MEC_CNTL__MEC_ME2_HALT_MASK
);
4821 if (grbm_soft_reset
) {
4822 tmp
= RREG32(mmGRBM_SOFT_RESET
);
4823 tmp
|= grbm_soft_reset
;
4824 dev_info(adev
->dev
, "GRBM_SOFT_RESET=0x%08X\n", tmp
);
4825 WREG32(mmGRBM_SOFT_RESET
, tmp
);
4826 tmp
= RREG32(mmGRBM_SOFT_RESET
);
4830 tmp
&= ~grbm_soft_reset
;
4831 WREG32(mmGRBM_SOFT_RESET
, tmp
);
4832 tmp
= RREG32(mmGRBM_SOFT_RESET
);
4835 if (srbm_soft_reset
) {
4836 tmp
= RREG32(mmSRBM_SOFT_RESET
);
4837 tmp
|= srbm_soft_reset
;
4838 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
4839 WREG32(mmSRBM_SOFT_RESET
, tmp
);
4840 tmp
= RREG32(mmSRBM_SOFT_RESET
);
4844 tmp
&= ~srbm_soft_reset
;
4845 WREG32(mmSRBM_SOFT_RESET
, tmp
);
4846 tmp
= RREG32(mmSRBM_SOFT_RESET
);
4848 /* Wait a little for things to settle down */
4854 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device
*adev
,
4855 enum amdgpu_interrupt_state state
)
4860 case AMDGPU_IRQ_STATE_DISABLE
:
4861 cp_int_cntl
= RREG32(mmCP_INT_CNTL_RING0
);
4862 cp_int_cntl
&= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK
;
4863 WREG32(mmCP_INT_CNTL_RING0
, cp_int_cntl
);
4865 case AMDGPU_IRQ_STATE_ENABLE
:
4866 cp_int_cntl
= RREG32(mmCP_INT_CNTL_RING0
);
4867 cp_int_cntl
|= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK
;
4868 WREG32(mmCP_INT_CNTL_RING0
, cp_int_cntl
);
4875 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device
*adev
,
4877 enum amdgpu_interrupt_state state
)
4879 u32 mec_int_cntl
, mec_int_cntl_reg
;
4882 * amdgpu controls only the first MEC. That's why this function only
4883 * handles the setting of interrupts for this specific MEC. All other
4884 * pipes' interrupts are set by amdkfd.
4890 mec_int_cntl_reg
= mmCP_ME1_PIPE0_INT_CNTL
;
4893 mec_int_cntl_reg
= mmCP_ME1_PIPE1_INT_CNTL
;
4896 mec_int_cntl_reg
= mmCP_ME1_PIPE2_INT_CNTL
;
4899 mec_int_cntl_reg
= mmCP_ME1_PIPE3_INT_CNTL
;
4902 DRM_DEBUG("invalid pipe %d\n", pipe
);
4906 DRM_DEBUG("invalid me %d\n", me
);
4911 case AMDGPU_IRQ_STATE_DISABLE
:
4912 mec_int_cntl
= RREG32(mec_int_cntl_reg
);
4913 mec_int_cntl
&= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK
;
4914 WREG32(mec_int_cntl_reg
, mec_int_cntl
);
4916 case AMDGPU_IRQ_STATE_ENABLE
:
4917 mec_int_cntl
= RREG32(mec_int_cntl_reg
);
4918 mec_int_cntl
|= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK
;
4919 WREG32(mec_int_cntl_reg
, mec_int_cntl
);
4926 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device
*adev
,
4927 struct amdgpu_irq_src
*src
,
4929 enum amdgpu_interrupt_state state
)
4934 case AMDGPU_IRQ_STATE_DISABLE
:
4935 cp_int_cntl
= RREG32(mmCP_INT_CNTL_RING0
);
4936 cp_int_cntl
&= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK
;
4937 WREG32(mmCP_INT_CNTL_RING0
, cp_int_cntl
);
4939 case AMDGPU_IRQ_STATE_ENABLE
:
4940 cp_int_cntl
= RREG32(mmCP_INT_CNTL_RING0
);
4941 cp_int_cntl
|= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK
;
4942 WREG32(mmCP_INT_CNTL_RING0
, cp_int_cntl
);
4951 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device
*adev
,
4952 struct amdgpu_irq_src
*src
,
4954 enum amdgpu_interrupt_state state
)
4959 case AMDGPU_IRQ_STATE_DISABLE
:
4960 cp_int_cntl
= RREG32(mmCP_INT_CNTL_RING0
);
4961 cp_int_cntl
&= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK
;
4962 WREG32(mmCP_INT_CNTL_RING0
, cp_int_cntl
);
4964 case AMDGPU_IRQ_STATE_ENABLE
:
4965 cp_int_cntl
= RREG32(mmCP_INT_CNTL_RING0
);
4966 cp_int_cntl
|= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK
;
4967 WREG32(mmCP_INT_CNTL_RING0
, cp_int_cntl
);
4976 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device
*adev
,
4977 struct amdgpu_irq_src
*src
,
4979 enum amdgpu_interrupt_state state
)
4982 case AMDGPU_CP_IRQ_GFX_EOP
:
4983 gfx_v7_0_set_gfx_eop_interrupt_state(adev
, state
);
4985 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
:
4986 gfx_v7_0_set_compute_eop_interrupt_state(adev
, 1, 0, state
);
4988 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP
:
4989 gfx_v7_0_set_compute_eop_interrupt_state(adev
, 1, 1, state
);
4991 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP
:
4992 gfx_v7_0_set_compute_eop_interrupt_state(adev
, 1, 2, state
);
4994 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP
:
4995 gfx_v7_0_set_compute_eop_interrupt_state(adev
, 1, 3, state
);
4997 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP
:
4998 gfx_v7_0_set_compute_eop_interrupt_state(adev
, 2, 0, state
);
5000 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP
:
5001 gfx_v7_0_set_compute_eop_interrupt_state(adev
, 2, 1, state
);
5003 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP
:
5004 gfx_v7_0_set_compute_eop_interrupt_state(adev
, 2, 2, state
);
5006 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP
:
5007 gfx_v7_0_set_compute_eop_interrupt_state(adev
, 2, 3, state
);
5015 static int gfx_v7_0_eop_irq(struct amdgpu_device
*adev
,
5016 struct amdgpu_irq_src
*source
,
5017 struct amdgpu_iv_entry
*entry
)
5020 struct amdgpu_ring
*ring
;
5023 DRM_DEBUG("IH: CP EOP\n");
5024 me_id
= (entry
->ring_id
& 0x0c) >> 2;
5025 pipe_id
= (entry
->ring_id
& 0x03) >> 0;
5028 amdgpu_fence_process(&adev
->gfx
.gfx_ring
[0]);
5032 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++) {
5033 ring
= &adev
->gfx
.compute_ring
[i
];
5034 if ((ring
->me
== me_id
) && (ring
->pipe
== pipe_id
))
5035 amdgpu_fence_process(ring
);
5042 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device
*adev
,
5043 struct amdgpu_irq_src
*source
,
5044 struct amdgpu_iv_entry
*entry
)
5046 DRM_ERROR("Illegal register access in command stream\n");
5047 schedule_work(&adev
->reset_work
);
5051 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device
*adev
,
5052 struct amdgpu_irq_src
*source
,
5053 struct amdgpu_iv_entry
*entry
)
5055 DRM_ERROR("Illegal instruction in command stream\n");
5056 // XXX soft reset the gfx block only
5057 schedule_work(&adev
->reset_work
);
5061 static int gfx_v7_0_set_clockgating_state(void *handle
,
5062 enum amd_clockgating_state state
)
5065 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
5067 if (state
== AMD_CG_STATE_GATE
)
5070 gfx_v7_0_enable_gui_idle_interrupt(adev
, false);
5071 /* order matters! */
5073 gfx_v7_0_enable_mgcg(adev
, true);
5074 gfx_v7_0_enable_cgcg(adev
, true);
5076 gfx_v7_0_enable_cgcg(adev
, false);
5077 gfx_v7_0_enable_mgcg(adev
, false);
5079 gfx_v7_0_enable_gui_idle_interrupt(adev
, true);
5084 static int gfx_v7_0_set_powergating_state(void *handle
,
5085 enum amd_powergating_state state
)
5088 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
5090 if (state
== AMD_PG_STATE_GATE
)
5093 if (adev
->pg_flags
& (AMD_PG_SUPPORT_GFX_PG
|
5094 AMD_PG_SUPPORT_GFX_SMG
|
5095 AMD_PG_SUPPORT_GFX_DMG
|
5097 AMD_PG_SUPPORT_GDS
|
5098 AMD_PG_SUPPORT_RLC_SMU_HS
)) {
5099 gfx_v7_0_update_gfx_pg(adev
, gate
);
5100 if (adev
->pg_flags
& AMD_PG_SUPPORT_GFX_PG
) {
5101 gfx_v7_0_enable_cp_pg(adev
, gate
);
5102 gfx_v7_0_enable_gds_pg(adev
, gate
);
5109 static const struct amd_ip_funcs gfx_v7_0_ip_funcs
= {
5111 .early_init
= gfx_v7_0_early_init
,
5112 .late_init
= gfx_v7_0_late_init
,
5113 .sw_init
= gfx_v7_0_sw_init
,
5114 .sw_fini
= gfx_v7_0_sw_fini
,
5115 .hw_init
= gfx_v7_0_hw_init
,
5116 .hw_fini
= gfx_v7_0_hw_fini
,
5117 .suspend
= gfx_v7_0_suspend
,
5118 .resume
= gfx_v7_0_resume
,
5119 .is_idle
= gfx_v7_0_is_idle
,
5120 .wait_for_idle
= gfx_v7_0_wait_for_idle
,
5121 .soft_reset
= gfx_v7_0_soft_reset
,
5122 .set_clockgating_state
= gfx_v7_0_set_clockgating_state
,
5123 .set_powergating_state
= gfx_v7_0_set_powergating_state
,
5126 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx
= {
5127 .type
= AMDGPU_RING_TYPE_GFX
,
5129 .nop
= PACKET3(PACKET3_NOP
, 0x3FFF),
5130 .support_64bit_ptrs
= false,
5131 .get_rptr
= gfx_v7_0_ring_get_rptr
,
5132 .get_wptr
= gfx_v7_0_ring_get_wptr_gfx
,
5133 .set_wptr
= gfx_v7_0_ring_set_wptr_gfx
,
5135 20 + /* gfx_v7_0_ring_emit_gds_switch */
5136 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5137 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
5138 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
5139 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
5140 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
5141 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
5142 .emit_ib_size
= 4, /* gfx_v7_0_ring_emit_ib_gfx */
5143 .emit_ib
= gfx_v7_0_ring_emit_ib_gfx
,
5144 .emit_fence
= gfx_v7_0_ring_emit_fence_gfx
,
5145 .emit_pipeline_sync
= gfx_v7_0_ring_emit_pipeline_sync
,
5146 .emit_vm_flush
= gfx_v7_0_ring_emit_vm_flush
,
5147 .emit_gds_switch
= gfx_v7_0_ring_emit_gds_switch
,
5148 .emit_hdp_flush
= gfx_v7_0_ring_emit_hdp_flush
,
5149 .emit_hdp_invalidate
= gfx_v7_0_ring_emit_hdp_invalidate
,
5150 .test_ring
= gfx_v7_0_ring_test_ring
,
5151 .test_ib
= gfx_v7_0_ring_test_ib
,
5152 .insert_nop
= amdgpu_ring_insert_nop
,
5153 .pad_ib
= amdgpu_ring_generic_pad_ib
,
5154 .emit_cntxcntl
= gfx_v7_ring_emit_cntxcntl
,
5157 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute
= {
5158 .type
= AMDGPU_RING_TYPE_COMPUTE
,
5160 .nop
= PACKET3(PACKET3_NOP
, 0x3FFF),
5161 .support_64bit_ptrs
= false,
5162 .get_rptr
= gfx_v7_0_ring_get_rptr
,
5163 .get_wptr
= gfx_v7_0_ring_get_wptr_compute
,
5164 .set_wptr
= gfx_v7_0_ring_set_wptr_compute
,
5166 20 + /* gfx_v7_0_ring_emit_gds_switch */
5167 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5168 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
5169 7 + /* gfx_v7_0_ring_emit_pipeline_sync */
5170 17 + /* gfx_v7_0_ring_emit_vm_flush */
5171 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
5172 .emit_ib_size
= 4, /* gfx_v7_0_ring_emit_ib_compute */
5173 .emit_ib
= gfx_v7_0_ring_emit_ib_compute
,
5174 .emit_fence
= gfx_v7_0_ring_emit_fence_compute
,
5175 .emit_pipeline_sync
= gfx_v7_0_ring_emit_pipeline_sync
,
5176 .emit_vm_flush
= gfx_v7_0_ring_emit_vm_flush
,
5177 .emit_gds_switch
= gfx_v7_0_ring_emit_gds_switch
,
5178 .emit_hdp_flush
= gfx_v7_0_ring_emit_hdp_flush
,
5179 .emit_hdp_invalidate
= gfx_v7_0_ring_emit_hdp_invalidate
,
5180 .test_ring
= gfx_v7_0_ring_test_ring
,
5181 .test_ib
= gfx_v7_0_ring_test_ib
,
5182 .insert_nop
= amdgpu_ring_insert_nop
,
5183 .pad_ib
= amdgpu_ring_generic_pad_ib
,
5186 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device
*adev
)
5190 for (i
= 0; i
< adev
->gfx
.num_gfx_rings
; i
++)
5191 adev
->gfx
.gfx_ring
[i
].funcs
= &gfx_v7_0_ring_funcs_gfx
;
5192 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++)
5193 adev
->gfx
.compute_ring
[i
].funcs
= &gfx_v7_0_ring_funcs_compute
;
5196 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs
= {
5197 .set
= gfx_v7_0_set_eop_interrupt_state
,
5198 .process
= gfx_v7_0_eop_irq
,
5201 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs
= {
5202 .set
= gfx_v7_0_set_priv_reg_fault_state
,
5203 .process
= gfx_v7_0_priv_reg_irq
,
5206 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs
= {
5207 .set
= gfx_v7_0_set_priv_inst_fault_state
,
5208 .process
= gfx_v7_0_priv_inst_irq
,
5211 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device
*adev
)
5213 adev
->gfx
.eop_irq
.num_types
= AMDGPU_CP_IRQ_LAST
;
5214 adev
->gfx
.eop_irq
.funcs
= &gfx_v7_0_eop_irq_funcs
;
5216 adev
->gfx
.priv_reg_irq
.num_types
= 1;
5217 adev
->gfx
.priv_reg_irq
.funcs
= &gfx_v7_0_priv_reg_irq_funcs
;
5219 adev
->gfx
.priv_inst_irq
.num_types
= 1;
5220 adev
->gfx
.priv_inst_irq
.funcs
= &gfx_v7_0_priv_inst_irq_funcs
;
5223 static void gfx_v7_0_set_gds_init(struct amdgpu_device
*adev
)
5225 /* init asci gds info */
5226 adev
->gds
.mem
.total_size
= RREG32(mmGDS_VMID0_SIZE
);
5227 adev
->gds
.gws
.total_size
= 64;
5228 adev
->gds
.oa
.total_size
= 16;
5230 if (adev
->gds
.mem
.total_size
== 64 * 1024) {
5231 adev
->gds
.mem
.gfx_partition_size
= 4096;
5232 adev
->gds
.mem
.cs_partition_size
= 4096;
5234 adev
->gds
.gws
.gfx_partition_size
= 4;
5235 adev
->gds
.gws
.cs_partition_size
= 4;
5237 adev
->gds
.oa
.gfx_partition_size
= 4;
5238 adev
->gds
.oa
.cs_partition_size
= 1;
5240 adev
->gds
.mem
.gfx_partition_size
= 1024;
5241 adev
->gds
.mem
.cs_partition_size
= 1024;
5243 adev
->gds
.gws
.gfx_partition_size
= 16;
5244 adev
->gds
.gws
.cs_partition_size
= 16;
5246 adev
->gds
.oa
.gfx_partition_size
= 4;
5247 adev
->gds
.oa
.cs_partition_size
= 4;
5252 static void gfx_v7_0_get_cu_info(struct amdgpu_device
*adev
)
5254 int i
, j
, k
, counter
, active_cu_number
= 0;
5255 u32 mask
, bitmap
, ao_bitmap
, ao_cu_mask
= 0;
5256 struct amdgpu_cu_info
*cu_info
= &adev
->gfx
.cu_info
;
5257 unsigned disable_masks
[4 * 2];
5260 if (adev
->flags
& AMD_IS_APU
)
5263 ao_cu_num
= adev
->gfx
.config
.max_cu_per_sh
;
5265 memset(cu_info
, 0, sizeof(*cu_info
));
5267 amdgpu_gfx_parse_disable_cu(disable_masks
, 4, 2);
5269 mutex_lock(&adev
->grbm_idx_mutex
);
5270 for (i
= 0; i
< adev
->gfx
.config
.max_shader_engines
; i
++) {
5271 for (j
= 0; j
< adev
->gfx
.config
.max_sh_per_se
; j
++) {
5275 gfx_v7_0_select_se_sh(adev
, i
, j
, 0xffffffff);
5277 gfx_v7_0_set_user_cu_inactive_bitmap(
5278 adev
, disable_masks
[i
* 2 + j
]);
5279 bitmap
= gfx_v7_0_get_cu_active_bitmap(adev
);
5280 cu_info
->bitmap
[i
][j
] = bitmap
;
5282 for (k
= 0; k
< adev
->gfx
.config
.max_cu_per_sh
; k
++) {
5283 if (bitmap
& mask
) {
5284 if (counter
< ao_cu_num
)
5290 active_cu_number
+= counter
;
5292 ao_cu_mask
|= (ao_bitmap
<< (i
* 16 + j
* 8));
5293 cu_info
->ao_cu_bitmap
[i
][j
] = ao_bitmap
;
5296 gfx_v7_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
5297 mutex_unlock(&adev
->grbm_idx_mutex
);
5299 cu_info
->number
= active_cu_number
;
5300 cu_info
->ao_cu_mask
= ao_cu_mask
;
5303 const struct amdgpu_ip_block_version gfx_v7_0_ip_block
=
5305 .type
= AMD_IP_BLOCK_TYPE_GFX
,
5309 .funcs
= &gfx_v7_0_ip_funcs
,
5312 const struct amdgpu_ip_block_version gfx_v7_1_ip_block
=
5314 .type
= AMD_IP_BLOCK_TYPE_GFX
,
5318 .funcs
= &gfx_v7_0_ip_funcs
,
5321 const struct amdgpu_ip_block_version gfx_v7_2_ip_block
=
5323 .type
= AMD_IP_BLOCK_TYPE_GFX
,
5327 .funcs
= &gfx_v7_0_ip_funcs
,
5330 const struct amdgpu_ip_block_version gfx_v7_3_ip_block
=
5332 .type
= AMD_IP_BLOCK_TYPE_GFX
,
5336 .funcs
= &gfx_v7_0_ip_funcs
,