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[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v8_0.c
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include "drmP.h"
25 #include "amdgpu.h"
26 #include "amdgpu_gfx.h"
27 #include "vi.h"
28 #include "vid.h"
29 #include "amdgpu_ucode.h"
30 #include "clearstate_vi.h"
31
32 #include "gmc/gmc_8_2_d.h"
33 #include "gmc/gmc_8_2_sh_mask.h"
34
35 #include "oss/oss_3_0_d.h"
36 #include "oss/oss_3_0_sh_mask.h"
37
38 #include "bif/bif_5_0_d.h"
39 #include "bif/bif_5_0_sh_mask.h"
40
41 #include "gca/gfx_8_0_d.h"
42 #include "gca/gfx_8_0_enum.h"
43 #include "gca/gfx_8_0_sh_mask.h"
44 #include "gca/gfx_8_0_enum.h"
45
46 #include "uvd/uvd_5_0_d.h"
47 #include "uvd/uvd_5_0_sh_mask.h"
48
49 #include "dce/dce_10_0_d.h"
50 #include "dce/dce_10_0_sh_mask.h"
51
52 #define GFX8_NUM_GFX_RINGS 1
53 #define GFX8_NUM_COMPUTE_RINGS 8
54
55 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
56 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
57 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
58
59 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
60 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
61 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
62 #define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
63 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
64 #define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
65 #define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
66 #define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
67 #define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
68
69 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
70 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
71 MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
72 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
73 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
74 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
75
76 MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
77 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
78 MODULE_FIRMWARE("amdgpu/tonga_me.bin");
79 MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
80 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
81 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
82
83 MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
84 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
85 MODULE_FIRMWARE("amdgpu/topaz_me.bin");
86 MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
87 MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
88 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
89
90 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
91 {
92 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
93 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
94 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
95 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
96 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
97 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
98 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
99 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
100 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
101 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
102 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
103 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
104 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
105 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
106 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
107 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
108 };
109
110 static const u32 golden_settings_tonga_a11[] =
111 {
112 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
113 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
114 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
115 mmGB_GPU_ID, 0x0000000f, 0x00000000,
116 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
117 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
118 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
119 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
120 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
121 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
122 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
123 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
124 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
125 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
126 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
127 };
128
129 static const u32 tonga_golden_common_all[] =
130 {
131 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
132 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
133 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
134 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
135 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
136 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
137 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
138 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
139 };
140
141 static const u32 tonga_mgcg_cgcg_init[] =
142 {
143 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
144 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
145 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
146 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
147 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
148 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
149 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
150 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
151 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
152 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
153 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
154 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
155 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
156 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
157 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
158 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
159 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
160 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
161 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
162 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
163 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
164 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
165 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
166 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
167 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
168 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
169 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
170 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
171 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
172 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
173 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
174 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
175 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
176 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
177 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
178 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
179 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
180 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
181 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
182 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
183 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
184 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
185 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
186 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
187 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
188 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
189 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
190 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
191 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
192 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
193 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
194 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
195 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
196 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
197 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
198 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
199 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
200 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
201 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
202 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
203 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
204 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
205 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
206 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
207 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
208 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
209 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
210 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
211 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
212 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
213 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
214 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
215 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
216 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
217 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
218 };
219
220 static const u32 golden_settings_iceland_a11[] =
221 {
222 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
223 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
224 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
225 mmGB_GPU_ID, 0x0000000f, 0x00000000,
226 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
227 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
228 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
229 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
230 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
231 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
232 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
233 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
234 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
235 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
236 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
237 };
238
239 static const u32 iceland_golden_common_all[] =
240 {
241 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
242 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
243 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
244 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
245 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
246 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
247 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
248 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
249 };
250
251 static const u32 iceland_mgcg_cgcg_init[] =
252 {
253 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
254 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
255 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
256 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
257 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
258 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
259 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
260 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
261 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
262 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
263 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
264 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
265 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
266 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
267 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
268 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
269 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
270 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
271 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
272 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
273 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
274 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
275 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
276 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
277 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
278 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
279 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
280 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
281 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
282 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
283 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
284 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
285 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
286 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
287 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
288 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
289 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
290 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
291 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
292 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
293 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
294 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
295 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
296 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
297 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
298 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
299 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
300 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
301 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
302 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
303 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
304 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
305 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
306 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
307 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
308 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
309 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
310 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
311 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
312 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
313 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
314 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
315 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
316 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
317 };
318
319 static const u32 cz_golden_settings_a11[] =
320 {
321 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
322 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
323 mmGB_GPU_ID, 0x0000000f, 0x00000000,
324 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
325 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
326 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
327 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
328 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
329 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
330 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
331 };
332
333 static const u32 cz_golden_common_all[] =
334 {
335 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
336 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
337 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
338 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
339 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
340 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
341 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
342 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
343 };
344
345 static const u32 cz_mgcg_cgcg_init[] =
346 {
347 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
348 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
349 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
350 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
351 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
352 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
353 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
354 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
355 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
356 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
357 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
358 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
359 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
360 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
361 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
362 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
363 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
364 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
365 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
366 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
367 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
368 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
369 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
370 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
371 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
372 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
373 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
374 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
375 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
376 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
377 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
378 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
379 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
380 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
381 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
382 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
383 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
384 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
385 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
386 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
387 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
388 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
389 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
390 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
391 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
392 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
393 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
394 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
395 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
396 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
397 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
398 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
399 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
400 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
401 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
402 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
403 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
404 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
405 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
406 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
407 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
408 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
409 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
410 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
411 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
412 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
413 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
414 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
415 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
416 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
417 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
418 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
419 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
420 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
421 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
422 };
423
424 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
425 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
426 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
427
428 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
429 {
430 switch (adev->asic_type) {
431 case CHIP_TOPAZ:
432 amdgpu_program_register_sequence(adev,
433 iceland_mgcg_cgcg_init,
434 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
435 amdgpu_program_register_sequence(adev,
436 golden_settings_iceland_a11,
437 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
438 amdgpu_program_register_sequence(adev,
439 iceland_golden_common_all,
440 (const u32)ARRAY_SIZE(iceland_golden_common_all));
441 break;
442 case CHIP_TONGA:
443 amdgpu_program_register_sequence(adev,
444 tonga_mgcg_cgcg_init,
445 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
446 amdgpu_program_register_sequence(adev,
447 golden_settings_tonga_a11,
448 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
449 amdgpu_program_register_sequence(adev,
450 tonga_golden_common_all,
451 (const u32)ARRAY_SIZE(tonga_golden_common_all));
452 break;
453 case CHIP_CARRIZO:
454 amdgpu_program_register_sequence(adev,
455 cz_mgcg_cgcg_init,
456 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
457 amdgpu_program_register_sequence(adev,
458 cz_golden_settings_a11,
459 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
460 amdgpu_program_register_sequence(adev,
461 cz_golden_common_all,
462 (const u32)ARRAY_SIZE(cz_golden_common_all));
463 break;
464 default:
465 break;
466 }
467 }
468
469 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
470 {
471 int i;
472
473 adev->gfx.scratch.num_reg = 7;
474 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
475 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
476 adev->gfx.scratch.free[i] = true;
477 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
478 }
479 }
480
481 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
482 {
483 struct amdgpu_device *adev = ring->adev;
484 uint32_t scratch;
485 uint32_t tmp = 0;
486 unsigned i;
487 int r;
488
489 r = amdgpu_gfx_scratch_get(adev, &scratch);
490 if (r) {
491 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
492 return r;
493 }
494 WREG32(scratch, 0xCAFEDEAD);
495 r = amdgpu_ring_lock(ring, 3);
496 if (r) {
497 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
498 ring->idx, r);
499 amdgpu_gfx_scratch_free(adev, scratch);
500 return r;
501 }
502 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
503 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
504 amdgpu_ring_write(ring, 0xDEADBEEF);
505 amdgpu_ring_unlock_commit(ring);
506
507 for (i = 0; i < adev->usec_timeout; i++) {
508 tmp = RREG32(scratch);
509 if (tmp == 0xDEADBEEF)
510 break;
511 DRM_UDELAY(1);
512 }
513 if (i < adev->usec_timeout) {
514 DRM_INFO("ring test on %d succeeded in %d usecs\n",
515 ring->idx, i);
516 } else {
517 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
518 ring->idx, scratch, tmp);
519 r = -EINVAL;
520 }
521 amdgpu_gfx_scratch_free(adev, scratch);
522 return r;
523 }
524
525 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
526 {
527 struct amdgpu_device *adev = ring->adev;
528 struct amdgpu_ib ib;
529 uint32_t scratch;
530 uint32_t tmp = 0;
531 unsigned i;
532 int r;
533
534 r = amdgpu_gfx_scratch_get(adev, &scratch);
535 if (r) {
536 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
537 return r;
538 }
539 WREG32(scratch, 0xCAFEDEAD);
540 r = amdgpu_ib_get(ring, NULL, 256, &ib);
541 if (r) {
542 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
543 amdgpu_gfx_scratch_free(adev, scratch);
544 return r;
545 }
546 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
547 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
548 ib.ptr[2] = 0xDEADBEEF;
549 ib.length_dw = 3;
550 r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
551 if (r) {
552 amdgpu_gfx_scratch_free(adev, scratch);
553 amdgpu_ib_free(adev, &ib);
554 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
555 return r;
556 }
557 r = amdgpu_fence_wait(ib.fence, false);
558 if (r) {
559 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
560 amdgpu_gfx_scratch_free(adev, scratch);
561 amdgpu_ib_free(adev, &ib);
562 return r;
563 }
564 for (i = 0; i < adev->usec_timeout; i++) {
565 tmp = RREG32(scratch);
566 if (tmp == 0xDEADBEEF)
567 break;
568 DRM_UDELAY(1);
569 }
570 if (i < adev->usec_timeout) {
571 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
572 ib.fence->ring->idx, i);
573 } else {
574 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
575 scratch, tmp);
576 r = -EINVAL;
577 }
578 amdgpu_gfx_scratch_free(adev, scratch);
579 amdgpu_ib_free(adev, &ib);
580 return r;
581 }
582
583 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
584 {
585 const char *chip_name;
586 char fw_name[30];
587 int err;
588 struct amdgpu_firmware_info *info = NULL;
589 const struct common_firmware_header *header = NULL;
590 const struct gfx_firmware_header_v1_0 *cp_hdr;
591
592 DRM_DEBUG("\n");
593
594 switch (adev->asic_type) {
595 case CHIP_TOPAZ:
596 chip_name = "topaz";
597 break;
598 case CHIP_TONGA:
599 chip_name = "tonga";
600 break;
601 case CHIP_CARRIZO:
602 chip_name = "carrizo";
603 break;
604 default:
605 BUG();
606 }
607
608 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
609 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
610 if (err)
611 goto out;
612 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
613 if (err)
614 goto out;
615 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
616 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
617 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
618
619 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
620 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
621 if (err)
622 goto out;
623 err = amdgpu_ucode_validate(adev->gfx.me_fw);
624 if (err)
625 goto out;
626 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
627 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
628 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
629
630 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
631 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
632 if (err)
633 goto out;
634 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
635 if (err)
636 goto out;
637 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
638 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
639 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
640
641 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
642 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
643 if (err)
644 goto out;
645 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
646 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
647 adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
648 adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
649
650 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
651 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
652 if (err)
653 goto out;
654 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
655 if (err)
656 goto out;
657 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
658 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
659 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
660
661 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
662 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
663 if (!err) {
664 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
665 if (err)
666 goto out;
667 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
668 adev->gfx.mec2_fw->data;
669 adev->gfx.mec2_fw_version = le32_to_cpu(
670 cp_hdr->header.ucode_version);
671 adev->gfx.mec2_feature_version = le32_to_cpu(
672 cp_hdr->ucode_feature_version);
673 } else {
674 err = 0;
675 adev->gfx.mec2_fw = NULL;
676 }
677
678 if (adev->firmware.smu_load) {
679 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
680 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
681 info->fw = adev->gfx.pfp_fw;
682 header = (const struct common_firmware_header *)info->fw->data;
683 adev->firmware.fw_size +=
684 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
685
686 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
687 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
688 info->fw = adev->gfx.me_fw;
689 header = (const struct common_firmware_header *)info->fw->data;
690 adev->firmware.fw_size +=
691 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
692
693 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
694 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
695 info->fw = adev->gfx.ce_fw;
696 header = (const struct common_firmware_header *)info->fw->data;
697 adev->firmware.fw_size +=
698 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
699
700 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
701 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
702 info->fw = adev->gfx.rlc_fw;
703 header = (const struct common_firmware_header *)info->fw->data;
704 adev->firmware.fw_size +=
705 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
706
707 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
708 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
709 info->fw = adev->gfx.mec_fw;
710 header = (const struct common_firmware_header *)info->fw->data;
711 adev->firmware.fw_size +=
712 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
713
714 if (adev->gfx.mec2_fw) {
715 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
716 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
717 info->fw = adev->gfx.mec2_fw;
718 header = (const struct common_firmware_header *)info->fw->data;
719 adev->firmware.fw_size +=
720 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
721 }
722
723 }
724
725 out:
726 if (err) {
727 dev_err(adev->dev,
728 "gfx8: Failed to load firmware \"%s\"\n",
729 fw_name);
730 release_firmware(adev->gfx.pfp_fw);
731 adev->gfx.pfp_fw = NULL;
732 release_firmware(adev->gfx.me_fw);
733 adev->gfx.me_fw = NULL;
734 release_firmware(adev->gfx.ce_fw);
735 adev->gfx.ce_fw = NULL;
736 release_firmware(adev->gfx.rlc_fw);
737 adev->gfx.rlc_fw = NULL;
738 release_firmware(adev->gfx.mec_fw);
739 adev->gfx.mec_fw = NULL;
740 release_firmware(adev->gfx.mec2_fw);
741 adev->gfx.mec2_fw = NULL;
742 }
743 return err;
744 }
745
746 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
747 {
748 int r;
749
750 if (adev->gfx.mec.hpd_eop_obj) {
751 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
752 if (unlikely(r != 0))
753 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
754 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
755 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
756
757 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
758 adev->gfx.mec.hpd_eop_obj = NULL;
759 }
760 }
761
762 #define MEC_HPD_SIZE 2048
763
764 static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
765 {
766 int r;
767 u32 *hpd;
768
769 /*
770 * we assign only 1 pipe because all other pipes will
771 * be handled by KFD
772 */
773 adev->gfx.mec.num_mec = 1;
774 adev->gfx.mec.num_pipe = 1;
775 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
776
777 if (adev->gfx.mec.hpd_eop_obj == NULL) {
778 r = amdgpu_bo_create(adev,
779 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
780 PAGE_SIZE, true,
781 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
782 &adev->gfx.mec.hpd_eop_obj);
783 if (r) {
784 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
785 return r;
786 }
787 }
788
789 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
790 if (unlikely(r != 0)) {
791 gfx_v8_0_mec_fini(adev);
792 return r;
793 }
794 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
795 &adev->gfx.mec.hpd_eop_gpu_addr);
796 if (r) {
797 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
798 gfx_v8_0_mec_fini(adev);
799 return r;
800 }
801 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
802 if (r) {
803 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
804 gfx_v8_0_mec_fini(adev);
805 return r;
806 }
807
808 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
809
810 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
811 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
812
813 return 0;
814 }
815
816 static int gfx_v8_0_sw_init(void *handle)
817 {
818 int i, r;
819 struct amdgpu_ring *ring;
820 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
821
822 /* EOP Event */
823 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
824 if (r)
825 return r;
826
827 /* Privileged reg */
828 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
829 if (r)
830 return r;
831
832 /* Privileged inst */
833 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
834 if (r)
835 return r;
836
837 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
838
839 gfx_v8_0_scratch_init(adev);
840
841 r = gfx_v8_0_init_microcode(adev);
842 if (r) {
843 DRM_ERROR("Failed to load gfx firmware!\n");
844 return r;
845 }
846
847 r = gfx_v8_0_mec_init(adev);
848 if (r) {
849 DRM_ERROR("Failed to init MEC BOs!\n");
850 return r;
851 }
852
853 r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs);
854 if (r) {
855 DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r);
856 return r;
857 }
858
859 /* set up the gfx ring */
860 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
861 ring = &adev->gfx.gfx_ring[i];
862 ring->ring_obj = NULL;
863 sprintf(ring->name, "gfx");
864 /* no gfx doorbells on iceland */
865 if (adev->asic_type != CHIP_TOPAZ) {
866 ring->use_doorbell = true;
867 ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
868 }
869
870 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
871 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
872 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
873 AMDGPU_RING_TYPE_GFX);
874 if (r)
875 return r;
876 }
877
878 /* set up the compute queues */
879 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
880 unsigned irq_type;
881
882 /* max 32 queues per MEC */
883 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
884 DRM_ERROR("Too many (%d) compute rings!\n", i);
885 break;
886 }
887 ring = &adev->gfx.compute_ring[i];
888 ring->ring_obj = NULL;
889 ring->use_doorbell = true;
890 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
891 ring->me = 1; /* first MEC */
892 ring->pipe = i / 8;
893 ring->queue = i % 8;
894 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
895 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
896 /* type-2 packets are deprecated on MEC, use type-3 instead */
897 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
898 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
899 &adev->gfx.eop_irq, irq_type,
900 AMDGPU_RING_TYPE_COMPUTE);
901 if (r)
902 return r;
903 }
904
905 /* reserve GDS, GWS and OA resource for gfx */
906 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
907 PAGE_SIZE, true,
908 AMDGPU_GEM_DOMAIN_GDS, 0,
909 NULL, &adev->gds.gds_gfx_bo);
910 if (r)
911 return r;
912
913 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
914 PAGE_SIZE, true,
915 AMDGPU_GEM_DOMAIN_GWS, 0,
916 NULL, &adev->gds.gws_gfx_bo);
917 if (r)
918 return r;
919
920 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
921 PAGE_SIZE, true,
922 AMDGPU_GEM_DOMAIN_OA, 0,
923 NULL, &adev->gds.oa_gfx_bo);
924 if (r)
925 return r;
926
927 adev->gfx.ce_ram_size = 0x8000;
928
929 return 0;
930 }
931
932 static int gfx_v8_0_sw_fini(void *handle)
933 {
934 int i;
935 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
936
937 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
938 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
939 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
940
941 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
942 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
943 for (i = 0; i < adev->gfx.num_compute_rings; i++)
944 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
945
946 amdgpu_wb_free(adev, adev->gfx.ce_sync_offs);
947
948 gfx_v8_0_mec_fini(adev);
949
950 return 0;
951 }
952
953 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
954 {
955 const u32 num_tile_mode_states = 32;
956 const u32 num_secondary_tile_mode_states = 16;
957 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
958
959 switch (adev->gfx.config.mem_row_size_in_kb) {
960 case 1:
961 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
962 break;
963 case 2:
964 default:
965 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
966 break;
967 case 4:
968 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
969 break;
970 }
971
972 switch (adev->asic_type) {
973 case CHIP_TOPAZ:
974 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
975 switch (reg_offset) {
976 case 0:
977 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
978 PIPE_CONFIG(ADDR_SURF_P2) |
979 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
980 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
981 break;
982 case 1:
983 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
984 PIPE_CONFIG(ADDR_SURF_P2) |
985 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
986 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
987 break;
988 case 2:
989 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
990 PIPE_CONFIG(ADDR_SURF_P2) |
991 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
992 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
993 break;
994 case 3:
995 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
996 PIPE_CONFIG(ADDR_SURF_P2) |
997 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
998 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
999 break;
1000 case 4:
1001 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1002 PIPE_CONFIG(ADDR_SURF_P2) |
1003 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1004 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1005 break;
1006 case 5:
1007 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1008 PIPE_CONFIG(ADDR_SURF_P2) |
1009 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1010 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1011 break;
1012 case 6:
1013 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1014 PIPE_CONFIG(ADDR_SURF_P2) |
1015 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1016 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1017 break;
1018 case 8:
1019 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1020 PIPE_CONFIG(ADDR_SURF_P2));
1021 break;
1022 case 9:
1023 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1024 PIPE_CONFIG(ADDR_SURF_P2) |
1025 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1026 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1027 break;
1028 case 10:
1029 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1030 PIPE_CONFIG(ADDR_SURF_P2) |
1031 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1032 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1033 break;
1034 case 11:
1035 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1036 PIPE_CONFIG(ADDR_SURF_P2) |
1037 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1038 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1039 break;
1040 case 13:
1041 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1042 PIPE_CONFIG(ADDR_SURF_P2) |
1043 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1044 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1045 break;
1046 case 14:
1047 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1048 PIPE_CONFIG(ADDR_SURF_P2) |
1049 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1050 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1051 break;
1052 case 15:
1053 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1054 PIPE_CONFIG(ADDR_SURF_P2) |
1055 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1056 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1057 break;
1058 case 16:
1059 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1060 PIPE_CONFIG(ADDR_SURF_P2) |
1061 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1062 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1063 break;
1064 case 18:
1065 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1066 PIPE_CONFIG(ADDR_SURF_P2) |
1067 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1068 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1069 break;
1070 case 19:
1071 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1072 PIPE_CONFIG(ADDR_SURF_P2) |
1073 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1074 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1075 break;
1076 case 20:
1077 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1078 PIPE_CONFIG(ADDR_SURF_P2) |
1079 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1080 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1081 break;
1082 case 21:
1083 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1084 PIPE_CONFIG(ADDR_SURF_P2) |
1085 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1086 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1087 break;
1088 case 22:
1089 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1090 PIPE_CONFIG(ADDR_SURF_P2) |
1091 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1092 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1093 break;
1094 case 24:
1095 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1096 PIPE_CONFIG(ADDR_SURF_P2) |
1097 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1098 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1099 break;
1100 case 25:
1101 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1102 PIPE_CONFIG(ADDR_SURF_P2) |
1103 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1104 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1105 break;
1106 case 26:
1107 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1108 PIPE_CONFIG(ADDR_SURF_P2) |
1109 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1110 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1111 break;
1112 case 27:
1113 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1114 PIPE_CONFIG(ADDR_SURF_P2) |
1115 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1116 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1117 break;
1118 case 28:
1119 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1120 PIPE_CONFIG(ADDR_SURF_P2) |
1121 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1122 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1123 break;
1124 case 29:
1125 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1126 PIPE_CONFIG(ADDR_SURF_P2) |
1127 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1128 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1129 break;
1130 case 7:
1131 case 12:
1132 case 17:
1133 case 23:
1134 /* unused idx */
1135 continue;
1136 default:
1137 gb_tile_moden = 0;
1138 break;
1139 };
1140 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1141 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1142 }
1143 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1144 switch (reg_offset) {
1145 case 0:
1146 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1147 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1148 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1149 NUM_BANKS(ADDR_SURF_8_BANK));
1150 break;
1151 case 1:
1152 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1153 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1154 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1155 NUM_BANKS(ADDR_SURF_8_BANK));
1156 break;
1157 case 2:
1158 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1159 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1160 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1161 NUM_BANKS(ADDR_SURF_8_BANK));
1162 break;
1163 case 3:
1164 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1167 NUM_BANKS(ADDR_SURF_8_BANK));
1168 break;
1169 case 4:
1170 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1171 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1172 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1173 NUM_BANKS(ADDR_SURF_8_BANK));
1174 break;
1175 case 5:
1176 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1179 NUM_BANKS(ADDR_SURF_8_BANK));
1180 break;
1181 case 6:
1182 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1183 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1184 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1185 NUM_BANKS(ADDR_SURF_8_BANK));
1186 break;
1187 case 8:
1188 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1191 NUM_BANKS(ADDR_SURF_16_BANK));
1192 break;
1193 case 9:
1194 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1195 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1196 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1197 NUM_BANKS(ADDR_SURF_16_BANK));
1198 break;
1199 case 10:
1200 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1201 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1202 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1203 NUM_BANKS(ADDR_SURF_16_BANK));
1204 break;
1205 case 11:
1206 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1207 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1208 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1209 NUM_BANKS(ADDR_SURF_16_BANK));
1210 break;
1211 case 12:
1212 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1213 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1214 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1215 NUM_BANKS(ADDR_SURF_16_BANK));
1216 break;
1217 case 13:
1218 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1219 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1220 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1221 NUM_BANKS(ADDR_SURF_16_BANK));
1222 break;
1223 case 14:
1224 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1225 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1226 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1227 NUM_BANKS(ADDR_SURF_8_BANK));
1228 break;
1229 case 7:
1230 /* unused idx */
1231 continue;
1232 default:
1233 gb_tile_moden = 0;
1234 break;
1235 };
1236 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1237 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1238 }
1239 case CHIP_TONGA:
1240 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1241 switch (reg_offset) {
1242 case 0:
1243 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1244 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1245 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1246 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1247 break;
1248 case 1:
1249 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1250 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1251 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1252 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1253 break;
1254 case 2:
1255 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1256 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1257 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1258 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1259 break;
1260 case 3:
1261 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1262 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1263 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1264 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1265 break;
1266 case 4:
1267 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1268 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1269 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1270 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1271 break;
1272 case 5:
1273 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1274 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1275 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1276 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1277 break;
1278 case 6:
1279 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1280 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1281 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1282 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1283 break;
1284 case 7:
1285 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1286 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1287 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1288 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1289 break;
1290 case 8:
1291 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1292 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
1293 break;
1294 case 9:
1295 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1296 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1297 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1298 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1299 break;
1300 case 10:
1301 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1302 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1303 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1304 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1305 break;
1306 case 11:
1307 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1308 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1309 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1310 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1311 break;
1312 case 12:
1313 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1314 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1315 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1316 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1317 break;
1318 case 13:
1319 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1320 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1321 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1322 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1323 break;
1324 case 14:
1325 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1326 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1327 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1328 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1329 break;
1330 case 15:
1331 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1332 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1333 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1334 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1335 break;
1336 case 16:
1337 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1338 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1339 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1340 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1341 break;
1342 case 17:
1343 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1344 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1345 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1346 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1347 break;
1348 case 18:
1349 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1350 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1351 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1352 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1353 break;
1354 case 19:
1355 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1356 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1357 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1358 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1359 break;
1360 case 20:
1361 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1362 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1363 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1364 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1365 break;
1366 case 21:
1367 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1368 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1369 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1370 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1371 break;
1372 case 22:
1373 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1374 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1375 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1376 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1377 break;
1378 case 23:
1379 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1380 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1381 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1382 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1383 break;
1384 case 24:
1385 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1386 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1387 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1388 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1389 break;
1390 case 25:
1391 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1392 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1393 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1394 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1395 break;
1396 case 26:
1397 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1398 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1399 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1400 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1401 break;
1402 case 27:
1403 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1404 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1405 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1406 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1407 break;
1408 case 28:
1409 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1410 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1411 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1412 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1413 break;
1414 case 29:
1415 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1416 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1417 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1418 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1419 break;
1420 case 30:
1421 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1422 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1423 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1424 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1425 break;
1426 default:
1427 gb_tile_moden = 0;
1428 break;
1429 };
1430 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1431 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1432 }
1433 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1434 switch (reg_offset) {
1435 case 0:
1436 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1437 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1438 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1439 NUM_BANKS(ADDR_SURF_16_BANK));
1440 break;
1441 case 1:
1442 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1443 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1444 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1445 NUM_BANKS(ADDR_SURF_16_BANK));
1446 break;
1447 case 2:
1448 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1449 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1450 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1451 NUM_BANKS(ADDR_SURF_16_BANK));
1452 break;
1453 case 3:
1454 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1455 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1456 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1457 NUM_BANKS(ADDR_SURF_16_BANK));
1458 break;
1459 case 4:
1460 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1461 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1462 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1463 NUM_BANKS(ADDR_SURF_16_BANK));
1464 break;
1465 case 5:
1466 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1467 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1468 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1469 NUM_BANKS(ADDR_SURF_16_BANK));
1470 break;
1471 case 6:
1472 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1473 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1474 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1475 NUM_BANKS(ADDR_SURF_16_BANK));
1476 break;
1477 case 8:
1478 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1479 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1480 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1481 NUM_BANKS(ADDR_SURF_16_BANK));
1482 break;
1483 case 9:
1484 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1485 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1486 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1487 NUM_BANKS(ADDR_SURF_16_BANK));
1488 break;
1489 case 10:
1490 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1491 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1492 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1493 NUM_BANKS(ADDR_SURF_16_BANK));
1494 break;
1495 case 11:
1496 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1497 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1498 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1499 NUM_BANKS(ADDR_SURF_16_BANK));
1500 break;
1501 case 12:
1502 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1503 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1504 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1505 NUM_BANKS(ADDR_SURF_8_BANK));
1506 break;
1507 case 13:
1508 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1509 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1510 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1511 NUM_BANKS(ADDR_SURF_4_BANK));
1512 break;
1513 case 14:
1514 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1515 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1516 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1517 NUM_BANKS(ADDR_SURF_4_BANK));
1518 break;
1519 case 7:
1520 /* unused idx */
1521 continue;
1522 default:
1523 gb_tile_moden = 0;
1524 break;
1525 };
1526 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1527 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1528 }
1529 break;
1530 case CHIP_CARRIZO:
1531 default:
1532 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1533 switch (reg_offset) {
1534 case 0:
1535 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1536 PIPE_CONFIG(ADDR_SURF_P2) |
1537 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1538 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1539 break;
1540 case 1:
1541 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1542 PIPE_CONFIG(ADDR_SURF_P2) |
1543 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1544 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1545 break;
1546 case 2:
1547 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1548 PIPE_CONFIG(ADDR_SURF_P2) |
1549 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1550 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1551 break;
1552 case 3:
1553 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1554 PIPE_CONFIG(ADDR_SURF_P2) |
1555 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1556 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1557 break;
1558 case 4:
1559 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1560 PIPE_CONFIG(ADDR_SURF_P2) |
1561 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1562 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1563 break;
1564 case 5:
1565 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1566 PIPE_CONFIG(ADDR_SURF_P2) |
1567 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1568 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1569 break;
1570 case 6:
1571 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1572 PIPE_CONFIG(ADDR_SURF_P2) |
1573 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1574 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1575 break;
1576 case 8:
1577 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1578 PIPE_CONFIG(ADDR_SURF_P2));
1579 break;
1580 case 9:
1581 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1582 PIPE_CONFIG(ADDR_SURF_P2) |
1583 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1584 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1585 break;
1586 case 10:
1587 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1588 PIPE_CONFIG(ADDR_SURF_P2) |
1589 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1590 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1591 break;
1592 case 11:
1593 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1594 PIPE_CONFIG(ADDR_SURF_P2) |
1595 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1596 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1597 break;
1598 case 13:
1599 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1600 PIPE_CONFIG(ADDR_SURF_P2) |
1601 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1602 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1603 break;
1604 case 14:
1605 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1606 PIPE_CONFIG(ADDR_SURF_P2) |
1607 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1608 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1609 break;
1610 case 15:
1611 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1612 PIPE_CONFIG(ADDR_SURF_P2) |
1613 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1614 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1615 break;
1616 case 16:
1617 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1618 PIPE_CONFIG(ADDR_SURF_P2) |
1619 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1620 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1621 break;
1622 case 18:
1623 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1624 PIPE_CONFIG(ADDR_SURF_P2) |
1625 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1626 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1627 break;
1628 case 19:
1629 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1630 PIPE_CONFIG(ADDR_SURF_P2) |
1631 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1632 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1633 break;
1634 case 20:
1635 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1636 PIPE_CONFIG(ADDR_SURF_P2) |
1637 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1638 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1639 break;
1640 case 21:
1641 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1642 PIPE_CONFIG(ADDR_SURF_P2) |
1643 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1644 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1645 break;
1646 case 22:
1647 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1648 PIPE_CONFIG(ADDR_SURF_P2) |
1649 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1650 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1651 break;
1652 case 24:
1653 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1654 PIPE_CONFIG(ADDR_SURF_P2) |
1655 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1656 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1657 break;
1658 case 25:
1659 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1660 PIPE_CONFIG(ADDR_SURF_P2) |
1661 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1662 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1663 break;
1664 case 26:
1665 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1666 PIPE_CONFIG(ADDR_SURF_P2) |
1667 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1668 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1669 break;
1670 case 27:
1671 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1672 PIPE_CONFIG(ADDR_SURF_P2) |
1673 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1674 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1675 break;
1676 case 28:
1677 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1678 PIPE_CONFIG(ADDR_SURF_P2) |
1679 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1680 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1681 break;
1682 case 29:
1683 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1684 PIPE_CONFIG(ADDR_SURF_P2) |
1685 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1686 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1687 break;
1688 case 7:
1689 case 12:
1690 case 17:
1691 case 23:
1692 /* unused idx */
1693 continue;
1694 default:
1695 gb_tile_moden = 0;
1696 break;
1697 };
1698 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1699 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1700 }
1701 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1702 switch (reg_offset) {
1703 case 0:
1704 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1705 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1706 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1707 NUM_BANKS(ADDR_SURF_8_BANK));
1708 break;
1709 case 1:
1710 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1711 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1712 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1713 NUM_BANKS(ADDR_SURF_8_BANK));
1714 break;
1715 case 2:
1716 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1717 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1718 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1719 NUM_BANKS(ADDR_SURF_8_BANK));
1720 break;
1721 case 3:
1722 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1723 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1724 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1725 NUM_BANKS(ADDR_SURF_8_BANK));
1726 break;
1727 case 4:
1728 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1729 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1730 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1731 NUM_BANKS(ADDR_SURF_8_BANK));
1732 break;
1733 case 5:
1734 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1735 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1736 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1737 NUM_BANKS(ADDR_SURF_8_BANK));
1738 break;
1739 case 6:
1740 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1741 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1742 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1743 NUM_BANKS(ADDR_SURF_8_BANK));
1744 break;
1745 case 8:
1746 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1747 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1748 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1749 NUM_BANKS(ADDR_SURF_16_BANK));
1750 break;
1751 case 9:
1752 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1753 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1754 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1755 NUM_BANKS(ADDR_SURF_16_BANK));
1756 break;
1757 case 10:
1758 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1759 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1760 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1761 NUM_BANKS(ADDR_SURF_16_BANK));
1762 break;
1763 case 11:
1764 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1765 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1766 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1767 NUM_BANKS(ADDR_SURF_16_BANK));
1768 break;
1769 case 12:
1770 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1771 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1772 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1773 NUM_BANKS(ADDR_SURF_16_BANK));
1774 break;
1775 case 13:
1776 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1777 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1778 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1779 NUM_BANKS(ADDR_SURF_16_BANK));
1780 break;
1781 case 14:
1782 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1783 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1784 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1785 NUM_BANKS(ADDR_SURF_8_BANK));
1786 break;
1787 case 7:
1788 /* unused idx */
1789 continue;
1790 default:
1791 gb_tile_moden = 0;
1792 break;
1793 };
1794 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1795 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1796 }
1797 }
1798 }
1799
1800 static u32 gfx_v8_0_create_bitmask(u32 bit_width)
1801 {
1802 u32 i, mask = 0;
1803
1804 for (i = 0; i < bit_width; i++) {
1805 mask <<= 1;
1806 mask |= 1;
1807 }
1808 return mask;
1809 }
1810
1811 void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1812 {
1813 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1814
1815 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1816 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1817 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1818 } else if (se_num == 0xffffffff) {
1819 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1820 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1821 } else if (sh_num == 0xffffffff) {
1822 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1823 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1824 } else {
1825 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1826 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1827 }
1828 WREG32(mmGRBM_GFX_INDEX, data);
1829 }
1830
1831 static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
1832 u32 max_rb_num_per_se,
1833 u32 sh_per_se)
1834 {
1835 u32 data, mask;
1836
1837 data = RREG32(mmCC_RB_BACKEND_DISABLE);
1838 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1839
1840 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1841
1842 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1843
1844 mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se);
1845
1846 return data & mask;
1847 }
1848
1849 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
1850 u32 se_num, u32 sh_per_se,
1851 u32 max_rb_num_per_se)
1852 {
1853 int i, j;
1854 u32 data, mask;
1855 u32 disabled_rbs = 0;
1856 u32 enabled_rbs = 0;
1857
1858 mutex_lock(&adev->grbm_idx_mutex);
1859 for (i = 0; i < se_num; i++) {
1860 for (j = 0; j < sh_per_se; j++) {
1861 gfx_v8_0_select_se_sh(adev, i, j);
1862 data = gfx_v8_0_get_rb_disabled(adev,
1863 max_rb_num_per_se, sh_per_se);
1864 disabled_rbs |= data << ((i * sh_per_se + j) *
1865 RB_BITMAP_WIDTH_PER_SH);
1866 }
1867 }
1868 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1869 mutex_unlock(&adev->grbm_idx_mutex);
1870
1871 mask = 1;
1872 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1873 if (!(disabled_rbs & mask))
1874 enabled_rbs |= mask;
1875 mask <<= 1;
1876 }
1877
1878 adev->gfx.config.backend_enable_mask = enabled_rbs;
1879
1880 mutex_lock(&adev->grbm_idx_mutex);
1881 for (i = 0; i < se_num; i++) {
1882 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
1883 data = 0;
1884 for (j = 0; j < sh_per_se; j++) {
1885 switch (enabled_rbs & 3) {
1886 case 0:
1887 if (j == 0)
1888 data |= (RASTER_CONFIG_RB_MAP_3 <<
1889 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1890 else
1891 data |= (RASTER_CONFIG_RB_MAP_0 <<
1892 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1893 break;
1894 case 1:
1895 data |= (RASTER_CONFIG_RB_MAP_0 <<
1896 (i * sh_per_se + j) * 2);
1897 break;
1898 case 2:
1899 data |= (RASTER_CONFIG_RB_MAP_3 <<
1900 (i * sh_per_se + j) * 2);
1901 break;
1902 case 3:
1903 default:
1904 data |= (RASTER_CONFIG_RB_MAP_2 <<
1905 (i * sh_per_se + j) * 2);
1906 break;
1907 }
1908 enabled_rbs >>= 2;
1909 }
1910 WREG32(mmPA_SC_RASTER_CONFIG, data);
1911 }
1912 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1913 mutex_unlock(&adev->grbm_idx_mutex);
1914 }
1915
1916 /**
1917 * gmc_v8_0_init_compute_vmid - gart enable
1918 *
1919 * @rdev: amdgpu_device pointer
1920 *
1921 * Initialize compute vmid sh_mem registers
1922 *
1923 */
1924 #define DEFAULT_SH_MEM_BASES (0x6000)
1925 #define FIRST_COMPUTE_VMID (8)
1926 #define LAST_COMPUTE_VMID (16)
1927 static void gmc_v8_0_init_compute_vmid(struct amdgpu_device *adev)
1928 {
1929 int i;
1930 uint32_t sh_mem_config;
1931 uint32_t sh_mem_bases;
1932
1933 /*
1934 * Configure apertures:
1935 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1936 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1937 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1938 */
1939 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1940
1941 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
1942 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
1943 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1944 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
1945 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
1946 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
1947
1948 mutex_lock(&adev->srbm_mutex);
1949 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1950 vi_srbm_select(adev, 0, 0, 0, i);
1951 /* CP and shaders */
1952 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1953 WREG32(mmSH_MEM_APE1_BASE, 1);
1954 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1955 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1956 }
1957 vi_srbm_select(adev, 0, 0, 0, 0);
1958 mutex_unlock(&adev->srbm_mutex);
1959 }
1960
1961 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
1962 {
1963 u32 gb_addr_config;
1964 u32 mc_shared_chmap, mc_arb_ramcfg;
1965 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1966 u32 tmp;
1967 int i;
1968
1969 switch (adev->asic_type) {
1970 case CHIP_TOPAZ:
1971 adev->gfx.config.max_shader_engines = 1;
1972 adev->gfx.config.max_tile_pipes = 2;
1973 adev->gfx.config.max_cu_per_sh = 6;
1974 adev->gfx.config.max_sh_per_se = 1;
1975 adev->gfx.config.max_backends_per_se = 2;
1976 adev->gfx.config.max_texture_channel_caches = 2;
1977 adev->gfx.config.max_gprs = 256;
1978 adev->gfx.config.max_gs_threads = 32;
1979 adev->gfx.config.max_hw_contexts = 8;
1980
1981 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1982 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1983 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1984 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1985 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1986 break;
1987 case CHIP_TONGA:
1988 adev->gfx.config.max_shader_engines = 4;
1989 adev->gfx.config.max_tile_pipes = 8;
1990 adev->gfx.config.max_cu_per_sh = 8;
1991 adev->gfx.config.max_sh_per_se = 1;
1992 adev->gfx.config.max_backends_per_se = 2;
1993 adev->gfx.config.max_texture_channel_caches = 8;
1994 adev->gfx.config.max_gprs = 256;
1995 adev->gfx.config.max_gs_threads = 32;
1996 adev->gfx.config.max_hw_contexts = 8;
1997
1998 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1999 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2000 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2001 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2002 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2003 break;
2004 case CHIP_CARRIZO:
2005 adev->gfx.config.max_shader_engines = 1;
2006 adev->gfx.config.max_tile_pipes = 2;
2007 adev->gfx.config.max_sh_per_se = 1;
2008 adev->gfx.config.max_backends_per_se = 2;
2009
2010 switch (adev->pdev->revision) {
2011 case 0xc4:
2012 case 0x84:
2013 case 0xc8:
2014 case 0xcc:
2015 /* B10 */
2016 adev->gfx.config.max_cu_per_sh = 8;
2017 break;
2018 case 0xc5:
2019 case 0x81:
2020 case 0x85:
2021 case 0xc9:
2022 case 0xcd:
2023 /* B8 */
2024 adev->gfx.config.max_cu_per_sh = 6;
2025 break;
2026 case 0xc6:
2027 case 0xca:
2028 case 0xce:
2029 /* B6 */
2030 adev->gfx.config.max_cu_per_sh = 6;
2031 break;
2032 case 0xc7:
2033 case 0x87:
2034 case 0xcb:
2035 default:
2036 /* B4 */
2037 adev->gfx.config.max_cu_per_sh = 4;
2038 break;
2039 }
2040
2041 adev->gfx.config.max_texture_channel_caches = 2;
2042 adev->gfx.config.max_gprs = 256;
2043 adev->gfx.config.max_gs_threads = 32;
2044 adev->gfx.config.max_hw_contexts = 8;
2045
2046 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2047 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2048 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2049 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2050 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
2051 break;
2052 default:
2053 adev->gfx.config.max_shader_engines = 2;
2054 adev->gfx.config.max_tile_pipes = 4;
2055 adev->gfx.config.max_cu_per_sh = 2;
2056 adev->gfx.config.max_sh_per_se = 1;
2057 adev->gfx.config.max_backends_per_se = 2;
2058 adev->gfx.config.max_texture_channel_caches = 4;
2059 adev->gfx.config.max_gprs = 256;
2060 adev->gfx.config.max_gs_threads = 32;
2061 adev->gfx.config.max_hw_contexts = 8;
2062
2063 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2064 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2065 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2066 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2067 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2068 break;
2069 }
2070
2071 tmp = RREG32(mmGRBM_CNTL);
2072 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
2073 WREG32(mmGRBM_CNTL, tmp);
2074
2075 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
2076 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
2077 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
2078
2079 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
2080 adev->gfx.config.mem_max_burst_length_bytes = 256;
2081 if (adev->flags & AMDGPU_IS_APU) {
2082 /* Get memory bank mapping mode. */
2083 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
2084 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2085 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2086
2087 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
2088 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2089 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2090
2091 /* Validate settings in case only one DIMM installed. */
2092 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
2093 dimm00_addr_map = 0;
2094 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
2095 dimm01_addr_map = 0;
2096 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
2097 dimm10_addr_map = 0;
2098 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
2099 dimm11_addr_map = 0;
2100
2101 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
2102 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
2103 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
2104 adev->gfx.config.mem_row_size_in_kb = 2;
2105 else
2106 adev->gfx.config.mem_row_size_in_kb = 1;
2107 } else {
2108 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
2109 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
2110 if (adev->gfx.config.mem_row_size_in_kb > 4)
2111 adev->gfx.config.mem_row_size_in_kb = 4;
2112 }
2113
2114 adev->gfx.config.shader_engine_tile_size = 32;
2115 adev->gfx.config.num_gpus = 1;
2116 adev->gfx.config.multi_gpu_tile_size = 64;
2117
2118 /* fix up row size */
2119 switch (adev->gfx.config.mem_row_size_in_kb) {
2120 case 1:
2121 default:
2122 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
2123 break;
2124 case 2:
2125 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
2126 break;
2127 case 4:
2128 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
2129 break;
2130 }
2131 adev->gfx.config.gb_addr_config = gb_addr_config;
2132
2133 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
2134 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
2135 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
2136 WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
2137 gb_addr_config & 0x70);
2138 WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
2139 gb_addr_config & 0x70);
2140 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
2141 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
2142 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2143
2144 gfx_v8_0_tiling_mode_table_init(adev);
2145
2146 gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
2147 adev->gfx.config.max_sh_per_se,
2148 adev->gfx.config.max_backends_per_se);
2149
2150 /* XXX SH_MEM regs */
2151 /* where to put LDS, scratch, GPUVM in FSA64 space */
2152 mutex_lock(&adev->srbm_mutex);
2153 for (i = 0; i < 16; i++) {
2154 vi_srbm_select(adev, 0, 0, 0, i);
2155 /* CP and shaders */
2156 if (i == 0) {
2157 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
2158 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
2159 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2160 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2161 WREG32(mmSH_MEM_CONFIG, tmp);
2162 } else {
2163 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
2164 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
2165 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2166 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2167 WREG32(mmSH_MEM_CONFIG, tmp);
2168 }
2169
2170 WREG32(mmSH_MEM_APE1_BASE, 1);
2171 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2172 WREG32(mmSH_MEM_BASES, 0);
2173 }
2174 vi_srbm_select(adev, 0, 0, 0, 0);
2175 mutex_unlock(&adev->srbm_mutex);
2176
2177 gmc_v8_0_init_compute_vmid(adev);
2178
2179 mutex_lock(&adev->grbm_idx_mutex);
2180 /*
2181 * making sure that the following register writes will be broadcasted
2182 * to all the shaders
2183 */
2184 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2185
2186 WREG32(mmPA_SC_FIFO_SIZE,
2187 (adev->gfx.config.sc_prim_fifo_size_frontend <<
2188 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2189 (adev->gfx.config.sc_prim_fifo_size_backend <<
2190 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2191 (adev->gfx.config.sc_hiz_tile_fifo_size <<
2192 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2193 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
2194 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
2195 mutex_unlock(&adev->grbm_idx_mutex);
2196
2197 }
2198
2199 static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2200 {
2201 u32 i, j, k;
2202 u32 mask;
2203
2204 mutex_lock(&adev->grbm_idx_mutex);
2205 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2206 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2207 gfx_v8_0_select_se_sh(adev, i, j);
2208 for (k = 0; k < adev->usec_timeout; k++) {
2209 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2210 break;
2211 udelay(1);
2212 }
2213 }
2214 }
2215 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2216 mutex_unlock(&adev->grbm_idx_mutex);
2217
2218 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2219 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2220 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2221 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2222 for (k = 0; k < adev->usec_timeout; k++) {
2223 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2224 break;
2225 udelay(1);
2226 }
2227 }
2228
2229 static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2230 bool enable)
2231 {
2232 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2233
2234 if (enable) {
2235 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1);
2236 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1);
2237 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1);
2238 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1);
2239 } else {
2240 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0);
2241 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0);
2242 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0);
2243 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0);
2244 }
2245 WREG32(mmCP_INT_CNTL_RING0, tmp);
2246 }
2247
2248 void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
2249 {
2250 u32 tmp = RREG32(mmRLC_CNTL);
2251
2252 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2253 WREG32(mmRLC_CNTL, tmp);
2254
2255 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
2256
2257 gfx_v8_0_wait_for_rlc_serdes(adev);
2258 }
2259
2260 static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
2261 {
2262 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
2263
2264 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2265 WREG32(mmGRBM_SOFT_RESET, tmp);
2266 udelay(50);
2267 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2268 WREG32(mmGRBM_SOFT_RESET, tmp);
2269 udelay(50);
2270 }
2271
2272 static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
2273 {
2274 u32 tmp = RREG32(mmRLC_CNTL);
2275
2276 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
2277 WREG32(mmRLC_CNTL, tmp);
2278
2279 /* carrizo do enable cp interrupt after cp inited */
2280 if (adev->asic_type != CHIP_CARRIZO)
2281 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
2282
2283 udelay(50);
2284 }
2285
2286 static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
2287 {
2288 const struct rlc_firmware_header_v2_0 *hdr;
2289 const __le32 *fw_data;
2290 unsigned i, fw_size;
2291
2292 if (!adev->gfx.rlc_fw)
2293 return -EINVAL;
2294
2295 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2296 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2297
2298 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2299 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2300 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2301
2302 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
2303 for (i = 0; i < fw_size; i++)
2304 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2305 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2306
2307 return 0;
2308 }
2309
2310 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
2311 {
2312 int r;
2313
2314 gfx_v8_0_rlc_stop(adev);
2315
2316 /* disable CG */
2317 WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
2318
2319 /* disable PG */
2320 WREG32(mmRLC_PG_CNTL, 0);
2321
2322 gfx_v8_0_rlc_reset(adev);
2323
2324 if (!adev->firmware.smu_load) {
2325 /* legacy rlc firmware loading */
2326 r = gfx_v8_0_rlc_load_microcode(adev);
2327 if (r)
2328 return r;
2329 } else {
2330 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
2331 AMDGPU_UCODE_ID_RLC_G);
2332 if (r)
2333 return -EINVAL;
2334 }
2335
2336 gfx_v8_0_rlc_start(adev);
2337
2338 return 0;
2339 }
2340
2341 static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2342 {
2343 int i;
2344 u32 tmp = RREG32(mmCP_ME_CNTL);
2345
2346 if (enable) {
2347 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
2348 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
2349 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
2350 } else {
2351 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
2352 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
2353 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
2354 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2355 adev->gfx.gfx_ring[i].ready = false;
2356 }
2357 WREG32(mmCP_ME_CNTL, tmp);
2358 udelay(50);
2359 }
2360
2361 static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2362 {
2363 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2364 const struct gfx_firmware_header_v1_0 *ce_hdr;
2365 const struct gfx_firmware_header_v1_0 *me_hdr;
2366 const __le32 *fw_data;
2367 unsigned i, fw_size;
2368
2369 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2370 return -EINVAL;
2371
2372 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2373 adev->gfx.pfp_fw->data;
2374 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2375 adev->gfx.ce_fw->data;
2376 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2377 adev->gfx.me_fw->data;
2378
2379 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2380 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2381 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2382
2383 gfx_v8_0_cp_gfx_enable(adev, false);
2384
2385 /* PFP */
2386 fw_data = (const __le32 *)
2387 (adev->gfx.pfp_fw->data +
2388 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2389 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2390 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2391 for (i = 0; i < fw_size; i++)
2392 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2393 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2394
2395 /* CE */
2396 fw_data = (const __le32 *)
2397 (adev->gfx.ce_fw->data +
2398 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2399 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2400 WREG32(mmCP_CE_UCODE_ADDR, 0);
2401 for (i = 0; i < fw_size; i++)
2402 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2403 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2404
2405 /* ME */
2406 fw_data = (const __le32 *)
2407 (adev->gfx.me_fw->data +
2408 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2409 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2410 WREG32(mmCP_ME_RAM_WADDR, 0);
2411 for (i = 0; i < fw_size; i++)
2412 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2413 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2414
2415 return 0;
2416 }
2417
2418 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
2419 {
2420 u32 count = 0;
2421 const struct cs_section_def *sect = NULL;
2422 const struct cs_extent_def *ext = NULL;
2423
2424 /* begin clear state */
2425 count += 2;
2426 /* context control state */
2427 count += 3;
2428
2429 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2430 for (ext = sect->section; ext->extent != NULL; ++ext) {
2431 if (sect->id == SECT_CONTEXT)
2432 count += 2 + ext->reg_count;
2433 else
2434 return 0;
2435 }
2436 }
2437 /* pa_sc_raster_config/pa_sc_raster_config1 */
2438 count += 4;
2439 /* end clear state */
2440 count += 2;
2441 /* clear state */
2442 count += 2;
2443
2444 return count;
2445 }
2446
2447 static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
2448 {
2449 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2450 const struct cs_section_def *sect = NULL;
2451 const struct cs_extent_def *ext = NULL;
2452 int r, i;
2453
2454 /* init the CP */
2455 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2456 WREG32(mmCP_ENDIAN_SWAP, 0);
2457 WREG32(mmCP_DEVICE_ID, 1);
2458
2459 gfx_v8_0_cp_gfx_enable(adev, true);
2460
2461 r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4);
2462 if (r) {
2463 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2464 return r;
2465 }
2466
2467 /* clear state buffer */
2468 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2469 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2470
2471 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2472 amdgpu_ring_write(ring, 0x80000000);
2473 amdgpu_ring_write(ring, 0x80000000);
2474
2475 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2476 for (ext = sect->section; ext->extent != NULL; ++ext) {
2477 if (sect->id == SECT_CONTEXT) {
2478 amdgpu_ring_write(ring,
2479 PACKET3(PACKET3_SET_CONTEXT_REG,
2480 ext->reg_count));
2481 amdgpu_ring_write(ring,
2482 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2483 for (i = 0; i < ext->reg_count; i++)
2484 amdgpu_ring_write(ring, ext->extent[i]);
2485 }
2486 }
2487 }
2488
2489 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2490 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2491 switch (adev->asic_type) {
2492 case CHIP_TONGA:
2493 amdgpu_ring_write(ring, 0x16000012);
2494 amdgpu_ring_write(ring, 0x0000002A);
2495 break;
2496 case CHIP_TOPAZ:
2497 case CHIP_CARRIZO:
2498 amdgpu_ring_write(ring, 0x00000002);
2499 amdgpu_ring_write(ring, 0x00000000);
2500 break;
2501 default:
2502 BUG();
2503 }
2504
2505 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2506 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2507
2508 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2509 amdgpu_ring_write(ring, 0);
2510
2511 /* init the CE partitions */
2512 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2513 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2514 amdgpu_ring_write(ring, 0x8000);
2515 amdgpu_ring_write(ring, 0x8000);
2516
2517 amdgpu_ring_unlock_commit(ring);
2518
2519 return 0;
2520 }
2521
2522 static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
2523 {
2524 struct amdgpu_ring *ring;
2525 u32 tmp;
2526 u32 rb_bufsz;
2527 u64 rb_addr, rptr_addr;
2528 int r;
2529
2530 /* Set the write pointer delay */
2531 WREG32(mmCP_RB_WPTR_DELAY, 0);
2532
2533 /* set the RB to use vmid 0 */
2534 WREG32(mmCP_RB_VMID, 0);
2535
2536 /* Set ring buffer size */
2537 ring = &adev->gfx.gfx_ring[0];
2538 rb_bufsz = order_base_2(ring->ring_size / 8);
2539 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2540 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2541 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
2542 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
2543 #ifdef __BIG_ENDIAN
2544 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2545 #endif
2546 WREG32(mmCP_RB0_CNTL, tmp);
2547
2548 /* Initialize the ring buffer's read and write pointers */
2549 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2550 ring->wptr = 0;
2551 WREG32(mmCP_RB0_WPTR, ring->wptr);
2552
2553 /* set the wb address wether it's enabled or not */
2554 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2555 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2556 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2557
2558 mdelay(1);
2559 WREG32(mmCP_RB0_CNTL, tmp);
2560
2561 rb_addr = ring->gpu_addr >> 8;
2562 WREG32(mmCP_RB0_BASE, rb_addr);
2563 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2564
2565 /* no gfx doorbells on iceland */
2566 if (adev->asic_type != CHIP_TOPAZ) {
2567 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
2568 if (ring->use_doorbell) {
2569 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2570 DOORBELL_OFFSET, ring->doorbell_index);
2571 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2572 DOORBELL_EN, 1);
2573 } else {
2574 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2575 DOORBELL_EN, 0);
2576 }
2577 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
2578
2579 if (adev->asic_type == CHIP_TONGA) {
2580 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2581 DOORBELL_RANGE_LOWER,
2582 AMDGPU_DOORBELL_GFX_RING0);
2583 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2584
2585 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
2586 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2587 }
2588
2589 }
2590
2591 /* start the ring */
2592 gfx_v8_0_cp_gfx_start(adev);
2593 ring->ready = true;
2594 r = amdgpu_ring_test_ring(ring);
2595 if (r) {
2596 ring->ready = false;
2597 return r;
2598 }
2599
2600 return 0;
2601 }
2602
2603 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2604 {
2605 int i;
2606
2607 if (enable) {
2608 WREG32(mmCP_MEC_CNTL, 0);
2609 } else {
2610 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2611 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2612 adev->gfx.compute_ring[i].ready = false;
2613 }
2614 udelay(50);
2615 }
2616
2617 static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
2618 {
2619 gfx_v8_0_cp_compute_enable(adev, true);
2620
2621 return 0;
2622 }
2623
2624 static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2625 {
2626 const struct gfx_firmware_header_v1_0 *mec_hdr;
2627 const __le32 *fw_data;
2628 unsigned i, fw_size;
2629
2630 if (!adev->gfx.mec_fw)
2631 return -EINVAL;
2632
2633 gfx_v8_0_cp_compute_enable(adev, false);
2634
2635 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2636 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2637
2638 fw_data = (const __le32 *)
2639 (adev->gfx.mec_fw->data +
2640 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2641 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2642
2643 /* MEC1 */
2644 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2645 for (i = 0; i < fw_size; i++)
2646 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
2647 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2648
2649 /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2650 if (adev->gfx.mec2_fw) {
2651 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2652
2653 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2654 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2655
2656 fw_data = (const __le32 *)
2657 (adev->gfx.mec2_fw->data +
2658 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2659 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2660
2661 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2662 for (i = 0; i < fw_size; i++)
2663 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
2664 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
2665 }
2666
2667 return 0;
2668 }
2669
2670 struct vi_mqd {
2671 uint32_t header; /* ordinal0 */
2672 uint32_t compute_dispatch_initiator; /* ordinal1 */
2673 uint32_t compute_dim_x; /* ordinal2 */
2674 uint32_t compute_dim_y; /* ordinal3 */
2675 uint32_t compute_dim_z; /* ordinal4 */
2676 uint32_t compute_start_x; /* ordinal5 */
2677 uint32_t compute_start_y; /* ordinal6 */
2678 uint32_t compute_start_z; /* ordinal7 */
2679 uint32_t compute_num_thread_x; /* ordinal8 */
2680 uint32_t compute_num_thread_y; /* ordinal9 */
2681 uint32_t compute_num_thread_z; /* ordinal10 */
2682 uint32_t compute_pipelinestat_enable; /* ordinal11 */
2683 uint32_t compute_perfcount_enable; /* ordinal12 */
2684 uint32_t compute_pgm_lo; /* ordinal13 */
2685 uint32_t compute_pgm_hi; /* ordinal14 */
2686 uint32_t compute_tba_lo; /* ordinal15 */
2687 uint32_t compute_tba_hi; /* ordinal16 */
2688 uint32_t compute_tma_lo; /* ordinal17 */
2689 uint32_t compute_tma_hi; /* ordinal18 */
2690 uint32_t compute_pgm_rsrc1; /* ordinal19 */
2691 uint32_t compute_pgm_rsrc2; /* ordinal20 */
2692 uint32_t compute_vmid; /* ordinal21 */
2693 uint32_t compute_resource_limits; /* ordinal22 */
2694 uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */
2695 uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */
2696 uint32_t compute_tmpring_size; /* ordinal25 */
2697 uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */
2698 uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */
2699 uint32_t compute_restart_x; /* ordinal28 */
2700 uint32_t compute_restart_y; /* ordinal29 */
2701 uint32_t compute_restart_z; /* ordinal30 */
2702 uint32_t compute_thread_trace_enable; /* ordinal31 */
2703 uint32_t compute_misc_reserved; /* ordinal32 */
2704 uint32_t compute_dispatch_id; /* ordinal33 */
2705 uint32_t compute_threadgroup_id; /* ordinal34 */
2706 uint32_t compute_relaunch; /* ordinal35 */
2707 uint32_t compute_wave_restore_addr_lo; /* ordinal36 */
2708 uint32_t compute_wave_restore_addr_hi; /* ordinal37 */
2709 uint32_t compute_wave_restore_control; /* ordinal38 */
2710 uint32_t reserved9; /* ordinal39 */
2711 uint32_t reserved10; /* ordinal40 */
2712 uint32_t reserved11; /* ordinal41 */
2713 uint32_t reserved12; /* ordinal42 */
2714 uint32_t reserved13; /* ordinal43 */
2715 uint32_t reserved14; /* ordinal44 */
2716 uint32_t reserved15; /* ordinal45 */
2717 uint32_t reserved16; /* ordinal46 */
2718 uint32_t reserved17; /* ordinal47 */
2719 uint32_t reserved18; /* ordinal48 */
2720 uint32_t reserved19; /* ordinal49 */
2721 uint32_t reserved20; /* ordinal50 */
2722 uint32_t reserved21; /* ordinal51 */
2723 uint32_t reserved22; /* ordinal52 */
2724 uint32_t reserved23; /* ordinal53 */
2725 uint32_t reserved24; /* ordinal54 */
2726 uint32_t reserved25; /* ordinal55 */
2727 uint32_t reserved26; /* ordinal56 */
2728 uint32_t reserved27; /* ordinal57 */
2729 uint32_t reserved28; /* ordinal58 */
2730 uint32_t reserved29; /* ordinal59 */
2731 uint32_t reserved30; /* ordinal60 */
2732 uint32_t reserved31; /* ordinal61 */
2733 uint32_t reserved32; /* ordinal62 */
2734 uint32_t reserved33; /* ordinal63 */
2735 uint32_t reserved34; /* ordinal64 */
2736 uint32_t compute_user_data_0; /* ordinal65 */
2737 uint32_t compute_user_data_1; /* ordinal66 */
2738 uint32_t compute_user_data_2; /* ordinal67 */
2739 uint32_t compute_user_data_3; /* ordinal68 */
2740 uint32_t compute_user_data_4; /* ordinal69 */
2741 uint32_t compute_user_data_5; /* ordinal70 */
2742 uint32_t compute_user_data_6; /* ordinal71 */
2743 uint32_t compute_user_data_7; /* ordinal72 */
2744 uint32_t compute_user_data_8; /* ordinal73 */
2745 uint32_t compute_user_data_9; /* ordinal74 */
2746 uint32_t compute_user_data_10; /* ordinal75 */
2747 uint32_t compute_user_data_11; /* ordinal76 */
2748 uint32_t compute_user_data_12; /* ordinal77 */
2749 uint32_t compute_user_data_13; /* ordinal78 */
2750 uint32_t compute_user_data_14; /* ordinal79 */
2751 uint32_t compute_user_data_15; /* ordinal80 */
2752 uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */
2753 uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */
2754 uint32_t reserved35; /* ordinal83 */
2755 uint32_t reserved36; /* ordinal84 */
2756 uint32_t reserved37; /* ordinal85 */
2757 uint32_t cp_mqd_query_time_lo; /* ordinal86 */
2758 uint32_t cp_mqd_query_time_hi; /* ordinal87 */
2759 uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */
2760 uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */
2761 uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */
2762 uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */
2763 uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */
2764 uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */
2765 uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */
2766 uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */
2767 uint32_t reserved38; /* ordinal96 */
2768 uint32_t reserved39; /* ordinal97 */
2769 uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */
2770 uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */
2771 uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */
2772 uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */
2773 uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */
2774 uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */
2775 uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */
2776 uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */
2777 uint32_t reserved40; /* ordinal106 */
2778 uint32_t reserved41; /* ordinal107 */
2779 uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */
2780 uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */
2781 uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */
2782 uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */
2783 uint32_t reserved42; /* ordinal112 */
2784 uint32_t reserved43; /* ordinal113 */
2785 uint32_t cp_pq_exe_status_lo; /* ordinal114 */
2786 uint32_t cp_pq_exe_status_hi; /* ordinal115 */
2787 uint32_t cp_packet_id_lo; /* ordinal116 */
2788 uint32_t cp_packet_id_hi; /* ordinal117 */
2789 uint32_t cp_packet_exe_status_lo; /* ordinal118 */
2790 uint32_t cp_packet_exe_status_hi; /* ordinal119 */
2791 uint32_t gds_save_base_addr_lo; /* ordinal120 */
2792 uint32_t gds_save_base_addr_hi; /* ordinal121 */
2793 uint32_t gds_save_mask_lo; /* ordinal122 */
2794 uint32_t gds_save_mask_hi; /* ordinal123 */
2795 uint32_t ctx_save_base_addr_lo; /* ordinal124 */
2796 uint32_t ctx_save_base_addr_hi; /* ordinal125 */
2797 uint32_t reserved44; /* ordinal126 */
2798 uint32_t reserved45; /* ordinal127 */
2799 uint32_t cp_mqd_base_addr_lo; /* ordinal128 */
2800 uint32_t cp_mqd_base_addr_hi; /* ordinal129 */
2801 uint32_t cp_hqd_active; /* ordinal130 */
2802 uint32_t cp_hqd_vmid; /* ordinal131 */
2803 uint32_t cp_hqd_persistent_state; /* ordinal132 */
2804 uint32_t cp_hqd_pipe_priority; /* ordinal133 */
2805 uint32_t cp_hqd_queue_priority; /* ordinal134 */
2806 uint32_t cp_hqd_quantum; /* ordinal135 */
2807 uint32_t cp_hqd_pq_base_lo; /* ordinal136 */
2808 uint32_t cp_hqd_pq_base_hi; /* ordinal137 */
2809 uint32_t cp_hqd_pq_rptr; /* ordinal138 */
2810 uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */
2811 uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */
2812 uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */
2813 uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */
2814 uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */
2815 uint32_t cp_hqd_pq_wptr; /* ordinal144 */
2816 uint32_t cp_hqd_pq_control; /* ordinal145 */
2817 uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */
2818 uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */
2819 uint32_t cp_hqd_ib_rptr; /* ordinal148 */
2820 uint32_t cp_hqd_ib_control; /* ordinal149 */
2821 uint32_t cp_hqd_iq_timer; /* ordinal150 */
2822 uint32_t cp_hqd_iq_rptr; /* ordinal151 */
2823 uint32_t cp_hqd_dequeue_request; /* ordinal152 */
2824 uint32_t cp_hqd_dma_offload; /* ordinal153 */
2825 uint32_t cp_hqd_sema_cmd; /* ordinal154 */
2826 uint32_t cp_hqd_msg_type; /* ordinal155 */
2827 uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */
2828 uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */
2829 uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */
2830 uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */
2831 uint32_t cp_hqd_hq_status0; /* ordinal160 */
2832 uint32_t cp_hqd_hq_control0; /* ordinal161 */
2833 uint32_t cp_mqd_control; /* ordinal162 */
2834 uint32_t cp_hqd_hq_status1; /* ordinal163 */
2835 uint32_t cp_hqd_hq_control1; /* ordinal164 */
2836 uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */
2837 uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */
2838 uint32_t cp_hqd_eop_control; /* ordinal167 */
2839 uint32_t cp_hqd_eop_rptr; /* ordinal168 */
2840 uint32_t cp_hqd_eop_wptr; /* ordinal169 */
2841 uint32_t cp_hqd_eop_done_events; /* ordinal170 */
2842 uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */
2843 uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */
2844 uint32_t cp_hqd_ctx_save_control; /* ordinal173 */
2845 uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */
2846 uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */
2847 uint32_t cp_hqd_wg_state_offset; /* ordinal176 */
2848 uint32_t cp_hqd_ctx_save_size; /* ordinal177 */
2849 uint32_t cp_hqd_gds_resource_state; /* ordinal178 */
2850 uint32_t cp_hqd_error; /* ordinal179 */
2851 uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */
2852 uint32_t cp_hqd_eop_dones; /* ordinal181 */
2853 uint32_t reserved46; /* ordinal182 */
2854 uint32_t reserved47; /* ordinal183 */
2855 uint32_t reserved48; /* ordinal184 */
2856 uint32_t reserved49; /* ordinal185 */
2857 uint32_t reserved50; /* ordinal186 */
2858 uint32_t reserved51; /* ordinal187 */
2859 uint32_t reserved52; /* ordinal188 */
2860 uint32_t reserved53; /* ordinal189 */
2861 uint32_t reserved54; /* ordinal190 */
2862 uint32_t reserved55; /* ordinal191 */
2863 uint32_t iqtimer_pkt_header; /* ordinal192 */
2864 uint32_t iqtimer_pkt_dw0; /* ordinal193 */
2865 uint32_t iqtimer_pkt_dw1; /* ordinal194 */
2866 uint32_t iqtimer_pkt_dw2; /* ordinal195 */
2867 uint32_t iqtimer_pkt_dw3; /* ordinal196 */
2868 uint32_t iqtimer_pkt_dw4; /* ordinal197 */
2869 uint32_t iqtimer_pkt_dw5; /* ordinal198 */
2870 uint32_t iqtimer_pkt_dw6; /* ordinal199 */
2871 uint32_t iqtimer_pkt_dw7; /* ordinal200 */
2872 uint32_t iqtimer_pkt_dw8; /* ordinal201 */
2873 uint32_t iqtimer_pkt_dw9; /* ordinal202 */
2874 uint32_t iqtimer_pkt_dw10; /* ordinal203 */
2875 uint32_t iqtimer_pkt_dw11; /* ordinal204 */
2876 uint32_t iqtimer_pkt_dw12; /* ordinal205 */
2877 uint32_t iqtimer_pkt_dw13; /* ordinal206 */
2878 uint32_t iqtimer_pkt_dw14; /* ordinal207 */
2879 uint32_t iqtimer_pkt_dw15; /* ordinal208 */
2880 uint32_t iqtimer_pkt_dw16; /* ordinal209 */
2881 uint32_t iqtimer_pkt_dw17; /* ordinal210 */
2882 uint32_t iqtimer_pkt_dw18; /* ordinal211 */
2883 uint32_t iqtimer_pkt_dw19; /* ordinal212 */
2884 uint32_t iqtimer_pkt_dw20; /* ordinal213 */
2885 uint32_t iqtimer_pkt_dw21; /* ordinal214 */
2886 uint32_t iqtimer_pkt_dw22; /* ordinal215 */
2887 uint32_t iqtimer_pkt_dw23; /* ordinal216 */
2888 uint32_t iqtimer_pkt_dw24; /* ordinal217 */
2889 uint32_t iqtimer_pkt_dw25; /* ordinal218 */
2890 uint32_t iqtimer_pkt_dw26; /* ordinal219 */
2891 uint32_t iqtimer_pkt_dw27; /* ordinal220 */
2892 uint32_t iqtimer_pkt_dw28; /* ordinal221 */
2893 uint32_t iqtimer_pkt_dw29; /* ordinal222 */
2894 uint32_t iqtimer_pkt_dw30; /* ordinal223 */
2895 uint32_t iqtimer_pkt_dw31; /* ordinal224 */
2896 uint32_t reserved56; /* ordinal225 */
2897 uint32_t reserved57; /* ordinal226 */
2898 uint32_t reserved58; /* ordinal227 */
2899 uint32_t set_resources_header; /* ordinal228 */
2900 uint32_t set_resources_dw1; /* ordinal229 */
2901 uint32_t set_resources_dw2; /* ordinal230 */
2902 uint32_t set_resources_dw3; /* ordinal231 */
2903 uint32_t set_resources_dw4; /* ordinal232 */
2904 uint32_t set_resources_dw5; /* ordinal233 */
2905 uint32_t set_resources_dw6; /* ordinal234 */
2906 uint32_t set_resources_dw7; /* ordinal235 */
2907 uint32_t reserved59; /* ordinal236 */
2908 uint32_t reserved60; /* ordinal237 */
2909 uint32_t reserved61; /* ordinal238 */
2910 uint32_t reserved62; /* ordinal239 */
2911 uint32_t reserved63; /* ordinal240 */
2912 uint32_t reserved64; /* ordinal241 */
2913 uint32_t reserved65; /* ordinal242 */
2914 uint32_t reserved66; /* ordinal243 */
2915 uint32_t reserved67; /* ordinal244 */
2916 uint32_t reserved68; /* ordinal245 */
2917 uint32_t reserved69; /* ordinal246 */
2918 uint32_t reserved70; /* ordinal247 */
2919 uint32_t reserved71; /* ordinal248 */
2920 uint32_t reserved72; /* ordinal249 */
2921 uint32_t reserved73; /* ordinal250 */
2922 uint32_t reserved74; /* ordinal251 */
2923 uint32_t reserved75; /* ordinal252 */
2924 uint32_t reserved76; /* ordinal253 */
2925 uint32_t reserved77; /* ordinal254 */
2926 uint32_t reserved78; /* ordinal255 */
2927
2928 uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
2929 };
2930
2931 static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
2932 {
2933 int i, r;
2934
2935 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2936 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2937
2938 if (ring->mqd_obj) {
2939 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2940 if (unlikely(r != 0))
2941 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2942
2943 amdgpu_bo_unpin(ring->mqd_obj);
2944 amdgpu_bo_unreserve(ring->mqd_obj);
2945
2946 amdgpu_bo_unref(&ring->mqd_obj);
2947 ring->mqd_obj = NULL;
2948 }
2949 }
2950 }
2951
2952 static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
2953 {
2954 int r, i, j;
2955 u32 tmp;
2956 bool use_doorbell = true;
2957 u64 hqd_gpu_addr;
2958 u64 mqd_gpu_addr;
2959 u64 eop_gpu_addr;
2960 u64 wb_gpu_addr;
2961 u32 *buf;
2962 struct vi_mqd *mqd;
2963
2964 /* init the pipes */
2965 mutex_lock(&adev->srbm_mutex);
2966 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
2967 int me = (i < 4) ? 1 : 2;
2968 int pipe = (i < 4) ? i : (i - 4);
2969
2970 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
2971 eop_gpu_addr >>= 8;
2972
2973 vi_srbm_select(adev, me, pipe, 0, 0);
2974
2975 /* write the EOP addr */
2976 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
2977 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
2978
2979 /* set the VMID assigned */
2980 WREG32(mmCP_HQD_VMID, 0);
2981
2982 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2983 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
2984 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2985 (order_base_2(MEC_HPD_SIZE / 4) - 1));
2986 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
2987 }
2988 vi_srbm_select(adev, 0, 0, 0, 0);
2989 mutex_unlock(&adev->srbm_mutex);
2990
2991 /* init the queues. Just two for now. */
2992 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2993 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2994
2995 if (ring->mqd_obj == NULL) {
2996 r = amdgpu_bo_create(adev,
2997 sizeof(struct vi_mqd),
2998 PAGE_SIZE, true,
2999 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3000 &ring->mqd_obj);
3001 if (r) {
3002 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3003 return r;
3004 }
3005 }
3006
3007 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3008 if (unlikely(r != 0)) {
3009 gfx_v8_0_cp_compute_fini(adev);
3010 return r;
3011 }
3012 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3013 &mqd_gpu_addr);
3014 if (r) {
3015 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3016 gfx_v8_0_cp_compute_fini(adev);
3017 return r;
3018 }
3019 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3020 if (r) {
3021 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3022 gfx_v8_0_cp_compute_fini(adev);
3023 return r;
3024 }
3025
3026 /* init the mqd struct */
3027 memset(buf, 0, sizeof(struct vi_mqd));
3028
3029 mqd = (struct vi_mqd *)buf;
3030 mqd->header = 0xC0310800;
3031 mqd->compute_pipelinestat_enable = 0x00000001;
3032 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3033 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3034 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3035 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3036 mqd->compute_misc_reserved = 0x00000003;
3037
3038 mutex_lock(&adev->srbm_mutex);
3039 vi_srbm_select(adev, ring->me,
3040 ring->pipe,
3041 ring->queue, 0);
3042
3043 /* disable wptr polling */
3044 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3045 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3046 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3047
3048 mqd->cp_hqd_eop_base_addr_lo =
3049 RREG32(mmCP_HQD_EOP_BASE_ADDR);
3050 mqd->cp_hqd_eop_base_addr_hi =
3051 RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
3052
3053 /* enable doorbell? */
3054 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3055 if (use_doorbell) {
3056 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3057 } else {
3058 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3059 }
3060 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
3061 mqd->cp_hqd_pq_doorbell_control = tmp;
3062
3063 /* disable the queue if it's active */
3064 mqd->cp_hqd_dequeue_request = 0;
3065 mqd->cp_hqd_pq_rptr = 0;
3066 mqd->cp_hqd_pq_wptr= 0;
3067 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3068 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3069 for (j = 0; j < adev->usec_timeout; j++) {
3070 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3071 break;
3072 udelay(1);
3073 }
3074 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
3075 WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
3076 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3077 }
3078
3079 /* set the pointer to the MQD */
3080 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3081 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3082 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
3083 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3084
3085 /* set MQD vmid to 0 */
3086 tmp = RREG32(mmCP_MQD_CONTROL);
3087 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3088 WREG32(mmCP_MQD_CONTROL, tmp);
3089 mqd->cp_mqd_control = tmp;
3090
3091 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3092 hqd_gpu_addr = ring->gpu_addr >> 8;
3093 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3094 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3095 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
3096 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
3097
3098 /* set up the HQD, this is similar to CP_RB0_CNTL */
3099 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
3100 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3101 (order_base_2(ring->ring_size / 4) - 1));
3102 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3103 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3104 #ifdef __BIG_ENDIAN
3105 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3106 #endif
3107 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3108 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3109 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3110 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3111 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
3112 mqd->cp_hqd_pq_control = tmp;
3113
3114 /* set the wb address wether it's enabled or not */
3115 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3116 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3117 mqd->cp_hqd_pq_rptr_report_addr_hi =
3118 upper_32_bits(wb_gpu_addr) & 0xffff;
3119 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3120 mqd->cp_hqd_pq_rptr_report_addr_lo);
3121 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3122 mqd->cp_hqd_pq_rptr_report_addr_hi);
3123
3124 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3125 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3126 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3127 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3128 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
3129 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3130 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3131
3132 /* enable the doorbell if requested */
3133 if (use_doorbell) {
3134 if (adev->asic_type == CHIP_CARRIZO) {
3135 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
3136 AMDGPU_DOORBELL_KIQ << 2);
3137 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
3138 AMDGPU_DOORBELL_MEC_RING7 << 2);
3139 }
3140 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3141 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3142 DOORBELL_OFFSET, ring->doorbell_index);
3143 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3144 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3145 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3146 mqd->cp_hqd_pq_doorbell_control = tmp;
3147
3148 } else {
3149 mqd->cp_hqd_pq_doorbell_control = 0;
3150 }
3151 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3152 mqd->cp_hqd_pq_doorbell_control);
3153
3154 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3155 ring->wptr = 0;
3156 mqd->cp_hqd_pq_wptr = ring->wptr;
3157 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3158 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3159
3160 /* set the vmid for the queue */
3161 mqd->cp_hqd_vmid = 0;
3162 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3163
3164 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
3165 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3166 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
3167 mqd->cp_hqd_persistent_state = tmp;
3168
3169 /* activate the queue */
3170 mqd->cp_hqd_active = 1;
3171 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
3172
3173 vi_srbm_select(adev, 0, 0, 0, 0);
3174 mutex_unlock(&adev->srbm_mutex);
3175
3176 amdgpu_bo_kunmap(ring->mqd_obj);
3177 amdgpu_bo_unreserve(ring->mqd_obj);
3178 }
3179
3180 if (use_doorbell) {
3181 tmp = RREG32(mmCP_PQ_STATUS);
3182 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3183 WREG32(mmCP_PQ_STATUS, tmp);
3184 }
3185
3186 r = gfx_v8_0_cp_compute_start(adev);
3187 if (r)
3188 return r;
3189
3190 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3191 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3192
3193 ring->ready = true;
3194 r = amdgpu_ring_test_ring(ring);
3195 if (r)
3196 ring->ready = false;
3197 }
3198
3199 return 0;
3200 }
3201
3202 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
3203 {
3204 int r;
3205
3206 if (adev->asic_type != CHIP_CARRIZO)
3207 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3208
3209 if (!adev->firmware.smu_load) {
3210 /* legacy firmware loading */
3211 r = gfx_v8_0_cp_gfx_load_microcode(adev);
3212 if (r)
3213 return r;
3214
3215 r = gfx_v8_0_cp_compute_load_microcode(adev);
3216 if (r)
3217 return r;
3218 } else {
3219 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3220 AMDGPU_UCODE_ID_CP_CE);
3221 if (r)
3222 return -EINVAL;
3223
3224 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3225 AMDGPU_UCODE_ID_CP_PFP);
3226 if (r)
3227 return -EINVAL;
3228
3229 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3230 AMDGPU_UCODE_ID_CP_ME);
3231 if (r)
3232 return -EINVAL;
3233
3234 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3235 AMDGPU_UCODE_ID_CP_MEC1);
3236 if (r)
3237 return -EINVAL;
3238 }
3239
3240 r = gfx_v8_0_cp_gfx_resume(adev);
3241 if (r)
3242 return r;
3243
3244 r = gfx_v8_0_cp_compute_resume(adev);
3245 if (r)
3246 return r;
3247
3248 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3249
3250 return 0;
3251 }
3252
3253 static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
3254 {
3255 gfx_v8_0_cp_gfx_enable(adev, enable);
3256 gfx_v8_0_cp_compute_enable(adev, enable);
3257 }
3258
3259 static int gfx_v8_0_hw_init(void *handle)
3260 {
3261 int r;
3262 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3263
3264 gfx_v8_0_init_golden_registers(adev);
3265
3266 gfx_v8_0_gpu_init(adev);
3267
3268 r = gfx_v8_0_rlc_resume(adev);
3269 if (r)
3270 return r;
3271
3272 r = gfx_v8_0_cp_resume(adev);
3273 if (r)
3274 return r;
3275
3276 return r;
3277 }
3278
3279 static int gfx_v8_0_hw_fini(void *handle)
3280 {
3281 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3282
3283 gfx_v8_0_cp_enable(adev, false);
3284 gfx_v8_0_rlc_stop(adev);
3285 gfx_v8_0_cp_compute_fini(adev);
3286
3287 return 0;
3288 }
3289
3290 static int gfx_v8_0_suspend(void *handle)
3291 {
3292 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3293
3294 return gfx_v8_0_hw_fini(adev);
3295 }
3296
3297 static int gfx_v8_0_resume(void *handle)
3298 {
3299 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3300
3301 return gfx_v8_0_hw_init(adev);
3302 }
3303
3304 static bool gfx_v8_0_is_idle(void *handle)
3305 {
3306 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3307
3308 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
3309 return false;
3310 else
3311 return true;
3312 }
3313
3314 static int gfx_v8_0_wait_for_idle(void *handle)
3315 {
3316 unsigned i;
3317 u32 tmp;
3318 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3319
3320 for (i = 0; i < adev->usec_timeout; i++) {
3321 /* read MC_STATUS */
3322 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
3323
3324 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3325 return 0;
3326 udelay(1);
3327 }
3328 return -ETIMEDOUT;
3329 }
3330
3331 static void gfx_v8_0_print_status(void *handle)
3332 {
3333 int i;
3334 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3335
3336 dev_info(adev->dev, "GFX 8.x registers\n");
3337 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
3338 RREG32(mmGRBM_STATUS));
3339 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
3340 RREG32(mmGRBM_STATUS2));
3341 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
3342 RREG32(mmGRBM_STATUS_SE0));
3343 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
3344 RREG32(mmGRBM_STATUS_SE1));
3345 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
3346 RREG32(mmGRBM_STATUS_SE2));
3347 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
3348 RREG32(mmGRBM_STATUS_SE3));
3349 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
3350 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
3351 RREG32(mmCP_STALLED_STAT1));
3352 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
3353 RREG32(mmCP_STALLED_STAT2));
3354 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
3355 RREG32(mmCP_STALLED_STAT3));
3356 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
3357 RREG32(mmCP_CPF_BUSY_STAT));
3358 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
3359 RREG32(mmCP_CPF_STALLED_STAT1));
3360 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
3361 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
3362 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
3363 RREG32(mmCP_CPC_STALLED_STAT1));
3364 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
3365
3366 for (i = 0; i < 32; i++) {
3367 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
3368 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
3369 }
3370 for (i = 0; i < 16; i++) {
3371 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
3372 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
3373 }
3374 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3375 dev_info(adev->dev, " se: %d\n", i);
3376 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
3377 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
3378 RREG32(mmPA_SC_RASTER_CONFIG));
3379 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
3380 RREG32(mmPA_SC_RASTER_CONFIG_1));
3381 }
3382 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3383
3384 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
3385 RREG32(mmGB_ADDR_CONFIG));
3386 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n",
3387 RREG32(mmHDP_ADDR_CONFIG));
3388 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n",
3389 RREG32(mmDMIF_ADDR_CALC));
3390 dev_info(adev->dev, " SDMA0_TILING_CONFIG=0x%08X\n",
3391 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
3392 dev_info(adev->dev, " SDMA1_TILING_CONFIG=0x%08X\n",
3393 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
3394 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
3395 RREG32(mmUVD_UDEC_ADDR_CONFIG));
3396 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
3397 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
3398 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
3399 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
3400
3401 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
3402 RREG32(mmCP_MEQ_THRESHOLDS));
3403 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
3404 RREG32(mmSX_DEBUG_1));
3405 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
3406 RREG32(mmTA_CNTL_AUX));
3407 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
3408 RREG32(mmSPI_CONFIG_CNTL));
3409 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
3410 RREG32(mmSQ_CONFIG));
3411 dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
3412 RREG32(mmDB_DEBUG));
3413 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
3414 RREG32(mmDB_DEBUG2));
3415 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
3416 RREG32(mmDB_DEBUG3));
3417 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
3418 RREG32(mmCB_HW_CONTROL));
3419 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
3420 RREG32(mmSPI_CONFIG_CNTL_1));
3421 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
3422 RREG32(mmPA_SC_FIFO_SIZE));
3423 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
3424 RREG32(mmVGT_NUM_INSTANCES));
3425 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
3426 RREG32(mmCP_PERFMON_CNTL));
3427 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
3428 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
3429 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
3430 RREG32(mmVGT_CACHE_INVALIDATION));
3431 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
3432 RREG32(mmVGT_GS_VERTEX_REUSE));
3433 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
3434 RREG32(mmPA_SC_LINE_STIPPLE_STATE));
3435 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
3436 RREG32(mmPA_CL_ENHANCE));
3437 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
3438 RREG32(mmPA_SC_ENHANCE));
3439
3440 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
3441 RREG32(mmCP_ME_CNTL));
3442 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
3443 RREG32(mmCP_MAX_CONTEXT));
3444 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n",
3445 RREG32(mmCP_ENDIAN_SWAP));
3446 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
3447 RREG32(mmCP_DEVICE_ID));
3448
3449 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
3450 RREG32(mmCP_SEM_WAIT_TIMER));
3451
3452 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
3453 RREG32(mmCP_RB_WPTR_DELAY));
3454 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
3455 RREG32(mmCP_RB_VMID));
3456 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
3457 RREG32(mmCP_RB0_CNTL));
3458 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
3459 RREG32(mmCP_RB0_WPTR));
3460 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
3461 RREG32(mmCP_RB0_RPTR_ADDR));
3462 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
3463 RREG32(mmCP_RB0_RPTR_ADDR_HI));
3464 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
3465 RREG32(mmCP_RB0_CNTL));
3466 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
3467 RREG32(mmCP_RB0_BASE));
3468 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
3469 RREG32(mmCP_RB0_BASE_HI));
3470 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
3471 RREG32(mmCP_MEC_CNTL));
3472 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n",
3473 RREG32(mmCP_CPF_DEBUG));
3474
3475 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
3476 RREG32(mmSCRATCH_ADDR));
3477 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
3478 RREG32(mmSCRATCH_UMSK));
3479
3480 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
3481 RREG32(mmCP_INT_CNTL_RING0));
3482 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
3483 RREG32(mmRLC_LB_CNTL));
3484 dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
3485 RREG32(mmRLC_CNTL));
3486 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
3487 RREG32(mmRLC_CGCG_CGLS_CTRL));
3488 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
3489 RREG32(mmRLC_LB_CNTR_INIT));
3490 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
3491 RREG32(mmRLC_LB_CNTR_MAX));
3492 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
3493 RREG32(mmRLC_LB_INIT_CU_MASK));
3494 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
3495 RREG32(mmRLC_LB_PARAMS));
3496 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
3497 RREG32(mmRLC_LB_CNTL));
3498 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n",
3499 RREG32(mmRLC_MC_CNTL));
3500 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
3501 RREG32(mmRLC_UCODE_CNTL));
3502
3503 mutex_lock(&adev->srbm_mutex);
3504 for (i = 0; i < 16; i++) {
3505 vi_srbm_select(adev, 0, 0, 0, i);
3506 dev_info(adev->dev, " VM %d:\n", i);
3507 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
3508 RREG32(mmSH_MEM_CONFIG));
3509 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n",
3510 RREG32(mmSH_MEM_APE1_BASE));
3511 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n",
3512 RREG32(mmSH_MEM_APE1_LIMIT));
3513 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
3514 RREG32(mmSH_MEM_BASES));
3515 }
3516 vi_srbm_select(adev, 0, 0, 0, 0);
3517 mutex_unlock(&adev->srbm_mutex);
3518 }
3519
3520 static int gfx_v8_0_soft_reset(void *handle)
3521 {
3522 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3523 u32 tmp;
3524 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3525
3526 /* GRBM_STATUS */
3527 tmp = RREG32(mmGRBM_STATUS);
3528 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3529 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3530 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3531 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3532 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3533 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3534 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3535 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3536 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3537 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3538 }
3539
3540 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3541 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3542 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3543 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3544 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3545 }
3546
3547 /* GRBM_STATUS2 */
3548 tmp = RREG32(mmGRBM_STATUS2);
3549 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3550 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3551 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3552
3553 /* SRBM_STATUS */
3554 tmp = RREG32(mmSRBM_STATUS);
3555 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
3556 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3557 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3558
3559 if (grbm_soft_reset || srbm_soft_reset) {
3560 gfx_v8_0_print_status((void *)adev);
3561 /* stop the rlc */
3562 gfx_v8_0_rlc_stop(adev);
3563
3564 /* Disable GFX parsing/prefetching */
3565 gfx_v8_0_cp_gfx_enable(adev, false);
3566
3567 /* Disable MEC parsing/prefetching */
3568 /* XXX todo */
3569
3570 if (grbm_soft_reset) {
3571 tmp = RREG32(mmGRBM_SOFT_RESET);
3572 tmp |= grbm_soft_reset;
3573 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3574 WREG32(mmGRBM_SOFT_RESET, tmp);
3575 tmp = RREG32(mmGRBM_SOFT_RESET);
3576
3577 udelay(50);
3578
3579 tmp &= ~grbm_soft_reset;
3580 WREG32(mmGRBM_SOFT_RESET, tmp);
3581 tmp = RREG32(mmGRBM_SOFT_RESET);
3582 }
3583
3584 if (srbm_soft_reset) {
3585 tmp = RREG32(mmSRBM_SOFT_RESET);
3586 tmp |= srbm_soft_reset;
3587 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3588 WREG32(mmSRBM_SOFT_RESET, tmp);
3589 tmp = RREG32(mmSRBM_SOFT_RESET);
3590
3591 udelay(50);
3592
3593 tmp &= ~srbm_soft_reset;
3594 WREG32(mmSRBM_SOFT_RESET, tmp);
3595 tmp = RREG32(mmSRBM_SOFT_RESET);
3596 }
3597 /* Wait a little for things to settle down */
3598 udelay(50);
3599 gfx_v8_0_print_status((void *)adev);
3600 }
3601 return 0;
3602 }
3603
3604 /**
3605 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
3606 *
3607 * @adev: amdgpu_device pointer
3608 *
3609 * Fetches a GPU clock counter snapshot.
3610 * Returns the 64 bit clock counter snapshot.
3611 */
3612 uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3613 {
3614 uint64_t clock;
3615
3616 mutex_lock(&adev->gfx.gpu_clock_mutex);
3617 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3618 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3619 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3620 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3621 return clock;
3622 }
3623
3624 static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3625 uint32_t vmid,
3626 uint32_t gds_base, uint32_t gds_size,
3627 uint32_t gws_base, uint32_t gws_size,
3628 uint32_t oa_base, uint32_t oa_size)
3629 {
3630 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3631 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3632
3633 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3634 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3635
3636 oa_base = oa_base >> AMDGPU_OA_SHIFT;
3637 oa_size = oa_size >> AMDGPU_OA_SHIFT;
3638
3639 /* GDS Base */
3640 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3641 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3642 WRITE_DATA_DST_SEL(0)));
3643 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
3644 amdgpu_ring_write(ring, 0);
3645 amdgpu_ring_write(ring, gds_base);
3646
3647 /* GDS Size */
3648 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3649 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3650 WRITE_DATA_DST_SEL(0)));
3651 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
3652 amdgpu_ring_write(ring, 0);
3653 amdgpu_ring_write(ring, gds_size);
3654
3655 /* GWS */
3656 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3657 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3658 WRITE_DATA_DST_SEL(0)));
3659 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
3660 amdgpu_ring_write(ring, 0);
3661 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3662
3663 /* OA */
3664 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3665 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3666 WRITE_DATA_DST_SEL(0)));
3667 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
3668 amdgpu_ring_write(ring, 0);
3669 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
3670 }
3671
3672 static int gfx_v8_0_early_init(void *handle)
3673 {
3674 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3675
3676 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
3677 adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
3678 gfx_v8_0_set_ring_funcs(adev);
3679 gfx_v8_0_set_irq_funcs(adev);
3680 gfx_v8_0_set_gds_init(adev);
3681
3682 return 0;
3683 }
3684
3685 static int gfx_v8_0_set_powergating_state(void *handle,
3686 enum amd_powergating_state state)
3687 {
3688 return 0;
3689 }
3690
3691 static int gfx_v8_0_set_clockgating_state(void *handle,
3692 enum amd_clockgating_state state)
3693 {
3694 return 0;
3695 }
3696
3697 static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3698 {
3699 u32 rptr;
3700
3701 rptr = ring->adev->wb.wb[ring->rptr_offs];
3702
3703 return rptr;
3704 }
3705
3706 static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3707 {
3708 struct amdgpu_device *adev = ring->adev;
3709 u32 wptr;
3710
3711 if (ring->use_doorbell)
3712 /* XXX check if swapping is necessary on BE */
3713 wptr = ring->adev->wb.wb[ring->wptr_offs];
3714 else
3715 wptr = RREG32(mmCP_RB0_WPTR);
3716
3717 return wptr;
3718 }
3719
3720 static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3721 {
3722 struct amdgpu_device *adev = ring->adev;
3723
3724 if (ring->use_doorbell) {
3725 /* XXX check if swapping is necessary on BE */
3726 adev->wb.wb[ring->wptr_offs] = ring->wptr;
3727 WDOORBELL32(ring->doorbell_index, ring->wptr);
3728 } else {
3729 WREG32(mmCP_RB0_WPTR, ring->wptr);
3730 (void)RREG32(mmCP_RB0_WPTR);
3731 }
3732 }
3733
3734 static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3735 {
3736 u32 ref_and_mask, reg_mem_engine;
3737
3738 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
3739 switch (ring->me) {
3740 case 1:
3741 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
3742 break;
3743 case 2:
3744 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
3745 break;
3746 default:
3747 return;
3748 }
3749 reg_mem_engine = 0;
3750 } else {
3751 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
3752 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
3753 }
3754
3755 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3756 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3757 WAIT_REG_MEM_FUNCTION(3) | /* == */
3758 reg_mem_engine));
3759 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
3760 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
3761 amdgpu_ring_write(ring, ref_and_mask);
3762 amdgpu_ring_write(ring, ref_and_mask);
3763 amdgpu_ring_write(ring, 0x20); /* poll interval */
3764 }
3765
3766 static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3767 struct amdgpu_ib *ib)
3768 {
3769 bool need_ctx_switch = ring->current_ctx != ib->ctx;
3770 u32 header, control = 0;
3771 u32 next_rptr = ring->wptr + 5;
3772
3773 /* drop the CE preamble IB for the same context */
3774 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
3775 return;
3776
3777 if (need_ctx_switch)
3778 next_rptr += 2;
3779
3780 next_rptr += 4;
3781 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3782 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3783 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3784 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3785 amdgpu_ring_write(ring, next_rptr);
3786
3787 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
3788 if (need_ctx_switch) {
3789 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3790 amdgpu_ring_write(ring, 0);
3791 }
3792
3793 if (ib->flags & AMDGPU_IB_FLAG_CE)
3794 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3795 else
3796 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3797
3798 control |= ib->length_dw |
3799 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3800
3801 amdgpu_ring_write(ring, header);
3802 amdgpu_ring_write(ring,
3803 #ifdef __BIG_ENDIAN
3804 (2 << 0) |
3805 #endif
3806 (ib->gpu_addr & 0xFFFFFFFC));
3807 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3808 amdgpu_ring_write(ring, control);
3809 }
3810
3811 static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3812 struct amdgpu_ib *ib)
3813 {
3814 u32 header, control = 0;
3815 u32 next_rptr = ring->wptr + 5;
3816
3817 control |= INDIRECT_BUFFER_VALID;
3818
3819 next_rptr += 4;
3820 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3821 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3822 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3823 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3824 amdgpu_ring_write(ring, next_rptr);
3825
3826 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3827
3828 control |= ib->length_dw |
3829 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3830
3831 amdgpu_ring_write(ring, header);
3832 amdgpu_ring_write(ring,
3833 #ifdef __BIG_ENDIAN
3834 (2 << 0) |
3835 #endif
3836 (ib->gpu_addr & 0xFFFFFFFC));
3837 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3838 amdgpu_ring_write(ring, control);
3839 }
3840
3841 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
3842 u64 seq, unsigned flags)
3843 {
3844 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3845 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3846
3847 /* EVENT_WRITE_EOP - flush caches, send int */
3848 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3849 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3850 EOP_TC_ACTION_EN |
3851 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3852 EVENT_INDEX(5)));
3853 amdgpu_ring_write(ring, addr & 0xfffffffc);
3854 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
3855 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3856 amdgpu_ring_write(ring, lower_32_bits(seq));
3857 amdgpu_ring_write(ring, upper_32_bits(seq));
3858 }
3859
3860 /**
3861 * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring
3862 *
3863 * @ring: amdgpu ring buffer object
3864 * @semaphore: amdgpu semaphore object
3865 * @emit_wait: Is this a sempahore wait?
3866 *
3867 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
3868 * from running ahead of semaphore waits.
3869 */
3870 static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
3871 struct amdgpu_semaphore *semaphore,
3872 bool emit_wait)
3873 {
3874 uint64_t addr = semaphore->gpu_addr;
3875 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3876
3877 if (ring->adev->asic_type == CHIP_TOPAZ ||
3878 ring->adev->asic_type == CHIP_TONGA)
3879 /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */
3880 return false;
3881 else {
3882 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
3883 amdgpu_ring_write(ring, lower_32_bits(addr));
3884 amdgpu_ring_write(ring, upper_32_bits(addr));
3885 amdgpu_ring_write(ring, sel);
3886 }
3887
3888 if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
3889 /* Prevent the PFP from running ahead of the semaphore wait */
3890 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3891 amdgpu_ring_write(ring, 0x0);
3892 }
3893
3894 return true;
3895 }
3896
3897 static void gfx_v8_0_ce_sync_me(struct amdgpu_ring *ring)
3898 {
3899 struct amdgpu_device *adev = ring->adev;
3900 u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4;
3901
3902 /* instruct DE to set a magic number */
3903 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3904 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3905 WRITE_DATA_DST_SEL(5)));
3906 amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3907 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3908 amdgpu_ring_write(ring, 1);
3909
3910 /* let CE wait till condition satisfied */
3911 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3912 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3913 WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3914 WAIT_REG_MEM_FUNCTION(3) | /* == */
3915 WAIT_REG_MEM_ENGINE(2))); /* ce */
3916 amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3917 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3918 amdgpu_ring_write(ring, 1);
3919 amdgpu_ring_write(ring, 0xffffffff);
3920 amdgpu_ring_write(ring, 4); /* poll interval */
3921
3922 /* instruct CE to reset wb of ce_sync to zero */
3923 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3924 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3925 WRITE_DATA_DST_SEL(5) |
3926 WR_CONFIRM));
3927 amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3928 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3929 amdgpu_ring_write(ring, 0);
3930 }
3931
3932 static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3933 unsigned vm_id, uint64_t pd_addr)
3934 {
3935 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
3936
3937 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3938 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3939 WRITE_DATA_DST_SEL(0)));
3940 if (vm_id < 8) {
3941 amdgpu_ring_write(ring,
3942 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3943 } else {
3944 amdgpu_ring_write(ring,
3945 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3946 }
3947 amdgpu_ring_write(ring, 0);
3948 amdgpu_ring_write(ring, pd_addr >> 12);
3949
3950 /* bits 0-15 are the VM contexts0-15 */
3951 /* invalidate the cache */
3952 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3953 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3954 WRITE_DATA_DST_SEL(0)));
3955 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3956 amdgpu_ring_write(ring, 0);
3957 amdgpu_ring_write(ring, 1 << vm_id);
3958
3959 /* wait for the invalidate to complete */
3960 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3961 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3962 WAIT_REG_MEM_FUNCTION(0) | /* always */
3963 WAIT_REG_MEM_ENGINE(0))); /* me */
3964 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3965 amdgpu_ring_write(ring, 0);
3966 amdgpu_ring_write(ring, 0); /* ref */
3967 amdgpu_ring_write(ring, 0); /* mask */
3968 amdgpu_ring_write(ring, 0x20); /* poll interval */
3969
3970 /* compute doesn't have PFP */
3971 if (usepfp) {
3972 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3973 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3974 amdgpu_ring_write(ring, 0x0);
3975
3976 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3977 gfx_v8_0_ce_sync_me(ring);
3978 }
3979 }
3980
3981 static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring)
3982 {
3983 if (gfx_v8_0_is_idle(ring->adev)) {
3984 amdgpu_ring_lockup_update(ring);
3985 return false;
3986 }
3987 return amdgpu_ring_test_lockup(ring);
3988 }
3989
3990 static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3991 {
3992 return ring->adev->wb.wb[ring->rptr_offs];
3993 }
3994
3995 static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3996 {
3997 return ring->adev->wb.wb[ring->wptr_offs];
3998 }
3999
4000 static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4001 {
4002 struct amdgpu_device *adev = ring->adev;
4003
4004 /* XXX check if swapping is necessary on BE */
4005 adev->wb.wb[ring->wptr_offs] = ring->wptr;
4006 WDOORBELL32(ring->doorbell_index, ring->wptr);
4007 }
4008
4009 static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
4010 u64 addr, u64 seq,
4011 unsigned flags)
4012 {
4013 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4014 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4015
4016 /* RELEASE_MEM - flush caches, send int */
4017 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
4018 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
4019 EOP_TC_ACTION_EN |
4020 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4021 EVENT_INDEX(5)));
4022 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4023 amdgpu_ring_write(ring, addr & 0xfffffffc);
4024 amdgpu_ring_write(ring, upper_32_bits(addr));
4025 amdgpu_ring_write(ring, lower_32_bits(seq));
4026 amdgpu_ring_write(ring, upper_32_bits(seq));
4027 }
4028
4029 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4030 enum amdgpu_interrupt_state state)
4031 {
4032 u32 cp_int_cntl;
4033
4034 switch (state) {
4035 case AMDGPU_IRQ_STATE_DISABLE:
4036 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4037 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4038 TIME_STAMP_INT_ENABLE, 0);
4039 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4040 break;
4041 case AMDGPU_IRQ_STATE_ENABLE:
4042 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4043 cp_int_cntl =
4044 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4045 TIME_STAMP_INT_ENABLE, 1);
4046 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4047 break;
4048 default:
4049 break;
4050 }
4051 }
4052
4053 static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4054 int me, int pipe,
4055 enum amdgpu_interrupt_state state)
4056 {
4057 u32 mec_int_cntl, mec_int_cntl_reg;
4058
4059 /*
4060 * amdgpu controls only pipe 0 of MEC1. That's why this function only
4061 * handles the setting of interrupts for this specific pipe. All other
4062 * pipes' interrupts are set by amdkfd.
4063 */
4064
4065 if (me == 1) {
4066 switch (pipe) {
4067 case 0:
4068 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4069 break;
4070 default:
4071 DRM_DEBUG("invalid pipe %d\n", pipe);
4072 return;
4073 }
4074 } else {
4075 DRM_DEBUG("invalid me %d\n", me);
4076 return;
4077 }
4078
4079 switch (state) {
4080 case AMDGPU_IRQ_STATE_DISABLE:
4081 mec_int_cntl = RREG32(mec_int_cntl_reg);
4082 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4083 TIME_STAMP_INT_ENABLE, 0);
4084 WREG32(mec_int_cntl_reg, mec_int_cntl);
4085 break;
4086 case AMDGPU_IRQ_STATE_ENABLE:
4087 mec_int_cntl = RREG32(mec_int_cntl_reg);
4088 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4089 TIME_STAMP_INT_ENABLE, 1);
4090 WREG32(mec_int_cntl_reg, mec_int_cntl);
4091 break;
4092 default:
4093 break;
4094 }
4095 }
4096
4097 static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4098 struct amdgpu_irq_src *source,
4099 unsigned type,
4100 enum amdgpu_interrupt_state state)
4101 {
4102 u32 cp_int_cntl;
4103
4104 switch (state) {
4105 case AMDGPU_IRQ_STATE_DISABLE:
4106 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4107 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4108 PRIV_REG_INT_ENABLE, 0);
4109 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4110 break;
4111 case AMDGPU_IRQ_STATE_ENABLE:
4112 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4113 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4114 PRIV_REG_INT_ENABLE, 0);
4115 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4116 break;
4117 default:
4118 break;
4119 }
4120
4121 return 0;
4122 }
4123
4124 static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4125 struct amdgpu_irq_src *source,
4126 unsigned type,
4127 enum amdgpu_interrupt_state state)
4128 {
4129 u32 cp_int_cntl;
4130
4131 switch (state) {
4132 case AMDGPU_IRQ_STATE_DISABLE:
4133 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4134 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4135 PRIV_INSTR_INT_ENABLE, 0);
4136 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4137 break;
4138 case AMDGPU_IRQ_STATE_ENABLE:
4139 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4140 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4141 PRIV_INSTR_INT_ENABLE, 1);
4142 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4143 break;
4144 default:
4145 break;
4146 }
4147
4148 return 0;
4149 }
4150
4151 static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4152 struct amdgpu_irq_src *src,
4153 unsigned type,
4154 enum amdgpu_interrupt_state state)
4155 {
4156 switch (type) {
4157 case AMDGPU_CP_IRQ_GFX_EOP:
4158 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
4159 break;
4160 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4161 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4162 break;
4163 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4164 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4165 break;
4166 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4167 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4168 break;
4169 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4170 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4171 break;
4172 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4173 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4174 break;
4175 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4176 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4177 break;
4178 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4179 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4180 break;
4181 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4182 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4183 break;
4184 default:
4185 break;
4186 }
4187 return 0;
4188 }
4189
4190 static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
4191 struct amdgpu_irq_src *source,
4192 struct amdgpu_iv_entry *entry)
4193 {
4194 int i;
4195 u8 me_id, pipe_id, queue_id;
4196 struct amdgpu_ring *ring;
4197
4198 DRM_DEBUG("IH: CP EOP\n");
4199 me_id = (entry->ring_id & 0x0c) >> 2;
4200 pipe_id = (entry->ring_id & 0x03) >> 0;
4201 queue_id = (entry->ring_id & 0x70) >> 4;
4202
4203 switch (me_id) {
4204 case 0:
4205 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4206 break;
4207 case 1:
4208 case 2:
4209 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4210 ring = &adev->gfx.compute_ring[i];
4211 /* Per-queue interrupt is supported for MEC starting from VI.
4212 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4213 */
4214 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4215 amdgpu_fence_process(ring);
4216 }
4217 break;
4218 }
4219 return 0;
4220 }
4221
4222 static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
4223 struct amdgpu_irq_src *source,
4224 struct amdgpu_iv_entry *entry)
4225 {
4226 DRM_ERROR("Illegal register access in command stream\n");
4227 schedule_work(&adev->reset_work);
4228 return 0;
4229 }
4230
4231 static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
4232 struct amdgpu_irq_src *source,
4233 struct amdgpu_iv_entry *entry)
4234 {
4235 DRM_ERROR("Illegal instruction in command stream\n");
4236 schedule_work(&adev->reset_work);
4237 return 0;
4238 }
4239
4240 const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
4241 .early_init = gfx_v8_0_early_init,
4242 .late_init = NULL,
4243 .sw_init = gfx_v8_0_sw_init,
4244 .sw_fini = gfx_v8_0_sw_fini,
4245 .hw_init = gfx_v8_0_hw_init,
4246 .hw_fini = gfx_v8_0_hw_fini,
4247 .suspend = gfx_v8_0_suspend,
4248 .resume = gfx_v8_0_resume,
4249 .is_idle = gfx_v8_0_is_idle,
4250 .wait_for_idle = gfx_v8_0_wait_for_idle,
4251 .soft_reset = gfx_v8_0_soft_reset,
4252 .print_status = gfx_v8_0_print_status,
4253 .set_clockgating_state = gfx_v8_0_set_clockgating_state,
4254 .set_powergating_state = gfx_v8_0_set_powergating_state,
4255 };
4256
4257 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
4258 .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
4259 .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
4260 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
4261 .parse_cs = NULL,
4262 .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
4263 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
4264 .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4265 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4266 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4267 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4268 .test_ring = gfx_v8_0_ring_test_ring,
4269 .test_ib = gfx_v8_0_ring_test_ib,
4270 .is_lockup = gfx_v8_0_ring_is_lockup,
4271 };
4272
4273 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
4274 .get_rptr = gfx_v8_0_ring_get_rptr_compute,
4275 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
4276 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
4277 .parse_cs = NULL,
4278 .emit_ib = gfx_v8_0_ring_emit_ib_compute,
4279 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
4280 .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4281 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4282 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4283 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4284 .test_ring = gfx_v8_0_ring_test_ring,
4285 .test_ib = gfx_v8_0_ring_test_ib,
4286 .is_lockup = gfx_v8_0_ring_is_lockup,
4287 };
4288
4289 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
4290 {
4291 int i;
4292
4293 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4294 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
4295
4296 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4297 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
4298 }
4299
4300 static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
4301 .set = gfx_v8_0_set_eop_interrupt_state,
4302 .process = gfx_v8_0_eop_irq,
4303 };
4304
4305 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
4306 .set = gfx_v8_0_set_priv_reg_fault_state,
4307 .process = gfx_v8_0_priv_reg_irq,
4308 };
4309
4310 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
4311 .set = gfx_v8_0_set_priv_inst_fault_state,
4312 .process = gfx_v8_0_priv_inst_irq,
4313 };
4314
4315 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
4316 {
4317 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4318 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
4319
4320 adev->gfx.priv_reg_irq.num_types = 1;
4321 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
4322
4323 adev->gfx.priv_inst_irq.num_types = 1;
4324 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
4325 }
4326
4327 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
4328 {
4329 /* init asci gds info */
4330 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
4331 adev->gds.gws.total_size = 64;
4332 adev->gds.oa.total_size = 16;
4333
4334 if (adev->gds.mem.total_size == 64 * 1024) {
4335 adev->gds.mem.gfx_partition_size = 4096;
4336 adev->gds.mem.cs_partition_size = 4096;
4337
4338 adev->gds.gws.gfx_partition_size = 4;
4339 adev->gds.gws.cs_partition_size = 4;
4340
4341 adev->gds.oa.gfx_partition_size = 4;
4342 adev->gds.oa.cs_partition_size = 1;
4343 } else {
4344 adev->gds.mem.gfx_partition_size = 1024;
4345 adev->gds.mem.cs_partition_size = 1024;
4346
4347 adev->gds.gws.gfx_partition_size = 16;
4348 adev->gds.gws.cs_partition_size = 16;
4349
4350 adev->gds.oa.gfx_partition_size = 4;
4351 adev->gds.oa.cs_partition_size = 4;
4352 }
4353 }
4354
4355 static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev,
4356 u32 se, u32 sh)
4357 {
4358 u32 mask = 0, tmp, tmp1;
4359 int i;
4360
4361 gfx_v8_0_select_se_sh(adev, se, sh);
4362 tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4363 tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4364 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4365
4366 tmp &= 0xffff0000;
4367
4368 tmp |= tmp1;
4369 tmp >>= 16;
4370
4371 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
4372 mask <<= 1;
4373 mask |= 1;
4374 }
4375
4376 return (~tmp) & mask;
4377 }
4378
4379 int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
4380 struct amdgpu_cu_info *cu_info)
4381 {
4382 int i, j, k, counter, active_cu_number = 0;
4383 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4384
4385 if (!adev || !cu_info)
4386 return -EINVAL;
4387
4388 mutex_lock(&adev->grbm_idx_mutex);
4389 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4390 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4391 mask = 1;
4392 ao_bitmap = 0;
4393 counter = 0;
4394 bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j);
4395 cu_info->bitmap[i][j] = bitmap;
4396
4397 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4398 if (bitmap & mask) {
4399 if (counter < 2)
4400 ao_bitmap |= mask;
4401 counter ++;
4402 }
4403 mask <<= 1;
4404 }
4405 active_cu_number += counter;
4406 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4407 }
4408 }
4409
4410 cu_info->number = active_cu_number;
4411 cu_info->ao_cu_mask = ao_cu_mask;
4412 mutex_unlock(&adev->grbm_idx_mutex);
4413 return 0;
4414 }
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