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Merge branch 'drm-next-4.2-amdgpu' of git://people.freedesktop.org/~agd5f/linux into...
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v8_0.c
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include "drmP.h"
25 #include "amdgpu.h"
26 #include "amdgpu_gfx.h"
27 #include "vi.h"
28 #include "vid.h"
29 #include "amdgpu_ucode.h"
30 #include "clearstate_vi.h"
31
32 #include "gmc/gmc_8_2_d.h"
33 #include "gmc/gmc_8_2_sh_mask.h"
34
35 #include "oss/oss_3_0_d.h"
36 #include "oss/oss_3_0_sh_mask.h"
37
38 #include "bif/bif_5_0_d.h"
39 #include "bif/bif_5_0_sh_mask.h"
40
41 #include "gca/gfx_8_0_d.h"
42 #include "gca/gfx_8_0_enum.h"
43 #include "gca/gfx_8_0_sh_mask.h"
44 #include "gca/gfx_8_0_enum.h"
45
46 #include "uvd/uvd_5_0_d.h"
47 #include "uvd/uvd_5_0_sh_mask.h"
48
49 #include "dce/dce_10_0_d.h"
50 #include "dce/dce_10_0_sh_mask.h"
51
52 #define GFX8_NUM_GFX_RINGS 1
53 #define GFX8_NUM_COMPUTE_RINGS 8
54
55 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
56 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
57 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
58
59 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
60 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
61 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
62 #define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
63 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
64 #define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
65 #define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
66 #define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
67 #define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
68
69 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
70 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
71 MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
72 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
73 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
74 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
75
76 MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
77 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
78 MODULE_FIRMWARE("amdgpu/tonga_me.bin");
79 MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
80 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
81 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
82
83 MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
84 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
85 MODULE_FIRMWARE("amdgpu/topaz_me.bin");
86 MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
87 MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
88 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
89
90 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
91 {
92 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
93 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
94 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
95 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
96 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
97 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
98 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
99 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
100 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
101 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
102 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
103 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
104 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
105 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
106 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
107 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
108 };
109
110 static const u32 golden_settings_tonga_a11[] =
111 {
112 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
113 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
114 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
115 mmGB_GPU_ID, 0x0000000f, 0x00000000,
116 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
117 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
118 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
119 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
120 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
121 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
122 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
123 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
124 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
125 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
126 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
127 };
128
129 static const u32 tonga_golden_common_all[] =
130 {
131 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
132 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
133 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
134 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
135 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
136 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
137 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
138 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
139 };
140
141 static const u32 tonga_mgcg_cgcg_init[] =
142 {
143 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
144 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
145 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
146 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
147 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
148 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
149 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
150 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
151 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
152 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
153 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
154 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
155 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
156 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
157 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
158 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
159 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
160 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
161 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
162 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
163 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
164 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
165 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
166 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
167 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
168 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
169 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
170 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
171 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
172 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
173 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
174 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
175 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
176 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
177 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
178 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
179 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
180 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
181 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
182 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
183 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
184 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
185 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
186 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
187 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
188 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
189 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
190 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
191 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
192 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
193 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
194 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
195 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
196 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
197 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
198 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
199 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
200 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
201 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
202 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
203 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
204 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
205 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
206 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
207 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
208 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
209 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
210 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
211 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
212 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
213 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
214 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
215 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
216 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
217 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
218 };
219
220 static const u32 golden_settings_iceland_a11[] =
221 {
222 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
223 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
224 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
225 mmGB_GPU_ID, 0x0000000f, 0x00000000,
226 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
227 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
228 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
229 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
230 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
231 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
232 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
233 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
234 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
235 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
236 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
237 };
238
239 static const u32 iceland_golden_common_all[] =
240 {
241 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
242 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
243 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
244 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
245 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
246 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
247 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
248 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
249 };
250
251 static const u32 iceland_mgcg_cgcg_init[] =
252 {
253 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
254 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
255 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
256 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
257 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
258 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
259 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
260 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
261 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
262 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
263 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
264 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
265 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
266 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
267 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
268 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
269 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
270 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
271 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
272 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
273 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
274 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
275 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
276 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
277 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
278 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
279 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
280 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
281 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
282 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
283 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
284 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
285 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
286 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
287 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
288 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
289 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
290 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
291 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
292 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
293 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
294 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
295 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
296 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
297 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
298 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
299 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
300 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
301 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
302 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
303 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
304 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
305 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
306 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
307 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
308 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
309 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
310 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
311 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
312 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
313 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
314 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
315 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
316 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
317 };
318
319 static const u32 cz_golden_settings_a11[] =
320 {
321 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
322 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
323 mmGB_GPU_ID, 0x0000000f, 0x00000000,
324 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
325 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
326 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
327 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
328 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
329 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
330 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
331 };
332
333 static const u32 cz_golden_common_all[] =
334 {
335 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
336 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
337 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
338 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
339 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
340 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
341 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
342 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
343 };
344
345 static const u32 cz_mgcg_cgcg_init[] =
346 {
347 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
348 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
349 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
350 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
351 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
352 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
353 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
354 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
355 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
356 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
357 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
358 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
359 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
360 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
361 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
362 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
363 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
364 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
365 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
366 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
367 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
368 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
369 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
370 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
371 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
372 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
373 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
374 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
375 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
376 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
377 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
378 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
379 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
380 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
381 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
382 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
383 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
384 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
385 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
386 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
387 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
388 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
389 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
390 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
391 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
392 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
393 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
394 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
395 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
396 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
397 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
398 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
399 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
400 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
401 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
402 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
403 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
404 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
405 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
406 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
407 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
408 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
409 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
410 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
411 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
412 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
413 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
414 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
415 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
416 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
417 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
418 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
419 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
420 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
421 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
422 };
423
424 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
425 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
426 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
427
428 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
429 {
430 switch (adev->asic_type) {
431 case CHIP_TOPAZ:
432 amdgpu_program_register_sequence(adev,
433 iceland_mgcg_cgcg_init,
434 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
435 amdgpu_program_register_sequence(adev,
436 golden_settings_iceland_a11,
437 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
438 amdgpu_program_register_sequence(adev,
439 iceland_golden_common_all,
440 (const u32)ARRAY_SIZE(iceland_golden_common_all));
441 break;
442 case CHIP_TONGA:
443 amdgpu_program_register_sequence(adev,
444 tonga_mgcg_cgcg_init,
445 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
446 amdgpu_program_register_sequence(adev,
447 golden_settings_tonga_a11,
448 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
449 amdgpu_program_register_sequence(adev,
450 tonga_golden_common_all,
451 (const u32)ARRAY_SIZE(tonga_golden_common_all));
452 break;
453 case CHIP_CARRIZO:
454 amdgpu_program_register_sequence(adev,
455 cz_mgcg_cgcg_init,
456 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
457 amdgpu_program_register_sequence(adev,
458 cz_golden_settings_a11,
459 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
460 amdgpu_program_register_sequence(adev,
461 cz_golden_common_all,
462 (const u32)ARRAY_SIZE(cz_golden_common_all));
463 break;
464 default:
465 break;
466 }
467 }
468
469 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
470 {
471 int i;
472
473 adev->gfx.scratch.num_reg = 7;
474 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
475 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
476 adev->gfx.scratch.free[i] = true;
477 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
478 }
479 }
480
481 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
482 {
483 struct amdgpu_device *adev = ring->adev;
484 uint32_t scratch;
485 uint32_t tmp = 0;
486 unsigned i;
487 int r;
488
489 r = amdgpu_gfx_scratch_get(adev, &scratch);
490 if (r) {
491 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
492 return r;
493 }
494 WREG32(scratch, 0xCAFEDEAD);
495 r = amdgpu_ring_lock(ring, 3);
496 if (r) {
497 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
498 ring->idx, r);
499 amdgpu_gfx_scratch_free(adev, scratch);
500 return r;
501 }
502 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
503 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
504 amdgpu_ring_write(ring, 0xDEADBEEF);
505 amdgpu_ring_unlock_commit(ring);
506
507 for (i = 0; i < adev->usec_timeout; i++) {
508 tmp = RREG32(scratch);
509 if (tmp == 0xDEADBEEF)
510 break;
511 DRM_UDELAY(1);
512 }
513 if (i < adev->usec_timeout) {
514 DRM_INFO("ring test on %d succeeded in %d usecs\n",
515 ring->idx, i);
516 } else {
517 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
518 ring->idx, scratch, tmp);
519 r = -EINVAL;
520 }
521 amdgpu_gfx_scratch_free(adev, scratch);
522 return r;
523 }
524
525 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
526 {
527 struct amdgpu_device *adev = ring->adev;
528 struct amdgpu_ib ib;
529 uint32_t scratch;
530 uint32_t tmp = 0;
531 unsigned i;
532 int r;
533
534 r = amdgpu_gfx_scratch_get(adev, &scratch);
535 if (r) {
536 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
537 return r;
538 }
539 WREG32(scratch, 0xCAFEDEAD);
540 r = amdgpu_ib_get(ring, NULL, 256, &ib);
541 if (r) {
542 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
543 amdgpu_gfx_scratch_free(adev, scratch);
544 return r;
545 }
546 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
547 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
548 ib.ptr[2] = 0xDEADBEEF;
549 ib.length_dw = 3;
550 r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
551 if (r) {
552 amdgpu_gfx_scratch_free(adev, scratch);
553 amdgpu_ib_free(adev, &ib);
554 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
555 return r;
556 }
557 r = amdgpu_fence_wait(ib.fence, false);
558 if (r) {
559 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
560 amdgpu_gfx_scratch_free(adev, scratch);
561 amdgpu_ib_free(adev, &ib);
562 return r;
563 }
564 for (i = 0; i < adev->usec_timeout; i++) {
565 tmp = RREG32(scratch);
566 if (tmp == 0xDEADBEEF)
567 break;
568 DRM_UDELAY(1);
569 }
570 if (i < adev->usec_timeout) {
571 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
572 ib.fence->ring->idx, i);
573 } else {
574 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
575 scratch, tmp);
576 r = -EINVAL;
577 }
578 amdgpu_gfx_scratch_free(adev, scratch);
579 amdgpu_ib_free(adev, &ib);
580 return r;
581 }
582
583 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
584 {
585 const char *chip_name;
586 char fw_name[30];
587 int err;
588 struct amdgpu_firmware_info *info = NULL;
589 const struct common_firmware_header *header = NULL;
590
591 DRM_DEBUG("\n");
592
593 switch (adev->asic_type) {
594 case CHIP_TOPAZ:
595 chip_name = "topaz";
596 break;
597 case CHIP_TONGA:
598 chip_name = "tonga";
599 break;
600 case CHIP_CARRIZO:
601 chip_name = "carrizo";
602 break;
603 default:
604 BUG();
605 }
606
607 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
608 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
609 if (err)
610 goto out;
611 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
612 if (err)
613 goto out;
614
615 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
616 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
617 if (err)
618 goto out;
619 err = amdgpu_ucode_validate(adev->gfx.me_fw);
620 if (err)
621 goto out;
622
623 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
624 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
625 if (err)
626 goto out;
627 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
628 if (err)
629 goto out;
630
631 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
632 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
633 if (err)
634 goto out;
635 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
636
637 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
638 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
639 if (err)
640 goto out;
641 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
642 if (err)
643 goto out;
644
645 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
646 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
647 if (!err) {
648 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
649 if (err)
650 goto out;
651 } else {
652 err = 0;
653 adev->gfx.mec2_fw = NULL;
654 }
655
656 if (adev->firmware.smu_load) {
657 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
658 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
659 info->fw = adev->gfx.pfp_fw;
660 header = (const struct common_firmware_header *)info->fw->data;
661 adev->firmware.fw_size +=
662 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
663
664 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
665 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
666 info->fw = adev->gfx.me_fw;
667 header = (const struct common_firmware_header *)info->fw->data;
668 adev->firmware.fw_size +=
669 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
670
671 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
672 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
673 info->fw = adev->gfx.ce_fw;
674 header = (const struct common_firmware_header *)info->fw->data;
675 adev->firmware.fw_size +=
676 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
677
678 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
679 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
680 info->fw = adev->gfx.rlc_fw;
681 header = (const struct common_firmware_header *)info->fw->data;
682 adev->firmware.fw_size +=
683 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
684
685 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
686 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
687 info->fw = adev->gfx.mec_fw;
688 header = (const struct common_firmware_header *)info->fw->data;
689 adev->firmware.fw_size +=
690 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
691
692 if (adev->gfx.mec2_fw) {
693 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
694 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
695 info->fw = adev->gfx.mec2_fw;
696 header = (const struct common_firmware_header *)info->fw->data;
697 adev->firmware.fw_size +=
698 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
699 }
700
701 }
702
703 out:
704 if (err) {
705 dev_err(adev->dev,
706 "gfx8: Failed to load firmware \"%s\"\n",
707 fw_name);
708 release_firmware(adev->gfx.pfp_fw);
709 adev->gfx.pfp_fw = NULL;
710 release_firmware(adev->gfx.me_fw);
711 adev->gfx.me_fw = NULL;
712 release_firmware(adev->gfx.ce_fw);
713 adev->gfx.ce_fw = NULL;
714 release_firmware(adev->gfx.rlc_fw);
715 adev->gfx.rlc_fw = NULL;
716 release_firmware(adev->gfx.mec_fw);
717 adev->gfx.mec_fw = NULL;
718 release_firmware(adev->gfx.mec2_fw);
719 adev->gfx.mec2_fw = NULL;
720 }
721 return err;
722 }
723
724 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
725 {
726 int r;
727
728 if (adev->gfx.mec.hpd_eop_obj) {
729 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
730 if (unlikely(r != 0))
731 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
732 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
733 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
734
735 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
736 adev->gfx.mec.hpd_eop_obj = NULL;
737 }
738 }
739
740 #define MEC_HPD_SIZE 2048
741
742 static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
743 {
744 int r;
745 u32 *hpd;
746
747 /*
748 * we assign only 1 pipe because all other pipes will
749 * be handled by KFD
750 */
751 adev->gfx.mec.num_mec = 1;
752 adev->gfx.mec.num_pipe = 1;
753 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
754
755 if (adev->gfx.mec.hpd_eop_obj == NULL) {
756 r = amdgpu_bo_create(adev,
757 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
758 PAGE_SIZE, true,
759 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
760 &adev->gfx.mec.hpd_eop_obj);
761 if (r) {
762 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
763 return r;
764 }
765 }
766
767 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
768 if (unlikely(r != 0)) {
769 gfx_v8_0_mec_fini(adev);
770 return r;
771 }
772 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
773 &adev->gfx.mec.hpd_eop_gpu_addr);
774 if (r) {
775 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
776 gfx_v8_0_mec_fini(adev);
777 return r;
778 }
779 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
780 if (r) {
781 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
782 gfx_v8_0_mec_fini(adev);
783 return r;
784 }
785
786 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
787
788 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
789 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
790
791 return 0;
792 }
793
794 static int gfx_v8_0_sw_init(void *handle)
795 {
796 int i, r;
797 struct amdgpu_ring *ring;
798 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
799
800 /* EOP Event */
801 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
802 if (r)
803 return r;
804
805 /* Privileged reg */
806 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
807 if (r)
808 return r;
809
810 /* Privileged inst */
811 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
812 if (r)
813 return r;
814
815 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
816
817 gfx_v8_0_scratch_init(adev);
818
819 r = gfx_v8_0_init_microcode(adev);
820 if (r) {
821 DRM_ERROR("Failed to load gfx firmware!\n");
822 return r;
823 }
824
825 r = gfx_v8_0_mec_init(adev);
826 if (r) {
827 DRM_ERROR("Failed to init MEC BOs!\n");
828 return r;
829 }
830
831 r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs);
832 if (r) {
833 DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r);
834 return r;
835 }
836
837 /* set up the gfx ring */
838 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
839 ring = &adev->gfx.gfx_ring[i];
840 ring->ring_obj = NULL;
841 sprintf(ring->name, "gfx");
842 /* no gfx doorbells on iceland */
843 if (adev->asic_type != CHIP_TOPAZ) {
844 ring->use_doorbell = true;
845 ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
846 }
847
848 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
849 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
850 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
851 AMDGPU_RING_TYPE_GFX);
852 if (r)
853 return r;
854 }
855
856 /* set up the compute queues */
857 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
858 unsigned irq_type;
859
860 /* max 32 queues per MEC */
861 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
862 DRM_ERROR("Too many (%d) compute rings!\n", i);
863 break;
864 }
865 ring = &adev->gfx.compute_ring[i];
866 ring->ring_obj = NULL;
867 ring->use_doorbell = true;
868 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
869 ring->me = 1; /* first MEC */
870 ring->pipe = i / 8;
871 ring->queue = i % 8;
872 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
873 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
874 /* type-2 packets are deprecated on MEC, use type-3 instead */
875 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
876 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
877 &adev->gfx.eop_irq, irq_type,
878 AMDGPU_RING_TYPE_COMPUTE);
879 if (r)
880 return r;
881 }
882
883 /* reserve GDS, GWS and OA resource for gfx */
884 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
885 PAGE_SIZE, true,
886 AMDGPU_GEM_DOMAIN_GDS, 0,
887 NULL, &adev->gds.gds_gfx_bo);
888 if (r)
889 return r;
890
891 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
892 PAGE_SIZE, true,
893 AMDGPU_GEM_DOMAIN_GWS, 0,
894 NULL, &adev->gds.gws_gfx_bo);
895 if (r)
896 return r;
897
898 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
899 PAGE_SIZE, true,
900 AMDGPU_GEM_DOMAIN_OA, 0,
901 NULL, &adev->gds.oa_gfx_bo);
902 if (r)
903 return r;
904
905 adev->gfx.ce_ram_size = 0x8000;
906
907 return 0;
908 }
909
910 static int gfx_v8_0_sw_fini(void *handle)
911 {
912 int i;
913 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
914
915 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
916 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
917 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
918
919 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
920 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
921 for (i = 0; i < adev->gfx.num_compute_rings; i++)
922 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
923
924 amdgpu_wb_free(adev, adev->gfx.ce_sync_offs);
925
926 gfx_v8_0_mec_fini(adev);
927
928 return 0;
929 }
930
931 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
932 {
933 const u32 num_tile_mode_states = 32;
934 const u32 num_secondary_tile_mode_states = 16;
935 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
936
937 switch (adev->gfx.config.mem_row_size_in_kb) {
938 case 1:
939 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
940 break;
941 case 2:
942 default:
943 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
944 break;
945 case 4:
946 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
947 break;
948 }
949
950 switch (adev->asic_type) {
951 case CHIP_TOPAZ:
952 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
953 switch (reg_offset) {
954 case 0:
955 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
956 PIPE_CONFIG(ADDR_SURF_P2) |
957 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
958 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
959 break;
960 case 1:
961 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
962 PIPE_CONFIG(ADDR_SURF_P2) |
963 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
964 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
965 break;
966 case 2:
967 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
968 PIPE_CONFIG(ADDR_SURF_P2) |
969 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
970 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
971 break;
972 case 3:
973 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
974 PIPE_CONFIG(ADDR_SURF_P2) |
975 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
976 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
977 break;
978 case 4:
979 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
980 PIPE_CONFIG(ADDR_SURF_P2) |
981 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
982 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
983 break;
984 case 5:
985 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
986 PIPE_CONFIG(ADDR_SURF_P2) |
987 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
988 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
989 break;
990 case 6:
991 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
992 PIPE_CONFIG(ADDR_SURF_P2) |
993 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
994 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
995 break;
996 case 8:
997 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
998 PIPE_CONFIG(ADDR_SURF_P2));
999 break;
1000 case 9:
1001 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1002 PIPE_CONFIG(ADDR_SURF_P2) |
1003 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1004 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1005 break;
1006 case 10:
1007 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1008 PIPE_CONFIG(ADDR_SURF_P2) |
1009 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1010 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1011 break;
1012 case 11:
1013 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1014 PIPE_CONFIG(ADDR_SURF_P2) |
1015 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1016 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1017 break;
1018 case 13:
1019 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1020 PIPE_CONFIG(ADDR_SURF_P2) |
1021 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1022 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1023 break;
1024 case 14:
1025 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1026 PIPE_CONFIG(ADDR_SURF_P2) |
1027 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1028 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1029 break;
1030 case 15:
1031 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1032 PIPE_CONFIG(ADDR_SURF_P2) |
1033 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1034 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1035 break;
1036 case 16:
1037 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1038 PIPE_CONFIG(ADDR_SURF_P2) |
1039 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1040 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1041 break;
1042 case 18:
1043 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1044 PIPE_CONFIG(ADDR_SURF_P2) |
1045 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1046 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1047 break;
1048 case 19:
1049 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1050 PIPE_CONFIG(ADDR_SURF_P2) |
1051 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1052 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1053 break;
1054 case 20:
1055 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1056 PIPE_CONFIG(ADDR_SURF_P2) |
1057 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1058 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1059 break;
1060 case 21:
1061 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1062 PIPE_CONFIG(ADDR_SURF_P2) |
1063 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1064 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1065 break;
1066 case 22:
1067 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1068 PIPE_CONFIG(ADDR_SURF_P2) |
1069 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1070 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1071 break;
1072 case 24:
1073 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1074 PIPE_CONFIG(ADDR_SURF_P2) |
1075 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1076 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1077 break;
1078 case 25:
1079 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1080 PIPE_CONFIG(ADDR_SURF_P2) |
1081 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1082 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1083 break;
1084 case 26:
1085 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1086 PIPE_CONFIG(ADDR_SURF_P2) |
1087 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1088 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1089 break;
1090 case 27:
1091 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1092 PIPE_CONFIG(ADDR_SURF_P2) |
1093 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1094 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1095 break;
1096 case 28:
1097 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1098 PIPE_CONFIG(ADDR_SURF_P2) |
1099 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1100 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1101 break;
1102 case 29:
1103 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1104 PIPE_CONFIG(ADDR_SURF_P2) |
1105 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1106 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1107 break;
1108 case 7:
1109 case 12:
1110 case 17:
1111 case 23:
1112 /* unused idx */
1113 continue;
1114 default:
1115 gb_tile_moden = 0;
1116 break;
1117 };
1118 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1119 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1120 }
1121 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1122 switch (reg_offset) {
1123 case 0:
1124 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1125 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1126 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1127 NUM_BANKS(ADDR_SURF_8_BANK));
1128 break;
1129 case 1:
1130 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1131 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1132 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1133 NUM_BANKS(ADDR_SURF_8_BANK));
1134 break;
1135 case 2:
1136 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1137 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1138 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1139 NUM_BANKS(ADDR_SURF_8_BANK));
1140 break;
1141 case 3:
1142 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1143 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1144 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1145 NUM_BANKS(ADDR_SURF_8_BANK));
1146 break;
1147 case 4:
1148 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1149 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1150 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1151 NUM_BANKS(ADDR_SURF_8_BANK));
1152 break;
1153 case 5:
1154 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1155 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1156 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1157 NUM_BANKS(ADDR_SURF_8_BANK));
1158 break;
1159 case 6:
1160 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1163 NUM_BANKS(ADDR_SURF_8_BANK));
1164 break;
1165 case 8:
1166 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1167 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1168 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1169 NUM_BANKS(ADDR_SURF_16_BANK));
1170 break;
1171 case 9:
1172 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1175 NUM_BANKS(ADDR_SURF_16_BANK));
1176 break;
1177 case 10:
1178 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1179 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1180 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1181 NUM_BANKS(ADDR_SURF_16_BANK));
1182 break;
1183 case 11:
1184 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1185 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1186 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1187 NUM_BANKS(ADDR_SURF_16_BANK));
1188 break;
1189 case 12:
1190 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1191 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1192 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1193 NUM_BANKS(ADDR_SURF_16_BANK));
1194 break;
1195 case 13:
1196 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1199 NUM_BANKS(ADDR_SURF_16_BANK));
1200 break;
1201 case 14:
1202 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1203 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1204 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1205 NUM_BANKS(ADDR_SURF_8_BANK));
1206 break;
1207 case 7:
1208 /* unused idx */
1209 continue;
1210 default:
1211 gb_tile_moden = 0;
1212 break;
1213 };
1214 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1215 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1216 }
1217 case CHIP_TONGA:
1218 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1219 switch (reg_offset) {
1220 case 0:
1221 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1222 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1223 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1224 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1225 break;
1226 case 1:
1227 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1228 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1229 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1230 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1231 break;
1232 case 2:
1233 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1234 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1235 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1236 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1237 break;
1238 case 3:
1239 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1240 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1241 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1242 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1243 break;
1244 case 4:
1245 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1246 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1247 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1248 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1249 break;
1250 case 5:
1251 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1252 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1253 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1254 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1255 break;
1256 case 6:
1257 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1258 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1259 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1260 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1261 break;
1262 case 7:
1263 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1264 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1265 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1266 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1267 break;
1268 case 8:
1269 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1270 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
1271 break;
1272 case 9:
1273 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1274 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1275 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1276 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1277 break;
1278 case 10:
1279 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1280 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1281 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1282 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1283 break;
1284 case 11:
1285 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1286 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1287 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1288 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1289 break;
1290 case 12:
1291 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1292 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1293 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1294 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1295 break;
1296 case 13:
1297 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1298 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1299 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1300 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1301 break;
1302 case 14:
1303 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1304 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1305 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1306 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1307 break;
1308 case 15:
1309 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1310 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1311 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1312 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1313 break;
1314 case 16:
1315 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1316 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1317 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1318 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1319 break;
1320 case 17:
1321 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1322 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1323 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1324 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1325 break;
1326 case 18:
1327 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1328 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1329 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1330 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1331 break;
1332 case 19:
1333 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1334 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1335 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1336 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1337 break;
1338 case 20:
1339 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1340 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1341 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1342 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1343 break;
1344 case 21:
1345 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1346 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1347 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1348 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1349 break;
1350 case 22:
1351 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1352 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1353 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1354 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1355 break;
1356 case 23:
1357 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1358 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1359 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1360 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1361 break;
1362 case 24:
1363 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1364 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1365 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1366 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1367 break;
1368 case 25:
1369 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1370 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1371 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1372 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1373 break;
1374 case 26:
1375 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1376 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1377 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1378 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1379 break;
1380 case 27:
1381 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1382 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1383 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1384 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1385 break;
1386 case 28:
1387 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1388 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1389 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1390 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1391 break;
1392 case 29:
1393 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1394 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1395 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1396 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1397 break;
1398 case 30:
1399 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1400 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1401 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1402 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1403 break;
1404 default:
1405 gb_tile_moden = 0;
1406 break;
1407 };
1408 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1409 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1410 }
1411 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1412 switch (reg_offset) {
1413 case 0:
1414 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1415 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1416 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1417 NUM_BANKS(ADDR_SURF_16_BANK));
1418 break;
1419 case 1:
1420 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1421 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1422 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1423 NUM_BANKS(ADDR_SURF_16_BANK));
1424 break;
1425 case 2:
1426 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1427 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1428 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1429 NUM_BANKS(ADDR_SURF_16_BANK));
1430 break;
1431 case 3:
1432 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1433 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1434 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1435 NUM_BANKS(ADDR_SURF_16_BANK));
1436 break;
1437 case 4:
1438 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1439 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1440 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1441 NUM_BANKS(ADDR_SURF_16_BANK));
1442 break;
1443 case 5:
1444 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1445 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1446 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1447 NUM_BANKS(ADDR_SURF_16_BANK));
1448 break;
1449 case 6:
1450 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1451 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1452 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1453 NUM_BANKS(ADDR_SURF_16_BANK));
1454 break;
1455 case 8:
1456 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1457 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1458 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1459 NUM_BANKS(ADDR_SURF_16_BANK));
1460 break;
1461 case 9:
1462 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1463 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1464 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1465 NUM_BANKS(ADDR_SURF_16_BANK));
1466 break;
1467 case 10:
1468 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1469 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1470 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1471 NUM_BANKS(ADDR_SURF_16_BANK));
1472 break;
1473 case 11:
1474 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1475 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1476 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1477 NUM_BANKS(ADDR_SURF_16_BANK));
1478 break;
1479 case 12:
1480 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1481 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1482 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1483 NUM_BANKS(ADDR_SURF_8_BANK));
1484 break;
1485 case 13:
1486 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1487 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1488 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1489 NUM_BANKS(ADDR_SURF_4_BANK));
1490 break;
1491 case 14:
1492 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1493 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1494 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1495 NUM_BANKS(ADDR_SURF_4_BANK));
1496 break;
1497 case 7:
1498 /* unused idx */
1499 continue;
1500 default:
1501 gb_tile_moden = 0;
1502 break;
1503 };
1504 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1505 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1506 }
1507 break;
1508 case CHIP_CARRIZO:
1509 default:
1510 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1511 switch (reg_offset) {
1512 case 0:
1513 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1514 PIPE_CONFIG(ADDR_SURF_P2) |
1515 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1516 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1517 break;
1518 case 1:
1519 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1520 PIPE_CONFIG(ADDR_SURF_P2) |
1521 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1522 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1523 break;
1524 case 2:
1525 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1526 PIPE_CONFIG(ADDR_SURF_P2) |
1527 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1528 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1529 break;
1530 case 3:
1531 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1532 PIPE_CONFIG(ADDR_SURF_P2) |
1533 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1534 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1535 break;
1536 case 4:
1537 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1538 PIPE_CONFIG(ADDR_SURF_P2) |
1539 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1540 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1541 break;
1542 case 5:
1543 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1544 PIPE_CONFIG(ADDR_SURF_P2) |
1545 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1546 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1547 break;
1548 case 6:
1549 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1550 PIPE_CONFIG(ADDR_SURF_P2) |
1551 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1552 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1553 break;
1554 case 8:
1555 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1556 PIPE_CONFIG(ADDR_SURF_P2));
1557 break;
1558 case 9:
1559 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1560 PIPE_CONFIG(ADDR_SURF_P2) |
1561 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1562 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1563 break;
1564 case 10:
1565 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1566 PIPE_CONFIG(ADDR_SURF_P2) |
1567 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1568 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1569 break;
1570 case 11:
1571 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1572 PIPE_CONFIG(ADDR_SURF_P2) |
1573 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1574 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1575 break;
1576 case 13:
1577 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1578 PIPE_CONFIG(ADDR_SURF_P2) |
1579 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1580 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1581 break;
1582 case 14:
1583 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1584 PIPE_CONFIG(ADDR_SURF_P2) |
1585 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1586 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1587 break;
1588 case 15:
1589 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1590 PIPE_CONFIG(ADDR_SURF_P2) |
1591 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1592 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1593 break;
1594 case 16:
1595 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1596 PIPE_CONFIG(ADDR_SURF_P2) |
1597 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1598 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1599 break;
1600 case 18:
1601 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1602 PIPE_CONFIG(ADDR_SURF_P2) |
1603 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1604 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1605 break;
1606 case 19:
1607 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1608 PIPE_CONFIG(ADDR_SURF_P2) |
1609 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1610 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1611 break;
1612 case 20:
1613 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1614 PIPE_CONFIG(ADDR_SURF_P2) |
1615 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1616 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1617 break;
1618 case 21:
1619 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1620 PIPE_CONFIG(ADDR_SURF_P2) |
1621 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1622 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1623 break;
1624 case 22:
1625 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1626 PIPE_CONFIG(ADDR_SURF_P2) |
1627 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1628 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1629 break;
1630 case 24:
1631 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1632 PIPE_CONFIG(ADDR_SURF_P2) |
1633 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1634 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1635 break;
1636 case 25:
1637 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1638 PIPE_CONFIG(ADDR_SURF_P2) |
1639 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1640 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1641 break;
1642 case 26:
1643 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1644 PIPE_CONFIG(ADDR_SURF_P2) |
1645 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1646 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1647 break;
1648 case 27:
1649 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1650 PIPE_CONFIG(ADDR_SURF_P2) |
1651 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1652 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1653 break;
1654 case 28:
1655 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1656 PIPE_CONFIG(ADDR_SURF_P2) |
1657 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1658 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1659 break;
1660 case 29:
1661 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1662 PIPE_CONFIG(ADDR_SURF_P2) |
1663 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1664 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1665 break;
1666 case 7:
1667 case 12:
1668 case 17:
1669 case 23:
1670 /* unused idx */
1671 continue;
1672 default:
1673 gb_tile_moden = 0;
1674 break;
1675 };
1676 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1677 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1678 }
1679 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1680 switch (reg_offset) {
1681 case 0:
1682 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1683 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1684 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1685 NUM_BANKS(ADDR_SURF_8_BANK));
1686 break;
1687 case 1:
1688 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1689 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1690 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1691 NUM_BANKS(ADDR_SURF_8_BANK));
1692 break;
1693 case 2:
1694 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1695 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1696 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1697 NUM_BANKS(ADDR_SURF_8_BANK));
1698 break;
1699 case 3:
1700 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1701 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1702 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1703 NUM_BANKS(ADDR_SURF_8_BANK));
1704 break;
1705 case 4:
1706 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1707 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1708 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1709 NUM_BANKS(ADDR_SURF_8_BANK));
1710 break;
1711 case 5:
1712 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1713 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1714 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1715 NUM_BANKS(ADDR_SURF_8_BANK));
1716 break;
1717 case 6:
1718 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1719 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1720 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1721 NUM_BANKS(ADDR_SURF_8_BANK));
1722 break;
1723 case 8:
1724 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1725 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1726 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1727 NUM_BANKS(ADDR_SURF_16_BANK));
1728 break;
1729 case 9:
1730 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1731 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1732 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1733 NUM_BANKS(ADDR_SURF_16_BANK));
1734 break;
1735 case 10:
1736 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1737 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1738 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1739 NUM_BANKS(ADDR_SURF_16_BANK));
1740 break;
1741 case 11:
1742 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1743 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1744 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1745 NUM_BANKS(ADDR_SURF_16_BANK));
1746 break;
1747 case 12:
1748 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1749 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1750 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1751 NUM_BANKS(ADDR_SURF_16_BANK));
1752 break;
1753 case 13:
1754 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1755 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1756 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1757 NUM_BANKS(ADDR_SURF_16_BANK));
1758 break;
1759 case 14:
1760 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1761 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1762 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1763 NUM_BANKS(ADDR_SURF_8_BANK));
1764 break;
1765 case 7:
1766 /* unused idx */
1767 continue;
1768 default:
1769 gb_tile_moden = 0;
1770 break;
1771 };
1772 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1773 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1774 }
1775 }
1776 }
1777
1778 static u32 gfx_v8_0_create_bitmask(u32 bit_width)
1779 {
1780 u32 i, mask = 0;
1781
1782 for (i = 0; i < bit_width; i++) {
1783 mask <<= 1;
1784 mask |= 1;
1785 }
1786 return mask;
1787 }
1788
1789 void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1790 {
1791 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1792
1793 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1794 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1795 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1796 } else if (se_num == 0xffffffff) {
1797 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1798 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1799 } else if (sh_num == 0xffffffff) {
1800 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1801 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1802 } else {
1803 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1804 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1805 }
1806 WREG32(mmGRBM_GFX_INDEX, data);
1807 }
1808
1809 static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
1810 u32 max_rb_num_per_se,
1811 u32 sh_per_se)
1812 {
1813 u32 data, mask;
1814
1815 data = RREG32(mmCC_RB_BACKEND_DISABLE);
1816 if (data & 1)
1817 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1818 else
1819 data = 0;
1820
1821 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1822
1823 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1824
1825 mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se);
1826
1827 return data & mask;
1828 }
1829
1830 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
1831 u32 se_num, u32 sh_per_se,
1832 u32 max_rb_num_per_se)
1833 {
1834 int i, j;
1835 u32 data, mask;
1836 u32 disabled_rbs = 0;
1837 u32 enabled_rbs = 0;
1838
1839 mutex_lock(&adev->grbm_idx_mutex);
1840 for (i = 0; i < se_num; i++) {
1841 for (j = 0; j < sh_per_se; j++) {
1842 gfx_v8_0_select_se_sh(adev, i, j);
1843 data = gfx_v8_0_get_rb_disabled(adev,
1844 max_rb_num_per_se, sh_per_se);
1845 disabled_rbs |= data << ((i * sh_per_se + j) *
1846 RB_BITMAP_WIDTH_PER_SH);
1847 }
1848 }
1849 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1850 mutex_unlock(&adev->grbm_idx_mutex);
1851
1852 mask = 1;
1853 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1854 if (!(disabled_rbs & mask))
1855 enabled_rbs |= mask;
1856 mask <<= 1;
1857 }
1858
1859 adev->gfx.config.backend_enable_mask = enabled_rbs;
1860
1861 mutex_lock(&adev->grbm_idx_mutex);
1862 for (i = 0; i < se_num; i++) {
1863 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
1864 data = 0;
1865 for (j = 0; j < sh_per_se; j++) {
1866 switch (enabled_rbs & 3) {
1867 case 0:
1868 if (j == 0)
1869 data |= (RASTER_CONFIG_RB_MAP_3 <<
1870 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1871 else
1872 data |= (RASTER_CONFIG_RB_MAP_0 <<
1873 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1874 break;
1875 case 1:
1876 data |= (RASTER_CONFIG_RB_MAP_0 <<
1877 (i * sh_per_se + j) * 2);
1878 break;
1879 case 2:
1880 data |= (RASTER_CONFIG_RB_MAP_3 <<
1881 (i * sh_per_se + j) * 2);
1882 break;
1883 case 3:
1884 default:
1885 data |= (RASTER_CONFIG_RB_MAP_2 <<
1886 (i * sh_per_se + j) * 2);
1887 break;
1888 }
1889 enabled_rbs >>= 2;
1890 }
1891 WREG32(mmPA_SC_RASTER_CONFIG, data);
1892 }
1893 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1894 mutex_unlock(&adev->grbm_idx_mutex);
1895 }
1896
1897 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
1898 {
1899 u32 gb_addr_config;
1900 u32 mc_shared_chmap, mc_arb_ramcfg;
1901 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1902 u32 tmp;
1903 int i;
1904
1905 switch (adev->asic_type) {
1906 case CHIP_TOPAZ:
1907 adev->gfx.config.max_shader_engines = 1;
1908 adev->gfx.config.max_tile_pipes = 2;
1909 adev->gfx.config.max_cu_per_sh = 6;
1910 adev->gfx.config.max_sh_per_se = 1;
1911 adev->gfx.config.max_backends_per_se = 2;
1912 adev->gfx.config.max_texture_channel_caches = 2;
1913 adev->gfx.config.max_gprs = 256;
1914 adev->gfx.config.max_gs_threads = 32;
1915 adev->gfx.config.max_hw_contexts = 8;
1916
1917 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1918 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1919 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1920 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1921 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1922 break;
1923 case CHIP_TONGA:
1924 adev->gfx.config.max_shader_engines = 4;
1925 adev->gfx.config.max_tile_pipes = 8;
1926 adev->gfx.config.max_cu_per_sh = 8;
1927 adev->gfx.config.max_sh_per_se = 1;
1928 adev->gfx.config.max_backends_per_se = 2;
1929 adev->gfx.config.max_texture_channel_caches = 8;
1930 adev->gfx.config.max_gprs = 256;
1931 adev->gfx.config.max_gs_threads = 32;
1932 adev->gfx.config.max_hw_contexts = 8;
1933
1934 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1935 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1936 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1937 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1938 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1939 break;
1940 case CHIP_CARRIZO:
1941 adev->gfx.config.max_shader_engines = 1;
1942 adev->gfx.config.max_tile_pipes = 2;
1943 adev->gfx.config.max_sh_per_se = 1;
1944
1945 switch (adev->pdev->revision) {
1946 case 0xc4:
1947 case 0x84:
1948 case 0xc8:
1949 case 0xcc:
1950 /* B10 */
1951 adev->gfx.config.max_cu_per_sh = 8;
1952 adev->gfx.config.max_backends_per_se = 2;
1953 break;
1954 case 0xc5:
1955 case 0x81:
1956 case 0x85:
1957 case 0xc9:
1958 case 0xcd:
1959 /* B8 */
1960 adev->gfx.config.max_cu_per_sh = 6;
1961 adev->gfx.config.max_backends_per_se = 2;
1962 break;
1963 case 0xc6:
1964 case 0xca:
1965 case 0xce:
1966 /* B6 */
1967 adev->gfx.config.max_cu_per_sh = 6;
1968 adev->gfx.config.max_backends_per_se = 2;
1969 break;
1970 case 0xc7:
1971 case 0x87:
1972 case 0xcb:
1973 default:
1974 /* B4 */
1975 adev->gfx.config.max_cu_per_sh = 4;
1976 adev->gfx.config.max_backends_per_se = 1;
1977 break;
1978 }
1979
1980 adev->gfx.config.max_texture_channel_caches = 2;
1981 adev->gfx.config.max_gprs = 256;
1982 adev->gfx.config.max_gs_threads = 32;
1983 adev->gfx.config.max_hw_contexts = 8;
1984
1985 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1986 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1987 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1988 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1989 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1990 break;
1991 default:
1992 adev->gfx.config.max_shader_engines = 2;
1993 adev->gfx.config.max_tile_pipes = 4;
1994 adev->gfx.config.max_cu_per_sh = 2;
1995 adev->gfx.config.max_sh_per_se = 1;
1996 adev->gfx.config.max_backends_per_se = 2;
1997 adev->gfx.config.max_texture_channel_caches = 4;
1998 adev->gfx.config.max_gprs = 256;
1999 adev->gfx.config.max_gs_threads = 32;
2000 adev->gfx.config.max_hw_contexts = 8;
2001
2002 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2003 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2004 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2005 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2006 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2007 break;
2008 }
2009
2010 tmp = RREG32(mmGRBM_CNTL);
2011 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
2012 WREG32(mmGRBM_CNTL, tmp);
2013
2014 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
2015 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
2016 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
2017
2018 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
2019 adev->gfx.config.mem_max_burst_length_bytes = 256;
2020 if (adev->flags & AMDGPU_IS_APU) {
2021 /* Get memory bank mapping mode. */
2022 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
2023 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2024 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2025
2026 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
2027 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2028 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2029
2030 /* Validate settings in case only one DIMM installed. */
2031 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
2032 dimm00_addr_map = 0;
2033 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
2034 dimm01_addr_map = 0;
2035 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
2036 dimm10_addr_map = 0;
2037 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
2038 dimm11_addr_map = 0;
2039
2040 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
2041 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
2042 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
2043 adev->gfx.config.mem_row_size_in_kb = 2;
2044 else
2045 adev->gfx.config.mem_row_size_in_kb = 1;
2046 } else {
2047 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
2048 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
2049 if (adev->gfx.config.mem_row_size_in_kb > 4)
2050 adev->gfx.config.mem_row_size_in_kb = 4;
2051 }
2052
2053 adev->gfx.config.shader_engine_tile_size = 32;
2054 adev->gfx.config.num_gpus = 1;
2055 adev->gfx.config.multi_gpu_tile_size = 64;
2056
2057 /* fix up row size */
2058 switch (adev->gfx.config.mem_row_size_in_kb) {
2059 case 1:
2060 default:
2061 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
2062 break;
2063 case 2:
2064 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
2065 break;
2066 case 4:
2067 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
2068 break;
2069 }
2070 adev->gfx.config.gb_addr_config = gb_addr_config;
2071
2072 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
2073 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
2074 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
2075 WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
2076 gb_addr_config & 0x70);
2077 WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
2078 gb_addr_config & 0x70);
2079 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
2080 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
2081 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2082
2083 gfx_v8_0_tiling_mode_table_init(adev);
2084
2085 gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
2086 adev->gfx.config.max_sh_per_se,
2087 adev->gfx.config.max_backends_per_se);
2088
2089 /* XXX SH_MEM regs */
2090 /* where to put LDS, scratch, GPUVM in FSA64 space */
2091 mutex_lock(&adev->srbm_mutex);
2092 for (i = 0; i < 16; i++) {
2093 vi_srbm_select(adev, 0, 0, 0, i);
2094 /* CP and shaders */
2095 if (i == 0) {
2096 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
2097 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
2098 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2099 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2100 WREG32(mmSH_MEM_CONFIG, tmp);
2101 } else {
2102 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
2103 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
2104 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2105 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2106 WREG32(mmSH_MEM_CONFIG, tmp);
2107 }
2108
2109 WREG32(mmSH_MEM_APE1_BASE, 1);
2110 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2111 WREG32(mmSH_MEM_BASES, 0);
2112 }
2113 vi_srbm_select(adev, 0, 0, 0, 0);
2114 mutex_unlock(&adev->srbm_mutex);
2115
2116 mutex_lock(&adev->grbm_idx_mutex);
2117 /*
2118 * making sure that the following register writes will be broadcasted
2119 * to all the shaders
2120 */
2121 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2122
2123 WREG32(mmPA_SC_FIFO_SIZE,
2124 (adev->gfx.config.sc_prim_fifo_size_frontend <<
2125 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2126 (adev->gfx.config.sc_prim_fifo_size_backend <<
2127 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2128 (adev->gfx.config.sc_hiz_tile_fifo_size <<
2129 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2130 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
2131 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
2132 mutex_unlock(&adev->grbm_idx_mutex);
2133
2134 }
2135
2136 static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2137 {
2138 u32 i, j, k;
2139 u32 mask;
2140
2141 mutex_lock(&adev->grbm_idx_mutex);
2142 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2143 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2144 gfx_v8_0_select_se_sh(adev, i, j);
2145 for (k = 0; k < adev->usec_timeout; k++) {
2146 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2147 break;
2148 udelay(1);
2149 }
2150 }
2151 }
2152 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2153 mutex_unlock(&adev->grbm_idx_mutex);
2154
2155 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2156 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2157 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2158 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2159 for (k = 0; k < adev->usec_timeout; k++) {
2160 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2161 break;
2162 udelay(1);
2163 }
2164 }
2165
2166 static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2167 bool enable)
2168 {
2169 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2170
2171 if (enable) {
2172 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1);
2173 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1);
2174 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1);
2175 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1);
2176 } else {
2177 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0);
2178 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0);
2179 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0);
2180 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0);
2181 }
2182 WREG32(mmCP_INT_CNTL_RING0, tmp);
2183 }
2184
2185 void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
2186 {
2187 u32 tmp = RREG32(mmRLC_CNTL);
2188
2189 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2190 WREG32(mmRLC_CNTL, tmp);
2191
2192 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
2193
2194 gfx_v8_0_wait_for_rlc_serdes(adev);
2195 }
2196
2197 static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
2198 {
2199 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
2200
2201 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2202 WREG32(mmGRBM_SOFT_RESET, tmp);
2203 udelay(50);
2204 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2205 WREG32(mmGRBM_SOFT_RESET, tmp);
2206 udelay(50);
2207 }
2208
2209 static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
2210 {
2211 u32 tmp = RREG32(mmRLC_CNTL);
2212
2213 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
2214 WREG32(mmRLC_CNTL, tmp);
2215
2216 /* carrizo do enable cp interrupt after cp inited */
2217 if (adev->asic_type != CHIP_CARRIZO)
2218 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
2219
2220 udelay(50);
2221 }
2222
2223 static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
2224 {
2225 const struct rlc_firmware_header_v2_0 *hdr;
2226 const __le32 *fw_data;
2227 unsigned i, fw_size;
2228
2229 if (!adev->gfx.rlc_fw)
2230 return -EINVAL;
2231
2232 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2233 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2234 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
2235
2236 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2237 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2238 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2239
2240 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
2241 for (i = 0; i < fw_size; i++)
2242 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2243 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2244
2245 return 0;
2246 }
2247
2248 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
2249 {
2250 int r;
2251
2252 gfx_v8_0_rlc_stop(adev);
2253
2254 /* disable CG */
2255 WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
2256
2257 /* disable PG */
2258 WREG32(mmRLC_PG_CNTL, 0);
2259
2260 gfx_v8_0_rlc_reset(adev);
2261
2262 if (!adev->firmware.smu_load) {
2263 /* legacy rlc firmware loading */
2264 r = gfx_v8_0_rlc_load_microcode(adev);
2265 if (r)
2266 return r;
2267 } else {
2268 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
2269 AMDGPU_UCODE_ID_RLC_G);
2270 if (r)
2271 return -EINVAL;
2272 }
2273
2274 gfx_v8_0_rlc_start(adev);
2275
2276 return 0;
2277 }
2278
2279 static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2280 {
2281 int i;
2282 u32 tmp = RREG32(mmCP_ME_CNTL);
2283
2284 if (enable) {
2285 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
2286 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
2287 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
2288 } else {
2289 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
2290 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
2291 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
2292 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2293 adev->gfx.gfx_ring[i].ready = false;
2294 }
2295 WREG32(mmCP_ME_CNTL, tmp);
2296 udelay(50);
2297 }
2298
2299 static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2300 {
2301 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2302 const struct gfx_firmware_header_v1_0 *ce_hdr;
2303 const struct gfx_firmware_header_v1_0 *me_hdr;
2304 const __le32 *fw_data;
2305 unsigned i, fw_size;
2306
2307 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2308 return -EINVAL;
2309
2310 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2311 adev->gfx.pfp_fw->data;
2312 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2313 adev->gfx.ce_fw->data;
2314 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2315 adev->gfx.me_fw->data;
2316
2317 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2318 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2319 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2320 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2321 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2322 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2323 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2324 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2325 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2326
2327 gfx_v8_0_cp_gfx_enable(adev, false);
2328
2329 /* PFP */
2330 fw_data = (const __le32 *)
2331 (adev->gfx.pfp_fw->data +
2332 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2333 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2334 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2335 for (i = 0; i < fw_size; i++)
2336 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2337 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2338
2339 /* CE */
2340 fw_data = (const __le32 *)
2341 (adev->gfx.ce_fw->data +
2342 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2343 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2344 WREG32(mmCP_CE_UCODE_ADDR, 0);
2345 for (i = 0; i < fw_size; i++)
2346 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2347 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2348
2349 /* ME */
2350 fw_data = (const __le32 *)
2351 (adev->gfx.me_fw->data +
2352 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2353 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2354 WREG32(mmCP_ME_RAM_WADDR, 0);
2355 for (i = 0; i < fw_size; i++)
2356 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2357 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2358
2359 return 0;
2360 }
2361
2362 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
2363 {
2364 u32 count = 0;
2365 const struct cs_section_def *sect = NULL;
2366 const struct cs_extent_def *ext = NULL;
2367
2368 /* begin clear state */
2369 count += 2;
2370 /* context control state */
2371 count += 3;
2372
2373 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2374 for (ext = sect->section; ext->extent != NULL; ++ext) {
2375 if (sect->id == SECT_CONTEXT)
2376 count += 2 + ext->reg_count;
2377 else
2378 return 0;
2379 }
2380 }
2381 /* pa_sc_raster_config/pa_sc_raster_config1 */
2382 count += 4;
2383 /* end clear state */
2384 count += 2;
2385 /* clear state */
2386 count += 2;
2387
2388 return count;
2389 }
2390
2391 static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
2392 {
2393 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2394 const struct cs_section_def *sect = NULL;
2395 const struct cs_extent_def *ext = NULL;
2396 int r, i;
2397
2398 /* init the CP */
2399 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2400 WREG32(mmCP_ENDIAN_SWAP, 0);
2401 WREG32(mmCP_DEVICE_ID, 1);
2402
2403 gfx_v8_0_cp_gfx_enable(adev, true);
2404
2405 r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4);
2406 if (r) {
2407 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2408 return r;
2409 }
2410
2411 /* clear state buffer */
2412 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2413 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2414
2415 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2416 amdgpu_ring_write(ring, 0x80000000);
2417 amdgpu_ring_write(ring, 0x80000000);
2418
2419 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2420 for (ext = sect->section; ext->extent != NULL; ++ext) {
2421 if (sect->id == SECT_CONTEXT) {
2422 amdgpu_ring_write(ring,
2423 PACKET3(PACKET3_SET_CONTEXT_REG,
2424 ext->reg_count));
2425 amdgpu_ring_write(ring,
2426 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2427 for (i = 0; i < ext->reg_count; i++)
2428 amdgpu_ring_write(ring, ext->extent[i]);
2429 }
2430 }
2431 }
2432
2433 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2434 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2435 switch (adev->asic_type) {
2436 case CHIP_TONGA:
2437 amdgpu_ring_write(ring, 0x16000012);
2438 amdgpu_ring_write(ring, 0x0000002A);
2439 break;
2440 case CHIP_TOPAZ:
2441 case CHIP_CARRIZO:
2442 amdgpu_ring_write(ring, 0x00000002);
2443 amdgpu_ring_write(ring, 0x00000000);
2444 break;
2445 default:
2446 BUG();
2447 }
2448
2449 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2450 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2451
2452 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2453 amdgpu_ring_write(ring, 0);
2454
2455 /* init the CE partitions */
2456 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2457 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2458 amdgpu_ring_write(ring, 0x8000);
2459 amdgpu_ring_write(ring, 0x8000);
2460
2461 amdgpu_ring_unlock_commit(ring);
2462
2463 return 0;
2464 }
2465
2466 static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
2467 {
2468 struct amdgpu_ring *ring;
2469 u32 tmp;
2470 u32 rb_bufsz;
2471 u64 rb_addr, rptr_addr;
2472 int r;
2473
2474 /* Set the write pointer delay */
2475 WREG32(mmCP_RB_WPTR_DELAY, 0);
2476
2477 /* set the RB to use vmid 0 */
2478 WREG32(mmCP_RB_VMID, 0);
2479
2480 /* Set ring buffer size */
2481 ring = &adev->gfx.gfx_ring[0];
2482 rb_bufsz = order_base_2(ring->ring_size / 8);
2483 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2484 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2485 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
2486 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
2487 #ifdef __BIG_ENDIAN
2488 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2489 #endif
2490 WREG32(mmCP_RB0_CNTL, tmp);
2491
2492 /* Initialize the ring buffer's read and write pointers */
2493 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2494 ring->wptr = 0;
2495 WREG32(mmCP_RB0_WPTR, ring->wptr);
2496
2497 /* set the wb address wether it's enabled or not */
2498 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2499 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2500 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2501
2502 mdelay(1);
2503 WREG32(mmCP_RB0_CNTL, tmp);
2504
2505 rb_addr = ring->gpu_addr >> 8;
2506 WREG32(mmCP_RB0_BASE, rb_addr);
2507 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2508
2509 /* no gfx doorbells on iceland */
2510 if (adev->asic_type != CHIP_TOPAZ) {
2511 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
2512 if (ring->use_doorbell) {
2513 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2514 DOORBELL_OFFSET, ring->doorbell_index);
2515 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2516 DOORBELL_EN, 1);
2517 } else {
2518 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2519 DOORBELL_EN, 0);
2520 }
2521 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
2522
2523 if (adev->asic_type == CHIP_TONGA) {
2524 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2525 DOORBELL_RANGE_LOWER,
2526 AMDGPU_DOORBELL_GFX_RING0);
2527 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2528
2529 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
2530 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2531 }
2532
2533 }
2534
2535 /* start the ring */
2536 gfx_v8_0_cp_gfx_start(adev);
2537 ring->ready = true;
2538 r = amdgpu_ring_test_ring(ring);
2539 if (r) {
2540 ring->ready = false;
2541 return r;
2542 }
2543
2544 return 0;
2545 }
2546
2547 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2548 {
2549 int i;
2550
2551 if (enable) {
2552 WREG32(mmCP_MEC_CNTL, 0);
2553 } else {
2554 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2555 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2556 adev->gfx.compute_ring[i].ready = false;
2557 }
2558 udelay(50);
2559 }
2560
2561 static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
2562 {
2563 gfx_v8_0_cp_compute_enable(adev, true);
2564
2565 return 0;
2566 }
2567
2568 static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2569 {
2570 const struct gfx_firmware_header_v1_0 *mec_hdr;
2571 const __le32 *fw_data;
2572 unsigned i, fw_size;
2573
2574 if (!adev->gfx.mec_fw)
2575 return -EINVAL;
2576
2577 gfx_v8_0_cp_compute_enable(adev, false);
2578
2579 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2580 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2581 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2582
2583 fw_data = (const __le32 *)
2584 (adev->gfx.mec_fw->data +
2585 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2586 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2587
2588 /* MEC1 */
2589 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2590 for (i = 0; i < fw_size; i++)
2591 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
2592 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2593
2594 /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2595 if (adev->gfx.mec2_fw) {
2596 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2597
2598 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2599 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2600 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2601
2602 fw_data = (const __le32 *)
2603 (adev->gfx.mec2_fw->data +
2604 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2605 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2606
2607 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2608 for (i = 0; i < fw_size; i++)
2609 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
2610 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
2611 }
2612
2613 return 0;
2614 }
2615
2616 struct vi_mqd {
2617 uint32_t header; /* ordinal0 */
2618 uint32_t compute_dispatch_initiator; /* ordinal1 */
2619 uint32_t compute_dim_x; /* ordinal2 */
2620 uint32_t compute_dim_y; /* ordinal3 */
2621 uint32_t compute_dim_z; /* ordinal4 */
2622 uint32_t compute_start_x; /* ordinal5 */
2623 uint32_t compute_start_y; /* ordinal6 */
2624 uint32_t compute_start_z; /* ordinal7 */
2625 uint32_t compute_num_thread_x; /* ordinal8 */
2626 uint32_t compute_num_thread_y; /* ordinal9 */
2627 uint32_t compute_num_thread_z; /* ordinal10 */
2628 uint32_t compute_pipelinestat_enable; /* ordinal11 */
2629 uint32_t compute_perfcount_enable; /* ordinal12 */
2630 uint32_t compute_pgm_lo; /* ordinal13 */
2631 uint32_t compute_pgm_hi; /* ordinal14 */
2632 uint32_t compute_tba_lo; /* ordinal15 */
2633 uint32_t compute_tba_hi; /* ordinal16 */
2634 uint32_t compute_tma_lo; /* ordinal17 */
2635 uint32_t compute_tma_hi; /* ordinal18 */
2636 uint32_t compute_pgm_rsrc1; /* ordinal19 */
2637 uint32_t compute_pgm_rsrc2; /* ordinal20 */
2638 uint32_t compute_vmid; /* ordinal21 */
2639 uint32_t compute_resource_limits; /* ordinal22 */
2640 uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */
2641 uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */
2642 uint32_t compute_tmpring_size; /* ordinal25 */
2643 uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */
2644 uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */
2645 uint32_t compute_restart_x; /* ordinal28 */
2646 uint32_t compute_restart_y; /* ordinal29 */
2647 uint32_t compute_restart_z; /* ordinal30 */
2648 uint32_t compute_thread_trace_enable; /* ordinal31 */
2649 uint32_t compute_misc_reserved; /* ordinal32 */
2650 uint32_t compute_dispatch_id; /* ordinal33 */
2651 uint32_t compute_threadgroup_id; /* ordinal34 */
2652 uint32_t compute_relaunch; /* ordinal35 */
2653 uint32_t compute_wave_restore_addr_lo; /* ordinal36 */
2654 uint32_t compute_wave_restore_addr_hi; /* ordinal37 */
2655 uint32_t compute_wave_restore_control; /* ordinal38 */
2656 uint32_t reserved9; /* ordinal39 */
2657 uint32_t reserved10; /* ordinal40 */
2658 uint32_t reserved11; /* ordinal41 */
2659 uint32_t reserved12; /* ordinal42 */
2660 uint32_t reserved13; /* ordinal43 */
2661 uint32_t reserved14; /* ordinal44 */
2662 uint32_t reserved15; /* ordinal45 */
2663 uint32_t reserved16; /* ordinal46 */
2664 uint32_t reserved17; /* ordinal47 */
2665 uint32_t reserved18; /* ordinal48 */
2666 uint32_t reserved19; /* ordinal49 */
2667 uint32_t reserved20; /* ordinal50 */
2668 uint32_t reserved21; /* ordinal51 */
2669 uint32_t reserved22; /* ordinal52 */
2670 uint32_t reserved23; /* ordinal53 */
2671 uint32_t reserved24; /* ordinal54 */
2672 uint32_t reserved25; /* ordinal55 */
2673 uint32_t reserved26; /* ordinal56 */
2674 uint32_t reserved27; /* ordinal57 */
2675 uint32_t reserved28; /* ordinal58 */
2676 uint32_t reserved29; /* ordinal59 */
2677 uint32_t reserved30; /* ordinal60 */
2678 uint32_t reserved31; /* ordinal61 */
2679 uint32_t reserved32; /* ordinal62 */
2680 uint32_t reserved33; /* ordinal63 */
2681 uint32_t reserved34; /* ordinal64 */
2682 uint32_t compute_user_data_0; /* ordinal65 */
2683 uint32_t compute_user_data_1; /* ordinal66 */
2684 uint32_t compute_user_data_2; /* ordinal67 */
2685 uint32_t compute_user_data_3; /* ordinal68 */
2686 uint32_t compute_user_data_4; /* ordinal69 */
2687 uint32_t compute_user_data_5; /* ordinal70 */
2688 uint32_t compute_user_data_6; /* ordinal71 */
2689 uint32_t compute_user_data_7; /* ordinal72 */
2690 uint32_t compute_user_data_8; /* ordinal73 */
2691 uint32_t compute_user_data_9; /* ordinal74 */
2692 uint32_t compute_user_data_10; /* ordinal75 */
2693 uint32_t compute_user_data_11; /* ordinal76 */
2694 uint32_t compute_user_data_12; /* ordinal77 */
2695 uint32_t compute_user_data_13; /* ordinal78 */
2696 uint32_t compute_user_data_14; /* ordinal79 */
2697 uint32_t compute_user_data_15; /* ordinal80 */
2698 uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */
2699 uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */
2700 uint32_t reserved35; /* ordinal83 */
2701 uint32_t reserved36; /* ordinal84 */
2702 uint32_t reserved37; /* ordinal85 */
2703 uint32_t cp_mqd_query_time_lo; /* ordinal86 */
2704 uint32_t cp_mqd_query_time_hi; /* ordinal87 */
2705 uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */
2706 uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */
2707 uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */
2708 uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */
2709 uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */
2710 uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */
2711 uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */
2712 uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */
2713 uint32_t reserved38; /* ordinal96 */
2714 uint32_t reserved39; /* ordinal97 */
2715 uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */
2716 uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */
2717 uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */
2718 uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */
2719 uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */
2720 uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */
2721 uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */
2722 uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */
2723 uint32_t reserved40; /* ordinal106 */
2724 uint32_t reserved41; /* ordinal107 */
2725 uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */
2726 uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */
2727 uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */
2728 uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */
2729 uint32_t reserved42; /* ordinal112 */
2730 uint32_t reserved43; /* ordinal113 */
2731 uint32_t cp_pq_exe_status_lo; /* ordinal114 */
2732 uint32_t cp_pq_exe_status_hi; /* ordinal115 */
2733 uint32_t cp_packet_id_lo; /* ordinal116 */
2734 uint32_t cp_packet_id_hi; /* ordinal117 */
2735 uint32_t cp_packet_exe_status_lo; /* ordinal118 */
2736 uint32_t cp_packet_exe_status_hi; /* ordinal119 */
2737 uint32_t gds_save_base_addr_lo; /* ordinal120 */
2738 uint32_t gds_save_base_addr_hi; /* ordinal121 */
2739 uint32_t gds_save_mask_lo; /* ordinal122 */
2740 uint32_t gds_save_mask_hi; /* ordinal123 */
2741 uint32_t ctx_save_base_addr_lo; /* ordinal124 */
2742 uint32_t ctx_save_base_addr_hi; /* ordinal125 */
2743 uint32_t reserved44; /* ordinal126 */
2744 uint32_t reserved45; /* ordinal127 */
2745 uint32_t cp_mqd_base_addr_lo; /* ordinal128 */
2746 uint32_t cp_mqd_base_addr_hi; /* ordinal129 */
2747 uint32_t cp_hqd_active; /* ordinal130 */
2748 uint32_t cp_hqd_vmid; /* ordinal131 */
2749 uint32_t cp_hqd_persistent_state; /* ordinal132 */
2750 uint32_t cp_hqd_pipe_priority; /* ordinal133 */
2751 uint32_t cp_hqd_queue_priority; /* ordinal134 */
2752 uint32_t cp_hqd_quantum; /* ordinal135 */
2753 uint32_t cp_hqd_pq_base_lo; /* ordinal136 */
2754 uint32_t cp_hqd_pq_base_hi; /* ordinal137 */
2755 uint32_t cp_hqd_pq_rptr; /* ordinal138 */
2756 uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */
2757 uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */
2758 uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */
2759 uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */
2760 uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */
2761 uint32_t cp_hqd_pq_wptr; /* ordinal144 */
2762 uint32_t cp_hqd_pq_control; /* ordinal145 */
2763 uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */
2764 uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */
2765 uint32_t cp_hqd_ib_rptr; /* ordinal148 */
2766 uint32_t cp_hqd_ib_control; /* ordinal149 */
2767 uint32_t cp_hqd_iq_timer; /* ordinal150 */
2768 uint32_t cp_hqd_iq_rptr; /* ordinal151 */
2769 uint32_t cp_hqd_dequeue_request; /* ordinal152 */
2770 uint32_t cp_hqd_dma_offload; /* ordinal153 */
2771 uint32_t cp_hqd_sema_cmd; /* ordinal154 */
2772 uint32_t cp_hqd_msg_type; /* ordinal155 */
2773 uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */
2774 uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */
2775 uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */
2776 uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */
2777 uint32_t cp_hqd_hq_status0; /* ordinal160 */
2778 uint32_t cp_hqd_hq_control0; /* ordinal161 */
2779 uint32_t cp_mqd_control; /* ordinal162 */
2780 uint32_t cp_hqd_hq_status1; /* ordinal163 */
2781 uint32_t cp_hqd_hq_control1; /* ordinal164 */
2782 uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */
2783 uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */
2784 uint32_t cp_hqd_eop_control; /* ordinal167 */
2785 uint32_t cp_hqd_eop_rptr; /* ordinal168 */
2786 uint32_t cp_hqd_eop_wptr; /* ordinal169 */
2787 uint32_t cp_hqd_eop_done_events; /* ordinal170 */
2788 uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */
2789 uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */
2790 uint32_t cp_hqd_ctx_save_control; /* ordinal173 */
2791 uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */
2792 uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */
2793 uint32_t cp_hqd_wg_state_offset; /* ordinal176 */
2794 uint32_t cp_hqd_ctx_save_size; /* ordinal177 */
2795 uint32_t cp_hqd_gds_resource_state; /* ordinal178 */
2796 uint32_t cp_hqd_error; /* ordinal179 */
2797 uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */
2798 uint32_t cp_hqd_eop_dones; /* ordinal181 */
2799 uint32_t reserved46; /* ordinal182 */
2800 uint32_t reserved47; /* ordinal183 */
2801 uint32_t reserved48; /* ordinal184 */
2802 uint32_t reserved49; /* ordinal185 */
2803 uint32_t reserved50; /* ordinal186 */
2804 uint32_t reserved51; /* ordinal187 */
2805 uint32_t reserved52; /* ordinal188 */
2806 uint32_t reserved53; /* ordinal189 */
2807 uint32_t reserved54; /* ordinal190 */
2808 uint32_t reserved55; /* ordinal191 */
2809 uint32_t iqtimer_pkt_header; /* ordinal192 */
2810 uint32_t iqtimer_pkt_dw0; /* ordinal193 */
2811 uint32_t iqtimer_pkt_dw1; /* ordinal194 */
2812 uint32_t iqtimer_pkt_dw2; /* ordinal195 */
2813 uint32_t iqtimer_pkt_dw3; /* ordinal196 */
2814 uint32_t iqtimer_pkt_dw4; /* ordinal197 */
2815 uint32_t iqtimer_pkt_dw5; /* ordinal198 */
2816 uint32_t iqtimer_pkt_dw6; /* ordinal199 */
2817 uint32_t iqtimer_pkt_dw7; /* ordinal200 */
2818 uint32_t iqtimer_pkt_dw8; /* ordinal201 */
2819 uint32_t iqtimer_pkt_dw9; /* ordinal202 */
2820 uint32_t iqtimer_pkt_dw10; /* ordinal203 */
2821 uint32_t iqtimer_pkt_dw11; /* ordinal204 */
2822 uint32_t iqtimer_pkt_dw12; /* ordinal205 */
2823 uint32_t iqtimer_pkt_dw13; /* ordinal206 */
2824 uint32_t iqtimer_pkt_dw14; /* ordinal207 */
2825 uint32_t iqtimer_pkt_dw15; /* ordinal208 */
2826 uint32_t iqtimer_pkt_dw16; /* ordinal209 */
2827 uint32_t iqtimer_pkt_dw17; /* ordinal210 */
2828 uint32_t iqtimer_pkt_dw18; /* ordinal211 */
2829 uint32_t iqtimer_pkt_dw19; /* ordinal212 */
2830 uint32_t iqtimer_pkt_dw20; /* ordinal213 */
2831 uint32_t iqtimer_pkt_dw21; /* ordinal214 */
2832 uint32_t iqtimer_pkt_dw22; /* ordinal215 */
2833 uint32_t iqtimer_pkt_dw23; /* ordinal216 */
2834 uint32_t iqtimer_pkt_dw24; /* ordinal217 */
2835 uint32_t iqtimer_pkt_dw25; /* ordinal218 */
2836 uint32_t iqtimer_pkt_dw26; /* ordinal219 */
2837 uint32_t iqtimer_pkt_dw27; /* ordinal220 */
2838 uint32_t iqtimer_pkt_dw28; /* ordinal221 */
2839 uint32_t iqtimer_pkt_dw29; /* ordinal222 */
2840 uint32_t iqtimer_pkt_dw30; /* ordinal223 */
2841 uint32_t iqtimer_pkt_dw31; /* ordinal224 */
2842 uint32_t reserved56; /* ordinal225 */
2843 uint32_t reserved57; /* ordinal226 */
2844 uint32_t reserved58; /* ordinal227 */
2845 uint32_t set_resources_header; /* ordinal228 */
2846 uint32_t set_resources_dw1; /* ordinal229 */
2847 uint32_t set_resources_dw2; /* ordinal230 */
2848 uint32_t set_resources_dw3; /* ordinal231 */
2849 uint32_t set_resources_dw4; /* ordinal232 */
2850 uint32_t set_resources_dw5; /* ordinal233 */
2851 uint32_t set_resources_dw6; /* ordinal234 */
2852 uint32_t set_resources_dw7; /* ordinal235 */
2853 uint32_t reserved59; /* ordinal236 */
2854 uint32_t reserved60; /* ordinal237 */
2855 uint32_t reserved61; /* ordinal238 */
2856 uint32_t reserved62; /* ordinal239 */
2857 uint32_t reserved63; /* ordinal240 */
2858 uint32_t reserved64; /* ordinal241 */
2859 uint32_t reserved65; /* ordinal242 */
2860 uint32_t reserved66; /* ordinal243 */
2861 uint32_t reserved67; /* ordinal244 */
2862 uint32_t reserved68; /* ordinal245 */
2863 uint32_t reserved69; /* ordinal246 */
2864 uint32_t reserved70; /* ordinal247 */
2865 uint32_t reserved71; /* ordinal248 */
2866 uint32_t reserved72; /* ordinal249 */
2867 uint32_t reserved73; /* ordinal250 */
2868 uint32_t reserved74; /* ordinal251 */
2869 uint32_t reserved75; /* ordinal252 */
2870 uint32_t reserved76; /* ordinal253 */
2871 uint32_t reserved77; /* ordinal254 */
2872 uint32_t reserved78; /* ordinal255 */
2873
2874 uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
2875 };
2876
2877 static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
2878 {
2879 int i, r;
2880
2881 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2882 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2883
2884 if (ring->mqd_obj) {
2885 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2886 if (unlikely(r != 0))
2887 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2888
2889 amdgpu_bo_unpin(ring->mqd_obj);
2890 amdgpu_bo_unreserve(ring->mqd_obj);
2891
2892 amdgpu_bo_unref(&ring->mqd_obj);
2893 ring->mqd_obj = NULL;
2894 }
2895 }
2896 }
2897
2898 static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
2899 {
2900 int r, i, j;
2901 u32 tmp;
2902 bool use_doorbell = true;
2903 u64 hqd_gpu_addr;
2904 u64 mqd_gpu_addr;
2905 u64 eop_gpu_addr;
2906 u64 wb_gpu_addr;
2907 u32 *buf;
2908 struct vi_mqd *mqd;
2909
2910 /* init the pipes */
2911 mutex_lock(&adev->srbm_mutex);
2912 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
2913 int me = (i < 4) ? 1 : 2;
2914 int pipe = (i < 4) ? i : (i - 4);
2915
2916 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
2917 eop_gpu_addr >>= 8;
2918
2919 vi_srbm_select(adev, me, pipe, 0, 0);
2920
2921 /* write the EOP addr */
2922 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
2923 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
2924
2925 /* set the VMID assigned */
2926 WREG32(mmCP_HQD_VMID, 0);
2927
2928 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2929 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
2930 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2931 (order_base_2(MEC_HPD_SIZE / 4) - 1));
2932 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
2933 }
2934 vi_srbm_select(adev, 0, 0, 0, 0);
2935 mutex_unlock(&adev->srbm_mutex);
2936
2937 /* init the queues. Just two for now. */
2938 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2939 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2940
2941 if (ring->mqd_obj == NULL) {
2942 r = amdgpu_bo_create(adev,
2943 sizeof(struct vi_mqd),
2944 PAGE_SIZE, true,
2945 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
2946 &ring->mqd_obj);
2947 if (r) {
2948 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2949 return r;
2950 }
2951 }
2952
2953 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2954 if (unlikely(r != 0)) {
2955 gfx_v8_0_cp_compute_fini(adev);
2956 return r;
2957 }
2958 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
2959 &mqd_gpu_addr);
2960 if (r) {
2961 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
2962 gfx_v8_0_cp_compute_fini(adev);
2963 return r;
2964 }
2965 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
2966 if (r) {
2967 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
2968 gfx_v8_0_cp_compute_fini(adev);
2969 return r;
2970 }
2971
2972 /* init the mqd struct */
2973 memset(buf, 0, sizeof(struct vi_mqd));
2974
2975 mqd = (struct vi_mqd *)buf;
2976 mqd->header = 0xC0310800;
2977 mqd->compute_pipelinestat_enable = 0x00000001;
2978 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2979 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2980 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2981 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2982 mqd->compute_misc_reserved = 0x00000003;
2983
2984 mutex_lock(&adev->srbm_mutex);
2985 vi_srbm_select(adev, ring->me,
2986 ring->pipe,
2987 ring->queue, 0);
2988
2989 /* disable wptr polling */
2990 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
2991 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2992 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
2993
2994 mqd->cp_hqd_eop_base_addr_lo =
2995 RREG32(mmCP_HQD_EOP_BASE_ADDR);
2996 mqd->cp_hqd_eop_base_addr_hi =
2997 RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
2998
2999 /* enable doorbell? */
3000 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3001 if (use_doorbell) {
3002 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3003 } else {
3004 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3005 }
3006 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
3007 mqd->cp_hqd_pq_doorbell_control = tmp;
3008
3009 /* disable the queue if it's active */
3010 mqd->cp_hqd_dequeue_request = 0;
3011 mqd->cp_hqd_pq_rptr = 0;
3012 mqd->cp_hqd_pq_wptr= 0;
3013 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3014 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3015 for (j = 0; j < adev->usec_timeout; j++) {
3016 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3017 break;
3018 udelay(1);
3019 }
3020 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
3021 WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
3022 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3023 }
3024
3025 /* set the pointer to the MQD */
3026 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3027 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3028 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
3029 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3030
3031 /* set MQD vmid to 0 */
3032 tmp = RREG32(mmCP_MQD_CONTROL);
3033 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3034 WREG32(mmCP_MQD_CONTROL, tmp);
3035 mqd->cp_mqd_control = tmp;
3036
3037 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3038 hqd_gpu_addr = ring->gpu_addr >> 8;
3039 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3040 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3041 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
3042 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
3043
3044 /* set up the HQD, this is similar to CP_RB0_CNTL */
3045 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
3046 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3047 (order_base_2(ring->ring_size / 4) - 1));
3048 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3049 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3050 #ifdef __BIG_ENDIAN
3051 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3052 #endif
3053 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3054 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3055 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3056 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3057 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
3058 mqd->cp_hqd_pq_control = tmp;
3059
3060 /* set the wb address wether it's enabled or not */
3061 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3062 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3063 mqd->cp_hqd_pq_rptr_report_addr_hi =
3064 upper_32_bits(wb_gpu_addr) & 0xffff;
3065 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3066 mqd->cp_hqd_pq_rptr_report_addr_lo);
3067 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3068 mqd->cp_hqd_pq_rptr_report_addr_hi);
3069
3070 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3071 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3072 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3073 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3074 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
3075 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3076 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3077
3078 /* enable the doorbell if requested */
3079 if (use_doorbell) {
3080 if (adev->asic_type == CHIP_CARRIZO) {
3081 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
3082 AMDGPU_DOORBELL_KIQ << 2);
3083 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
3084 AMDGPU_DOORBELL_MEC_RING7 << 2);
3085 }
3086 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3087 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3088 DOORBELL_OFFSET, ring->doorbell_index);
3089 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3090 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3091 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3092 mqd->cp_hqd_pq_doorbell_control = tmp;
3093
3094 } else {
3095 mqd->cp_hqd_pq_doorbell_control = 0;
3096 }
3097 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3098 mqd->cp_hqd_pq_doorbell_control);
3099
3100 /* set the vmid for the queue */
3101 mqd->cp_hqd_vmid = 0;
3102 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3103
3104 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
3105 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3106 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
3107 mqd->cp_hqd_persistent_state = tmp;
3108
3109 /* activate the queue */
3110 mqd->cp_hqd_active = 1;
3111 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
3112
3113 vi_srbm_select(adev, 0, 0, 0, 0);
3114 mutex_unlock(&adev->srbm_mutex);
3115
3116 amdgpu_bo_kunmap(ring->mqd_obj);
3117 amdgpu_bo_unreserve(ring->mqd_obj);
3118 }
3119
3120 if (use_doorbell) {
3121 tmp = RREG32(mmCP_PQ_STATUS);
3122 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3123 WREG32(mmCP_PQ_STATUS, tmp);
3124 }
3125
3126 r = gfx_v8_0_cp_compute_start(adev);
3127 if (r)
3128 return r;
3129
3130 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3131 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3132
3133 ring->ready = true;
3134 r = amdgpu_ring_test_ring(ring);
3135 if (r)
3136 ring->ready = false;
3137 }
3138
3139 return 0;
3140 }
3141
3142 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
3143 {
3144 int r;
3145
3146 if (adev->asic_type != CHIP_CARRIZO)
3147 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3148
3149 if (!adev->firmware.smu_load) {
3150 /* legacy firmware loading */
3151 r = gfx_v8_0_cp_gfx_load_microcode(adev);
3152 if (r)
3153 return r;
3154
3155 r = gfx_v8_0_cp_compute_load_microcode(adev);
3156 if (r)
3157 return r;
3158 } else {
3159 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3160 AMDGPU_UCODE_ID_CP_CE);
3161 if (r)
3162 return -EINVAL;
3163
3164 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3165 AMDGPU_UCODE_ID_CP_PFP);
3166 if (r)
3167 return -EINVAL;
3168
3169 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3170 AMDGPU_UCODE_ID_CP_ME);
3171 if (r)
3172 return -EINVAL;
3173
3174 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3175 AMDGPU_UCODE_ID_CP_MEC1);
3176 if (r)
3177 return -EINVAL;
3178 }
3179
3180 r = gfx_v8_0_cp_gfx_resume(adev);
3181 if (r)
3182 return r;
3183
3184 r = gfx_v8_0_cp_compute_resume(adev);
3185 if (r)
3186 return r;
3187
3188 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3189
3190 return 0;
3191 }
3192
3193 static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
3194 {
3195 gfx_v8_0_cp_gfx_enable(adev, enable);
3196 gfx_v8_0_cp_compute_enable(adev, enable);
3197 }
3198
3199 static int gfx_v8_0_hw_init(void *handle)
3200 {
3201 int r;
3202 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3203
3204 gfx_v8_0_init_golden_registers(adev);
3205
3206 gfx_v8_0_gpu_init(adev);
3207
3208 r = gfx_v8_0_rlc_resume(adev);
3209 if (r)
3210 return r;
3211
3212 r = gfx_v8_0_cp_resume(adev);
3213 if (r)
3214 return r;
3215
3216 return r;
3217 }
3218
3219 static int gfx_v8_0_hw_fini(void *handle)
3220 {
3221 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3222
3223 gfx_v8_0_cp_enable(adev, false);
3224 gfx_v8_0_rlc_stop(adev);
3225 gfx_v8_0_cp_compute_fini(adev);
3226
3227 return 0;
3228 }
3229
3230 static int gfx_v8_0_suspend(void *handle)
3231 {
3232 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3233
3234 return gfx_v8_0_hw_fini(adev);
3235 }
3236
3237 static int gfx_v8_0_resume(void *handle)
3238 {
3239 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3240
3241 return gfx_v8_0_hw_init(adev);
3242 }
3243
3244 static bool gfx_v8_0_is_idle(void *handle)
3245 {
3246 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3247
3248 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
3249 return false;
3250 else
3251 return true;
3252 }
3253
3254 static int gfx_v8_0_wait_for_idle(void *handle)
3255 {
3256 unsigned i;
3257 u32 tmp;
3258 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3259
3260 for (i = 0; i < adev->usec_timeout; i++) {
3261 /* read MC_STATUS */
3262 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
3263
3264 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3265 return 0;
3266 udelay(1);
3267 }
3268 return -ETIMEDOUT;
3269 }
3270
3271 static void gfx_v8_0_print_status(void *handle)
3272 {
3273 int i;
3274 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3275
3276 dev_info(adev->dev, "GFX 8.x registers\n");
3277 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
3278 RREG32(mmGRBM_STATUS));
3279 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
3280 RREG32(mmGRBM_STATUS2));
3281 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
3282 RREG32(mmGRBM_STATUS_SE0));
3283 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
3284 RREG32(mmGRBM_STATUS_SE1));
3285 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
3286 RREG32(mmGRBM_STATUS_SE2));
3287 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
3288 RREG32(mmGRBM_STATUS_SE3));
3289 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
3290 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
3291 RREG32(mmCP_STALLED_STAT1));
3292 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
3293 RREG32(mmCP_STALLED_STAT2));
3294 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
3295 RREG32(mmCP_STALLED_STAT3));
3296 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
3297 RREG32(mmCP_CPF_BUSY_STAT));
3298 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
3299 RREG32(mmCP_CPF_STALLED_STAT1));
3300 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
3301 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
3302 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
3303 RREG32(mmCP_CPC_STALLED_STAT1));
3304 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
3305
3306 for (i = 0; i < 32; i++) {
3307 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
3308 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
3309 }
3310 for (i = 0; i < 16; i++) {
3311 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
3312 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
3313 }
3314 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3315 dev_info(adev->dev, " se: %d\n", i);
3316 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
3317 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
3318 RREG32(mmPA_SC_RASTER_CONFIG));
3319 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
3320 RREG32(mmPA_SC_RASTER_CONFIG_1));
3321 }
3322 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3323
3324 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
3325 RREG32(mmGB_ADDR_CONFIG));
3326 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n",
3327 RREG32(mmHDP_ADDR_CONFIG));
3328 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n",
3329 RREG32(mmDMIF_ADDR_CALC));
3330 dev_info(adev->dev, " SDMA0_TILING_CONFIG=0x%08X\n",
3331 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
3332 dev_info(adev->dev, " SDMA1_TILING_CONFIG=0x%08X\n",
3333 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
3334 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
3335 RREG32(mmUVD_UDEC_ADDR_CONFIG));
3336 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
3337 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
3338 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
3339 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
3340
3341 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
3342 RREG32(mmCP_MEQ_THRESHOLDS));
3343 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
3344 RREG32(mmSX_DEBUG_1));
3345 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
3346 RREG32(mmTA_CNTL_AUX));
3347 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
3348 RREG32(mmSPI_CONFIG_CNTL));
3349 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
3350 RREG32(mmSQ_CONFIG));
3351 dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
3352 RREG32(mmDB_DEBUG));
3353 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
3354 RREG32(mmDB_DEBUG2));
3355 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
3356 RREG32(mmDB_DEBUG3));
3357 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
3358 RREG32(mmCB_HW_CONTROL));
3359 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
3360 RREG32(mmSPI_CONFIG_CNTL_1));
3361 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
3362 RREG32(mmPA_SC_FIFO_SIZE));
3363 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
3364 RREG32(mmVGT_NUM_INSTANCES));
3365 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
3366 RREG32(mmCP_PERFMON_CNTL));
3367 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
3368 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
3369 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
3370 RREG32(mmVGT_CACHE_INVALIDATION));
3371 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
3372 RREG32(mmVGT_GS_VERTEX_REUSE));
3373 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
3374 RREG32(mmPA_SC_LINE_STIPPLE_STATE));
3375 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
3376 RREG32(mmPA_CL_ENHANCE));
3377 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
3378 RREG32(mmPA_SC_ENHANCE));
3379
3380 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
3381 RREG32(mmCP_ME_CNTL));
3382 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
3383 RREG32(mmCP_MAX_CONTEXT));
3384 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n",
3385 RREG32(mmCP_ENDIAN_SWAP));
3386 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
3387 RREG32(mmCP_DEVICE_ID));
3388
3389 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
3390 RREG32(mmCP_SEM_WAIT_TIMER));
3391
3392 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
3393 RREG32(mmCP_RB_WPTR_DELAY));
3394 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
3395 RREG32(mmCP_RB_VMID));
3396 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
3397 RREG32(mmCP_RB0_CNTL));
3398 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
3399 RREG32(mmCP_RB0_WPTR));
3400 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
3401 RREG32(mmCP_RB0_RPTR_ADDR));
3402 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
3403 RREG32(mmCP_RB0_RPTR_ADDR_HI));
3404 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
3405 RREG32(mmCP_RB0_CNTL));
3406 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
3407 RREG32(mmCP_RB0_BASE));
3408 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
3409 RREG32(mmCP_RB0_BASE_HI));
3410 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
3411 RREG32(mmCP_MEC_CNTL));
3412 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n",
3413 RREG32(mmCP_CPF_DEBUG));
3414
3415 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
3416 RREG32(mmSCRATCH_ADDR));
3417 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
3418 RREG32(mmSCRATCH_UMSK));
3419
3420 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
3421 RREG32(mmCP_INT_CNTL_RING0));
3422 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
3423 RREG32(mmRLC_LB_CNTL));
3424 dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
3425 RREG32(mmRLC_CNTL));
3426 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
3427 RREG32(mmRLC_CGCG_CGLS_CTRL));
3428 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
3429 RREG32(mmRLC_LB_CNTR_INIT));
3430 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
3431 RREG32(mmRLC_LB_CNTR_MAX));
3432 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
3433 RREG32(mmRLC_LB_INIT_CU_MASK));
3434 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
3435 RREG32(mmRLC_LB_PARAMS));
3436 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
3437 RREG32(mmRLC_LB_CNTL));
3438 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n",
3439 RREG32(mmRLC_MC_CNTL));
3440 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
3441 RREG32(mmRLC_UCODE_CNTL));
3442
3443 mutex_lock(&adev->srbm_mutex);
3444 for (i = 0; i < 16; i++) {
3445 vi_srbm_select(adev, 0, 0, 0, i);
3446 dev_info(adev->dev, " VM %d:\n", i);
3447 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
3448 RREG32(mmSH_MEM_CONFIG));
3449 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n",
3450 RREG32(mmSH_MEM_APE1_BASE));
3451 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n",
3452 RREG32(mmSH_MEM_APE1_LIMIT));
3453 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
3454 RREG32(mmSH_MEM_BASES));
3455 }
3456 vi_srbm_select(adev, 0, 0, 0, 0);
3457 mutex_unlock(&adev->srbm_mutex);
3458 }
3459
3460 static int gfx_v8_0_soft_reset(void *handle)
3461 {
3462 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3463 u32 tmp;
3464 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3465
3466 /* GRBM_STATUS */
3467 tmp = RREG32(mmGRBM_STATUS);
3468 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3469 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3470 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3471 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3472 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3473 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3474 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3475 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3476 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3477 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3478 }
3479
3480 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3481 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3482 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3483 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3484 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3485 }
3486
3487 /* GRBM_STATUS2 */
3488 tmp = RREG32(mmGRBM_STATUS2);
3489 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3490 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3491 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3492
3493 /* SRBM_STATUS */
3494 tmp = RREG32(mmSRBM_STATUS);
3495 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
3496 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3497 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3498
3499 if (grbm_soft_reset || srbm_soft_reset) {
3500 gfx_v8_0_print_status((void *)adev);
3501 /* stop the rlc */
3502 gfx_v8_0_rlc_stop(adev);
3503
3504 /* Disable GFX parsing/prefetching */
3505 gfx_v8_0_cp_gfx_enable(adev, false);
3506
3507 /* Disable MEC parsing/prefetching */
3508 /* XXX todo */
3509
3510 if (grbm_soft_reset) {
3511 tmp = RREG32(mmGRBM_SOFT_RESET);
3512 tmp |= grbm_soft_reset;
3513 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3514 WREG32(mmGRBM_SOFT_RESET, tmp);
3515 tmp = RREG32(mmGRBM_SOFT_RESET);
3516
3517 udelay(50);
3518
3519 tmp &= ~grbm_soft_reset;
3520 WREG32(mmGRBM_SOFT_RESET, tmp);
3521 tmp = RREG32(mmGRBM_SOFT_RESET);
3522 }
3523
3524 if (srbm_soft_reset) {
3525 tmp = RREG32(mmSRBM_SOFT_RESET);
3526 tmp |= srbm_soft_reset;
3527 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3528 WREG32(mmSRBM_SOFT_RESET, tmp);
3529 tmp = RREG32(mmSRBM_SOFT_RESET);
3530
3531 udelay(50);
3532
3533 tmp &= ~srbm_soft_reset;
3534 WREG32(mmSRBM_SOFT_RESET, tmp);
3535 tmp = RREG32(mmSRBM_SOFT_RESET);
3536 }
3537 /* Wait a little for things to settle down */
3538 udelay(50);
3539 gfx_v8_0_print_status((void *)adev);
3540 }
3541 return 0;
3542 }
3543
3544 /**
3545 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
3546 *
3547 * @adev: amdgpu_device pointer
3548 *
3549 * Fetches a GPU clock counter snapshot.
3550 * Returns the 64 bit clock counter snapshot.
3551 */
3552 uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3553 {
3554 uint64_t clock;
3555
3556 mutex_lock(&adev->gfx.gpu_clock_mutex);
3557 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3558 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3559 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3560 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3561 return clock;
3562 }
3563
3564 static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3565 uint32_t vmid,
3566 uint32_t gds_base, uint32_t gds_size,
3567 uint32_t gws_base, uint32_t gws_size,
3568 uint32_t oa_base, uint32_t oa_size)
3569 {
3570 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3571 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3572
3573 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3574 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3575
3576 oa_base = oa_base >> AMDGPU_OA_SHIFT;
3577 oa_size = oa_size >> AMDGPU_OA_SHIFT;
3578
3579 /* GDS Base */
3580 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3581 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3582 WRITE_DATA_DST_SEL(0)));
3583 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
3584 amdgpu_ring_write(ring, 0);
3585 amdgpu_ring_write(ring, gds_base);
3586
3587 /* GDS Size */
3588 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3589 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3590 WRITE_DATA_DST_SEL(0)));
3591 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
3592 amdgpu_ring_write(ring, 0);
3593 amdgpu_ring_write(ring, gds_size);
3594
3595 /* GWS */
3596 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3597 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3598 WRITE_DATA_DST_SEL(0)));
3599 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
3600 amdgpu_ring_write(ring, 0);
3601 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3602
3603 /* OA */
3604 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3605 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3606 WRITE_DATA_DST_SEL(0)));
3607 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
3608 amdgpu_ring_write(ring, 0);
3609 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
3610 }
3611
3612 static int gfx_v8_0_early_init(void *handle)
3613 {
3614 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3615
3616 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
3617 adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
3618 gfx_v8_0_set_ring_funcs(adev);
3619 gfx_v8_0_set_irq_funcs(adev);
3620 gfx_v8_0_set_gds_init(adev);
3621
3622 return 0;
3623 }
3624
3625 static int gfx_v8_0_set_powergating_state(void *handle,
3626 enum amd_powergating_state state)
3627 {
3628 return 0;
3629 }
3630
3631 static int gfx_v8_0_set_clockgating_state(void *handle,
3632 enum amd_clockgating_state state)
3633 {
3634 return 0;
3635 }
3636
3637 static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3638 {
3639 u32 rptr;
3640
3641 rptr = ring->adev->wb.wb[ring->rptr_offs];
3642
3643 return rptr;
3644 }
3645
3646 static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3647 {
3648 struct amdgpu_device *adev = ring->adev;
3649 u32 wptr;
3650
3651 if (ring->use_doorbell)
3652 /* XXX check if swapping is necessary on BE */
3653 wptr = ring->adev->wb.wb[ring->wptr_offs];
3654 else
3655 wptr = RREG32(mmCP_RB0_WPTR);
3656
3657 return wptr;
3658 }
3659
3660 static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3661 {
3662 struct amdgpu_device *adev = ring->adev;
3663
3664 if (ring->use_doorbell) {
3665 /* XXX check if swapping is necessary on BE */
3666 adev->wb.wb[ring->wptr_offs] = ring->wptr;
3667 WDOORBELL32(ring->doorbell_index, ring->wptr);
3668 } else {
3669 WREG32(mmCP_RB0_WPTR, ring->wptr);
3670 (void)RREG32(mmCP_RB0_WPTR);
3671 }
3672 }
3673
3674 static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3675 {
3676 u32 ref_and_mask, reg_mem_engine;
3677
3678 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
3679 switch (ring->me) {
3680 case 1:
3681 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
3682 break;
3683 case 2:
3684 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
3685 break;
3686 default:
3687 return;
3688 }
3689 reg_mem_engine = 0;
3690 } else {
3691 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
3692 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
3693 }
3694
3695 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3696 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3697 WAIT_REG_MEM_FUNCTION(3) | /* == */
3698 reg_mem_engine));
3699 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
3700 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
3701 amdgpu_ring_write(ring, ref_and_mask);
3702 amdgpu_ring_write(ring, ref_and_mask);
3703 amdgpu_ring_write(ring, 0x20); /* poll interval */
3704 }
3705
3706 static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring,
3707 struct amdgpu_ib *ib)
3708 {
3709 bool need_ctx_switch = ring->current_ctx != ib->ctx;
3710 u32 header, control = 0;
3711 u32 next_rptr = ring->wptr + 5;
3712
3713 /* drop the CE preamble IB for the same context */
3714 if ((ring->type == AMDGPU_RING_TYPE_GFX) &&
3715 (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
3716 !need_ctx_switch)
3717 return;
3718
3719 if (ring->type == AMDGPU_RING_TYPE_COMPUTE)
3720 control |= INDIRECT_BUFFER_VALID;
3721
3722 if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX)
3723 next_rptr += 2;
3724
3725 next_rptr += 4;
3726 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3727 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3728 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3729 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3730 amdgpu_ring_write(ring, next_rptr);
3731
3732 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
3733 if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) {
3734 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3735 amdgpu_ring_write(ring, 0);
3736 }
3737
3738 if (ib->flags & AMDGPU_IB_FLAG_CE)
3739 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3740 else
3741 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3742
3743 control |= ib->length_dw |
3744 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3745
3746 amdgpu_ring_write(ring, header);
3747 amdgpu_ring_write(ring,
3748 #ifdef __BIG_ENDIAN
3749 (2 << 0) |
3750 #endif
3751 (ib->gpu_addr & 0xFFFFFFFC));
3752 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3753 amdgpu_ring_write(ring, control);
3754 }
3755
3756 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
3757 u64 seq, unsigned flags)
3758 {
3759 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3760 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3761
3762 /* EVENT_WRITE_EOP - flush caches, send int */
3763 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3764 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3765 EOP_TC_ACTION_EN |
3766 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3767 EVENT_INDEX(5)));
3768 amdgpu_ring_write(ring, addr & 0xfffffffc);
3769 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
3770 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3771 amdgpu_ring_write(ring, lower_32_bits(seq));
3772 amdgpu_ring_write(ring, upper_32_bits(seq));
3773 }
3774
3775 /**
3776 * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring
3777 *
3778 * @ring: amdgpu ring buffer object
3779 * @semaphore: amdgpu semaphore object
3780 * @emit_wait: Is this a sempahore wait?
3781 *
3782 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
3783 * from running ahead of semaphore waits.
3784 */
3785 static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
3786 struct amdgpu_semaphore *semaphore,
3787 bool emit_wait)
3788 {
3789 uint64_t addr = semaphore->gpu_addr;
3790 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3791
3792 if (ring->adev->asic_type == CHIP_TOPAZ ||
3793 ring->adev->asic_type == CHIP_TONGA)
3794 /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */
3795 return false;
3796 else {
3797 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
3798 amdgpu_ring_write(ring, lower_32_bits(addr));
3799 amdgpu_ring_write(ring, upper_32_bits(addr));
3800 amdgpu_ring_write(ring, sel);
3801 }
3802
3803 if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
3804 /* Prevent the PFP from running ahead of the semaphore wait */
3805 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3806 amdgpu_ring_write(ring, 0x0);
3807 }
3808
3809 return true;
3810 }
3811
3812 static void gfx_v8_0_ce_sync_me(struct amdgpu_ring *ring)
3813 {
3814 struct amdgpu_device *adev = ring->adev;
3815 u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4;
3816
3817 /* instruct DE to set a magic number */
3818 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3819 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3820 WRITE_DATA_DST_SEL(5)));
3821 amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3822 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3823 amdgpu_ring_write(ring, 1);
3824
3825 /* let CE wait till condition satisfied */
3826 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3827 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3828 WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3829 WAIT_REG_MEM_FUNCTION(3) | /* == */
3830 WAIT_REG_MEM_ENGINE(2))); /* ce */
3831 amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3832 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3833 amdgpu_ring_write(ring, 1);
3834 amdgpu_ring_write(ring, 0xffffffff);
3835 amdgpu_ring_write(ring, 4); /* poll interval */
3836
3837 /* instruct CE to reset wb of ce_sync to zero */
3838 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3839 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3840 WRITE_DATA_DST_SEL(5) |
3841 WR_CONFIRM));
3842 amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3843 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3844 amdgpu_ring_write(ring, 0);
3845 }
3846
3847 static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3848 unsigned vm_id, uint64_t pd_addr)
3849 {
3850 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
3851
3852 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3853 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3854 WRITE_DATA_DST_SEL(0)));
3855 if (vm_id < 8) {
3856 amdgpu_ring_write(ring,
3857 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3858 } else {
3859 amdgpu_ring_write(ring,
3860 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3861 }
3862 amdgpu_ring_write(ring, 0);
3863 amdgpu_ring_write(ring, pd_addr >> 12);
3864
3865 /* bits 0-15 are the VM contexts0-15 */
3866 /* invalidate the cache */
3867 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3868 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3869 WRITE_DATA_DST_SEL(0)));
3870 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3871 amdgpu_ring_write(ring, 0);
3872 amdgpu_ring_write(ring, 1 << vm_id);
3873
3874 /* wait for the invalidate to complete */
3875 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3876 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3877 WAIT_REG_MEM_FUNCTION(0) | /* always */
3878 WAIT_REG_MEM_ENGINE(0))); /* me */
3879 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3880 amdgpu_ring_write(ring, 0);
3881 amdgpu_ring_write(ring, 0); /* ref */
3882 amdgpu_ring_write(ring, 0); /* mask */
3883 amdgpu_ring_write(ring, 0x20); /* poll interval */
3884
3885 /* compute doesn't have PFP */
3886 if (usepfp) {
3887 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3888 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3889 amdgpu_ring_write(ring, 0x0);
3890
3891 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3892 gfx_v8_0_ce_sync_me(ring);
3893 }
3894 }
3895
3896 static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring)
3897 {
3898 if (gfx_v8_0_is_idle(ring->adev)) {
3899 amdgpu_ring_lockup_update(ring);
3900 return false;
3901 }
3902 return amdgpu_ring_test_lockup(ring);
3903 }
3904
3905 static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3906 {
3907 return ring->adev->wb.wb[ring->rptr_offs];
3908 }
3909
3910 static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3911 {
3912 return ring->adev->wb.wb[ring->wptr_offs];
3913 }
3914
3915 static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3916 {
3917 struct amdgpu_device *adev = ring->adev;
3918
3919 /* XXX check if swapping is necessary on BE */
3920 adev->wb.wb[ring->wptr_offs] = ring->wptr;
3921 WDOORBELL32(ring->doorbell_index, ring->wptr);
3922 }
3923
3924 static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
3925 u64 addr, u64 seq,
3926 unsigned flags)
3927 {
3928 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3929 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3930
3931 /* RELEASE_MEM - flush caches, send int */
3932 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
3933 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3934 EOP_TC_ACTION_EN |
3935 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3936 EVENT_INDEX(5)));
3937 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3938 amdgpu_ring_write(ring, addr & 0xfffffffc);
3939 amdgpu_ring_write(ring, upper_32_bits(addr));
3940 amdgpu_ring_write(ring, lower_32_bits(seq));
3941 amdgpu_ring_write(ring, upper_32_bits(seq));
3942 }
3943
3944 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3945 enum amdgpu_interrupt_state state)
3946 {
3947 u32 cp_int_cntl;
3948
3949 switch (state) {
3950 case AMDGPU_IRQ_STATE_DISABLE:
3951 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3952 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
3953 TIME_STAMP_INT_ENABLE, 0);
3954 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3955 break;
3956 case AMDGPU_IRQ_STATE_ENABLE:
3957 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3958 cp_int_cntl =
3959 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
3960 TIME_STAMP_INT_ENABLE, 1);
3961 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3962 break;
3963 default:
3964 break;
3965 }
3966 }
3967
3968 static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3969 int me, int pipe,
3970 enum amdgpu_interrupt_state state)
3971 {
3972 u32 mec_int_cntl, mec_int_cntl_reg;
3973
3974 /*
3975 * amdgpu controls only pipe 0 of MEC1. That's why this function only
3976 * handles the setting of interrupts for this specific pipe. All other
3977 * pipes' interrupts are set by amdkfd.
3978 */
3979
3980 if (me == 1) {
3981 switch (pipe) {
3982 case 0:
3983 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
3984 break;
3985 default:
3986 DRM_DEBUG("invalid pipe %d\n", pipe);
3987 return;
3988 }
3989 } else {
3990 DRM_DEBUG("invalid me %d\n", me);
3991 return;
3992 }
3993
3994 switch (state) {
3995 case AMDGPU_IRQ_STATE_DISABLE:
3996 mec_int_cntl = RREG32(mec_int_cntl_reg);
3997 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3998 TIME_STAMP_INT_ENABLE, 0);
3999 WREG32(mec_int_cntl_reg, mec_int_cntl);
4000 break;
4001 case AMDGPU_IRQ_STATE_ENABLE:
4002 mec_int_cntl = RREG32(mec_int_cntl_reg);
4003 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4004 TIME_STAMP_INT_ENABLE, 1);
4005 WREG32(mec_int_cntl_reg, mec_int_cntl);
4006 break;
4007 default:
4008 break;
4009 }
4010 }
4011
4012 static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4013 struct amdgpu_irq_src *source,
4014 unsigned type,
4015 enum amdgpu_interrupt_state state)
4016 {
4017 u32 cp_int_cntl;
4018
4019 switch (state) {
4020 case AMDGPU_IRQ_STATE_DISABLE:
4021 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4022 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4023 PRIV_REG_INT_ENABLE, 0);
4024 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4025 break;
4026 case AMDGPU_IRQ_STATE_ENABLE:
4027 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4028 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4029 PRIV_REG_INT_ENABLE, 0);
4030 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4031 break;
4032 default:
4033 break;
4034 }
4035
4036 return 0;
4037 }
4038
4039 static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4040 struct amdgpu_irq_src *source,
4041 unsigned type,
4042 enum amdgpu_interrupt_state state)
4043 {
4044 u32 cp_int_cntl;
4045
4046 switch (state) {
4047 case AMDGPU_IRQ_STATE_DISABLE:
4048 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4049 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4050 PRIV_INSTR_INT_ENABLE, 0);
4051 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4052 break;
4053 case AMDGPU_IRQ_STATE_ENABLE:
4054 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4055 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4056 PRIV_INSTR_INT_ENABLE, 1);
4057 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4058 break;
4059 default:
4060 break;
4061 }
4062
4063 return 0;
4064 }
4065
4066 static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4067 struct amdgpu_irq_src *src,
4068 unsigned type,
4069 enum amdgpu_interrupt_state state)
4070 {
4071 switch (type) {
4072 case AMDGPU_CP_IRQ_GFX_EOP:
4073 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
4074 break;
4075 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4076 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4077 break;
4078 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4079 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4080 break;
4081 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4082 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4083 break;
4084 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4085 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4086 break;
4087 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4088 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4089 break;
4090 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4091 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4092 break;
4093 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4094 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4095 break;
4096 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4097 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4098 break;
4099 default:
4100 break;
4101 }
4102 return 0;
4103 }
4104
4105 static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
4106 struct amdgpu_irq_src *source,
4107 struct amdgpu_iv_entry *entry)
4108 {
4109 int i;
4110 u8 me_id, pipe_id, queue_id;
4111 struct amdgpu_ring *ring;
4112
4113 DRM_DEBUG("IH: CP EOP\n");
4114 me_id = (entry->ring_id & 0x0c) >> 2;
4115 pipe_id = (entry->ring_id & 0x03) >> 0;
4116 queue_id = (entry->ring_id & 0x70) >> 4;
4117
4118 switch (me_id) {
4119 case 0:
4120 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4121 break;
4122 case 1:
4123 case 2:
4124 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4125 ring = &adev->gfx.compute_ring[i];
4126 /* Per-queue interrupt is supported for MEC starting from VI.
4127 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4128 */
4129 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4130 amdgpu_fence_process(ring);
4131 }
4132 break;
4133 }
4134 return 0;
4135 }
4136
4137 static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
4138 struct amdgpu_irq_src *source,
4139 struct amdgpu_iv_entry *entry)
4140 {
4141 DRM_ERROR("Illegal register access in command stream\n");
4142 schedule_work(&adev->reset_work);
4143 return 0;
4144 }
4145
4146 static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
4147 struct amdgpu_irq_src *source,
4148 struct amdgpu_iv_entry *entry)
4149 {
4150 DRM_ERROR("Illegal instruction in command stream\n");
4151 schedule_work(&adev->reset_work);
4152 return 0;
4153 }
4154
4155 const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
4156 .early_init = gfx_v8_0_early_init,
4157 .late_init = NULL,
4158 .sw_init = gfx_v8_0_sw_init,
4159 .sw_fini = gfx_v8_0_sw_fini,
4160 .hw_init = gfx_v8_0_hw_init,
4161 .hw_fini = gfx_v8_0_hw_fini,
4162 .suspend = gfx_v8_0_suspend,
4163 .resume = gfx_v8_0_resume,
4164 .is_idle = gfx_v8_0_is_idle,
4165 .wait_for_idle = gfx_v8_0_wait_for_idle,
4166 .soft_reset = gfx_v8_0_soft_reset,
4167 .print_status = gfx_v8_0_print_status,
4168 .set_clockgating_state = gfx_v8_0_set_clockgating_state,
4169 .set_powergating_state = gfx_v8_0_set_powergating_state,
4170 };
4171
4172 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
4173 .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
4174 .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
4175 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
4176 .parse_cs = NULL,
4177 .emit_ib = gfx_v8_0_ring_emit_ib,
4178 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
4179 .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4180 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4181 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4182 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4183 .test_ring = gfx_v8_0_ring_test_ring,
4184 .test_ib = gfx_v8_0_ring_test_ib,
4185 .is_lockup = gfx_v8_0_ring_is_lockup,
4186 };
4187
4188 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
4189 .get_rptr = gfx_v8_0_ring_get_rptr_compute,
4190 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
4191 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
4192 .parse_cs = NULL,
4193 .emit_ib = gfx_v8_0_ring_emit_ib,
4194 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
4195 .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4196 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4197 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4198 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4199 .test_ring = gfx_v8_0_ring_test_ring,
4200 .test_ib = gfx_v8_0_ring_test_ib,
4201 .is_lockup = gfx_v8_0_ring_is_lockup,
4202 };
4203
4204 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
4205 {
4206 int i;
4207
4208 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4209 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
4210
4211 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4212 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
4213 }
4214
4215 static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
4216 .set = gfx_v8_0_set_eop_interrupt_state,
4217 .process = gfx_v8_0_eop_irq,
4218 };
4219
4220 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
4221 .set = gfx_v8_0_set_priv_reg_fault_state,
4222 .process = gfx_v8_0_priv_reg_irq,
4223 };
4224
4225 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
4226 .set = gfx_v8_0_set_priv_inst_fault_state,
4227 .process = gfx_v8_0_priv_inst_irq,
4228 };
4229
4230 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
4231 {
4232 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4233 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
4234
4235 adev->gfx.priv_reg_irq.num_types = 1;
4236 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
4237
4238 adev->gfx.priv_inst_irq.num_types = 1;
4239 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
4240 }
4241
4242 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
4243 {
4244 /* init asci gds info */
4245 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
4246 adev->gds.gws.total_size = 64;
4247 adev->gds.oa.total_size = 16;
4248
4249 if (adev->gds.mem.total_size == 64 * 1024) {
4250 adev->gds.mem.gfx_partition_size = 4096;
4251 adev->gds.mem.cs_partition_size = 4096;
4252
4253 adev->gds.gws.gfx_partition_size = 4;
4254 adev->gds.gws.cs_partition_size = 4;
4255
4256 adev->gds.oa.gfx_partition_size = 4;
4257 adev->gds.oa.cs_partition_size = 1;
4258 } else {
4259 adev->gds.mem.gfx_partition_size = 1024;
4260 adev->gds.mem.cs_partition_size = 1024;
4261
4262 adev->gds.gws.gfx_partition_size = 16;
4263 adev->gds.gws.cs_partition_size = 16;
4264
4265 adev->gds.oa.gfx_partition_size = 4;
4266 adev->gds.oa.cs_partition_size = 4;
4267 }
4268 }
4269
4270 static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev,
4271 u32 se, u32 sh)
4272 {
4273 u32 mask = 0, tmp, tmp1;
4274 int i;
4275
4276 gfx_v8_0_select_se_sh(adev, se, sh);
4277 tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4278 tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4279 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4280
4281 tmp &= 0xffff0000;
4282
4283 tmp |= tmp1;
4284 tmp >>= 16;
4285
4286 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
4287 mask <<= 1;
4288 mask |= 1;
4289 }
4290
4291 return (~tmp) & mask;
4292 }
4293
4294 int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
4295 struct amdgpu_cu_info *cu_info)
4296 {
4297 int i, j, k, counter, active_cu_number = 0;
4298 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4299
4300 if (!adev || !cu_info)
4301 return -EINVAL;
4302
4303 mutex_lock(&adev->grbm_idx_mutex);
4304 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4305 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4306 mask = 1;
4307 ao_bitmap = 0;
4308 counter = 0;
4309 bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j);
4310 cu_info->bitmap[i][j] = bitmap;
4311
4312 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4313 if (bitmap & mask) {
4314 if (counter < 2)
4315 ao_bitmap |= mask;
4316 counter ++;
4317 }
4318 mask <<= 1;
4319 }
4320 active_cu_number += counter;
4321 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4322 }
4323 }
4324
4325 cu_info->number = active_cu_number;
4326 cu_info->ao_cu_mask = ao_cu_mask;
4327 mutex_unlock(&adev->grbm_idx_mutex);
4328 return 0;
4329 }
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