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drm/amdgpu/gfx9: drop duplicate gfx info init (v3)
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c
1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include "drmP.h"
25 #include "amdgpu.h"
26 #include "amdgpu_gfx.h"
27 #include "soc15.h"
28 #include "soc15d.h"
29
30 #include "vega10/soc15ip.h"
31 #include "vega10/GC/gc_9_0_offset.h"
32 #include "vega10/GC/gc_9_0_sh_mask.h"
33 #include "vega10/vega10_enum.h"
34 #include "vega10/HDP/hdp_4_0_offset.h"
35
36 #include "soc15_common.h"
37 #include "clearstate_gfx9.h"
38 #include "v9_structs.h"
39
40 #define GFX9_NUM_GFX_RINGS 1
41 #define GFX9_NUM_COMPUTE_RINGS 8
42 #define RLCG_UCODE_LOADING_START_ADDRESS 0x2000
43
44 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
45 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
46 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
47 MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
48 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
49 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
50
51 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
52 {
53 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
54 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},
55 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
56 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},
57 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
58 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},
59 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
60 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},
61 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
62 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},
63 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
64 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},
65 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
66 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},
67 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
68 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},
69 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
70 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},
71 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
72 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},
73 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
74 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},
75 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
76 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},
77 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
78 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
79 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
80 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},
81 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
82 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},
83 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
84 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}
85 };
86
87 static const u32 golden_settings_gc_9_0[] =
88 {
89 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00ffeff, 0x00000400,
90 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
91 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
92 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
93 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
94 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
95 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
96 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff
97 };
98
99 static const u32 golden_settings_gc_9_0_vg10[] =
100 {
101 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
102 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
103 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
104 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
105 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
106 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
107 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800,
108 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1),0x0000000f, 0x00000007
109 };
110
111 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
112
113 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
114 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
115 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
116 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
117 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
118 struct amdgpu_cu_info *cu_info);
119 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
120 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
121
122 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
123 {
124 switch (adev->asic_type) {
125 case CHIP_VEGA10:
126 amdgpu_program_register_sequence(adev,
127 golden_settings_gc_9_0,
128 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
129 amdgpu_program_register_sequence(adev,
130 golden_settings_gc_9_0_vg10,
131 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
132 break;
133 default:
134 break;
135 }
136 }
137
138 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
139 {
140 adev->gfx.scratch.num_reg = 7;
141 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
142 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
143 }
144
145 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
146 bool wc, uint32_t reg, uint32_t val)
147 {
148 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
149 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
150 WRITE_DATA_DST_SEL(0) |
151 (wc ? WR_CONFIRM : 0));
152 amdgpu_ring_write(ring, reg);
153 amdgpu_ring_write(ring, 0);
154 amdgpu_ring_write(ring, val);
155 }
156
157 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
158 int mem_space, int opt, uint32_t addr0,
159 uint32_t addr1, uint32_t ref, uint32_t mask,
160 uint32_t inv)
161 {
162 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
163 amdgpu_ring_write(ring,
164 /* memory (1) or register (0) */
165 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
166 WAIT_REG_MEM_OPERATION(opt) | /* wait */
167 WAIT_REG_MEM_FUNCTION(3) | /* equal */
168 WAIT_REG_MEM_ENGINE(eng_sel)));
169
170 if (mem_space)
171 BUG_ON(addr0 & 0x3); /* Dword align */
172 amdgpu_ring_write(ring, addr0);
173 amdgpu_ring_write(ring, addr1);
174 amdgpu_ring_write(ring, ref);
175 amdgpu_ring_write(ring, mask);
176 amdgpu_ring_write(ring, inv); /* poll interval */
177 }
178
179 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
180 {
181 struct amdgpu_device *adev = ring->adev;
182 uint32_t scratch;
183 uint32_t tmp = 0;
184 unsigned i;
185 int r;
186
187 r = amdgpu_gfx_scratch_get(adev, &scratch);
188 if (r) {
189 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
190 return r;
191 }
192 WREG32(scratch, 0xCAFEDEAD);
193 r = amdgpu_ring_alloc(ring, 3);
194 if (r) {
195 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
196 ring->idx, r);
197 amdgpu_gfx_scratch_free(adev, scratch);
198 return r;
199 }
200 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
201 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
202 amdgpu_ring_write(ring, 0xDEADBEEF);
203 amdgpu_ring_commit(ring);
204
205 for (i = 0; i < adev->usec_timeout; i++) {
206 tmp = RREG32(scratch);
207 if (tmp == 0xDEADBEEF)
208 break;
209 DRM_UDELAY(1);
210 }
211 if (i < adev->usec_timeout) {
212 DRM_INFO("ring test on %d succeeded in %d usecs\n",
213 ring->idx, i);
214 } else {
215 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
216 ring->idx, scratch, tmp);
217 r = -EINVAL;
218 }
219 amdgpu_gfx_scratch_free(adev, scratch);
220 return r;
221 }
222
223 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
224 {
225 struct amdgpu_device *adev = ring->adev;
226 struct amdgpu_ib ib;
227 struct dma_fence *f = NULL;
228 uint32_t scratch;
229 uint32_t tmp = 0;
230 long r;
231
232 r = amdgpu_gfx_scratch_get(adev, &scratch);
233 if (r) {
234 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
235 return r;
236 }
237 WREG32(scratch, 0xCAFEDEAD);
238 memset(&ib, 0, sizeof(ib));
239 r = amdgpu_ib_get(adev, NULL, 256, &ib);
240 if (r) {
241 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
242 goto err1;
243 }
244 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
245 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
246 ib.ptr[2] = 0xDEADBEEF;
247 ib.length_dw = 3;
248
249 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
250 if (r)
251 goto err2;
252
253 r = dma_fence_wait_timeout(f, false, timeout);
254 if (r == 0) {
255 DRM_ERROR("amdgpu: IB test timed out.\n");
256 r = -ETIMEDOUT;
257 goto err2;
258 } else if (r < 0) {
259 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
260 goto err2;
261 }
262 tmp = RREG32(scratch);
263 if (tmp == 0xDEADBEEF) {
264 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
265 r = 0;
266 } else {
267 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
268 scratch, tmp);
269 r = -EINVAL;
270 }
271 err2:
272 amdgpu_ib_free(adev, &ib, NULL);
273 dma_fence_put(f);
274 err1:
275 amdgpu_gfx_scratch_free(adev, scratch);
276 return r;
277 }
278
279 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
280 {
281 const char *chip_name;
282 char fw_name[30];
283 int err;
284 struct amdgpu_firmware_info *info = NULL;
285 const struct common_firmware_header *header = NULL;
286 const struct gfx_firmware_header_v1_0 *cp_hdr;
287
288 DRM_DEBUG("\n");
289
290 switch (adev->asic_type) {
291 case CHIP_VEGA10:
292 chip_name = "vega10";
293 break;
294 default:
295 BUG();
296 }
297
298 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
299 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
300 if (err)
301 goto out;
302 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
303 if (err)
304 goto out;
305 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
306 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
307 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
308
309 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
310 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
311 if (err)
312 goto out;
313 err = amdgpu_ucode_validate(adev->gfx.me_fw);
314 if (err)
315 goto out;
316 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
317 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
318 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
319
320 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
321 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
322 if (err)
323 goto out;
324 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
325 if (err)
326 goto out;
327 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
328 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
329 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
330
331 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
332 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
333 if (err)
334 goto out;
335 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
336 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
337 adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
338 adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
339
340 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
341 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
342 if (err)
343 goto out;
344 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
345 if (err)
346 goto out;
347 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
348 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
349 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
350
351
352 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
353 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
354 if (!err) {
355 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
356 if (err)
357 goto out;
358 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
359 adev->gfx.mec2_fw->data;
360 adev->gfx.mec2_fw_version =
361 le32_to_cpu(cp_hdr->header.ucode_version);
362 adev->gfx.mec2_feature_version =
363 le32_to_cpu(cp_hdr->ucode_feature_version);
364 } else {
365 err = 0;
366 adev->gfx.mec2_fw = NULL;
367 }
368
369 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
370 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
371 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
372 info->fw = adev->gfx.pfp_fw;
373 header = (const struct common_firmware_header *)info->fw->data;
374 adev->firmware.fw_size +=
375 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
376
377 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
378 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
379 info->fw = adev->gfx.me_fw;
380 header = (const struct common_firmware_header *)info->fw->data;
381 adev->firmware.fw_size +=
382 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
383
384 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
385 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
386 info->fw = adev->gfx.ce_fw;
387 header = (const struct common_firmware_header *)info->fw->data;
388 adev->firmware.fw_size +=
389 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
390
391 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
392 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
393 info->fw = adev->gfx.rlc_fw;
394 header = (const struct common_firmware_header *)info->fw->data;
395 adev->firmware.fw_size +=
396 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
397
398 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
399 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
400 info->fw = adev->gfx.mec_fw;
401 header = (const struct common_firmware_header *)info->fw->data;
402 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
403 adev->firmware.fw_size +=
404 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
405
406 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
407 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
408 info->fw = adev->gfx.mec_fw;
409 adev->firmware.fw_size +=
410 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
411
412 if (adev->gfx.mec2_fw) {
413 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
414 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
415 info->fw = adev->gfx.mec2_fw;
416 header = (const struct common_firmware_header *)info->fw->data;
417 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
418 adev->firmware.fw_size +=
419 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
420 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
421 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
422 info->fw = adev->gfx.mec2_fw;
423 adev->firmware.fw_size +=
424 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
425 }
426
427 }
428
429 out:
430 if (err) {
431 dev_err(adev->dev,
432 "gfx9: Failed to load firmware \"%s\"\n",
433 fw_name);
434 release_firmware(adev->gfx.pfp_fw);
435 adev->gfx.pfp_fw = NULL;
436 release_firmware(adev->gfx.me_fw);
437 adev->gfx.me_fw = NULL;
438 release_firmware(adev->gfx.ce_fw);
439 adev->gfx.ce_fw = NULL;
440 release_firmware(adev->gfx.rlc_fw);
441 adev->gfx.rlc_fw = NULL;
442 release_firmware(adev->gfx.mec_fw);
443 adev->gfx.mec_fw = NULL;
444 release_firmware(adev->gfx.mec2_fw);
445 adev->gfx.mec2_fw = NULL;
446 }
447 return err;
448 }
449
450 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
451 {
452 int r;
453
454 if (adev->gfx.mec.hpd_eop_obj) {
455 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, true);
456 if (unlikely(r != 0))
457 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
458 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
459 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
460
461 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
462 adev->gfx.mec.hpd_eop_obj = NULL;
463 }
464 if (adev->gfx.mec.mec_fw_obj) {
465 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, true);
466 if (unlikely(r != 0))
467 dev_warn(adev->dev, "(%d) reserve mec firmware bo failed\n", r);
468 amdgpu_bo_unpin(adev->gfx.mec.mec_fw_obj);
469 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
470
471 amdgpu_bo_unref(&adev->gfx.mec.mec_fw_obj);
472 adev->gfx.mec.mec_fw_obj = NULL;
473 }
474 }
475
476 #define MEC_HPD_SIZE 2048
477
478 static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
479 {
480 int r;
481 u32 *hpd;
482 const __le32 *fw_data;
483 unsigned fw_size;
484 u32 *fw;
485
486 const struct gfx_firmware_header_v1_0 *mec_hdr;
487
488 /*
489 * we assign only 1 pipe because all other pipes will
490 * be handled by KFD
491 */
492 adev->gfx.mec.num_mec = 1;
493 adev->gfx.mec.num_pipe = 1;
494 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
495
496 if (adev->gfx.mec.hpd_eop_obj == NULL) {
497 r = amdgpu_bo_create(adev,
498 adev->gfx.mec.num_queue * MEC_HPD_SIZE,
499 PAGE_SIZE, true,
500 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
501 &adev->gfx.mec.hpd_eop_obj);
502 if (r) {
503 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
504 return r;
505 }
506 }
507
508 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
509 if (unlikely(r != 0)) {
510 gfx_v9_0_mec_fini(adev);
511 return r;
512 }
513 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
514 &adev->gfx.mec.hpd_eop_gpu_addr);
515 if (r) {
516 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
517 gfx_v9_0_mec_fini(adev);
518 return r;
519 }
520 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
521 if (r) {
522 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
523 gfx_v9_0_mec_fini(adev);
524 return r;
525 }
526
527 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
528
529 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
530 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
531
532 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
533
534 fw_data = (const __le32 *)
535 (adev->gfx.mec_fw->data +
536 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
537 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
538
539 if (adev->gfx.mec.mec_fw_obj == NULL) {
540 r = amdgpu_bo_create(adev,
541 mec_hdr->header.ucode_size_bytes,
542 PAGE_SIZE, true,
543 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
544 &adev->gfx.mec.mec_fw_obj);
545 if (r) {
546 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
547 return r;
548 }
549 }
550
551 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
552 if (unlikely(r != 0)) {
553 gfx_v9_0_mec_fini(adev);
554 return r;
555 }
556 r = amdgpu_bo_pin(adev->gfx.mec.mec_fw_obj, AMDGPU_GEM_DOMAIN_GTT,
557 &adev->gfx.mec.mec_fw_gpu_addr);
558 if (r) {
559 dev_warn(adev->dev, "(%d) pin mec firmware bo failed\n", r);
560 gfx_v9_0_mec_fini(adev);
561 return r;
562 }
563 r = amdgpu_bo_kmap(adev->gfx.mec.mec_fw_obj, (void **)&fw);
564 if (r) {
565 dev_warn(adev->dev, "(%d) map firmware bo failed\n", r);
566 gfx_v9_0_mec_fini(adev);
567 return r;
568 }
569 memcpy(fw, fw_data, fw_size);
570
571 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
572 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
573
574
575 return 0;
576 }
577
578 static void gfx_v9_0_kiq_fini(struct amdgpu_device *adev)
579 {
580 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
581
582 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
583 }
584
585 static int gfx_v9_0_kiq_init(struct amdgpu_device *adev)
586 {
587 int r;
588 u32 *hpd;
589 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
590
591 r = amdgpu_bo_create_kernel(adev, MEC_HPD_SIZE, PAGE_SIZE,
592 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
593 &kiq->eop_gpu_addr, (void **)&hpd);
594 if (r) {
595 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
596 return r;
597 }
598
599 memset(hpd, 0, MEC_HPD_SIZE);
600
601 r = amdgpu_bo_reserve(kiq->eop_obj, true);
602 if (unlikely(r != 0))
603 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
604 amdgpu_bo_kunmap(kiq->eop_obj);
605 amdgpu_bo_unreserve(kiq->eop_obj);
606
607 return 0;
608 }
609
610 static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev,
611 struct amdgpu_ring *ring,
612 struct amdgpu_irq_src *irq)
613 {
614 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
615 int r = 0;
616
617 r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs);
618 if (r)
619 return r;
620
621 ring->adev = NULL;
622 ring->ring_obj = NULL;
623 ring->use_doorbell = true;
624 ring->doorbell_index = AMDGPU_DOORBELL_KIQ;
625 if (adev->gfx.mec2_fw) {
626 ring->me = 2;
627 ring->pipe = 0;
628 } else {
629 ring->me = 1;
630 ring->pipe = 1;
631 }
632
633 ring->queue = 0;
634 ring->eop_gpu_addr = kiq->eop_gpu_addr;
635 sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue);
636 r = amdgpu_ring_init(adev, ring, 1024,
637 irq, AMDGPU_CP_KIQ_IRQ_DRIVER0);
638 if (r)
639 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
640
641 return r;
642 }
643 static void gfx_v9_0_kiq_free_ring(struct amdgpu_ring *ring,
644 struct amdgpu_irq_src *irq)
645 {
646 amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
647 amdgpu_ring_fini(ring);
648 }
649
650 /* create MQD for each compute queue */
651 static int gfx_v9_0_compute_mqd_sw_init(struct amdgpu_device *adev)
652 {
653 struct amdgpu_ring *ring = NULL;
654 int r, i;
655
656 /* create MQD for KIQ */
657 ring = &adev->gfx.kiq.ring;
658 if (!ring->mqd_obj) {
659 r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE,
660 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
661 &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
662 if (r) {
663 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
664 return r;
665 }
666
667 /*TODO: prepare MQD backup */
668 }
669
670 /* create MQD for each KCQ */
671 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
672 ring = &adev->gfx.compute_ring[i];
673 if (!ring->mqd_obj) {
674 r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE,
675 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
676 &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
677 if (r) {
678 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
679 return r;
680 }
681
682 /* TODO: prepare MQD backup */
683 }
684 }
685
686 return 0;
687 }
688
689 static void gfx_v9_0_compute_mqd_sw_fini(struct amdgpu_device *adev)
690 {
691 struct amdgpu_ring *ring = NULL;
692 int i;
693
694 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
695 ring = &adev->gfx.compute_ring[i];
696 amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
697 }
698
699 ring = &adev->gfx.kiq.ring;
700 amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
701 }
702
703 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
704 {
705 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
706 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
707 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
708 (address << SQ_IND_INDEX__INDEX__SHIFT) |
709 (SQ_IND_INDEX__FORCE_READ_MASK));
710 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
711 }
712
713 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
714 uint32_t wave, uint32_t thread,
715 uint32_t regno, uint32_t num, uint32_t *out)
716 {
717 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
718 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
719 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
720 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
721 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
722 (SQ_IND_INDEX__FORCE_READ_MASK) |
723 (SQ_IND_INDEX__AUTO_INCR_MASK));
724 while (num--)
725 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
726 }
727
728 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
729 {
730 /* type 1 wave data */
731 dst[(*no_fields)++] = 1;
732 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
733 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
734 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
735 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
736 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
737 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
738 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
739 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
740 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
741 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
742 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
743 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
744 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
745 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
746 }
747
748 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
749 uint32_t wave, uint32_t start,
750 uint32_t size, uint32_t *dst)
751 {
752 wave_read_regs(
753 adev, simd, wave, 0,
754 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
755 }
756
757
758 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
759 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
760 .select_se_sh = &gfx_v9_0_select_se_sh,
761 .read_wave_data = &gfx_v9_0_read_wave_data,
762 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
763 };
764
765 static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
766 {
767 u32 gb_addr_config;
768
769 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
770
771 switch (adev->asic_type) {
772 case CHIP_VEGA10:
773 adev->gfx.config.max_hw_contexts = 8;
774 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
775 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
776 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
777 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
778 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
779 break;
780 default:
781 BUG();
782 break;
783 }
784
785 adev->gfx.config.gb_addr_config = gb_addr_config;
786
787 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
788 REG_GET_FIELD(
789 adev->gfx.config.gb_addr_config,
790 GB_ADDR_CONFIG,
791 NUM_PIPES);
792
793 adev->gfx.config.max_tile_pipes =
794 adev->gfx.config.gb_addr_config_fields.num_pipes;
795
796 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
797 REG_GET_FIELD(
798 adev->gfx.config.gb_addr_config,
799 GB_ADDR_CONFIG,
800 NUM_BANKS);
801 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
802 REG_GET_FIELD(
803 adev->gfx.config.gb_addr_config,
804 GB_ADDR_CONFIG,
805 MAX_COMPRESSED_FRAGS);
806 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
807 REG_GET_FIELD(
808 adev->gfx.config.gb_addr_config,
809 GB_ADDR_CONFIG,
810 NUM_RB_PER_SE);
811 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
812 REG_GET_FIELD(
813 adev->gfx.config.gb_addr_config,
814 GB_ADDR_CONFIG,
815 NUM_SHADER_ENGINES);
816 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
817 REG_GET_FIELD(
818 adev->gfx.config.gb_addr_config,
819 GB_ADDR_CONFIG,
820 PIPE_INTERLEAVE_SIZE));
821 }
822
823 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
824 struct amdgpu_ngg_buf *ngg_buf,
825 int size_se,
826 int default_size_se)
827 {
828 int r;
829
830 if (size_se < 0) {
831 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
832 return -EINVAL;
833 }
834 size_se = size_se ? size_se : default_size_se;
835
836 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
837 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
838 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
839 &ngg_buf->bo,
840 &ngg_buf->gpu_addr,
841 NULL);
842 if (r) {
843 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
844 return r;
845 }
846 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
847
848 return r;
849 }
850
851 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
852 {
853 int i;
854
855 for (i = 0; i < NGG_BUF_MAX; i++)
856 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
857 &adev->gfx.ngg.buf[i].gpu_addr,
858 NULL);
859
860 memset(&adev->gfx.ngg.buf[0], 0,
861 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
862
863 adev->gfx.ngg.init = false;
864
865 return 0;
866 }
867
868 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
869 {
870 int r;
871
872 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
873 return 0;
874
875 /* GDS reserve memory: 64 bytes alignment */
876 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
877 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
878 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
879 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
880 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
881
882 /* Primitive Buffer */
883 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
884 amdgpu_prim_buf_per_se,
885 64 * 1024);
886 if (r) {
887 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
888 goto err;
889 }
890
891 /* Position Buffer */
892 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
893 amdgpu_pos_buf_per_se,
894 256 * 1024);
895 if (r) {
896 dev_err(adev->dev, "Failed to create Position Buffer\n");
897 goto err;
898 }
899
900 /* Control Sideband */
901 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
902 amdgpu_cntl_sb_buf_per_se,
903 256);
904 if (r) {
905 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
906 goto err;
907 }
908
909 /* Parameter Cache, not created by default */
910 if (amdgpu_param_buf_per_se <= 0)
911 goto out;
912
913 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
914 amdgpu_param_buf_per_se,
915 512 * 1024);
916 if (r) {
917 dev_err(adev->dev, "Failed to create Parameter Cache\n");
918 goto err;
919 }
920
921 out:
922 adev->gfx.ngg.init = true;
923 return 0;
924 err:
925 gfx_v9_0_ngg_fini(adev);
926 return r;
927 }
928
929 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
930 {
931 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
932 int r;
933 u32 data;
934 u32 size;
935 u32 base;
936
937 if (!amdgpu_ngg)
938 return 0;
939
940 /* Program buffer size */
941 data = 0;
942 size = adev->gfx.ngg.buf[NGG_PRIM].size / 256;
943 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
944
945 size = adev->gfx.ngg.buf[NGG_POS].size / 256;
946 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
947
948 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
949
950 data = 0;
951 size = adev->gfx.ngg.buf[NGG_CNTL].size / 256;
952 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
953
954 size = adev->gfx.ngg.buf[NGG_PARAM].size / 1024;
955 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
956
957 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
958
959 /* Program buffer base address */
960 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
961 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
962 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
963
964 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
965 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
966 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
967
968 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
969 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
970 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
971
972 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
973 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
974 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
975
976 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
977 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
978 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
979
980 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
981 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
982 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
983
984 /* Clear GDS reserved memory */
985 r = amdgpu_ring_alloc(ring, 17);
986 if (r) {
987 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
988 ring->idx, r);
989 return r;
990 }
991
992 gfx_v9_0_write_data_to_reg(ring, 0, false,
993 amdgpu_gds_reg_offset[0].mem_size,
994 (adev->gds.mem.total_size +
995 adev->gfx.ngg.gds_reserve_size) >>
996 AMDGPU_GDS_SHIFT);
997
998 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
999 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1000 PACKET3_DMA_DATA_SRC_SEL(2)));
1001 amdgpu_ring_write(ring, 0);
1002 amdgpu_ring_write(ring, 0);
1003 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1004 amdgpu_ring_write(ring, 0);
1005 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
1006
1007
1008 gfx_v9_0_write_data_to_reg(ring, 0, false,
1009 amdgpu_gds_reg_offset[0].mem_size, 0);
1010
1011 amdgpu_ring_commit(ring);
1012
1013 return 0;
1014 }
1015
1016 static int gfx_v9_0_sw_init(void *handle)
1017 {
1018 int i, r;
1019 struct amdgpu_ring *ring;
1020 struct amdgpu_kiq *kiq;
1021 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1022
1023 /* KIQ event */
1024 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1025 if (r)
1026 return r;
1027
1028 /* EOP Event */
1029 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1030 if (r)
1031 return r;
1032
1033 /* Privileged reg */
1034 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
1035 &adev->gfx.priv_reg_irq);
1036 if (r)
1037 return r;
1038
1039 /* Privileged inst */
1040 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
1041 &adev->gfx.priv_inst_irq);
1042 if (r)
1043 return r;
1044
1045 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1046
1047 gfx_v9_0_scratch_init(adev);
1048
1049 r = gfx_v9_0_init_microcode(adev);
1050 if (r) {
1051 DRM_ERROR("Failed to load gfx firmware!\n");
1052 return r;
1053 }
1054
1055 r = gfx_v9_0_mec_init(adev);
1056 if (r) {
1057 DRM_ERROR("Failed to init MEC BOs!\n");
1058 return r;
1059 }
1060
1061 /* set up the gfx ring */
1062 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1063 ring = &adev->gfx.gfx_ring[i];
1064 ring->ring_obj = NULL;
1065 sprintf(ring->name, "gfx");
1066 ring->use_doorbell = true;
1067 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1068 r = amdgpu_ring_init(adev, ring, 1024,
1069 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1070 if (r)
1071 return r;
1072 }
1073
1074 /* set up the compute queues */
1075 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1076 unsigned irq_type;
1077
1078 /* max 32 queues per MEC */
1079 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
1080 DRM_ERROR("Too many (%d) compute rings!\n", i);
1081 break;
1082 }
1083 ring = &adev->gfx.compute_ring[i];
1084 ring->ring_obj = NULL;
1085 ring->use_doorbell = true;
1086 ring->doorbell_index = (AMDGPU_DOORBELL64_MEC_RING0 + i) << 1;
1087 ring->me = 1; /* first MEC */
1088 ring->pipe = i / 8;
1089 ring->queue = i % 8;
1090 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
1091 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1092 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
1093 /* type-2 packets are deprecated on MEC, use type-3 instead */
1094 r = amdgpu_ring_init(adev, ring, 1024,
1095 &adev->gfx.eop_irq, irq_type);
1096 if (r)
1097 return r;
1098 }
1099
1100 if (amdgpu_sriov_vf(adev)) {
1101 r = gfx_v9_0_kiq_init(adev);
1102 if (r) {
1103 DRM_ERROR("Failed to init KIQ BOs!\n");
1104 return r;
1105 }
1106
1107 kiq = &adev->gfx.kiq;
1108 r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1109 if (r)
1110 return r;
1111
1112 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
1113 r = gfx_v9_0_compute_mqd_sw_init(adev);
1114 if (r)
1115 return r;
1116 }
1117
1118 /* reserve GDS, GWS and OA resource for gfx */
1119 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1120 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1121 &adev->gds.gds_gfx_bo, NULL, NULL);
1122 if (r)
1123 return r;
1124
1125 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1126 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1127 &adev->gds.gws_gfx_bo, NULL, NULL);
1128 if (r)
1129 return r;
1130
1131 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1132 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1133 &adev->gds.oa_gfx_bo, NULL, NULL);
1134 if (r)
1135 return r;
1136
1137 adev->gfx.ce_ram_size = 0x8000;
1138
1139 gfx_v9_0_gpu_early_init(adev);
1140
1141 r = gfx_v9_0_ngg_init(adev);
1142 if (r)
1143 return r;
1144
1145 return 0;
1146 }
1147
1148
1149 static int gfx_v9_0_sw_fini(void *handle)
1150 {
1151 int i;
1152 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1153
1154 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1155 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1156 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1157
1158 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1159 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1160 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1161 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1162
1163 if (amdgpu_sriov_vf(adev)) {
1164 gfx_v9_0_compute_mqd_sw_fini(adev);
1165 gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1166 gfx_v9_0_kiq_fini(adev);
1167 }
1168
1169 gfx_v9_0_mec_fini(adev);
1170 gfx_v9_0_ngg_fini(adev);
1171
1172 return 0;
1173 }
1174
1175
1176 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1177 {
1178 /* TODO */
1179 }
1180
1181 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1182 {
1183 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1184
1185 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1186 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1187 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1188 } else if (se_num == 0xffffffff) {
1189 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1190 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1191 } else if (sh_num == 0xffffffff) {
1192 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1193 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1194 } else {
1195 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1196 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1197 }
1198 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1199 }
1200
1201 static u32 gfx_v9_0_create_bitmask(u32 bit_width)
1202 {
1203 return (u32)((1ULL << bit_width) - 1);
1204 }
1205
1206 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1207 {
1208 u32 data, mask;
1209
1210 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1211 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1212
1213 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1214 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1215
1216 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1217 adev->gfx.config.max_sh_per_se);
1218
1219 return (~data) & mask;
1220 }
1221
1222 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1223 {
1224 int i, j;
1225 u32 data;
1226 u32 active_rbs = 0;
1227 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1228 adev->gfx.config.max_sh_per_se;
1229
1230 mutex_lock(&adev->grbm_idx_mutex);
1231 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1232 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1233 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1234 data = gfx_v9_0_get_rb_active_bitmap(adev);
1235 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1236 rb_bitmap_width_per_sh);
1237 }
1238 }
1239 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1240 mutex_unlock(&adev->grbm_idx_mutex);
1241
1242 adev->gfx.config.backend_enable_mask = active_rbs;
1243 adev->gfx.config.num_rbs = hweight32(active_rbs);
1244 }
1245
1246 #define DEFAULT_SH_MEM_BASES (0x6000)
1247 #define FIRST_COMPUTE_VMID (8)
1248 #define LAST_COMPUTE_VMID (16)
1249 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1250 {
1251 int i;
1252 uint32_t sh_mem_config;
1253 uint32_t sh_mem_bases;
1254
1255 /*
1256 * Configure apertures:
1257 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1258 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1259 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1260 */
1261 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1262
1263 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1264 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1265 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1266
1267 mutex_lock(&adev->srbm_mutex);
1268 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1269 soc15_grbm_select(adev, 0, 0, 0, i);
1270 /* CP and shaders */
1271 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1272 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1273 }
1274 soc15_grbm_select(adev, 0, 0, 0, 0);
1275 mutex_unlock(&adev->srbm_mutex);
1276 }
1277
1278 static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1279 {
1280 u32 tmp;
1281 int i;
1282
1283 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1284
1285 gfx_v9_0_tiling_mode_table_init(adev);
1286
1287 gfx_v9_0_setup_rb(adev);
1288 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1289
1290 /* XXX SH_MEM regs */
1291 /* where to put LDS, scratch, GPUVM in FSA64 space */
1292 mutex_lock(&adev->srbm_mutex);
1293 for (i = 0; i < 16; i++) {
1294 soc15_grbm_select(adev, 0, 0, 0, i);
1295 /* CP and shaders */
1296 tmp = 0;
1297 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1298 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1299 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1300 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
1301 }
1302 soc15_grbm_select(adev, 0, 0, 0, 0);
1303
1304 mutex_unlock(&adev->srbm_mutex);
1305
1306 gfx_v9_0_init_compute_vmid(adev);
1307
1308 mutex_lock(&adev->grbm_idx_mutex);
1309 /*
1310 * making sure that the following register writes will be broadcasted
1311 * to all the shaders
1312 */
1313 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1314
1315 WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
1316 (adev->gfx.config.sc_prim_fifo_size_frontend <<
1317 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1318 (adev->gfx.config.sc_prim_fifo_size_backend <<
1319 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1320 (adev->gfx.config.sc_hiz_tile_fifo_size <<
1321 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1322 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1323 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1324 mutex_unlock(&adev->grbm_idx_mutex);
1325
1326 }
1327
1328 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1329 {
1330 u32 i, j, k;
1331 u32 mask;
1332
1333 mutex_lock(&adev->grbm_idx_mutex);
1334 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1335 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1336 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1337 for (k = 0; k < adev->usec_timeout; k++) {
1338 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
1339 break;
1340 udelay(1);
1341 }
1342 }
1343 }
1344 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1345 mutex_unlock(&adev->grbm_idx_mutex);
1346
1347 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1348 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1349 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1350 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1351 for (k = 0; k < adev->usec_timeout; k++) {
1352 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
1353 break;
1354 udelay(1);
1355 }
1356 }
1357
1358 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1359 bool enable)
1360 {
1361 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1362
1363 if (enable)
1364 return;
1365
1366 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1367 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1368 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1369 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1370
1371 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1372 }
1373
1374 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
1375 {
1376 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
1377
1378 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1379 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
1380
1381 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
1382
1383 gfx_v9_0_wait_for_rlc_serdes(adev);
1384 }
1385
1386 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
1387 {
1388 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1389 udelay(50);
1390 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1391 udelay(50);
1392 }
1393
1394 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
1395 {
1396 #ifdef AMDGPU_RLC_DEBUG_RETRY
1397 u32 rlc_ucode_ver;
1398 #endif
1399
1400 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1401
1402 /* carrizo do enable cp interrupt after cp inited */
1403 if (!(adev->flags & AMD_IS_APU))
1404 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
1405
1406 udelay(50);
1407
1408 #ifdef AMDGPU_RLC_DEBUG_RETRY
1409 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
1410 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
1411 if(rlc_ucode_ver == 0x108) {
1412 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
1413 rlc_ucode_ver, adev->gfx.rlc_fw_version);
1414 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
1415 * default is 0x9C4 to create a 100us interval */
1416 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
1417 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
1418 * to disable the page fault retry interrupts, default is
1419 * 0x100 (256) */
1420 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
1421 }
1422 #endif
1423 }
1424
1425 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
1426 {
1427 const struct rlc_firmware_header_v2_0 *hdr;
1428 const __le32 *fw_data;
1429 unsigned i, fw_size;
1430
1431 if (!adev->gfx.rlc_fw)
1432 return -EINVAL;
1433
1434 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1435 amdgpu_ucode_print_rlc_hdr(&hdr->header);
1436
1437 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1438 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1439 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1440
1441 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
1442 RLCG_UCODE_LOADING_START_ADDRESS);
1443 for (i = 0; i < fw_size; i++)
1444 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
1445 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1446
1447 return 0;
1448 }
1449
1450 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
1451 {
1452 int r;
1453
1454 if (amdgpu_sriov_vf(adev))
1455 return 0;
1456
1457 gfx_v9_0_rlc_stop(adev);
1458
1459 /* disable CG */
1460 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
1461
1462 /* disable PG */
1463 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
1464
1465 gfx_v9_0_rlc_reset(adev);
1466
1467 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1468 /* legacy rlc firmware loading */
1469 r = gfx_v9_0_rlc_load_microcode(adev);
1470 if (r)
1471 return r;
1472 }
1473
1474 gfx_v9_0_rlc_start(adev);
1475
1476 return 0;
1477 }
1478
1479 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1480 {
1481 int i;
1482 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
1483
1484 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
1485 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
1486 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
1487 if (!enable) {
1488 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1489 adev->gfx.gfx_ring[i].ready = false;
1490 }
1491 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
1492 udelay(50);
1493 }
1494
1495 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1496 {
1497 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1498 const struct gfx_firmware_header_v1_0 *ce_hdr;
1499 const struct gfx_firmware_header_v1_0 *me_hdr;
1500 const __le32 *fw_data;
1501 unsigned i, fw_size;
1502
1503 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1504 return -EINVAL;
1505
1506 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
1507 adev->gfx.pfp_fw->data;
1508 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
1509 adev->gfx.ce_fw->data;
1510 me_hdr = (const struct gfx_firmware_header_v1_0 *)
1511 adev->gfx.me_fw->data;
1512
1513 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1514 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1515 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1516
1517 gfx_v9_0_cp_gfx_enable(adev, false);
1518
1519 /* PFP */
1520 fw_data = (const __le32 *)
1521 (adev->gfx.pfp_fw->data +
1522 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1523 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1524 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
1525 for (i = 0; i < fw_size; i++)
1526 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1527 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
1528
1529 /* CE */
1530 fw_data = (const __le32 *)
1531 (adev->gfx.ce_fw->data +
1532 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1533 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1534 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
1535 for (i = 0; i < fw_size; i++)
1536 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1537 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
1538
1539 /* ME */
1540 fw_data = (const __le32 *)
1541 (adev->gfx.me_fw->data +
1542 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1543 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1544 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
1545 for (i = 0; i < fw_size; i++)
1546 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
1547 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
1548
1549 return 0;
1550 }
1551
1552 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
1553 {
1554 u32 count = 0;
1555 const struct cs_section_def *sect = NULL;
1556 const struct cs_extent_def *ext = NULL;
1557
1558 /* begin clear state */
1559 count += 2;
1560 /* context control state */
1561 count += 3;
1562
1563 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
1564 for (ext = sect->section; ext->extent != NULL; ++ext) {
1565 if (sect->id == SECT_CONTEXT)
1566 count += 2 + ext->reg_count;
1567 else
1568 return 0;
1569 }
1570 }
1571 /* pa_sc_raster_config/pa_sc_raster_config1 */
1572 count += 4;
1573 /* end clear state */
1574 count += 2;
1575 /* clear state */
1576 count += 2;
1577
1578 return count;
1579 }
1580
1581 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
1582 {
1583 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1584 const struct cs_section_def *sect = NULL;
1585 const struct cs_extent_def *ext = NULL;
1586 int r, i;
1587
1588 /* init the CP */
1589 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
1590 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
1591
1592 gfx_v9_0_cp_gfx_enable(adev, true);
1593
1594 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);
1595 if (r) {
1596 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1597 return r;
1598 }
1599
1600 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1601 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1602
1603 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1604 amdgpu_ring_write(ring, 0x80000000);
1605 amdgpu_ring_write(ring, 0x80000000);
1606
1607 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
1608 for (ext = sect->section; ext->extent != NULL; ++ext) {
1609 if (sect->id == SECT_CONTEXT) {
1610 amdgpu_ring_write(ring,
1611 PACKET3(PACKET3_SET_CONTEXT_REG,
1612 ext->reg_count));
1613 amdgpu_ring_write(ring,
1614 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
1615 for (i = 0; i < ext->reg_count; i++)
1616 amdgpu_ring_write(ring, ext->extent[i]);
1617 }
1618 }
1619 }
1620
1621 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1622 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1623
1624 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1625 amdgpu_ring_write(ring, 0);
1626
1627 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1628 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1629 amdgpu_ring_write(ring, 0x8000);
1630 amdgpu_ring_write(ring, 0x8000);
1631
1632 amdgpu_ring_commit(ring);
1633
1634 return 0;
1635 }
1636
1637 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
1638 {
1639 struct amdgpu_ring *ring;
1640 u32 tmp;
1641 u32 rb_bufsz;
1642 u64 rb_addr, rptr_addr, wptr_gpu_addr;
1643
1644 /* Set the write pointer delay */
1645 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
1646
1647 /* set the RB to use vmid 0 */
1648 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
1649
1650 /* Set ring buffer size */
1651 ring = &adev->gfx.gfx_ring[0];
1652 rb_bufsz = order_base_2(ring->ring_size / 8);
1653 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
1654 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
1655 #ifdef __BIG_ENDIAN
1656 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
1657 #endif
1658 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
1659
1660 /* Initialize the ring buffer's write pointers */
1661 ring->wptr = 0;
1662 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
1663 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
1664
1665 /* set the wb address wether it's enabled or not */
1666 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1667 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
1668 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
1669
1670 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1671 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
1672 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
1673
1674 mdelay(1);
1675 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
1676
1677 rb_addr = ring->gpu_addr >> 8;
1678 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
1679 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
1680
1681 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
1682 if (ring->use_doorbell) {
1683 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
1684 DOORBELL_OFFSET, ring->doorbell_index);
1685 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
1686 DOORBELL_EN, 1);
1687 } else {
1688 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
1689 }
1690 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
1691
1692 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
1693 DOORBELL_RANGE_LOWER, ring->doorbell_index);
1694 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
1695
1696 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
1697 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
1698
1699
1700 /* start the ring */
1701 gfx_v9_0_cp_gfx_start(adev);
1702 ring->ready = true;
1703
1704 return 0;
1705 }
1706
1707 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
1708 {
1709 int i;
1710
1711 if (enable) {
1712 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
1713 } else {
1714 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
1715 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
1716 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1717 adev->gfx.compute_ring[i].ready = false;
1718 adev->gfx.kiq.ring.ready = false;
1719 }
1720 udelay(50);
1721 }
1722
1723 static int gfx_v9_0_cp_compute_start(struct amdgpu_device *adev)
1724 {
1725 gfx_v9_0_cp_compute_enable(adev, true);
1726
1727 return 0;
1728 }
1729
1730 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
1731 {
1732 const struct gfx_firmware_header_v1_0 *mec_hdr;
1733 const __le32 *fw_data;
1734 unsigned i;
1735 u32 tmp;
1736
1737 if (!adev->gfx.mec_fw)
1738 return -EINVAL;
1739
1740 gfx_v9_0_cp_compute_enable(adev, false);
1741
1742 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1743 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
1744
1745 fw_data = (const __le32 *)
1746 (adev->gfx.mec_fw->data +
1747 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1748 tmp = 0;
1749 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
1750 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
1751 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
1752
1753 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
1754 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
1755 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
1756 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
1757
1758 /* MEC1 */
1759 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
1760 mec_hdr->jt_offset);
1761 for (i = 0; i < mec_hdr->jt_size; i++)
1762 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
1763 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
1764
1765 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
1766 adev->gfx.mec_fw_version);
1767 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
1768
1769 return 0;
1770 }
1771
1772 static void gfx_v9_0_cp_compute_fini(struct amdgpu_device *adev)
1773 {
1774 int i, r;
1775
1776 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1777 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
1778
1779 if (ring->mqd_obj) {
1780 r = amdgpu_bo_reserve(ring->mqd_obj, true);
1781 if (unlikely(r != 0))
1782 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
1783
1784 amdgpu_bo_unpin(ring->mqd_obj);
1785 amdgpu_bo_unreserve(ring->mqd_obj);
1786
1787 amdgpu_bo_unref(&ring->mqd_obj);
1788 ring->mqd_obj = NULL;
1789 }
1790 }
1791 }
1792
1793 static int gfx_v9_0_init_queue(struct amdgpu_ring *ring);
1794
1795 static int gfx_v9_0_cp_compute_resume(struct amdgpu_device *adev)
1796 {
1797 int i, r;
1798 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1799 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
1800 if (gfx_v9_0_init_queue(ring))
1801 dev_warn(adev->dev, "compute queue %d init failed!\n", i);
1802 }
1803
1804 r = gfx_v9_0_cp_compute_start(adev);
1805 if (r)
1806 return r;
1807
1808 return 0;
1809 }
1810
1811 /* KIQ functions */
1812 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
1813 {
1814 uint32_t tmp;
1815 struct amdgpu_device *adev = ring->adev;
1816
1817 /* tell RLC which is KIQ queue */
1818 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
1819 tmp &= 0xffffff00;
1820 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1821 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
1822 tmp |= 0x80;
1823 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
1824 }
1825
1826 static void gfx_v9_0_kiq_enable(struct amdgpu_ring *ring)
1827 {
1828 amdgpu_ring_alloc(ring, 8);
1829 /* set resources */
1830 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_RESOURCES, 6));
1831 amdgpu_ring_write(ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */
1832 amdgpu_ring_write(ring, 0x000000FF); /* queue mask lo */
1833 amdgpu_ring_write(ring, 0); /* queue mask hi */
1834 amdgpu_ring_write(ring, 0); /* gws mask lo */
1835 amdgpu_ring_write(ring, 0); /* gws mask hi */
1836 amdgpu_ring_write(ring, 0); /* oac mask */
1837 amdgpu_ring_write(ring, 0); /* gds heap base:0, gds heap size:0 */
1838 amdgpu_ring_commit(ring);
1839 udelay(50);
1840 }
1841
1842 static void gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring,
1843 struct amdgpu_ring *ring)
1844 {
1845 struct amdgpu_device *adev = kiq_ring->adev;
1846 uint64_t mqd_addr, wptr_addr;
1847
1848 mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
1849 wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1850 amdgpu_ring_alloc(kiq_ring, 8);
1851
1852 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
1853 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
1854 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
1855 (0 << 4) | /* Queue_Sel */
1856 (0 << 8) | /* VMID */
1857 (ring->queue << 13 ) |
1858 (ring->pipe << 16) |
1859 ((ring->me == 1 ? 0 : 1) << 18) |
1860 (0 << 21) | /*queue_type: normal compute queue */
1861 (1 << 24) | /* alloc format: all_on_one_pipe */
1862 (0 << 26) | /* engine_sel: compute */
1863 (1 << 29)); /* num_queues: must be 1 */
1864 amdgpu_ring_write(kiq_ring, (ring->doorbell_index << 2));
1865 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
1866 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
1867 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
1868 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
1869 amdgpu_ring_commit(kiq_ring);
1870 udelay(50);
1871 }
1872
1873 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
1874 {
1875 struct amdgpu_device *adev = ring->adev;
1876 struct v9_mqd *mqd = ring->mqd_ptr;
1877 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
1878 uint32_t tmp;
1879
1880 mqd->header = 0xC0310800;
1881 mqd->compute_pipelinestat_enable = 0x00000001;
1882 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
1883 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
1884 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
1885 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
1886 mqd->compute_misc_reserved = 0x00000003;
1887
1888 eop_base_addr = ring->eop_gpu_addr >> 8;
1889 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
1890 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
1891
1892 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1893 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
1894 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
1895 (order_base_2(MEC_HPD_SIZE / 4) - 1));
1896
1897 mqd->cp_hqd_eop_control = tmp;
1898
1899 /* enable doorbell? */
1900 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
1901
1902 if (ring->use_doorbell) {
1903 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1904 DOORBELL_OFFSET, ring->doorbell_index);
1905 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1906 DOORBELL_EN, 1);
1907 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1908 DOORBELL_SOURCE, 0);
1909 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1910 DOORBELL_HIT, 0);
1911 }
1912 else
1913 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1914 DOORBELL_EN, 0);
1915
1916 mqd->cp_hqd_pq_doorbell_control = tmp;
1917
1918 /* disable the queue if it's active */
1919 ring->wptr = 0;
1920 mqd->cp_hqd_dequeue_request = 0;
1921 mqd->cp_hqd_pq_rptr = 0;
1922 mqd->cp_hqd_pq_wptr_lo = 0;
1923 mqd->cp_hqd_pq_wptr_hi = 0;
1924
1925 /* set the pointer to the MQD */
1926 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
1927 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
1928
1929 /* set MQD vmid to 0 */
1930 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
1931 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
1932 mqd->cp_mqd_control = tmp;
1933
1934 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1935 hqd_gpu_addr = ring->gpu_addr >> 8;
1936 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
1937 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
1938
1939 /* set up the HQD, this is similar to CP_RB0_CNTL */
1940 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
1941 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
1942 (order_base_2(ring->ring_size / 4) - 1));
1943 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
1944 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
1945 #ifdef __BIG_ENDIAN
1946 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
1947 #endif
1948 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
1949 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
1950 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
1951 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
1952 mqd->cp_hqd_pq_control = tmp;
1953
1954 /* set the wb address whether it's enabled or not */
1955 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1956 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
1957 mqd->cp_hqd_pq_rptr_report_addr_hi =
1958 upper_32_bits(wb_gpu_addr) & 0xffff;
1959
1960 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1961 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1962 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
1963 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
1964
1965 tmp = 0;
1966 /* enable the doorbell if requested */
1967 if (ring->use_doorbell) {
1968 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
1969 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1970 DOORBELL_OFFSET, ring->doorbell_index);
1971
1972 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1973 DOORBELL_EN, 1);
1974 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1975 DOORBELL_SOURCE, 0);
1976 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1977 DOORBELL_HIT, 0);
1978 }
1979
1980 mqd->cp_hqd_pq_doorbell_control = tmp;
1981
1982 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
1983 ring->wptr = 0;
1984 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
1985
1986 /* set the vmid for the queue */
1987 mqd->cp_hqd_vmid = 0;
1988
1989 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
1990 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
1991 mqd->cp_hqd_persistent_state = tmp;
1992
1993 /* set MIN_IB_AVAIL_SIZE */
1994 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
1995 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
1996 mqd->cp_hqd_ib_control = tmp;
1997
1998 /* activate the queue */
1999 mqd->cp_hqd_active = 1;
2000
2001 return 0;
2002 }
2003
2004 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
2005 {
2006 struct amdgpu_device *adev = ring->adev;
2007 struct v9_mqd *mqd = ring->mqd_ptr;
2008 int j;
2009
2010 /* disable wptr polling */
2011 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2012
2013 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
2014 mqd->cp_hqd_eop_base_addr_lo);
2015 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
2016 mqd->cp_hqd_eop_base_addr_hi);
2017
2018 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2019 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
2020 mqd->cp_hqd_eop_control);
2021
2022 /* enable doorbell? */
2023 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2024 mqd->cp_hqd_pq_doorbell_control);
2025
2026 /* disable the queue if it's active */
2027 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2028 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
2029 for (j = 0; j < adev->usec_timeout; j++) {
2030 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
2031 break;
2032 udelay(1);
2033 }
2034 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
2035 mqd->cp_hqd_dequeue_request);
2036 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
2037 mqd->cp_hqd_pq_rptr);
2038 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2039 mqd->cp_hqd_pq_wptr_lo);
2040 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2041 mqd->cp_hqd_pq_wptr_hi);
2042 }
2043
2044 /* set the pointer to the MQD */
2045 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
2046 mqd->cp_mqd_base_addr_lo);
2047 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
2048 mqd->cp_mqd_base_addr_hi);
2049
2050 /* set MQD vmid to 0 */
2051 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
2052 mqd->cp_mqd_control);
2053
2054 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2055 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
2056 mqd->cp_hqd_pq_base_lo);
2057 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
2058 mqd->cp_hqd_pq_base_hi);
2059
2060 /* set up the HQD, this is similar to CP_RB0_CNTL */
2061 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
2062 mqd->cp_hqd_pq_control);
2063
2064 /* set the wb address whether it's enabled or not */
2065 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2066 mqd->cp_hqd_pq_rptr_report_addr_lo);
2067 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2068 mqd->cp_hqd_pq_rptr_report_addr_hi);
2069
2070 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2071 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
2072 mqd->cp_hqd_pq_wptr_poll_addr_lo);
2073 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2074 mqd->cp_hqd_pq_wptr_poll_addr_hi);
2075
2076 /* enable the doorbell if requested */
2077 if (ring->use_doorbell) {
2078 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
2079 (AMDGPU_DOORBELL64_KIQ *2) << 2);
2080 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
2081 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2082 }
2083
2084 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2085 mqd->cp_hqd_pq_doorbell_control);
2086
2087 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2088 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2089 mqd->cp_hqd_pq_wptr_lo);
2090 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2091 mqd->cp_hqd_pq_wptr_hi);
2092
2093 /* set the vmid for the queue */
2094 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
2095
2096 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
2097 mqd->cp_hqd_persistent_state);
2098
2099 /* activate the queue */
2100 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
2101 mqd->cp_hqd_active);
2102
2103 if (ring->use_doorbell)
2104 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
2105
2106 return 0;
2107 }
2108
2109 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
2110 {
2111 struct amdgpu_device *adev = ring->adev;
2112 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
2113 struct v9_mqd *mqd = ring->mqd_ptr;
2114 bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ);
2115 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2116
2117 if (is_kiq) {
2118 gfx_v9_0_kiq_setting(&kiq->ring);
2119 } else {
2120 mqd_idx = ring - &adev->gfx.compute_ring[0];
2121 }
2122
2123 if (!adev->gfx.in_reset) {
2124 memset((void *)mqd, 0, sizeof(*mqd));
2125 mutex_lock(&adev->srbm_mutex);
2126 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2127 gfx_v9_0_mqd_init(ring);
2128 if (is_kiq)
2129 gfx_v9_0_kiq_init_register(ring);
2130 soc15_grbm_select(adev, 0, 0, 0, 0);
2131 mutex_unlock(&adev->srbm_mutex);
2132
2133 } else { /* for GPU_RESET case */
2134 /* reset MQD to a clean status */
2135
2136 /* reset ring buffer */
2137 ring->wptr = 0;
2138
2139 if (is_kiq) {
2140 mutex_lock(&adev->srbm_mutex);
2141 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2142 gfx_v9_0_kiq_init_register(ring);
2143 soc15_grbm_select(adev, 0, 0, 0, 0);
2144 mutex_unlock(&adev->srbm_mutex);
2145 }
2146 }
2147
2148 if (is_kiq)
2149 gfx_v9_0_kiq_enable(ring);
2150 else
2151 gfx_v9_0_map_queue_enable(&kiq->ring, ring);
2152
2153 return 0;
2154 }
2155
2156 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
2157 {
2158 struct amdgpu_ring *ring = NULL;
2159 int r = 0, i;
2160
2161 gfx_v9_0_cp_compute_enable(adev, true);
2162
2163 ring = &adev->gfx.kiq.ring;
2164
2165 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2166 if (unlikely(r != 0))
2167 goto done;
2168
2169 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2170 if (!r) {
2171 r = gfx_v9_0_kiq_init_queue(ring);
2172 amdgpu_bo_kunmap(ring->mqd_obj);
2173 ring->mqd_ptr = NULL;
2174 }
2175 amdgpu_bo_unreserve(ring->mqd_obj);
2176 if (r)
2177 goto done;
2178
2179 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2180 ring = &adev->gfx.compute_ring[i];
2181
2182 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2183 if (unlikely(r != 0))
2184 goto done;
2185 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2186 if (!r) {
2187 r = gfx_v9_0_kiq_init_queue(ring);
2188 amdgpu_bo_kunmap(ring->mqd_obj);
2189 ring->mqd_ptr = NULL;
2190 }
2191 amdgpu_bo_unreserve(ring->mqd_obj);
2192 if (r)
2193 goto done;
2194 }
2195
2196 done:
2197 return r;
2198 }
2199
2200 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
2201 {
2202 int r,i;
2203 struct amdgpu_ring *ring;
2204
2205 if (!(adev->flags & AMD_IS_APU))
2206 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2207
2208 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2209 /* legacy firmware loading */
2210 r = gfx_v9_0_cp_gfx_load_microcode(adev);
2211 if (r)
2212 return r;
2213
2214 r = gfx_v9_0_cp_compute_load_microcode(adev);
2215 if (r)
2216 return r;
2217 }
2218
2219 r = gfx_v9_0_cp_gfx_resume(adev);
2220 if (r)
2221 return r;
2222
2223 if (amdgpu_sriov_vf(adev))
2224 r = gfx_v9_0_kiq_resume(adev);
2225 else
2226 r = gfx_v9_0_cp_compute_resume(adev);
2227 if (r)
2228 return r;
2229
2230 ring = &adev->gfx.gfx_ring[0];
2231 r = amdgpu_ring_test_ring(ring);
2232 if (r) {
2233 ring->ready = false;
2234 return r;
2235 }
2236 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2237 ring = &adev->gfx.compute_ring[i];
2238
2239 ring->ready = true;
2240 r = amdgpu_ring_test_ring(ring);
2241 if (r)
2242 ring->ready = false;
2243 }
2244
2245 if (amdgpu_sriov_vf(adev)) {
2246 ring = &adev->gfx.kiq.ring;
2247 ring->ready = true;
2248 r = amdgpu_ring_test_ring(ring);
2249 if (r)
2250 ring->ready = false;
2251 }
2252
2253 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2254
2255 return 0;
2256 }
2257
2258 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
2259 {
2260 gfx_v9_0_cp_gfx_enable(adev, enable);
2261 gfx_v9_0_cp_compute_enable(adev, enable);
2262 }
2263
2264 static int gfx_v9_0_hw_init(void *handle)
2265 {
2266 int r;
2267 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2268
2269 gfx_v9_0_init_golden_registers(adev);
2270
2271 gfx_v9_0_gpu_init(adev);
2272
2273 r = gfx_v9_0_rlc_resume(adev);
2274 if (r)
2275 return r;
2276
2277 r = gfx_v9_0_cp_resume(adev);
2278 if (r)
2279 return r;
2280
2281 r = gfx_v9_0_ngg_en(adev);
2282 if (r)
2283 return r;
2284
2285 return r;
2286 }
2287
2288 static int gfx_v9_0_hw_fini(void *handle)
2289 {
2290 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2291
2292 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2293 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
2294 if (amdgpu_sriov_vf(adev)) {
2295 pr_debug("For SRIOV client, shouldn't do anything.\n");
2296 return 0;
2297 }
2298 gfx_v9_0_cp_enable(adev, false);
2299 gfx_v9_0_rlc_stop(adev);
2300 gfx_v9_0_cp_compute_fini(adev);
2301
2302 return 0;
2303 }
2304
2305 static int gfx_v9_0_suspend(void *handle)
2306 {
2307 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2308
2309 return gfx_v9_0_hw_fini(adev);
2310 }
2311
2312 static int gfx_v9_0_resume(void *handle)
2313 {
2314 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2315
2316 return gfx_v9_0_hw_init(adev);
2317 }
2318
2319 static bool gfx_v9_0_is_idle(void *handle)
2320 {
2321 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2322
2323 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
2324 GRBM_STATUS, GUI_ACTIVE))
2325 return false;
2326 else
2327 return true;
2328 }
2329
2330 static int gfx_v9_0_wait_for_idle(void *handle)
2331 {
2332 unsigned i;
2333 u32 tmp;
2334 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2335
2336 for (i = 0; i < adev->usec_timeout; i++) {
2337 /* read MC_STATUS */
2338 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
2339 GRBM_STATUS__GUI_ACTIVE_MASK;
2340
2341 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
2342 return 0;
2343 udelay(1);
2344 }
2345 return -ETIMEDOUT;
2346 }
2347
2348 static int gfx_v9_0_soft_reset(void *handle)
2349 {
2350 u32 grbm_soft_reset = 0;
2351 u32 tmp;
2352 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2353
2354 /* GRBM_STATUS */
2355 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
2356 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
2357 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
2358 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
2359 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
2360 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
2361 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
2362 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2363 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2364 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2365 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
2366 }
2367
2368 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
2369 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2370 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2371 }
2372
2373 /* GRBM_STATUS2 */
2374 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
2375 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
2376 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2377 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2378
2379
2380 if (grbm_soft_reset) {
2381 /* stop the rlc */
2382 gfx_v9_0_rlc_stop(adev);
2383
2384 /* Disable GFX parsing/prefetching */
2385 gfx_v9_0_cp_gfx_enable(adev, false);
2386
2387 /* Disable MEC parsing/prefetching */
2388 gfx_v9_0_cp_compute_enable(adev, false);
2389
2390 if (grbm_soft_reset) {
2391 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
2392 tmp |= grbm_soft_reset;
2393 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2394 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
2395 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
2396
2397 udelay(50);
2398
2399 tmp &= ~grbm_soft_reset;
2400 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
2401 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
2402 }
2403
2404 /* Wait a little for things to settle down */
2405 udelay(50);
2406 }
2407 return 0;
2408 }
2409
2410 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2411 {
2412 uint64_t clock;
2413
2414 mutex_lock(&adev->gfx.gpu_clock_mutex);
2415 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2416 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
2417 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2418 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2419 return clock;
2420 }
2421
2422 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
2423 uint32_t vmid,
2424 uint32_t gds_base, uint32_t gds_size,
2425 uint32_t gws_base, uint32_t gws_size,
2426 uint32_t oa_base, uint32_t oa_size)
2427 {
2428 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
2429 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
2430
2431 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
2432 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
2433
2434 oa_base = oa_base >> AMDGPU_OA_SHIFT;
2435 oa_size = oa_size >> AMDGPU_OA_SHIFT;
2436
2437 /* GDS Base */
2438 gfx_v9_0_write_data_to_reg(ring, 0, false,
2439 amdgpu_gds_reg_offset[vmid].mem_base,
2440 gds_base);
2441
2442 /* GDS Size */
2443 gfx_v9_0_write_data_to_reg(ring, 0, false,
2444 amdgpu_gds_reg_offset[vmid].mem_size,
2445 gds_size);
2446
2447 /* GWS */
2448 gfx_v9_0_write_data_to_reg(ring, 0, false,
2449 amdgpu_gds_reg_offset[vmid].gws,
2450 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
2451
2452 /* OA */
2453 gfx_v9_0_write_data_to_reg(ring, 0, false,
2454 amdgpu_gds_reg_offset[vmid].oa,
2455 (1 << (oa_size + oa_base)) - (1 << oa_base));
2456 }
2457
2458 static int gfx_v9_0_early_init(void *handle)
2459 {
2460 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2461
2462 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
2463 adev->gfx.num_compute_rings = GFX9_NUM_COMPUTE_RINGS;
2464 gfx_v9_0_set_ring_funcs(adev);
2465 gfx_v9_0_set_irq_funcs(adev);
2466 gfx_v9_0_set_gds_init(adev);
2467 gfx_v9_0_set_rlc_funcs(adev);
2468
2469 return 0;
2470 }
2471
2472 static int gfx_v9_0_late_init(void *handle)
2473 {
2474 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2475 int r;
2476
2477 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
2478 if (r)
2479 return r;
2480
2481 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
2482 if (r)
2483 return r;
2484
2485 return 0;
2486 }
2487
2488 static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
2489 {
2490 uint32_t rlc_setting, data;
2491 unsigned i;
2492
2493 if (adev->gfx.rlc.in_safe_mode)
2494 return;
2495
2496 /* if RLC is not enabled, do nothing */
2497 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
2498 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
2499 return;
2500
2501 if (adev->cg_flags &
2502 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
2503 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
2504 data = RLC_SAFE_MODE__CMD_MASK;
2505 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
2506 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
2507
2508 /* wait for RLC_SAFE_MODE */
2509 for (i = 0; i < adev->usec_timeout; i++) {
2510 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
2511 break;
2512 udelay(1);
2513 }
2514 adev->gfx.rlc.in_safe_mode = true;
2515 }
2516 }
2517
2518 static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
2519 {
2520 uint32_t rlc_setting, data;
2521
2522 if (!adev->gfx.rlc.in_safe_mode)
2523 return;
2524
2525 /* if RLC is not enabled, do nothing */
2526 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
2527 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
2528 return;
2529
2530 if (adev->cg_flags &
2531 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
2532 /*
2533 * Try to exit safe mode only if it is already in safe
2534 * mode.
2535 */
2536 data = RLC_SAFE_MODE__CMD_MASK;
2537 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
2538 adev->gfx.rlc.in_safe_mode = false;
2539 }
2540 }
2541
2542 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
2543 bool enable)
2544 {
2545 uint32_t data, def;
2546
2547 /* It is disabled by HW by default */
2548 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2549 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
2550 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
2551 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
2552 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2553 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2554 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2555
2556 /* only for Vega10 & Raven1 */
2557 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
2558
2559 if (def != data)
2560 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
2561
2562 /* MGLS is a global flag to control all MGLS in GFX */
2563 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
2564 /* 2 - RLC memory Light sleep */
2565 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
2566 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
2567 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2568 if (def != data)
2569 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
2570 }
2571 /* 3 - CP memory Light sleep */
2572 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2573 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
2574 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2575 if (def != data)
2576 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
2577 }
2578 }
2579 } else {
2580 /* 1 - MGCG_OVERRIDE */
2581 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
2582 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
2583 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
2584 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2585 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2586 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2587 if (def != data)
2588 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
2589
2590 /* 2 - disable MGLS in RLC */
2591 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
2592 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
2593 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2594 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
2595 }
2596
2597 /* 3 - disable MGLS in CP */
2598 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
2599 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2600 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2601 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
2602 }
2603 }
2604 }
2605
2606 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
2607 bool enable)
2608 {
2609 uint32_t data, def;
2610
2611 adev->gfx.rlc.funcs->enter_safe_mode(adev);
2612
2613 /* Enable 3D CGCG/CGLS */
2614 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
2615 /* write cmd to clear cgcg/cgls ov */
2616 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
2617 /* unset CGCG override */
2618 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
2619 /* update CGCG and CGLS override bits */
2620 if (def != data)
2621 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
2622 /* enable 3Dcgcg FSM(0x0020003f) */
2623 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
2624 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2625 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
2626 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
2627 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2628 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
2629 if (def != data)
2630 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
2631
2632 /* set IDLE_POLL_COUNT(0x00900100) */
2633 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
2634 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2635 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2636 if (def != data)
2637 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
2638 } else {
2639 /* Disable CGCG/CGLS */
2640 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
2641 /* disable cgcg, cgls should be disabled */
2642 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
2643 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
2644 /* disable cgcg and cgls in FSM */
2645 if (def != data)
2646 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
2647 }
2648
2649 adev->gfx.rlc.funcs->exit_safe_mode(adev);
2650 }
2651
2652 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
2653 bool enable)
2654 {
2655 uint32_t def, data;
2656
2657 adev->gfx.rlc.funcs->enter_safe_mode(adev);
2658
2659 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2660 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
2661 /* unset CGCG override */
2662 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
2663 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2664 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2665 else
2666 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2667 /* update CGCG and CGLS override bits */
2668 if (def != data)
2669 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
2670
2671 /* enable cgcg FSM(0x0020003F) */
2672 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
2673 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2674 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
2675 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2676 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2677 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2678 if (def != data)
2679 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
2680
2681 /* set IDLE_POLL_COUNT(0x00900100) */
2682 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
2683 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2684 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2685 if (def != data)
2686 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
2687 } else {
2688 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
2689 /* reset CGCG/CGLS bits */
2690 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2691 /* disable cgcg and cgls in FSM */
2692 if (def != data)
2693 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
2694 }
2695
2696 adev->gfx.rlc.funcs->exit_safe_mode(adev);
2697 }
2698
2699 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
2700 bool enable)
2701 {
2702 if (enable) {
2703 /* CGCG/CGLS should be enabled after MGCG/MGLS
2704 * === MGCG + MGLS ===
2705 */
2706 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
2707 /* === CGCG /CGLS for GFX 3D Only === */
2708 gfx_v9_0_update_3d_clock_gating(adev, enable);
2709 /* === CGCG + CGLS === */
2710 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
2711 } else {
2712 /* CGCG/CGLS should be disabled before MGCG/MGLS
2713 * === CGCG + CGLS ===
2714 */
2715 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
2716 /* === CGCG /CGLS for GFX 3D Only === */
2717 gfx_v9_0_update_3d_clock_gating(adev, enable);
2718 /* === MGCG + MGLS === */
2719 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
2720 }
2721 return 0;
2722 }
2723
2724 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
2725 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
2726 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
2727 };
2728
2729 static int gfx_v9_0_set_powergating_state(void *handle,
2730 enum amd_powergating_state state)
2731 {
2732 return 0;
2733 }
2734
2735 static int gfx_v9_0_set_clockgating_state(void *handle,
2736 enum amd_clockgating_state state)
2737 {
2738 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2739
2740 if (amdgpu_sriov_vf(adev))
2741 return 0;
2742
2743 switch (adev->asic_type) {
2744 case CHIP_VEGA10:
2745 gfx_v9_0_update_gfx_clock_gating(adev,
2746 state == AMD_CG_STATE_GATE ? true : false);
2747 break;
2748 default:
2749 break;
2750 }
2751 return 0;
2752 }
2753
2754 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
2755 {
2756 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2757 int data;
2758
2759 if (amdgpu_sriov_vf(adev))
2760 *flags = 0;
2761
2762 /* AMD_CG_SUPPORT_GFX_MGCG */
2763 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
2764 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
2765 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
2766
2767 /* AMD_CG_SUPPORT_GFX_CGCG */
2768 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
2769 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
2770 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
2771
2772 /* AMD_CG_SUPPORT_GFX_CGLS */
2773 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
2774 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
2775
2776 /* AMD_CG_SUPPORT_GFX_RLC_LS */
2777 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
2778 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
2779 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
2780
2781 /* AMD_CG_SUPPORT_GFX_CP_LS */
2782 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
2783 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
2784 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
2785
2786 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
2787 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
2788 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
2789 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
2790
2791 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
2792 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
2793 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
2794 }
2795
2796 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
2797 {
2798 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
2799 }
2800
2801 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2802 {
2803 struct amdgpu_device *adev = ring->adev;
2804 u64 wptr;
2805
2806 /* XXX check if swapping is necessary on BE */
2807 if (ring->use_doorbell) {
2808 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
2809 } else {
2810 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
2811 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
2812 }
2813
2814 return wptr;
2815 }
2816
2817 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2818 {
2819 struct amdgpu_device *adev = ring->adev;
2820
2821 if (ring->use_doorbell) {
2822 /* XXX check if swapping is necessary on BE */
2823 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
2824 WDOORBELL64(ring->doorbell_index, ring->wptr);
2825 } else {
2826 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2827 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2828 }
2829 }
2830
2831 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2832 {
2833 u32 ref_and_mask, reg_mem_engine;
2834 struct nbio_hdp_flush_reg *nbio_hf_reg;
2835
2836 if (ring->adev->asic_type == CHIP_VEGA10)
2837 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
2838
2839 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2840 switch (ring->me) {
2841 case 1:
2842 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
2843 break;
2844 case 2:
2845 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
2846 break;
2847 default:
2848 return;
2849 }
2850 reg_mem_engine = 0;
2851 } else {
2852 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
2853 reg_mem_engine = 1; /* pfp */
2854 }
2855
2856 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
2857 nbio_hf_reg->hdp_flush_req_offset,
2858 nbio_hf_reg->hdp_flush_done_offset,
2859 ref_and_mask, ref_and_mask, 0x20);
2860 }
2861
2862 static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
2863 {
2864 gfx_v9_0_write_data_to_reg(ring, 0, true,
2865 SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
2866 }
2867
2868 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2869 struct amdgpu_ib *ib,
2870 unsigned vm_id, bool ctx_switch)
2871 {
2872 u32 header, control = 0;
2873
2874 if (ib->flags & AMDGPU_IB_FLAG_CE)
2875 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2876 else
2877 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2878
2879 control |= ib->length_dw | (vm_id << 24);
2880
2881 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT))
2882 control |= INDIRECT_BUFFER_PRE_ENB(1);
2883
2884 amdgpu_ring_write(ring, header);
2885 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
2886 amdgpu_ring_write(ring,
2887 #ifdef __BIG_ENDIAN
2888 (2 << 0) |
2889 #endif
2890 lower_32_bits(ib->gpu_addr));
2891 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
2892 amdgpu_ring_write(ring, control);
2893 }
2894
2895 #define INDIRECT_BUFFER_VALID (1 << 23)
2896
2897 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2898 struct amdgpu_ib *ib,
2899 unsigned vm_id, bool ctx_switch)
2900 {
2901 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
2902
2903 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2904 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
2905 amdgpu_ring_write(ring,
2906 #ifdef __BIG_ENDIAN
2907 (2 << 0) |
2908 #endif
2909 lower_32_bits(ib->gpu_addr));
2910 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
2911 amdgpu_ring_write(ring, control);
2912 }
2913
2914 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
2915 u64 seq, unsigned flags)
2916 {
2917 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2918 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2919
2920 /* RELEASE_MEM - flush caches, send int */
2921 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
2922 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2923 EOP_TC_ACTION_EN |
2924 EOP_TC_WB_ACTION_EN |
2925 EOP_TC_MD_ACTION_EN |
2926 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2927 EVENT_INDEX(5)));
2928 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2929
2930 /*
2931 * the address should be Qword aligned if 64bit write, Dword
2932 * aligned if only send 32bit data low (discard data high)
2933 */
2934 if (write64bit)
2935 BUG_ON(addr & 0x7);
2936 else
2937 BUG_ON(addr & 0x3);
2938 amdgpu_ring_write(ring, lower_32_bits(addr));
2939 amdgpu_ring_write(ring, upper_32_bits(addr));
2940 amdgpu_ring_write(ring, lower_32_bits(seq));
2941 amdgpu_ring_write(ring, upper_32_bits(seq));
2942 amdgpu_ring_write(ring, 0);
2943 }
2944
2945 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2946 {
2947 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2948 uint32_t seq = ring->fence_drv.sync_seq;
2949 uint64_t addr = ring->fence_drv.gpu_addr;
2950
2951 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
2952 lower_32_bits(addr), upper_32_bits(addr),
2953 seq, 0xffffffff, 4);
2954 }
2955
2956 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2957 unsigned vm_id, uint64_t pd_addr)
2958 {
2959 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
2960 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2961 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
2962 unsigned eng = ring->vm_inv_eng;
2963
2964 pd_addr = pd_addr | 0x1; /* valid bit */
2965 /* now only use physical base address of PDE and valid */
2966 BUG_ON(pd_addr & 0xFFFF00000000003EULL);
2967
2968 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
2969 hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
2970 lower_32_bits(pd_addr));
2971
2972 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
2973 hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
2974 upper_32_bits(pd_addr));
2975
2976 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
2977 hub->vm_inv_eng0_req + eng, req);
2978
2979 /* wait for the invalidate to complete */
2980 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
2981 eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
2982
2983 /* compute doesn't have PFP */
2984 if (usepfp) {
2985 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2986 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2987 amdgpu_ring_write(ring, 0x0);
2988 }
2989 }
2990
2991 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
2992 {
2993 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
2994 }
2995
2996 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2997 {
2998 u64 wptr;
2999
3000 /* XXX check if swapping is necessary on BE */
3001 if (ring->use_doorbell)
3002 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3003 else
3004 BUG();
3005 return wptr;
3006 }
3007
3008 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3009 {
3010 struct amdgpu_device *adev = ring->adev;
3011
3012 /* XXX check if swapping is necessary on BE */
3013 if (ring->use_doorbell) {
3014 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3015 WDOORBELL64(ring->doorbell_index, ring->wptr);
3016 } else{
3017 BUG(); /* only DOORBELL method supported on gfx9 now */
3018 }
3019 }
3020
3021 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
3022 u64 seq, unsigned int flags)
3023 {
3024 /* we only allocate 32bit for each seq wb address */
3025 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
3026
3027 /* write fence seq to the "addr" */
3028 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3029 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3030 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3031 amdgpu_ring_write(ring, lower_32_bits(addr));
3032 amdgpu_ring_write(ring, upper_32_bits(addr));
3033 amdgpu_ring_write(ring, lower_32_bits(seq));
3034
3035 if (flags & AMDGPU_FENCE_FLAG_INT) {
3036 /* set register to trigger INT */
3037 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3038 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3039 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3040 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
3041 amdgpu_ring_write(ring, 0);
3042 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
3043 }
3044 }
3045
3046 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
3047 {
3048 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3049 amdgpu_ring_write(ring, 0);
3050 }
3051
3052 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
3053 {
3054 static struct v9_ce_ib_state ce_payload = {0};
3055 uint64_t csa_addr;
3056 int cnt;
3057
3058 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
3059 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3060
3061 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3062 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3063 WRITE_DATA_DST_SEL(8) |
3064 WR_CONFIRM) |
3065 WRITE_DATA_CACHE_POLICY(0));
3066 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3067 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3068 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
3069 }
3070
3071 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
3072 {
3073 static struct v9_de_ib_state de_payload = {0};
3074 uint64_t csa_addr, gds_addr;
3075 int cnt;
3076
3077 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3078 gds_addr = csa_addr + 4096;
3079 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
3080 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
3081
3082 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
3083 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3084 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
3085 WRITE_DATA_DST_SEL(8) |
3086 WR_CONFIRM) |
3087 WRITE_DATA_CACHE_POLICY(0));
3088 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3089 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3090 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
3091 }
3092
3093 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3094 {
3095 uint32_t dw2 = 0;
3096
3097 if (amdgpu_sriov_vf(ring->adev))
3098 gfx_v9_0_ring_emit_ce_meta(ring);
3099
3100 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
3101 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
3102 /* set load_global_config & load_global_uconfig */
3103 dw2 |= 0x8001;
3104 /* set load_cs_sh_regs */
3105 dw2 |= 0x01000000;
3106 /* set load_per_context_state & load_gfx_sh_regs for GFX */
3107 dw2 |= 0x10002;
3108
3109 /* set load_ce_ram if preamble presented */
3110 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
3111 dw2 |= 0x10000000;
3112 } else {
3113 /* still load_ce_ram if this is the first time preamble presented
3114 * although there is no context switch happens.
3115 */
3116 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
3117 dw2 |= 0x10000000;
3118 }
3119
3120 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3121 amdgpu_ring_write(ring, dw2);
3122 amdgpu_ring_write(ring, 0);
3123
3124 if (amdgpu_sriov_vf(ring->adev))
3125 gfx_v9_0_ring_emit_de_meta(ring);
3126 }
3127
3128 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
3129 {
3130 unsigned ret;
3131 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
3132 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
3133 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
3134 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
3135 ret = ring->wptr & ring->buf_mask;
3136 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
3137 return ret;
3138 }
3139
3140 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
3141 {
3142 unsigned cur;
3143 BUG_ON(offset > ring->buf_mask);
3144 BUG_ON(ring->ring[offset] != 0x55aa55aa);
3145
3146 cur = (ring->wptr & ring->buf_mask) - 1;
3147 if (likely(cur > offset))
3148 ring->ring[offset] = cur - offset;
3149 else
3150 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
3151 }
3152
3153 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
3154 {
3155 struct amdgpu_device *adev = ring->adev;
3156
3157 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
3158 amdgpu_ring_write(ring, 0 | /* src: register*/
3159 (5 << 8) | /* dst: memory */
3160 (1 << 20)); /* write confirm */
3161 amdgpu_ring_write(ring, reg);
3162 amdgpu_ring_write(ring, 0);
3163 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
3164 adev->virt.reg_val_offs * 4));
3165 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
3166 adev->virt.reg_val_offs * 4));
3167 }
3168
3169 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
3170 uint32_t val)
3171 {
3172 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3173 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
3174 amdgpu_ring_write(ring, reg);
3175 amdgpu_ring_write(ring, 0);
3176 amdgpu_ring_write(ring, val);
3177 }
3178
3179 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3180 enum amdgpu_interrupt_state state)
3181 {
3182 switch (state) {
3183 case AMDGPU_IRQ_STATE_DISABLE:
3184 case AMDGPU_IRQ_STATE_ENABLE:
3185 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3186 TIME_STAMP_INT_ENABLE,
3187 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
3188 break;
3189 default:
3190 break;
3191 }
3192 }
3193
3194 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3195 int me, int pipe,
3196 enum amdgpu_interrupt_state state)
3197 {
3198 u32 mec_int_cntl, mec_int_cntl_reg;
3199
3200 /*
3201 * amdgpu controls only pipe 0 of MEC1. That's why this function only
3202 * handles the setting of interrupts for this specific pipe. All other
3203 * pipes' interrupts are set by amdkfd.
3204 */
3205
3206 if (me == 1) {
3207 switch (pipe) {
3208 case 0:
3209 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
3210 break;
3211 default:
3212 DRM_DEBUG("invalid pipe %d\n", pipe);
3213 return;
3214 }
3215 } else {
3216 DRM_DEBUG("invalid me %d\n", me);
3217 return;
3218 }
3219
3220 switch (state) {
3221 case AMDGPU_IRQ_STATE_DISABLE:
3222 mec_int_cntl = RREG32(mec_int_cntl_reg);
3223 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3224 TIME_STAMP_INT_ENABLE, 0);
3225 WREG32(mec_int_cntl_reg, mec_int_cntl);
3226 break;
3227 case AMDGPU_IRQ_STATE_ENABLE:
3228 mec_int_cntl = RREG32(mec_int_cntl_reg);
3229 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3230 TIME_STAMP_INT_ENABLE, 1);
3231 WREG32(mec_int_cntl_reg, mec_int_cntl);
3232 break;
3233 default:
3234 break;
3235 }
3236 }
3237
3238 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3239 struct amdgpu_irq_src *source,
3240 unsigned type,
3241 enum amdgpu_interrupt_state state)
3242 {
3243 switch (state) {
3244 case AMDGPU_IRQ_STATE_DISABLE:
3245 case AMDGPU_IRQ_STATE_ENABLE:
3246 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3247 PRIV_REG_INT_ENABLE,
3248 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
3249 break;
3250 default:
3251 break;
3252 }
3253
3254 return 0;
3255 }
3256
3257 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3258 struct amdgpu_irq_src *source,
3259 unsigned type,
3260 enum amdgpu_interrupt_state state)
3261 {
3262 switch (state) {
3263 case AMDGPU_IRQ_STATE_DISABLE:
3264 case AMDGPU_IRQ_STATE_ENABLE:
3265 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3266 PRIV_INSTR_INT_ENABLE,
3267 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
3268 default:
3269 break;
3270 }
3271
3272 return 0;
3273 }
3274
3275 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3276 struct amdgpu_irq_src *src,
3277 unsigned type,
3278 enum amdgpu_interrupt_state state)
3279 {
3280 switch (type) {
3281 case AMDGPU_CP_IRQ_GFX_EOP:
3282 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
3283 break;
3284 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3285 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
3286 break;
3287 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3288 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
3289 break;
3290 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
3291 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
3292 break;
3293 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
3294 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
3295 break;
3296 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
3297 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
3298 break;
3299 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
3300 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
3301 break;
3302 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
3303 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
3304 break;
3305 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
3306 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
3307 break;
3308 default:
3309 break;
3310 }
3311 return 0;
3312 }
3313
3314 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
3315 struct amdgpu_irq_src *source,
3316 struct amdgpu_iv_entry *entry)
3317 {
3318 int i;
3319 u8 me_id, pipe_id, queue_id;
3320 struct amdgpu_ring *ring;
3321
3322 DRM_DEBUG("IH: CP EOP\n");
3323 me_id = (entry->ring_id & 0x0c) >> 2;
3324 pipe_id = (entry->ring_id & 0x03) >> 0;
3325 queue_id = (entry->ring_id & 0x70) >> 4;
3326
3327 switch (me_id) {
3328 case 0:
3329 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3330 break;
3331 case 1:
3332 case 2:
3333 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3334 ring = &adev->gfx.compute_ring[i];
3335 /* Per-queue interrupt is supported for MEC starting from VI.
3336 * The interrupt can only be enabled/disabled per pipe instead of per queue.
3337 */
3338 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
3339 amdgpu_fence_process(ring);
3340 }
3341 break;
3342 }
3343 return 0;
3344 }
3345
3346 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
3347 struct amdgpu_irq_src *source,
3348 struct amdgpu_iv_entry *entry)
3349 {
3350 DRM_ERROR("Illegal register access in command stream\n");
3351 schedule_work(&adev->reset_work);
3352 return 0;
3353 }
3354
3355 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
3356 struct amdgpu_irq_src *source,
3357 struct amdgpu_iv_entry *entry)
3358 {
3359 DRM_ERROR("Illegal instruction in command stream\n");
3360 schedule_work(&adev->reset_work);
3361 return 0;
3362 }
3363
3364 static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
3365 struct amdgpu_irq_src *src,
3366 unsigned int type,
3367 enum amdgpu_interrupt_state state)
3368 {
3369 uint32_t tmp, target;
3370 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
3371
3372 if (ring->me == 1)
3373 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
3374 else
3375 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
3376 target += ring->pipe;
3377
3378 switch (type) {
3379 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
3380 if (state == AMDGPU_IRQ_STATE_DISABLE) {
3381 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
3382 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
3383 GENERIC2_INT_ENABLE, 0);
3384 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
3385
3386 tmp = RREG32(target);
3387 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
3388 GENERIC2_INT_ENABLE, 0);
3389 WREG32(target, tmp);
3390 } else {
3391 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
3392 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
3393 GENERIC2_INT_ENABLE, 1);
3394 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
3395
3396 tmp = RREG32(target);
3397 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
3398 GENERIC2_INT_ENABLE, 1);
3399 WREG32(target, tmp);
3400 }
3401 break;
3402 default:
3403 BUG(); /* kiq only support GENERIC2_INT now */
3404 break;
3405 }
3406 return 0;
3407 }
3408
3409 static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
3410 struct amdgpu_irq_src *source,
3411 struct amdgpu_iv_entry *entry)
3412 {
3413 u8 me_id, pipe_id, queue_id;
3414 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
3415
3416 me_id = (entry->ring_id & 0x0c) >> 2;
3417 pipe_id = (entry->ring_id & 0x03) >> 0;
3418 queue_id = (entry->ring_id & 0x70) >> 4;
3419 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
3420 me_id, pipe_id, queue_id);
3421
3422 amdgpu_fence_process(ring);
3423 return 0;
3424 }
3425
3426 const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
3427 .name = "gfx_v9_0",
3428 .early_init = gfx_v9_0_early_init,
3429 .late_init = gfx_v9_0_late_init,
3430 .sw_init = gfx_v9_0_sw_init,
3431 .sw_fini = gfx_v9_0_sw_fini,
3432 .hw_init = gfx_v9_0_hw_init,
3433 .hw_fini = gfx_v9_0_hw_fini,
3434 .suspend = gfx_v9_0_suspend,
3435 .resume = gfx_v9_0_resume,
3436 .is_idle = gfx_v9_0_is_idle,
3437 .wait_for_idle = gfx_v9_0_wait_for_idle,
3438 .soft_reset = gfx_v9_0_soft_reset,
3439 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
3440 .set_powergating_state = gfx_v9_0_set_powergating_state,
3441 .get_clockgating_state = gfx_v9_0_get_clockgating_state,
3442 };
3443
3444 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
3445 .type = AMDGPU_RING_TYPE_GFX,
3446 .align_mask = 0xff,
3447 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3448 .support_64bit_ptrs = true,
3449 .vmhub = AMDGPU_GFXHUB,
3450 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
3451 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
3452 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
3453 .emit_frame_size = /* totally 242 maximum if 16 IBs */
3454 5 + /* COND_EXEC */
3455 7 + /* PIPELINE_SYNC */
3456 24 + /* VM_FLUSH */
3457 8 + /* FENCE for VM_FLUSH */
3458 20 + /* GDS switch */
3459 4 + /* double SWITCH_BUFFER,
3460 the first COND_EXEC jump to the place just
3461 prior to this double SWITCH_BUFFER */
3462 5 + /* COND_EXEC */
3463 7 + /* HDP_flush */
3464 4 + /* VGT_flush */
3465 14 + /* CE_META */
3466 31 + /* DE_META */
3467 3 + /* CNTX_CTRL */
3468 5 + /* HDP_INVL */
3469 8 + 8 + /* FENCE x2 */
3470 2, /* SWITCH_BUFFER */
3471 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
3472 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
3473 .emit_fence = gfx_v9_0_ring_emit_fence,
3474 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
3475 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
3476 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
3477 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
3478 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
3479 .test_ring = gfx_v9_0_ring_test_ring,
3480 .test_ib = gfx_v9_0_ring_test_ib,
3481 .insert_nop = amdgpu_ring_insert_nop,
3482 .pad_ib = amdgpu_ring_generic_pad_ib,
3483 .emit_switch_buffer = gfx_v9_ring_emit_sb,
3484 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
3485 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
3486 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
3487 };
3488
3489 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
3490 .type = AMDGPU_RING_TYPE_COMPUTE,
3491 .align_mask = 0xff,
3492 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3493 .support_64bit_ptrs = true,
3494 .vmhub = AMDGPU_GFXHUB,
3495 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
3496 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
3497 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
3498 .emit_frame_size =
3499 20 + /* gfx_v9_0_ring_emit_gds_switch */
3500 7 + /* gfx_v9_0_ring_emit_hdp_flush */
3501 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
3502 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
3503 24 + /* gfx_v9_0_ring_emit_vm_flush */
3504 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
3505 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
3506 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
3507 .emit_fence = gfx_v9_0_ring_emit_fence,
3508 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
3509 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
3510 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
3511 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
3512 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
3513 .test_ring = gfx_v9_0_ring_test_ring,
3514 .test_ib = gfx_v9_0_ring_test_ib,
3515 .insert_nop = amdgpu_ring_insert_nop,
3516 .pad_ib = amdgpu_ring_generic_pad_ib,
3517 };
3518
3519 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
3520 .type = AMDGPU_RING_TYPE_KIQ,
3521 .align_mask = 0xff,
3522 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3523 .support_64bit_ptrs = true,
3524 .vmhub = AMDGPU_GFXHUB,
3525 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
3526 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
3527 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
3528 .emit_frame_size =
3529 20 + /* gfx_v9_0_ring_emit_gds_switch */
3530 7 + /* gfx_v9_0_ring_emit_hdp_flush */
3531 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
3532 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
3533 24 + /* gfx_v9_0_ring_emit_vm_flush */
3534 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
3535 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
3536 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
3537 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
3538 .test_ring = gfx_v9_0_ring_test_ring,
3539 .test_ib = gfx_v9_0_ring_test_ib,
3540 .insert_nop = amdgpu_ring_insert_nop,
3541 .pad_ib = amdgpu_ring_generic_pad_ib,
3542 .emit_rreg = gfx_v9_0_ring_emit_rreg,
3543 .emit_wreg = gfx_v9_0_ring_emit_wreg,
3544 };
3545
3546 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
3547 {
3548 int i;
3549
3550 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
3551
3552 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3553 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
3554
3555 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3556 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
3557 }
3558
3559 static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
3560 .set = gfx_v9_0_kiq_set_interrupt_state,
3561 .process = gfx_v9_0_kiq_irq,
3562 };
3563
3564 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
3565 .set = gfx_v9_0_set_eop_interrupt_state,
3566 .process = gfx_v9_0_eop_irq,
3567 };
3568
3569 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
3570 .set = gfx_v9_0_set_priv_reg_fault_state,
3571 .process = gfx_v9_0_priv_reg_irq,
3572 };
3573
3574 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
3575 .set = gfx_v9_0_set_priv_inst_fault_state,
3576 .process = gfx_v9_0_priv_inst_irq,
3577 };
3578
3579 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
3580 {
3581 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3582 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
3583
3584 adev->gfx.priv_reg_irq.num_types = 1;
3585 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
3586
3587 adev->gfx.priv_inst_irq.num_types = 1;
3588 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
3589
3590 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
3591 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
3592 }
3593
3594 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
3595 {
3596 switch (adev->asic_type) {
3597 case CHIP_VEGA10:
3598 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
3599 break;
3600 default:
3601 break;
3602 }
3603 }
3604
3605 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
3606 {
3607 /* init asci gds info */
3608 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
3609 adev->gds.gws.total_size = 64;
3610 adev->gds.oa.total_size = 16;
3611
3612 if (adev->gds.mem.total_size == 64 * 1024) {
3613 adev->gds.mem.gfx_partition_size = 4096;
3614 adev->gds.mem.cs_partition_size = 4096;
3615
3616 adev->gds.gws.gfx_partition_size = 4;
3617 adev->gds.gws.cs_partition_size = 4;
3618
3619 adev->gds.oa.gfx_partition_size = 4;
3620 adev->gds.oa.cs_partition_size = 1;
3621 } else {
3622 adev->gds.mem.gfx_partition_size = 1024;
3623 adev->gds.mem.cs_partition_size = 1024;
3624
3625 adev->gds.gws.gfx_partition_size = 16;
3626 adev->gds.gws.cs_partition_size = 16;
3627
3628 adev->gds.oa.gfx_partition_size = 4;
3629 adev->gds.oa.cs_partition_size = 4;
3630 }
3631 }
3632
3633 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3634 {
3635 u32 data, mask;
3636
3637 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
3638 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
3639
3640 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3641 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3642
3643 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
3644
3645 return (~data) & mask;
3646 }
3647
3648 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
3649 struct amdgpu_cu_info *cu_info)
3650 {
3651 int i, j, k, counter, active_cu_number = 0;
3652 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3653
3654 if (!adev || !cu_info)
3655 return -EINVAL;
3656
3657 memset(cu_info, 0, sizeof(*cu_info));
3658
3659 mutex_lock(&adev->grbm_idx_mutex);
3660 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3661 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3662 mask = 1;
3663 ao_bitmap = 0;
3664 counter = 0;
3665 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
3666 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
3667 cu_info->bitmap[i][j] = bitmap;
3668
3669 for (k = 0; k < 16; k ++) {
3670 if (bitmap & mask) {
3671 if (counter < 2)
3672 ao_bitmap |= mask;
3673 counter ++;
3674 }
3675 mask <<= 1;
3676 }
3677 active_cu_number += counter;
3678 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3679 }
3680 }
3681 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3682 mutex_unlock(&adev->grbm_idx_mutex);
3683
3684 cu_info->number = active_cu_number;
3685 cu_info->ao_cu_mask = ao_cu_mask;
3686
3687 return 0;
3688 }
3689
3690 static int gfx_v9_0_init_queue(struct amdgpu_ring *ring)
3691 {
3692 int r, j;
3693 u32 tmp;
3694 bool use_doorbell = true;
3695 u64 hqd_gpu_addr;
3696 u64 mqd_gpu_addr;
3697 u64 eop_gpu_addr;
3698 u64 wb_gpu_addr;
3699 u32 *buf;
3700 struct v9_mqd *mqd;
3701 struct amdgpu_device *adev;
3702
3703 adev = ring->adev;
3704 if (ring->mqd_obj == NULL) {
3705 r = amdgpu_bo_create(adev,
3706 sizeof(struct v9_mqd),
3707 PAGE_SIZE,true,
3708 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3709 NULL, &ring->mqd_obj);
3710 if (r) {
3711 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3712 return r;
3713 }
3714 }
3715
3716 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3717 if (unlikely(r != 0)) {
3718 gfx_v9_0_cp_compute_fini(adev);
3719 return r;
3720 }
3721
3722 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3723 &mqd_gpu_addr);
3724 if (r) {
3725 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3726 gfx_v9_0_cp_compute_fini(adev);
3727 return r;
3728 }
3729 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3730 if (r) {
3731 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3732 gfx_v9_0_cp_compute_fini(adev);
3733 return r;
3734 }
3735
3736 /* init the mqd struct */
3737 memset(buf, 0, sizeof(struct v9_mqd));
3738
3739 mqd = (struct v9_mqd *)buf;
3740 mqd->header = 0xC0310800;
3741 mqd->compute_pipelinestat_enable = 0x00000001;
3742 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3743 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3744 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3745 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3746 mqd->compute_misc_reserved = 0x00000003;
3747 mutex_lock(&adev->srbm_mutex);
3748 soc15_grbm_select(adev, ring->me,
3749 ring->pipe,
3750 ring->queue, 0);
3751 /* disable wptr polling */
3752 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3753
3754 /* write the EOP addr */
3755 BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases eop address */
3756 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring->queue * MEC_HPD_SIZE);
3757 eop_gpu_addr >>= 8;
3758
3759 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, lower_32_bits(eop_gpu_addr));
3760 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
3761 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_gpu_addr);
3762 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_gpu_addr);
3763
3764 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3765 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
3766 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3767 (order_base_2(MEC_HPD_SIZE / 4) - 1));
3768 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, tmp);
3769
3770 /* enable doorbell? */
3771 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3772 if (use_doorbell)
3773 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3774 else
3775 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3776
3777 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
3778 mqd->cp_hqd_pq_doorbell_control = tmp;
3779
3780 /* disable the queue if it's active */
3781 ring->wptr = 0;
3782 mqd->cp_hqd_dequeue_request = 0;
3783 mqd->cp_hqd_pq_rptr = 0;
3784 mqd->cp_hqd_pq_wptr_lo = 0;
3785 mqd->cp_hqd_pq_wptr_hi = 0;
3786 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3787 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3788 for (j = 0; j < adev->usec_timeout; j++) {
3789 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3790 break;
3791 udelay(1);
3792 }
3793 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
3794 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
3795 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, mqd->cp_hqd_pq_wptr_lo);
3796 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, mqd->cp_hqd_pq_wptr_hi);
3797 }
3798
3799 /* set the pointer to the MQD */
3800 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3801 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3802 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
3803 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3804
3805 /* set MQD vmid to 0 */
3806 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
3807 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3808 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, tmp);
3809 mqd->cp_mqd_control = tmp;
3810
3811 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3812 hqd_gpu_addr = ring->gpu_addr >> 8;
3813 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3814 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3815 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
3816 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
3817
3818 /* set up the HQD, this is similar to CP_RB0_CNTL */
3819 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
3820 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3821 (order_base_2(ring->ring_size / 4) - 1));
3822 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3823 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3824 #ifdef __BIG_ENDIAN
3825 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3826 #endif
3827 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3828 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3829 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3830 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3831 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, tmp);
3832 mqd->cp_hqd_pq_control = tmp;
3833
3834 /* set the wb address wether it's enabled or not */
3835 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3836 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3837 mqd->cp_hqd_pq_rptr_report_addr_hi =
3838 upper_32_bits(wb_gpu_addr) & 0xffff;
3839 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3840 mqd->cp_hqd_pq_rptr_report_addr_lo);
3841 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3842 mqd->cp_hqd_pq_rptr_report_addr_hi);
3843
3844 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3845 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3846 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3847 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3848 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
3849 mqd->cp_hqd_pq_wptr_poll_addr_lo);
3850 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3851 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3852
3853 /* enable the doorbell if requested */
3854 if (use_doorbell) {
3855 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
3856 (AMDGPU_DOORBELL64_KIQ * 2) << 2);
3857 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3858 (AMDGPU_DOORBELL64_MEC_RING7 * 2) << 2);
3859 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3860 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3861 DOORBELL_OFFSET, ring->doorbell_index);
3862 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3863 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3864 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3865 mqd->cp_hqd_pq_doorbell_control = tmp;
3866
3867 } else {
3868 mqd->cp_hqd_pq_doorbell_control = 0;
3869 }
3870 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3871 mqd->cp_hqd_pq_doorbell_control);
3872
3873 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3874 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, mqd->cp_hqd_pq_wptr_lo);
3875 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, mqd->cp_hqd_pq_wptr_hi);
3876
3877 /* set the vmid for the queue */
3878 mqd->cp_hqd_vmid = 0;
3879 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3880
3881 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
3882 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3883 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, tmp);
3884 mqd->cp_hqd_persistent_state = tmp;
3885
3886 /* activate the queue */
3887 mqd->cp_hqd_active = 1;
3888 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
3889
3890 soc15_grbm_select(adev, 0, 0, 0, 0);
3891 mutex_unlock(&adev->srbm_mutex);
3892
3893 amdgpu_bo_kunmap(ring->mqd_obj);
3894 amdgpu_bo_unreserve(ring->mqd_obj);
3895
3896 if (use_doorbell)
3897 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3898
3899 return 0;
3900 }
3901
3902 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
3903 {
3904 .type = AMD_IP_BLOCK_TYPE_GFX,
3905 .major = 9,
3906 .minor = 0,
3907 .rev = 0,
3908 .funcs = &gfx_v9_0_ip_funcs,
3909 };
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