drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "gfxhub_v2_1.h"
  26
  27 #include "gc/gc_10_3_0_offset.h"
  28 #include "gc/gc_10_3_0_sh_mask.h"
  29 #include "gc/gc_10_3_0_default.h"
  30 #include "navi10_enum.h"
  31
  32 #include "soc15_common.h"
  33
  34 static const char *gfxhub_client_ids[] = {
  35         "CB/DB",
  36         "Reserved",
  37         "GE1",
  38         "GE2",
  39         "CPF",
  40         "CPC",
  41         "CPG",
  42         "RLC",
  43         "TCP",
  44         "SQC (inst)",
  45         "SQC (data)",
  46         "SQG",
  47         "Reserved",
  48         "SDMA0",
  49         "SDMA1",
  50         "GCR",
  51         "SDMA2",
  52         "SDMA3",
  53 };
  54
  55 static uint32_t gfxhub_v2_1_get_invalidate_req(unsigned int vmid,
  56                                                uint32_t flush_type)
  57 {
  58         u32 req = 0;
  59
  60         /* invalidate using legacy mode on vmid*/
  61         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
  62                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
  63         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
  64         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
  65         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
  66         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
  67         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
  68         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
  69         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
  70                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
  71
  72         return req;
  73 }
  74
  75 static void
  76 gfxhub_v2_1_print_l2_protection_fault_status(struct amdgpu_device *adev,
  77                                              uint32_t status)
  78 {
  79         u32 cid = REG_GET_FIELD(status,
  80                                 GCVM_L2_PROTECTION_FAULT_STATUS, CID);
  81
  82         dev_err(adev->dev,
  83                 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
  84                 status);
  85         dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
  86                 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],
  87                 cid);
  88         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
  89                 REG_GET_FIELD(status,
  90                 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
  91         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
  92                 REG_GET_FIELD(status,
  93                 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
  94         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
  95                 REG_GET_FIELD(status,
  96                 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
  97         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
  98                 REG_GET_FIELD(status,
  99                 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 100         dev_err(adev->dev, "\t RW: 0x%lx\n",
 101                 REG_GET_FIELD(status,
 102                 GCVM_L2_PROTECTION_FAULT_STATUS, RW));
 103 }
 104
 105 u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev)
 106 {
 107         u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
 108
 109         base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
 110         base <<= 24;
 111
 112         return base;
 113 }
 114
 115 u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev)
 116 {
 117         return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;
 118 }
 119
 120 void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
 121                                 uint64_t page_table_base)
 122 {
 123         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 124
 125         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
 126                             hub->ctx_addr_distance * vmid,
 127                             lower_32_bits(page_table_base));
 128
 129         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
 130                             hub->ctx_addr_distance * vmid,
 131                             upper_32_bits(page_table_base));
 132 }
 133
 134 static void gfxhub_v2_1_init_gart_aperture_regs(struct amdgpu_device *adev)
 135 {
 136         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
 137
 138         gfxhub_v2_1_setup_vm_pt_regs(adev, 0, pt_base);
 139
 140         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
 141                      (u32)(adev->gmc.gart_start >> 12));
 142         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
 143                      (u32)(adev->gmc.gart_start >> 44));
 144
 145         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
 146                      (u32)(adev->gmc.gart_end >> 12));
 147         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 148                      (u32)(adev->gmc.gart_end >> 44));
 149 }
 150
 151 static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev)
 152 {
 153         uint64_t value;
 154
 155         /* Disable AGP. */
 156         WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
 157         WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0);
 158         WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF);
 159
 160         /* Program the system aperture low logical page number. */
 161         WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 162                      adev->gmc.vram_start >> 18);
 163         WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 164                      adev->gmc.vram_end >> 18);
 165
 166         /* Set default page address. */
 167         value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
 168                 + adev->vm_manager.vram_base_offset;
 169         WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 170                      (u32)(value >> 12));
 171         WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 172                      (u32)(value >> 44));
 173
 174         /* Program "protection fault". */
 175         WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 176                      (u32)(adev->dummy_page_addr >> 12));
 177         WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 178                      (u32)((u64)adev->dummy_page_addr >> 44));
 179
 180         WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
 181                        ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 182 }
 183
 184
 185 static void gfxhub_v2_1_init_tlb_regs(struct amdgpu_device *adev)
 186 {
 187         uint32_t tmp;
 188
 189         /* Setup TLB control */
 190         tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
 191
 192         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 193         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 194         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 195                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 196         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 197                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 198         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 199         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 200                             MTYPE, MTYPE_UC); /* UC, uncached */
 201
 202         WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
 203 }
 204
 205 static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev)
 206 {
 207         uint32_t tmp;
 208
 209         /* These registers are not accessible to VF-SRIOV.
 210          * The PF will program them instead.
 211          */
 212         if (amdgpu_sriov_vf(adev))
 213                 return;
 214
 215         /* Setup L2 cache */
 216         tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
 217         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
 218         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
 219         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
 220                             ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 221         /* XXX for emulation, Refer to closed source code.*/
 222         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
 223                             L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
 224         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 225         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 226         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 227         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);
 228
 229         tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
 230         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 231         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 232         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
 233
 234         tmp = mmGCVM_L2_CNTL3_DEFAULT;
 235         if (adev->gmc.translate_further) {
 236                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
 237                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
 238                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 239         } else {
 240                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
 241                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
 242                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 243         }
 244         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
 245
 246         tmp = mmGCVM_L2_CNTL4_DEFAULT;
 247         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 248         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 249         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);
 250
 251         tmp = mmGCVM_L2_CNTL5_DEFAULT;
 252         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
 253         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp);
 254 }
 255
 256 static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev)
 257 {
 258         uint32_t tmp;
 259
 260         tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);
 261         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 262         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 263         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
 264                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 265         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);
 266 }
 267
 268 static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev)
 269 {
 270         /* These registers are not accessible to VF-SRIOV.
 271          * The PF will program them instead.
 272          */
 273         if (amdgpu_sriov_vf(adev))
 274                 return;
 275
 276         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 277                      0xFFFFFFFF);
 278         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 279                      0x0000000F);
 280
 281         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
 282                      0);
 283         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
 284                      0);
 285
 286         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
 287         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
 288
 289 }
 290
 291 static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev)
 292 {
 293         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 294         int i;
 295         uint32_t tmp;
 296
 297         for (i = 0; i <= 14; i++) {
 298                 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
 299                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 300                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 301                                     adev->vm_manager.num_level);
 302                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 303                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 304                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 305                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 306                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 307                                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 308                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 309                                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 310                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 311                                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 312                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 313                                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 314                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 315                                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 316                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 317                                 PAGE_TABLE_BLOCK_SIZE,
 318                                 adev->vm_manager.block_size - 9);
 319                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 320                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 321                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 322                                     !adev->gmc.noretry);
 323                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL,
 324                                     i * hub->ctx_distance, tmp);
 325                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 326                                     i * hub->ctx_addr_distance, 0);
 327                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 328                                     i * hub->ctx_addr_distance, 0);
 329                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 330                                     i * hub->ctx_addr_distance,
 331                                     lower_32_bits(adev->vm_manager.max_pfn - 1));
 332                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 333                                     i * hub->ctx_addr_distance,
 334                                     upper_32_bits(adev->vm_manager.max_pfn - 1));
 335         }
 336 }
 337
 338 static void gfxhub_v2_1_program_invalidation(struct amdgpu_device *adev)
 339 {
 340         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 341         unsigned i;
 342
 343         for (i = 0 ; i < 18; ++i) {
 344                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 345                                     i * hub->eng_addr_distance, 0xffffffff);
 346                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 347                                     i * hub->eng_addr_distance, 0x1f);
 348         }
 349 }
 350
 351 int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev)
 352 {
 353         if (amdgpu_sriov_vf(adev)) {
 354                 /*
 355                  * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 356                  * VF copy registers so vbios post doesn't program them, for
 357                  * SRIOV driver need to program them
 358                  */
 359                 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE,
 360                              adev->gmc.vram_start >> 24);
 361                 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP,
 362                              adev->gmc.vram_end >> 24);
 363         }
 364
 365         /* GART Enable. */
 366         gfxhub_v2_1_init_gart_aperture_regs(adev);
 367         gfxhub_v2_1_init_system_aperture_regs(adev);
 368         gfxhub_v2_1_init_tlb_regs(adev);
 369         gfxhub_v2_1_init_cache_regs(adev);
 370
 371         gfxhub_v2_1_enable_system_domain(adev);
 372         gfxhub_v2_1_disable_identity_aperture(adev);
 373         gfxhub_v2_1_setup_vmid_config(adev);
 374         gfxhub_v2_1_program_invalidation(adev);
 375
 376         return 0;
 377 }
 378
 379 void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev)
 380 {
 381         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 382         u32 tmp;
 383         u32 i;
 384
 385         /* Disable all tables */
 386         for (i = 0; i < 16; i++)
 387                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL,
 388                                     i * hub->ctx_distance, 0);
 389
 390         /* Setup TLB control */
 391         tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
 392         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 393         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 394                             ENABLE_ADVANCED_DRIVER_MODEL, 0);
 395         WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
 396
 397         /* Setup L2 cache */
 398         WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
 399         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
 400 }
 401
 402 /**
 403  * gfxhub_v2_1_set_fault_enable_default - update GART/VM fault handling
 404  *
 405  * @adev: amdgpu_device pointer
 406  * @value: true redirects VM faults to the default page
 407  */
 408 void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,
 409                                           bool value)
 410 {
 411         u32 tmp;
 412
 413         /* These registers are not accessible to VF-SRIOV.
 414          * The PF will program them instead.
 415          */
 416         if (amdgpu_sriov_vf(adev))
 417                 return;
 418
 419         tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
 420         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 421                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 422         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 423                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 424         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 425                             PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 426         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 427                             PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 428         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 429                             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 430                             value);
 431         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 432                             NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 433         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 434                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 435         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 436                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 437         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 438                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 439         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 440                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 441         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 442                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 443         if (!value) {
 444                 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 445                                 CRASH_ON_NO_RETRY_FAULT, 1);
 446                 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 447                                 CRASH_ON_RETRY_FAULT, 1);
 448         }
 449         WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
 450 }
 451
 452 static const struct amdgpu_vmhub_funcs gfxhub_v2_1_vmhub_funcs = {
 453         .print_l2_protection_fault_status = gfxhub_v2_1_print_l2_protection_fault_status,
 454         .get_invalidate_req = gfxhub_v2_1_get_invalidate_req,
 455 };
 456
 457 void gfxhub_v2_1_init(struct amdgpu_device *adev)
 458 {
 459         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 460
 461         hub->ctx0_ptb_addr_lo32 =
 462                 SOC15_REG_OFFSET(GC, 0,
 463                                  mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 464         hub->ctx0_ptb_addr_hi32 =
 465                 SOC15_REG_OFFSET(GC, 0,
 466                                  mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 467         hub->vm_inv_eng0_sem =
 468                 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
 469         hub->vm_inv_eng0_req =
 470                 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
 471         hub->vm_inv_eng0_ack =
 472                 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK);
 473         hub->vm_context0_cntl =
 474                 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL);
 475         hub->vm_l2_pro_fault_status =
 476                 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS);
 477         hub->vm_l2_pro_fault_cntl =
 478                 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
 479
 480         hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL;
 481         hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 482                 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 483         hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ -
 484                 mmGCVM_INVALIDATE_ENG0_REQ;
 485         hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 486                 mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 487
 488         hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 489                 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 490                 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 491                 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 492                 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 493                 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 494                 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 495
 496         hub->vmhub_funcs = &gfxhub_v2_1_vmhub_funcs;
 497 }
 498
 499 int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
 500 {
 501         u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL);
 502         u32 max_region =
 503                 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
 504         u32 max_num_physical_nodes   = 0;
 505         u32 max_physical_node_id     = 0;
 506
 507         switch (adev->asic_type) {
 508         case CHIP_SIENNA_CICHLID:
 509                 max_num_physical_nodes   = 4;
 510                 max_physical_node_id     = 3;
 511                 break;
 512         default:
 513                 return -EINVAL;
 514         }
 515
 516         /* PF_MAX_REGION=0 means xgmi is disabled */
 517         if (max_region) {
 518                 adev->gmc.xgmi.num_physical_nodes = max_region + 1;
 519                 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
 520                         return -EINVAL;
 521
 522                 adev->gmc.xgmi.physical_node_id =
 523                         REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION);
 524                 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
 525                         return -EINVAL;
 526
 527                 adev->gmc.xgmi.node_segment_size = REG_GET_FIELD(
 528                         RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE),
 529                         GCMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
 530         }
 531
 532         return 0;
 533 }