2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
29 #include "bif/bif_3_0_d.h"
30 #include "bif/bif_3_0_sh_mask.h"
31 #include "oss/oss_1_0_d.h"
32 #include "oss/oss_1_0_sh_mask.h"
33 #include "gmc/gmc_6_0_d.h"
34 #include "gmc/gmc_6_0_sh_mask.h"
35 #include "dce/dce_6_0_d.h"
36 #include "dce/dce_6_0_sh_mask.h"
39 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device
*adev
);
40 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device
*adev
);
41 static int gmc_v6_0_wait_for_idle(void *handle
);
43 MODULE_FIRMWARE("radeon/tahiti_mc.bin");
44 MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
45 MODULE_FIRMWARE("radeon/verde_mc.bin");
46 MODULE_FIRMWARE("radeon/oland_mc.bin");
47 MODULE_FIRMWARE("radeon/si58_mc.bin");
49 #define MC_SEQ_MISC0__MT__MASK 0xf0000000
50 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000
51 #define MC_SEQ_MISC0__MT__DDR2 0x20000000
52 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000
53 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000
54 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000
55 #define MC_SEQ_MISC0__MT__HBM 0x60000000
56 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000
59 static const u32 crtc_offsets
[6] =
61 SI_CRTC0_REGISTER_OFFSET
,
62 SI_CRTC1_REGISTER_OFFSET
,
63 SI_CRTC2_REGISTER_OFFSET
,
64 SI_CRTC3_REGISTER_OFFSET
,
65 SI_CRTC4_REGISTER_OFFSET
,
66 SI_CRTC5_REGISTER_OFFSET
69 static void gmc_v6_0_mc_stop(struct amdgpu_device
*adev
,
70 struct amdgpu_mode_mc_save
*save
)
74 if (adev
->mode_info
.num_crtc
)
75 amdgpu_display_stop_mc_access(adev
, save
);
77 gmc_v6_0_wait_for_idle((void *)adev
);
79 blackout
= RREG32(mmMC_SHARED_BLACKOUT_CNTL
);
80 if (REG_GET_FIELD(blackout
, MC_SHARED_BLACKOUT_CNTL
, BLACKOUT_MODE
) != 1) {
81 /* Block CPU access */
82 WREG32(mmBIF_FB_EN
, 0);
84 blackout
= REG_SET_FIELD(blackout
,
85 MC_SHARED_BLACKOUT_CNTL
, BLACKOUT_MODE
, 0);
86 WREG32(mmMC_SHARED_BLACKOUT_CNTL
, blackout
| 1);
88 /* wait for the MC to settle */
93 static void gmc_v6_0_mc_resume(struct amdgpu_device
*adev
,
94 struct amdgpu_mode_mc_save
*save
)
98 /* unblackout the MC */
99 tmp
= RREG32(mmMC_SHARED_BLACKOUT_CNTL
);
100 tmp
= REG_SET_FIELD(tmp
, MC_SHARED_BLACKOUT_CNTL
, BLACKOUT_MODE
, 0);
101 WREG32(mmMC_SHARED_BLACKOUT_CNTL
, tmp
);
102 /* allow CPU access */
103 tmp
= REG_SET_FIELD(0, BIF_FB_EN
, FB_READ_EN
, 1);
104 tmp
= REG_SET_FIELD(tmp
, BIF_FB_EN
, FB_WRITE_EN
, 1);
105 WREG32(mmBIF_FB_EN
, tmp
);
107 if (adev
->mode_info
.num_crtc
)
108 amdgpu_display_resume_mc_access(adev
, save
);
112 static int gmc_v6_0_init_microcode(struct amdgpu_device
*adev
)
114 const char *chip_name
;
117 bool is_58_fw
= false;
121 switch (adev
->asic_type
) {
123 chip_name
= "tahiti";
126 chip_name
= "pitcairn";
135 chip_name
= "hainan";
140 /* this memory configuration requires special firmware */
141 if (((RREG32(mmMC_SEQ_MISC0
) & 0xff000000) >> 24) == 0x58)
145 snprintf(fw_name
, sizeof(fw_name
), "radeon/si58_mc.bin");
147 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_mc.bin", chip_name
);
148 err
= request_firmware(&adev
->mc
.fw
, fw_name
, adev
->dev
);
152 err
= amdgpu_ucode_validate(adev
->mc
.fw
);
157 "si_mc: Failed to load firmware \"%s\"\n",
159 release_firmware(adev
->mc
.fw
);
165 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device
*adev
)
167 const __le32
*new_fw_data
= NULL
;
169 const __le32
*new_io_mc_regs
= NULL
;
170 int i
, regs_size
, ucode_size
;
171 const struct mc_firmware_header_v1_0
*hdr
;
176 hdr
= (const struct mc_firmware_header_v1_0
*)adev
->mc
.fw
->data
;
178 amdgpu_ucode_print_mc_hdr(&hdr
->header
);
180 adev
->mc
.fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
181 regs_size
= le32_to_cpu(hdr
->io_debug_size_bytes
) / (4 * 2);
182 new_io_mc_regs
= (const __le32
*)
183 (adev
->mc
.fw
->data
+ le32_to_cpu(hdr
->io_debug_array_offset_bytes
));
184 ucode_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
185 new_fw_data
= (const __le32
*)
186 (adev
->mc
.fw
->data
+ le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
188 running
= RREG32(mmMC_SEQ_SUP_CNTL
) & MC_SEQ_SUP_CNTL__RUN_MASK
;
192 /* reset the engine and set to writable */
193 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000008);
194 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000010);
196 /* load mc io regs */
197 for (i
= 0; i
< regs_size
; i
++) {
198 WREG32(mmMC_SEQ_IO_DEBUG_INDEX
, le32_to_cpup(new_io_mc_regs
++));
199 WREG32(mmMC_SEQ_IO_DEBUG_DATA
, le32_to_cpup(new_io_mc_regs
++));
201 /* load the MC ucode */
202 for (i
= 0; i
< ucode_size
; i
++) {
203 WREG32(mmMC_SEQ_SUP_PGM
, le32_to_cpup(new_fw_data
++));
206 /* put the engine back into the active state */
207 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000008);
208 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000004);
209 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000001);
211 /* wait for training to complete */
212 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
213 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL
) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK
)
217 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
218 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL
) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK
)
228 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device
*adev
,
229 struct amdgpu_mc
*mc
)
231 if (mc
->mc_vram_size
> 0xFFC0000000ULL
) {
232 dev_warn(adev
->dev
, "limiting VRAM\n");
233 mc
->real_vram_size
= 0xFFC0000000ULL
;
234 mc
->mc_vram_size
= 0xFFC0000000ULL
;
236 amdgpu_vram_location(adev
, &adev
->mc
, 0);
237 adev
->mc
.gtt_base_align
= 0;
238 amdgpu_gtt_location(adev
, mc
);
241 static void gmc_v6_0_mc_program(struct amdgpu_device
*adev
)
243 struct amdgpu_mode_mc_save save
;
248 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x6) {
249 WREG32((0xb05 + j
), 0x00000000);
250 WREG32((0xb06 + j
), 0x00000000);
251 WREG32((0xb07 + j
), 0x00000000);
252 WREG32((0xb08 + j
), 0x00000000);
253 WREG32((0xb09 + j
), 0x00000000);
255 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL
, 0);
257 if (adev
->mode_info
.num_crtc
)
258 amdgpu_display_set_vga_render_state(adev
, false);
260 gmc_v6_0_mc_stop(adev
, &save
);
262 if (gmc_v6_0_wait_for_idle((void *)adev
)) {
263 dev_warn(adev
->dev
, "Wait for MC idle timedout !\n");
266 WREG32(mmVGA_HDP_CONTROL
, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK
);
267 /* Update configuration */
268 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR
,
269 adev
->mc
.vram_start
>> 12);
270 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
271 adev
->mc
.vram_end
>> 12);
272 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
,
273 adev
->vram_scratch
.gpu_addr
>> 12);
274 tmp
= ((adev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
275 tmp
|= ((adev
->mc
.vram_start
>> 24) & 0xFFFF);
276 WREG32(mmMC_VM_FB_LOCATION
, tmp
);
277 /* XXX double check these! */
278 WREG32(mmHDP_NONSURFACE_BASE
, (adev
->mc
.vram_start
>> 8));
279 WREG32(mmHDP_NONSURFACE_INFO
, (2 << 7) | (1 << 30));
280 WREG32(mmHDP_NONSURFACE_SIZE
, 0x3FFFFFFF);
281 WREG32(mmMC_VM_AGP_BASE
, 0);
282 WREG32(mmMC_VM_AGP_TOP
, 0x0FFFFFFF);
283 WREG32(mmMC_VM_AGP_BOT
, 0x0FFFFFFF);
285 if (gmc_v6_0_wait_for_idle((void *)adev
)) {
286 dev_warn(adev
->dev
, "Wait for MC idle timedout !\n");
288 gmc_v6_0_mc_resume(adev
, &save
);
291 static int gmc_v6_0_mc_init(struct amdgpu_device
*adev
)
295 int chansize
, numchan
;
297 tmp
= RREG32(mmMC_ARB_RAMCFG
);
298 if (tmp
& (1 << 11)) {
300 } else if (tmp
& MC_ARB_RAMCFG__CHANSIZE_MASK
) {
305 tmp
= RREG32(mmMC_SHARED_CHMAP
);
306 switch ((tmp
& MC_SHARED_CHMAP__NOOFCHAN_MASK
) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT
) {
336 adev
->mc
.vram_width
= numchan
* chansize
;
337 /* Could aper size report 0 ? */
338 adev
->mc
.aper_base
= pci_resource_start(adev
->pdev
, 0);
339 adev
->mc
.aper_size
= pci_resource_len(adev
->pdev
, 0);
340 /* size in MB on si */
341 adev
->mc
.mc_vram_size
= RREG32(mmCONFIG_MEMSIZE
) * 1024ULL * 1024ULL;
342 adev
->mc
.real_vram_size
= RREG32(mmCONFIG_MEMSIZE
) * 1024ULL * 1024ULL;
343 adev
->mc
.visible_vram_size
= adev
->mc
.aper_size
;
345 /* unless the user had overridden it, set the gart
346 * size equal to the 1024 or vram, whichever is larger.
348 if (amdgpu_gart_size
== -1)
349 adev
->mc
.gtt_size
= max((1024ULL << 20), adev
->mc
.mc_vram_size
);
351 adev
->mc
.gtt_size
= (uint64_t)amdgpu_gart_size
<< 20;
353 gmc_v6_0_vram_gtt_location(adev
, &adev
->mc
);
358 static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device
*adev
,
361 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL
, 0);
363 WREG32(mmVM_INVALIDATE_REQUEST
, 1 << vmid
);
366 static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device
*adev
,
368 uint32_t gpu_page_idx
,
372 void __iomem
*ptr
= (void *)cpu_pt_addr
;
375 value
= addr
& 0xFFFFFFFFFFFFF000ULL
;
377 writeq(value
, ptr
+ (gpu_page_idx
* 8));
382 static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device
*adev
,
385 uint64_t pte_flag
= 0;
387 if (flags
& AMDGPU_VM_PAGE_READABLE
)
388 pte_flag
|= AMDGPU_PTE_READABLE
;
389 if (flags
& AMDGPU_VM_PAGE_WRITEABLE
)
390 pte_flag
|= AMDGPU_PTE_WRITEABLE
;
391 if (flags
& AMDGPU_VM_PAGE_PRT
)
392 pte_flag
|= AMDGPU_PTE_PRT
;
397 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device
*adev
,
402 tmp
= RREG32(mmVM_CONTEXT1_CNTL
);
403 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
404 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
405 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
406 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
407 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
408 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
409 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
410 VALID_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
411 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
412 READ_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
413 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
414 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
415 WREG32(mmVM_CONTEXT1_CNTL
, tmp
);
419 + * gmc_v8_0_set_prt - set PRT VM fault
421 + * @adev: amdgpu_device pointer
422 + * @enable: enable/disable VM fault handling for PRT
424 static void gmc_v6_0_set_prt(struct amdgpu_device
*adev
, bool enable
)
428 if (enable
&& !adev
->mc
.prt_warning
) {
429 dev_warn(adev
->dev
, "Disabling VM faults because of PRT request!\n");
430 adev
->mc
.prt_warning
= true;
433 tmp
= RREG32(mmVM_PRT_CNTL
);
434 tmp
= REG_SET_FIELD(tmp
, VM_PRT_CNTL
,
435 CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS
,
437 tmp
= REG_SET_FIELD(tmp
, VM_PRT_CNTL
,
438 TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS
,
440 tmp
= REG_SET_FIELD(tmp
, VM_PRT_CNTL
,
441 L2_CACHE_STORE_INVALID_ENTRIES
,
443 tmp
= REG_SET_FIELD(tmp
, VM_PRT_CNTL
,
444 L1_TLB_STORE_INVALID_ENTRIES
,
446 WREG32(mmVM_PRT_CNTL
, tmp
);
449 uint32_t low
= AMDGPU_VA_RESERVED_SIZE
>> AMDGPU_GPU_PAGE_SHIFT
;
450 uint32_t high
= adev
->vm_manager
.max_pfn
;
452 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR
, low
);
453 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR
, low
);
454 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR
, low
);
455 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR
, low
);
456 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR
, high
);
457 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR
, high
);
458 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR
, high
);
459 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR
, high
);
461 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR
, 0xfffffff);
462 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR
, 0xfffffff);
463 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR
, 0xfffffff);
464 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR
, 0xfffffff);
465 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR
, 0x0);
466 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR
, 0x0);
467 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR
, 0x0);
468 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR
, 0x0);
472 static int gmc_v6_0_gart_enable(struct amdgpu_device
*adev
)
476 if (adev
->gart
.robj
== NULL
) {
477 dev_err(adev
->dev
, "No VRAM object for PCIE GART.\n");
480 r
= amdgpu_gart_table_vram_pin(adev
);
483 /* Setup TLB control */
484 WREG32(mmMC_VM_MX_L1_TLB_CNTL
,
486 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK
|
487 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK
|
488 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK
|
489 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK
|
490 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT
));
493 VM_L2_CNTL__ENABLE_L2_CACHE_MASK
|
494 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK
|
495 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK
|
496 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK
|
497 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT
) |
498 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT
));
499 WREG32(mmVM_L2_CNTL2
,
500 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK
|
501 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK
);
502 WREG32(mmVM_L2_CNTL3
,
503 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK
|
504 (4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT
) |
505 (4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT
));
507 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR
, adev
->mc
.gtt_start
>> 12);
508 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR
, adev
->mc
.gtt_end
>> 12);
509 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, adev
->gart
.table_addr
>> 12);
510 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
511 (u32
)(adev
->dummy_page
.addr
>> 12));
512 WREG32(mmVM_CONTEXT0_CNTL2
, 0);
513 WREG32(mmVM_CONTEXT0_CNTL
,
514 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK
|
515 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT
) |
516 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
);
522 /* empty context1-15 */
523 /* set vm size, must be a multiple of 4 */
524 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR
, 0);
525 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR
, adev
->vm_manager
.max_pfn
- 1);
526 /* Assign the pt base to something valid for now; the pts used for
527 * the VMs are determined by the application and setup and assigned
528 * on the fly in the vm part of radeon_gart.c
530 for (i
= 1; i
< 16; i
++) {
532 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ i
,
533 adev
->gart
.table_addr
>> 12);
535 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ i
- 8,
536 adev
->gart
.table_addr
>> 12);
539 /* enable context1-15 */
540 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR
,
541 (u32
)(adev
->dummy_page
.addr
>> 12));
542 WREG32(mmVM_CONTEXT1_CNTL2
, 4);
543 WREG32(mmVM_CONTEXT1_CNTL
,
544 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK
|
545 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT
) |
546 ((adev
->vm_manager
.block_size
- 9)
547 << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
));
548 if (amdgpu_vm_fault_stop
== AMDGPU_VM_FAULT_STOP_ALWAYS
)
549 gmc_v6_0_set_fault_enable_default(adev
, false);
551 gmc_v6_0_set_fault_enable_default(adev
, true);
553 gmc_v6_0_gart_flush_gpu_tlb(adev
, 0);
554 dev_info(adev
->dev
, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
555 (unsigned)(adev
->mc
.gtt_size
>> 20),
556 (unsigned long long)adev
->gart
.table_addr
);
557 adev
->gart
.ready
= true;
561 static int gmc_v6_0_gart_init(struct amdgpu_device
*adev
)
565 if (adev
->gart
.robj
) {
566 dev_warn(adev
->dev
, "gmc_v6_0 PCIE GART already initialized\n");
569 r
= amdgpu_gart_init(adev
);
572 adev
->gart
.table_size
= adev
->gart
.num_gpu_pages
* 8;
573 adev
->gart
.gart_pte_flags
= 0;
574 return amdgpu_gart_table_vram_alloc(adev
);
577 static void gmc_v6_0_gart_disable(struct amdgpu_device
*adev
)
581 for (i = 1; i < 16; ++i) {
584 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
586 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
587 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
590 /* Disable all tables */
591 WREG32(mmVM_CONTEXT0_CNTL
, 0);
592 WREG32(mmVM_CONTEXT1_CNTL
, 0);
593 /* Setup TLB control */
594 WREG32(mmMC_VM_MX_L1_TLB_CNTL
,
595 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK
|
596 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT
));
599 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK
|
600 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK
|
601 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT
) |
602 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT
));
603 WREG32(mmVM_L2_CNTL2
, 0);
604 WREG32(mmVM_L2_CNTL3
,
605 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK
|
606 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT
));
607 amdgpu_gart_table_vram_unpin(adev
);
610 static void gmc_v6_0_gart_fini(struct amdgpu_device
*adev
)
612 amdgpu_gart_table_vram_free(adev
);
613 amdgpu_gart_fini(adev
);
616 static int gmc_v6_0_vm_init(struct amdgpu_device
*adev
)
620 * VMID 0 is reserved for System
621 * amdgpu graphics/compute will use VMIDs 1-7
622 * amdkfd will use VMIDs 8-15
624 adev
->vm_manager
.id_mgr
[0].num_ids
= AMDGPU_NUM_OF_VMIDS
;
625 adev
->vm_manager
.num_level
= 1;
626 amdgpu_vm_manager_init(adev
);
628 /* base offset of vram pages */
629 if (adev
->flags
& AMD_IS_APU
) {
630 u64 tmp
= RREG32(mmMC_VM_FB_OFFSET
);
632 adev
->vm_manager
.vram_base_offset
= tmp
;
634 adev
->vm_manager
.vram_base_offset
= 0;
639 static void gmc_v6_0_vm_fini(struct amdgpu_device
*adev
)
643 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device
*adev
,
644 u32 status
, u32 addr
, u32 mc_client
)
647 u32 vmid
= REG_GET_FIELD(status
, VM_CONTEXT1_PROTECTION_FAULT_STATUS
, VMID
);
648 u32 protections
= REG_GET_FIELD(status
, VM_CONTEXT1_PROTECTION_FAULT_STATUS
,
650 char block
[5] = { mc_client
>> 24, (mc_client
>> 16) & 0xff,
651 (mc_client
>> 8) & 0xff, mc_client
& 0xff, 0 };
653 mc_id
= REG_GET_FIELD(status
, VM_CONTEXT1_PROTECTION_FAULT_STATUS
,
656 dev_err(adev
->dev
, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
657 protections
, vmid
, addr
,
658 REG_GET_FIELD(status
, VM_CONTEXT1_PROTECTION_FAULT_STATUS
,
660 "write" : "read", block
, mc_client
, mc_id
);
664 static const u32 mc_cg_registers[] = {
676 static const u32 mc_cg_ls_en[] = {
677 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
678 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
679 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
680 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
681 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
682 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
683 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
684 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
685 VM_L2_CG__MEM_LS_ENABLE_MASK,
688 static const u32 mc_cg_en[] = {
689 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
690 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
691 MC_HUB_MISC_VM_CG__ENABLE_MASK,
692 MC_XPB_CLK_GAT__ENABLE_MASK,
693 ATC_MISC_CG__ENABLE_MASK,
694 MC_CITF_MISC_WR_CG__ENABLE_MASK,
695 MC_CITF_MISC_RD_CG__ENABLE_MASK,
696 MC_CITF_MISC_VM_CG__ENABLE_MASK,
697 VM_L2_CG__ENABLE_MASK,
700 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
706 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
707 orig = data = RREG32(mc_cg_registers[i]);
708 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
709 data |= mc_cg_ls_en[i];
711 data &= ~mc_cg_ls_en[i];
713 WREG32(mc_cg_registers[i], data);
717 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
723 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
724 orig = data = RREG32(mc_cg_registers[i]);
725 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
728 data &= ~mc_cg_en[i];
730 WREG32(mc_cg_registers[i], data);
734 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
739 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
741 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
742 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
743 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
744 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
745 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
747 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
748 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
749 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
750 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
754 WREG32_PCIE(ixPCIE_CNTL2, data);
757 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
762 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
764 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
765 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
767 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
770 WREG32(mmHDP_HOST_PATH_CNTL, data);
773 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
778 orig = data = RREG32(mmHDP_MEM_POWER_LS);
780 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
781 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
783 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
786 WREG32(mmHDP_MEM_POWER_LS, data);
790 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type
)
792 switch (mc_seq_vram_type
) {
793 case MC_SEQ_MISC0__MT__GDDR1
:
794 return AMDGPU_VRAM_TYPE_GDDR1
;
795 case MC_SEQ_MISC0__MT__DDR2
:
796 return AMDGPU_VRAM_TYPE_DDR2
;
797 case MC_SEQ_MISC0__MT__GDDR3
:
798 return AMDGPU_VRAM_TYPE_GDDR3
;
799 case MC_SEQ_MISC0__MT__GDDR4
:
800 return AMDGPU_VRAM_TYPE_GDDR4
;
801 case MC_SEQ_MISC0__MT__GDDR5
:
802 return AMDGPU_VRAM_TYPE_GDDR5
;
803 case MC_SEQ_MISC0__MT__DDR3
:
804 return AMDGPU_VRAM_TYPE_DDR3
;
806 return AMDGPU_VRAM_TYPE_UNKNOWN
;
810 static int gmc_v6_0_early_init(void *handle
)
812 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
814 gmc_v6_0_set_gart_funcs(adev
);
815 gmc_v6_0_set_irq_funcs(adev
);
817 if (adev
->flags
& AMD_IS_APU
) {
818 adev
->mc
.vram_type
= AMDGPU_VRAM_TYPE_UNKNOWN
;
820 u32 tmp
= RREG32(mmMC_SEQ_MISC0
);
821 tmp
&= MC_SEQ_MISC0__MT__MASK
;
822 adev
->mc
.vram_type
= gmc_v6_0_convert_vram_type(tmp
);
828 static int gmc_v6_0_late_init(void *handle
)
830 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
832 if (amdgpu_vm_fault_stop
!= AMDGPU_VM_FAULT_STOP_ALWAYS
)
833 return amdgpu_irq_get(adev
, &adev
->mc
.vm_fault
, 0);
838 static int gmc_v6_0_sw_init(void *handle
)
842 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
844 r
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_LEGACY
, 146, &adev
->mc
.vm_fault
);
848 r
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_LEGACY
, 147, &adev
->mc
.vm_fault
);
852 amdgpu_vm_adjust_size(adev
, 64);
853 adev
->vm_manager
.max_pfn
= adev
->vm_manager
.vm_size
<< 18;
855 adev
->mc
.mc_mask
= 0xffffffffffULL
;
857 adev
->need_dma32
= false;
858 dma_bits
= adev
->need_dma32
? 32 : 40;
859 r
= pci_set_dma_mask(adev
->pdev
, DMA_BIT_MASK(dma_bits
));
861 adev
->need_dma32
= true;
863 dev_warn(adev
->dev
, "amdgpu: No suitable DMA available.\n");
865 r
= pci_set_consistent_dma_mask(adev
->pdev
, DMA_BIT_MASK(dma_bits
));
867 pci_set_consistent_dma_mask(adev
->pdev
, DMA_BIT_MASK(32));
868 dev_warn(adev
->dev
, "amdgpu: No coherent DMA available.\n");
871 r
= gmc_v6_0_init_microcode(adev
);
873 dev_err(adev
->dev
, "Failed to load mc firmware!\n");
877 r
= gmc_v6_0_mc_init(adev
);
881 r
= amdgpu_bo_init(adev
);
885 r
= gmc_v6_0_gart_init(adev
);
889 if (!adev
->vm_manager
.enabled
) {
890 r
= gmc_v6_0_vm_init(adev
);
892 dev_err(adev
->dev
, "vm manager initialization failed (%d).\n", r
);
895 adev
->vm_manager
.enabled
= true;
901 static int gmc_v6_0_sw_fini(void *handle
)
903 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
905 if (adev
->vm_manager
.enabled
) {
906 gmc_v6_0_vm_fini(adev
);
907 adev
->vm_manager
.enabled
= false;
909 gmc_v6_0_gart_fini(adev
);
910 amdgpu_gem_force_release(adev
);
911 amdgpu_bo_fini(adev
);
916 static int gmc_v6_0_hw_init(void *handle
)
919 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
921 gmc_v6_0_mc_program(adev
);
923 if (!(adev
->flags
& AMD_IS_APU
)) {
924 r
= gmc_v6_0_mc_load_microcode(adev
);
926 dev_err(adev
->dev
, "Failed to load MC firmware!\n");
931 r
= gmc_v6_0_gart_enable(adev
);
938 static int gmc_v6_0_hw_fini(void *handle
)
940 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
942 amdgpu_irq_put(adev
, &adev
->mc
.vm_fault
, 0);
943 gmc_v6_0_gart_disable(adev
);
948 static int gmc_v6_0_suspend(void *handle
)
950 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
952 if (adev
->vm_manager
.enabled
) {
953 gmc_v6_0_vm_fini(adev
);
954 adev
->vm_manager
.enabled
= false;
956 gmc_v6_0_hw_fini(adev
);
961 static int gmc_v6_0_resume(void *handle
)
964 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
966 r
= gmc_v6_0_hw_init(adev
);
970 if (!adev
->vm_manager
.enabled
) {
971 r
= gmc_v6_0_vm_init(adev
);
973 dev_err(adev
->dev
, "vm manager initialization failed (%d).\n", r
);
976 adev
->vm_manager
.enabled
= true;
982 static bool gmc_v6_0_is_idle(void *handle
)
984 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
985 u32 tmp
= RREG32(mmSRBM_STATUS
);
987 if (tmp
& (SRBM_STATUS__MCB_BUSY_MASK
| SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK
|
988 SRBM_STATUS__MCC_BUSY_MASK
| SRBM_STATUS__MCD_BUSY_MASK
| SRBM_STATUS__VMC_BUSY_MASK
))
994 static int gmc_v6_0_wait_for_idle(void *handle
)
998 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1000 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1001 tmp
= RREG32(mmSRBM_STATUS
) & (SRBM_STATUS__MCB_BUSY_MASK
|
1002 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK
|
1003 SRBM_STATUS__MCC_BUSY_MASK
|
1004 SRBM_STATUS__MCD_BUSY_MASK
|
1005 SRBM_STATUS__VMC_BUSY_MASK
);
1014 static int gmc_v6_0_soft_reset(void *handle
)
1016 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1017 struct amdgpu_mode_mc_save save
;
1018 u32 srbm_soft_reset
= 0;
1019 u32 tmp
= RREG32(mmSRBM_STATUS
);
1021 if (tmp
& SRBM_STATUS__VMC_BUSY_MASK
)
1022 srbm_soft_reset
= REG_SET_FIELD(srbm_soft_reset
,
1023 SRBM_SOFT_RESET
, SOFT_RESET_VMC
, 1);
1025 if (tmp
& (SRBM_STATUS__MCB_BUSY_MASK
| SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK
|
1026 SRBM_STATUS__MCC_BUSY_MASK
| SRBM_STATUS__MCD_BUSY_MASK
)) {
1027 if (!(adev
->flags
& AMD_IS_APU
))
1028 srbm_soft_reset
= REG_SET_FIELD(srbm_soft_reset
,
1029 SRBM_SOFT_RESET
, SOFT_RESET_MC
, 1);
1032 if (srbm_soft_reset
) {
1033 gmc_v6_0_mc_stop(adev
, &save
);
1034 if (gmc_v6_0_wait_for_idle(adev
)) {
1035 dev_warn(adev
->dev
, "Wait for GMC idle timed out !\n");
1039 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1040 tmp
|= srbm_soft_reset
;
1041 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
1042 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1043 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1047 tmp
&= ~srbm_soft_reset
;
1048 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1049 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1053 gmc_v6_0_mc_resume(adev
, &save
);
1060 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device
*adev
,
1061 struct amdgpu_irq_src
*src
,
1063 enum amdgpu_interrupt_state state
)
1066 u32 bits
= (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1067 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1068 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1069 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1070 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1071 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
);
1074 case AMDGPU_IRQ_STATE_DISABLE
:
1075 tmp
= RREG32(mmVM_CONTEXT0_CNTL
);
1077 WREG32(mmVM_CONTEXT0_CNTL
, tmp
);
1078 tmp
= RREG32(mmVM_CONTEXT1_CNTL
);
1080 WREG32(mmVM_CONTEXT1_CNTL
, tmp
);
1082 case AMDGPU_IRQ_STATE_ENABLE
:
1083 tmp
= RREG32(mmVM_CONTEXT0_CNTL
);
1085 WREG32(mmVM_CONTEXT0_CNTL
, tmp
);
1086 tmp
= RREG32(mmVM_CONTEXT1_CNTL
);
1088 WREG32(mmVM_CONTEXT1_CNTL
, tmp
);
1097 static int gmc_v6_0_process_interrupt(struct amdgpu_device
*adev
,
1098 struct amdgpu_irq_src
*source
,
1099 struct amdgpu_iv_entry
*entry
)
1103 addr
= RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR
);
1104 status
= RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS
);
1105 WREG32_P(mmVM_CONTEXT1_CNTL2
, 1, ~1);
1107 if (!addr
&& !status
)
1110 if (amdgpu_vm_fault_stop
== AMDGPU_VM_FAULT_STOP_FIRST
)
1111 gmc_v6_0_set_fault_enable_default(adev
, false);
1113 if (printk_ratelimit()) {
1114 dev_err(adev
->dev
, "GPU fault detected: %d 0x%08x\n",
1115 entry
->src_id
, entry
->src_data
[0]);
1116 dev_err(adev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1118 dev_err(adev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1120 gmc_v6_0_vm_decode_fault(adev
, status
, addr
, 0);
1126 static int gmc_v6_0_set_clockgating_state(void *handle
,
1127 enum amd_clockgating_state state
)
1132 static int gmc_v6_0_set_powergating_state(void *handle
,
1133 enum amd_powergating_state state
)
1138 static const struct amd_ip_funcs gmc_v6_0_ip_funcs
= {
1140 .early_init
= gmc_v6_0_early_init
,
1141 .late_init
= gmc_v6_0_late_init
,
1142 .sw_init
= gmc_v6_0_sw_init
,
1143 .sw_fini
= gmc_v6_0_sw_fini
,
1144 .hw_init
= gmc_v6_0_hw_init
,
1145 .hw_fini
= gmc_v6_0_hw_fini
,
1146 .suspend
= gmc_v6_0_suspend
,
1147 .resume
= gmc_v6_0_resume
,
1148 .is_idle
= gmc_v6_0_is_idle
,
1149 .wait_for_idle
= gmc_v6_0_wait_for_idle
,
1150 .soft_reset
= gmc_v6_0_soft_reset
,
1151 .set_clockgating_state
= gmc_v6_0_set_clockgating_state
,
1152 .set_powergating_state
= gmc_v6_0_set_powergating_state
,
1155 static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs
= {
1156 .flush_gpu_tlb
= gmc_v6_0_gart_flush_gpu_tlb
,
1157 .set_pte_pde
= gmc_v6_0_gart_set_pte_pde
,
1158 .set_prt
= gmc_v6_0_set_prt
,
1159 .get_vm_pte_flags
= gmc_v6_0_get_vm_pte_flags
1162 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs
= {
1163 .set
= gmc_v6_0_vm_fault_interrupt_state
,
1164 .process
= gmc_v6_0_process_interrupt
,
1167 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device
*adev
)
1169 if (adev
->gart
.gart_funcs
== NULL
)
1170 adev
->gart
.gart_funcs
= &gmc_v6_0_gart_funcs
;
1173 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device
*adev
)
1175 adev
->mc
.vm_fault
.num_types
= 1;
1176 adev
->mc
.vm_fault
.funcs
= &gmc_v6_0_irq_funcs
;
1179 const struct amdgpu_ip_block_version gmc_v6_0_ip_block
=
1181 .type
= AMD_IP_BLOCK_TYPE_GMC
,
1185 .funcs
= &gmc_v6_0_ip_funcs
,