drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "cikd.h"
  27 #include "cik.h"
  28 #include "gmc_v7_0.h"
  29 #include "amdgpu_ucode.h"
  30
  31 #include "bif/bif_4_1_d.h"
  32 #include "bif/bif_4_1_sh_mask.h"
  33
  34 #include "gmc/gmc_7_1_d.h"
  35 #include "gmc/gmc_7_1_sh_mask.h"
  36
  37 #include "oss/oss_2_0_d.h"
  38 #include "oss/oss_2_0_sh_mask.h"
  39
  40 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev);
  41 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  42 static int gmc_v7_0_wait_for_idle(void *handle);
  43
  44 MODULE_FIRMWARE("radeon/bonaire_mc.bin");
  45 MODULE_FIRMWARE("radeon/hawaii_mc.bin");
  46 MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
  47
  48 static const u32 golden_settings_iceland_a11[] =
  49 {
  50         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  51         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  52         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  53         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  54 };
  55
  56 static const u32 iceland_mgcg_cgcg_init[] =
  57 {
  58         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  59 };
  60
  61 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
  62 {
  63         switch (adev->asic_type) {
  64         case CHIP_TOPAZ:
  65                 amdgpu_program_register_sequence(adev,
  66                                                  iceland_mgcg_cgcg_init,
  67                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  68                 amdgpu_program_register_sequence(adev,
  69                                                  golden_settings_iceland_a11,
  70                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
  71                 break;
  72         default:
  73                 break;
  74         }
  75 }
  76
  77 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev,
  78                              struct amdgpu_mode_mc_save *save)
  79 {
  80         u32 blackout;
  81
  82         if (adev->mode_info.num_crtc)
  83                 amdgpu_display_stop_mc_access(adev, save);
  84
  85         gmc_v7_0_wait_for_idle((void *)adev);
  86
  87         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  88         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  89                 /* Block CPU access */
  90                 WREG32(mmBIF_FB_EN, 0);
  91                 /* blackout the MC */
  92                 blackout = REG_SET_FIELD(blackout,
  93                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  94                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  95         }
  96         /* wait for the MC to settle */
  97         udelay(100);
  98 }
  99
 100 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev,
 101                                struct amdgpu_mode_mc_save *save)
 102 {
 103         u32 tmp;
 104
 105         /* unblackout the MC */
 106         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 107         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 108         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 109         /* allow CPU access */
 110         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 111         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 112         WREG32(mmBIF_FB_EN, tmp);
 113
 114         if (adev->mode_info.num_crtc)
 115                 amdgpu_display_resume_mc_access(adev, save);
 116 }
 117
 118 /**
 119  * gmc_v7_0_init_microcode - load ucode images from disk
 120  *
 121  * @adev: amdgpu_device pointer
 122  *
 123  * Use the firmware interface to load the ucode images into
 124  * the driver (not loaded into hw).
 125  * Returns 0 on success, error on failure.
 126  */
 127 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
 128 {
 129         const char *chip_name;
 130         char fw_name[30];
 131         int err;
 132
 133         DRM_DEBUG("\n");
 134
 135         switch (adev->asic_type) {
 136         case CHIP_BONAIRE:
 137                 chip_name = "bonaire";
 138                 break;
 139         case CHIP_HAWAII:
 140                 chip_name = "hawaii";
 141                 break;
 142         case CHIP_TOPAZ:
 143                 chip_name = "topaz";
 144                 break;
 145         case CHIP_KAVERI:
 146         case CHIP_KABINI:
 147         case CHIP_MULLINS:
 148                 return 0;
 149         default: BUG();
 150         }
 151
 152         if (adev->asic_type == CHIP_TOPAZ)
 153                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 154         else
 155                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 156
 157         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 158         if (err)
 159                 goto out;
 160         err = amdgpu_ucode_validate(adev->mc.fw);
 161
 162 out:
 163         if (err) {
 164                 printk(KERN_ERR
 165                        "cik_mc: Failed to load firmware \"%s\"\n",
 166                        fw_name);
 167                 release_firmware(adev->mc.fw);
 168                 adev->mc.fw = NULL;
 169         }
 170         return err;
 171 }
 172
 173 /**
 174  * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
 175  *
 176  * @adev: amdgpu_device pointer
 177  *
 178  * Load the GDDR MC ucode into the hw (CIK).
 179  * Returns 0 on success, error on failure.
 180  */
 181 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
 182 {
 183         const struct mc_firmware_header_v1_0 *hdr;
 184         const __le32 *fw_data = NULL;
 185         const __le32 *io_mc_regs = NULL;
 186         u32 running, blackout = 0;
 187         int i, ucode_size, regs_size;
 188
 189         if (!adev->mc.fw)
 190                 return -EINVAL;
 191
 192         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 193         amdgpu_ucode_print_mc_hdr(&hdr->header);
 194
 195         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 196         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 197         io_mc_regs = (const __le32 *)
 198                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 199         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 200         fw_data = (const __le32 *)
 201                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 202
 203         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 204
 205         if (running == 0) {
 206                 if (running) {
 207                         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 208                         WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
 209                 }
 210
 211                 /* reset the engine and set to writable */
 212                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 213                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 214
 215                 /* load mc io regs */
 216                 for (i = 0; i < regs_size; i++) {
 217                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 218                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 219                 }
 220                 /* load the MC ucode */
 221                 for (i = 0; i < ucode_size; i++)
 222                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 223
 224                 /* put the engine back into the active state */
 225                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 226                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 227                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 228
 229                 /* wait for training to complete */
 230                 for (i = 0; i < adev->usec_timeout; i++) {
 231                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 232                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 233                                 break;
 234                         udelay(1);
 235                 }
 236                 for (i = 0; i < adev->usec_timeout; i++) {
 237                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 238                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 239                                 break;
 240                         udelay(1);
 241                 }
 242
 243                 if (running)
 244                         WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 245         }
 246
 247         return 0;
 248 }
 249
 250 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
 251                                        struct amdgpu_mc *mc)
 252 {
 253         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 254                 /* leave room for at least 1024M GTT */
 255                 dev_warn(adev->dev, "limiting VRAM\n");
 256                 mc->real_vram_size = 0xFFC0000000ULL;
 257                 mc->mc_vram_size = 0xFFC0000000ULL;
 258         }
 259         amdgpu_vram_location(adev, &adev->mc, 0);
 260         adev->mc.gtt_base_align = 0;
 261         amdgpu_gtt_location(adev, mc);
 262 }
 263
 264 /**
 265  * gmc_v7_0_mc_program - program the GPU memory controller
 266  *
 267  * @adev: amdgpu_device pointer
 268  *
 269  * Set the location of vram, gart, and AGP in the GPU's
 270  * physical address space (CIK).
 271  */
 272 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
 273 {
 274         struct amdgpu_mode_mc_save save;
 275         u32 tmp;
 276         int i, j;
 277
 278         /* Initialize HDP */
 279         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 280                 WREG32((0xb05 + j), 0x00000000);
 281                 WREG32((0xb06 + j), 0x00000000);
 282                 WREG32((0xb07 + j), 0x00000000);
 283                 WREG32((0xb08 + j), 0x00000000);
 284                 WREG32((0xb09 + j), 0x00000000);
 285         }
 286         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 287
 288         if (adev->mode_info.num_crtc)
 289                 amdgpu_display_set_vga_render_state(adev, false);
 290
 291         gmc_v7_0_mc_stop(adev, &save);
 292         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 293                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 294         }
 295         /* Update configuration */
 296         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 297                adev->mc.vram_start >> 12);
 298         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 299                adev->mc.vram_end >> 12);
 300         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 301                adev->vram_scratch.gpu_addr >> 12);
 302         tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 303         tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 304         WREG32(mmMC_VM_FB_LOCATION, tmp);
 305         /* XXX double check these! */
 306         WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 307         WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 308         WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 309         WREG32(mmMC_VM_AGP_BASE, 0);
 310         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 311         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 312         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 313                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 314         }
 315         gmc_v7_0_mc_resume(adev, &save);
 316
 317         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 318
 319         tmp = RREG32(mmHDP_MISC_CNTL);
 320         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 321         WREG32(mmHDP_MISC_CNTL, tmp);
 322
 323         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 324         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 325 }
 326
 327 /**
 328  * gmc_v7_0_mc_init - initialize the memory controller driver params
 329  *
 330  * @adev: amdgpu_device pointer
 331  *
 332  * Look up the amount of vram, vram width, and decide how to place
 333  * vram and gart within the GPU's physical address space (CIK).
 334  * Returns 0 for success.
 335  */
 336 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
 337 {
 338         u32 tmp;
 339         int chansize, numchan;
 340
 341         /* Get VRAM informations */
 342         tmp = RREG32(mmMC_ARB_RAMCFG);
 343         if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 344                 chansize = 64;
 345         } else {
 346                 chansize = 32;
 347         }
 348         tmp = RREG32(mmMC_SHARED_CHMAP);
 349         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 350         case 0:
 351         default:
 352                 numchan = 1;
 353                 break;
 354         case 1:
 355                 numchan = 2;
 356                 break;
 357         case 2:
 358                 numchan = 4;
 359                 break;
 360         case 3:
 361                 numchan = 8;
 362                 break;
 363         case 4:
 364                 numchan = 3;
 365                 break;
 366         case 5:
 367                 numchan = 6;
 368                 break;
 369         case 6:
 370                 numchan = 10;
 371                 break;
 372         case 7:
 373                 numchan = 12;
 374                 break;
 375         case 8:
 376                 numchan = 16;
 377                 break;
 378         }
 379         adev->mc.vram_width = numchan * chansize;
 380         /* Could aper size report 0 ? */
 381         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 382         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 383         /* size in MB on si */
 384         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 385         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 386         adev->mc.visible_vram_size = adev->mc.aper_size;
 387
 388         /* In case the PCI BAR is larger than the actual amount of vram */
 389         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 390                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 391
 392         /* unless the user had overridden it, set the gart
 393          * size equal to the 1024 or vram, whichever is larger.
 394          */
 395         if (amdgpu_gart_size == -1)
 396                 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
 397         else
 398                 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
 399
 400         gmc_v7_0_vram_gtt_location(adev, &adev->mc);
 401
 402         return 0;
 403 }
 404
 405 /*
 406  * GART
 407  * VMID 0 is the physical GPU addresses as used by the kernel.
 408  * VMIDs 1-15 are used for userspace clients and are handled
 409  * by the amdgpu vm/hsa code.
 410  */
 411
 412 /**
 413  * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback
 414  *
 415  * @adev: amdgpu_device pointer
 416  * @vmid: vm instance to flush
 417  *
 418  * Flush the TLB for the requested page table (CIK).
 419  */
 420 static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 421                                         uint32_t vmid)
 422 {
 423         /* flush hdp cache */
 424         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 425
 426         /* bits 0-15 are the VM contexts0-15 */
 427         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 428 }
 429
 430 /**
 431  * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO
 432  *
 433  * @adev: amdgpu_device pointer
 434  * @cpu_pt_addr: cpu address of the page table
 435  * @gpu_page_idx: entry in the page table to update
 436  * @addr: dst addr to write into pte/pde
 437  * @flags: access flags
 438  *
 439  * Update the page tables using the CPU.
 440  */
 441 static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
 442                                      void *cpu_pt_addr,
 443                                      uint32_t gpu_page_idx,
 444                                      uint64_t addr,
 445                                      uint32_t flags)
 446 {
 447         void __iomem *ptr = (void *)cpu_pt_addr;
 448         uint64_t value;
 449
 450         value = addr & 0xFFFFFFFFFFFFF000ULL;
 451         value |= flags;
 452         writeq(value, ptr + (gpu_page_idx * 8));
 453
 454         return 0;
 455 }
 456
 457 /**
 458  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 459  *
 460  * @adev: amdgpu_device pointer
 461  * @value: true redirects VM faults to the default page
 462  */
 463 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
 464                                               bool value)
 465 {
 466         u32 tmp;
 467
 468         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 469         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 470                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 471         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 472                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 473         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 474                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 475         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 476                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 477         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 478                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 479         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 480                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 481         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 482 }
 483
 484 /**
 485  * gmc_v7_0_gart_enable - gart enable
 486  *
 487  * @adev: amdgpu_device pointer
 488  *
 489  * This sets up the TLBs, programs the page tables for VMID0,
 490  * sets up the hw for VMIDs 1-15 which are allocated on
 491  * demand, and sets up the global locations for the LDS, GDS,
 492  * and GPUVM for FSA64 clients (CIK).
 493  * Returns 0 for success, errors for failure.
 494  */
 495 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 496 {
 497         int r, i;
 498         u32 tmp;
 499
 500         if (adev->gart.robj == NULL) {
 501                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 502                 return -EINVAL;
 503         }
 504         r = amdgpu_gart_table_vram_pin(adev);
 505         if (r)
 506                 return r;
 507         /* Setup TLB control */
 508         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 509         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 510         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 511         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 512         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 513         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 514         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 515         /* Setup L2 cache */
 516         tmp = RREG32(mmVM_L2_CNTL);
 517         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 518         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 519         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 520         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 521         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 522         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 523         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 524         WREG32(mmVM_L2_CNTL, tmp);
 525         tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 526         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 527         WREG32(mmVM_L2_CNTL2, tmp);
 528         tmp = RREG32(mmVM_L2_CNTL3);
 529         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 530         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
 531         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
 532         WREG32(mmVM_L2_CNTL3, tmp);
 533         /* setup context0 */
 534         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 535         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
 536         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 537         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 538                         (u32)(adev->dummy_page.addr >> 12));
 539         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 540         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 541         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 542         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 543         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 544         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 545
 546         WREG32(0x575, 0);
 547         WREG32(0x576, 0);
 548         WREG32(0x577, 0);
 549
 550         /* empty context1-15 */
 551         /* FIXME start with 4G, once using 2 level pt switch to full
 552          * vm size space
 553          */
 554         /* set vm size, must be a multiple of 4 */
 555         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 556         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 557         for (i = 1; i < 16; i++) {
 558                 if (i < 8)
 559                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 560                                adev->gart.table_addr >> 12);
 561                 else
 562                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 563                                adev->gart.table_addr >> 12);
 564         }
 565
 566         /* enable context1-15 */
 567         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 568                (u32)(adev->dummy_page.addr >> 12));
 569         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 570         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 571         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 572         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 573         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 574                             amdgpu_vm_block_size - 9);
 575         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 576         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 577                 gmc_v7_0_set_fault_enable_default(adev, false);
 578         else
 579                 gmc_v7_0_set_fault_enable_default(adev, true);
 580
 581         if (adev->asic_type == CHIP_KAVERI) {
 582                 tmp = RREG32(mmCHUB_CONTROL);
 583                 tmp &= ~BYPASS_VM;
 584                 WREG32(mmCHUB_CONTROL, tmp);
 585         }
 586
 587         gmc_v7_0_gart_flush_gpu_tlb(adev, 0);
 588         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 589                  (unsigned)(adev->mc.gtt_size >> 20),
 590                  (unsigned long long)adev->gart.table_addr);
 591         adev->gart.ready = true;
 592         return 0;
 593 }
 594
 595 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
 596 {
 597         int r;
 598
 599         if (adev->gart.robj) {
 600                 WARN(1, "R600 PCIE GART already initialized\n");
 601                 return 0;
 602         }
 603         /* Initialize common gart structure */
 604         r = amdgpu_gart_init(adev);
 605         if (r)
 606                 return r;
 607         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 608         return amdgpu_gart_table_vram_alloc(adev);
 609 }
 610
 611 /**
 612  * gmc_v7_0_gart_disable - gart disable
 613  *
 614  * @adev: amdgpu_device pointer
 615  *
 616  * This disables all VM page table (CIK).
 617  */
 618 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
 619 {
 620         u32 tmp;
 621
 622         /* Disable all tables */
 623         WREG32(mmVM_CONTEXT0_CNTL, 0);
 624         WREG32(mmVM_CONTEXT1_CNTL, 0);
 625         /* Setup TLB control */
 626         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 627         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 628         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 629         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 630         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 631         /* Setup L2 cache */
 632         tmp = RREG32(mmVM_L2_CNTL);
 633         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 634         WREG32(mmVM_L2_CNTL, tmp);
 635         WREG32(mmVM_L2_CNTL2, 0);
 636         amdgpu_gart_table_vram_unpin(adev);
 637 }
 638
 639 /**
 640  * gmc_v7_0_gart_fini - vm fini callback
 641  *
 642  * @adev: amdgpu_device pointer
 643  *
 644  * Tears down the driver GART/VM setup (CIK).
 645  */
 646 static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
 647 {
 648         amdgpu_gart_table_vram_free(adev);
 649         amdgpu_gart_fini(adev);
 650 }
 651
 652 /*
 653  * vm
 654  * VMID 0 is the physical GPU addresses as used by the kernel.
 655  * VMIDs 1-15 are used for userspace clients and are handled
 656  * by the amdgpu vm/hsa code.
 657  */
 658 /**
 659  * gmc_v7_0_vm_init - cik vm init callback
 660  *
 661  * @adev: amdgpu_device pointer
 662  *
 663  * Inits cik specific vm parameters (number of VMs, base of vram for
 664  * VMIDs 1-15) (CIK).
 665  * Returns 0 for success.
 666  */
 667 static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
 668 {
 669         /*
 670          * number of VMs
 671          * VMID 0 is reserved for System
 672          * amdgpu graphics/compute will use VMIDs 1-7
 673          * amdkfd will use VMIDs 8-15
 674          */
 675         adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
 676         amdgpu_vm_manager_init(adev);
 677
 678         /* base offset of vram pages */
 679         if (adev->flags & AMD_IS_APU) {
 680                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 681                 tmp <<= 22;
 682                 adev->vm_manager.vram_base_offset = tmp;
 683         } else
 684                 adev->vm_manager.vram_base_offset = 0;
 685
 686         return 0;
 687 }
 688
 689 /**
 690  * gmc_v7_0_vm_fini - cik vm fini callback
 691  *
 692  * @adev: amdgpu_device pointer
 693  *
 694  * Tear down any asic specific VM setup (CIK).
 695  */
 696 static void gmc_v7_0_vm_fini(struct amdgpu_device *adev)
 697 {
 698 }
 699
 700 /**
 701  * gmc_v7_0_vm_decode_fault - print human readable fault info
 702  *
 703  * @adev: amdgpu_device pointer
 704  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 705  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 706  *
 707  * Print human readable fault information (CIK).
 708  */
 709 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
 710                                      u32 status, u32 addr, u32 mc_client)
 711 {
 712         u32 mc_id;
 713         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 714         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 715                                         PROTECTIONS);
 716         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 717                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 718
 719         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 720                               MEMORY_CLIENT_ID);
 721
 722         printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 723                protections, vmid, addr,
 724                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 725                              MEMORY_CLIENT_RW) ?
 726                "write" : "read", block, mc_client, mc_id);
 727 }
 728
 729
 730 static const u32 mc_cg_registers[] = {
 731         mmMC_HUB_MISC_HUB_CG,
 732         mmMC_HUB_MISC_SIP_CG,
 733         mmMC_HUB_MISC_VM_CG,
 734         mmMC_XPB_CLK_GAT,
 735         mmATC_MISC_CG,
 736         mmMC_CITF_MISC_WR_CG,
 737         mmMC_CITF_MISC_RD_CG,
 738         mmMC_CITF_MISC_VM_CG,
 739         mmVM_L2_CG,
 740 };
 741
 742 static const u32 mc_cg_ls_en[] = {
 743         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 744         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 745         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 746         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 747         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 748         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 749         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 750         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 751         VM_L2_CG__MEM_LS_ENABLE_MASK,
 752 };
 753
 754 static const u32 mc_cg_en[] = {
 755         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 756         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 757         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 758         MC_XPB_CLK_GAT__ENABLE_MASK,
 759         ATC_MISC_CG__ENABLE_MASK,
 760         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 761         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 762         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 763         VM_L2_CG__ENABLE_MASK,
 764 };
 765
 766 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
 767                                   bool enable)
 768 {
 769         int i;
 770         u32 orig, data;
 771
 772         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 773                 orig = data = RREG32(mc_cg_registers[i]);
 774                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 775                         data |= mc_cg_ls_en[i];
 776                 else
 777                         data &= ~mc_cg_ls_en[i];
 778                 if (data != orig)
 779                         WREG32(mc_cg_registers[i], data);
 780         }
 781 }
 782
 783 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
 784                                     bool enable)
 785 {
 786         int i;
 787         u32 orig, data;
 788
 789         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 790                 orig = data = RREG32(mc_cg_registers[i]);
 791                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 792                         data |= mc_cg_en[i];
 793                 else
 794                         data &= ~mc_cg_en[i];
 795                 if (data != orig)
 796                         WREG32(mc_cg_registers[i], data);
 797         }
 798 }
 799
 800 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
 801                                      bool enable)
 802 {
 803         u32 orig, data;
 804
 805         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 806
 807         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 808                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 809                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 810                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 811                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 812         } else {
 813                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 814                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 815                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 816                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 817         }
 818
 819         if (orig != data)
 820                 WREG32_PCIE(ixPCIE_CNTL2, data);
 821 }
 822
 823 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 824                                      bool enable)
 825 {
 826         u32 orig, data;
 827
 828         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 829
 830         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
 831                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 832         else
 833                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 834
 835         if (orig != data)
 836                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 837 }
 838
 839 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
 840                                    bool enable)
 841 {
 842         u32 orig, data;
 843
 844         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 845
 846         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 847                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 848         else
 849                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 850
 851         if (orig != data)
 852                 WREG32(mmHDP_MEM_POWER_LS, data);
 853 }
 854
 855 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
 856 {
 857         switch (mc_seq_vram_type) {
 858         case MC_SEQ_MISC0__MT__GDDR1:
 859                 return AMDGPU_VRAM_TYPE_GDDR1;
 860         case MC_SEQ_MISC0__MT__DDR2:
 861                 return AMDGPU_VRAM_TYPE_DDR2;
 862         case MC_SEQ_MISC0__MT__GDDR3:
 863                 return AMDGPU_VRAM_TYPE_GDDR3;
 864         case MC_SEQ_MISC0__MT__GDDR4:
 865                 return AMDGPU_VRAM_TYPE_GDDR4;
 866         case MC_SEQ_MISC0__MT__GDDR5:
 867                 return AMDGPU_VRAM_TYPE_GDDR5;
 868         case MC_SEQ_MISC0__MT__HBM:
 869                 return AMDGPU_VRAM_TYPE_HBM;
 870         case MC_SEQ_MISC0__MT__DDR3:
 871                 return AMDGPU_VRAM_TYPE_DDR3;
 872         default:
 873                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 874         }
 875 }
 876
 877 static int gmc_v7_0_early_init(void *handle)
 878 {
 879         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 880
 881         gmc_v7_0_set_gart_funcs(adev);
 882         gmc_v7_0_set_irq_funcs(adev);
 883
 884         return 0;
 885 }
 886
 887 static int gmc_v7_0_late_init(void *handle)
 888 {
 889         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 890
 891         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 892                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 893         else
 894                 return 0;
 895 }
 896
 897 static int gmc_v7_0_sw_init(void *handle)
 898 {
 899         int r;
 900         int dma_bits;
 901         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 902
 903         if (adev->flags & AMD_IS_APU) {
 904                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 905         } else {
 906                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 907                 tmp &= MC_SEQ_MISC0__MT__MASK;
 908                 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
 909         }
 910
 911         r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
 912         if (r)
 913                 return r;
 914
 915         r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
 916         if (r)
 917                 return r;
 918
 919         /* Adjust VM size here.
 920          * Currently set to 4GB ((1 << 20) 4k pages).
 921          * Max GPUVM size for cayman and SI is 40 bits.
 922          */
 923         adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
 924
 925         /* Set the internal MC address mask
 926          * This is the max address of the GPU's
 927          * internal address space.
 928          */
 929         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 930
 931         /* set DMA mask + need_dma32 flags.
 932          * PCIE - can handle 40-bits.
 933          * IGP - can handle 40-bits
 934          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 935          */
 936         adev->need_dma32 = false;
 937         dma_bits = adev->need_dma32 ? 32 : 40;
 938         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 939         if (r) {
 940                 adev->need_dma32 = true;
 941                 dma_bits = 32;
 942                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 943         }
 944         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 945         if (r) {
 946                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 947                 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
 948         }
 949
 950         r = gmc_v7_0_init_microcode(adev);
 951         if (r) {
 952                 DRM_ERROR("Failed to load mc firmware!\n");
 953                 return r;
 954         }
 955
 956         r = gmc_v7_0_mc_init(adev);
 957         if (r)
 958                 return r;
 959
 960         /* Memory manager */
 961         r = amdgpu_bo_init(adev);
 962         if (r)
 963                 return r;
 964
 965         r = gmc_v7_0_gart_init(adev);
 966         if (r)
 967                 return r;
 968
 969         if (!adev->vm_manager.enabled) {
 970                 r = gmc_v7_0_vm_init(adev);
 971                 if (r) {
 972                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
 973                         return r;
 974                 }
 975                 adev->vm_manager.enabled = true;
 976         }
 977
 978         return r;
 979 }
 980
 981 static int gmc_v7_0_sw_fini(void *handle)
 982 {
 983         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 984
 985         if (adev->vm_manager.enabled) {
 986                 amdgpu_vm_manager_fini(adev);
 987                 gmc_v7_0_vm_fini(adev);
 988                 adev->vm_manager.enabled = false;
 989         }
 990         gmc_v7_0_gart_fini(adev);
 991         amdgpu_gem_force_release(adev);
 992         amdgpu_bo_fini(adev);
 993
 994         return 0;
 995 }
 996
 997 static int gmc_v7_0_hw_init(void *handle)
 998 {
 999         int r;
1000         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1001
1002         gmc_v7_0_init_golden_registers(adev);
1003
1004         gmc_v7_0_mc_program(adev);
1005
1006         if (!(adev->flags & AMD_IS_APU)) {
1007                 r = gmc_v7_0_mc_load_microcode(adev);
1008                 if (r) {
1009                         DRM_ERROR("Failed to load MC firmware!\n");
1010                         return r;
1011                 }
1012         }
1013
1014         r = gmc_v7_0_gart_enable(adev);
1015         if (r)
1016                 return r;
1017
1018         return r;
1019 }
1020
1021 static int gmc_v7_0_hw_fini(void *handle)
1022 {
1023         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1024
1025         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1026         gmc_v7_0_gart_disable(adev);
1027
1028         return 0;
1029 }
1030
1031 static int gmc_v7_0_suspend(void *handle)
1032 {
1033         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1034
1035         if (adev->vm_manager.enabled) {
1036                 gmc_v7_0_vm_fini(adev);
1037                 adev->vm_manager.enabled = false;
1038         }
1039         gmc_v7_0_hw_fini(adev);
1040
1041         return 0;
1042 }
1043
1044 static int gmc_v7_0_resume(void *handle)
1045 {
1046         int r;
1047         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1048
1049         r = gmc_v7_0_hw_init(adev);
1050         if (r)
1051                 return r;
1052
1053         if (!adev->vm_manager.enabled) {
1054                 r = gmc_v7_0_vm_init(adev);
1055                 if (r) {
1056                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1057                         return r;
1058                 }
1059                 adev->vm_manager.enabled = true;
1060         }
1061
1062         return r;
1063 }
1064
1065 static bool gmc_v7_0_is_idle(void *handle)
1066 {
1067         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1068         u32 tmp = RREG32(mmSRBM_STATUS);
1069
1070         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1071                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1072                 return false;
1073
1074         return true;
1075 }
1076
1077 static int gmc_v7_0_wait_for_idle(void *handle)
1078 {
1079         unsigned i;
1080         u32 tmp;
1081         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1082
1083         for (i = 0; i < adev->usec_timeout; i++) {
1084                 /* read MC_STATUS */
1085                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1086                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1087                                                SRBM_STATUS__MCC_BUSY_MASK |
1088                                                SRBM_STATUS__MCD_BUSY_MASK |
1089                                                SRBM_STATUS__VMC_BUSY_MASK);
1090                 if (!tmp)
1091                         return 0;
1092                 udelay(1);
1093         }
1094         return -ETIMEDOUT;
1095
1096 }
1097
1098 static int gmc_v7_0_soft_reset(void *handle)
1099 {
1100         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1101         struct amdgpu_mode_mc_save save;
1102         u32 srbm_soft_reset = 0;
1103         u32 tmp = RREG32(mmSRBM_STATUS);
1104
1105         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1106                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1107                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1108
1109         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1110                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1111                 if (!(adev->flags & AMD_IS_APU))
1112                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1113                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1114         }
1115
1116         if (srbm_soft_reset) {
1117                 gmc_v7_0_mc_stop(adev, &save);
1118                 if (gmc_v7_0_wait_for_idle((void *)adev)) {
1119                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1120                 }
1121
1122
1123                 tmp = RREG32(mmSRBM_SOFT_RESET);
1124                 tmp |= srbm_soft_reset;
1125                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1126                 WREG32(mmSRBM_SOFT_RESET, tmp);
1127                 tmp = RREG32(mmSRBM_SOFT_RESET);
1128
1129                 udelay(50);
1130
1131                 tmp &= ~srbm_soft_reset;
1132                 WREG32(mmSRBM_SOFT_RESET, tmp);
1133                 tmp = RREG32(mmSRBM_SOFT_RESET);
1134
1135                 /* Wait a little for things to settle down */
1136                 udelay(50);
1137
1138                 gmc_v7_0_mc_resume(adev, &save);
1139                 udelay(50);
1140         }
1141
1142         return 0;
1143 }
1144
1145 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1146                                              struct amdgpu_irq_src *src,
1147                                              unsigned type,
1148                                              enum amdgpu_interrupt_state state)
1149 {
1150         u32 tmp;
1151         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1152                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1153                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1154                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1155                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1156                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1157
1158         switch (state) {
1159         case AMDGPU_IRQ_STATE_DISABLE:
1160                 /* system context */
1161                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1162                 tmp &= ~bits;
1163                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1164                 /* VMs */
1165                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1166                 tmp &= ~bits;
1167                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1168                 break;
1169         case AMDGPU_IRQ_STATE_ENABLE:
1170                 /* system context */
1171                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1172                 tmp |= bits;
1173                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1174                 /* VMs */
1175                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1176                 tmp |= bits;
1177                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1178                 break;
1179         default:
1180                 break;
1181         }
1182
1183         return 0;
1184 }
1185
1186 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1187                                       struct amdgpu_irq_src *source,
1188                                       struct amdgpu_iv_entry *entry)
1189 {
1190         u32 addr, status, mc_client;
1191
1192         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1193         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1194         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1195         /* reset addr and status */
1196         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1197
1198         if (!addr && !status)
1199                 return 0;
1200
1201         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1202                 gmc_v7_0_set_fault_enable_default(adev, false);
1203
1204         dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1205                 entry->src_id, entry->src_data);
1206         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1207                 addr);
1208         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1209                 status);
1210         gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
1211
1212         return 0;
1213 }
1214
1215 static int gmc_v7_0_set_clockgating_state(void *handle,
1216                                           enum amd_clockgating_state state)
1217 {
1218         bool gate = false;
1219         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1220
1221         if (state == AMD_CG_STATE_GATE)
1222                 gate = true;
1223
1224         if (!(adev->flags & AMD_IS_APU)) {
1225                 gmc_v7_0_enable_mc_mgcg(adev, gate);
1226                 gmc_v7_0_enable_mc_ls(adev, gate);
1227         }
1228         gmc_v7_0_enable_bif_mgls(adev, gate);
1229         gmc_v7_0_enable_hdp_mgcg(adev, gate);
1230         gmc_v7_0_enable_hdp_ls(adev, gate);
1231
1232         return 0;
1233 }
1234
1235 static int gmc_v7_0_set_powergating_state(void *handle,
1236                                           enum amd_powergating_state state)
1237 {
1238         return 0;
1239 }
1240
1241 const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1242         .name = "gmc_v7_0",
1243         .early_init = gmc_v7_0_early_init,
1244         .late_init = gmc_v7_0_late_init,
1245         .sw_init = gmc_v7_0_sw_init,
1246         .sw_fini = gmc_v7_0_sw_fini,
1247         .hw_init = gmc_v7_0_hw_init,
1248         .hw_fini = gmc_v7_0_hw_fini,
1249         .suspend = gmc_v7_0_suspend,
1250         .resume = gmc_v7_0_resume,
1251         .is_idle = gmc_v7_0_is_idle,
1252         .wait_for_idle = gmc_v7_0_wait_for_idle,
1253         .soft_reset = gmc_v7_0_soft_reset,
1254         .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1255         .set_powergating_state = gmc_v7_0_set_powergating_state,
1256 };
1257
1258 static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
1259         .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
1260         .set_pte_pde = gmc_v7_0_gart_set_pte_pde,
1261 };
1262
1263 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1264         .set = gmc_v7_0_vm_fault_interrupt_state,
1265         .process = gmc_v7_0_process_interrupt,
1266 };
1267
1268 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev)
1269 {
1270         if (adev->gart.gart_funcs == NULL)
1271                 adev->gart.gart_funcs = &gmc_v7_0_gart_funcs;
1272 }
1273
1274 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1275 {
1276         adev->mc.vm_fault.num_types = 1;
1277         adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1278 }