2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
29 #include "gmc/gmc_8_1_d.h"
30 #include "gmc/gmc_8_1_sh_mask.h"
32 #include "bif/bif_5_0_d.h"
33 #include "bif/bif_5_0_sh_mask.h"
35 #include "oss/oss_3_0_d.h"
36 #include "oss/oss_3_0_sh_mask.h"
42 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device
*adev
);
43 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device
*adev
);
45 MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
46 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
47 MODULE_FIRMWARE("amdgpu/fiji_mc.bin");
49 static const u32 golden_settings_tonga_a11
[] =
51 mmMC_ARB_WTM_GRPWT_RD
, 0x00000003, 0x00000000,
52 mmMC_HUB_RDREQ_DMIF_LIMIT
, 0x0000007f, 0x00000028,
53 mmMC_HUB_WDP_UMC
, 0x00007fb6, 0x00000991,
54 mmVM_PRT_APERTURE0_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
55 mmVM_PRT_APERTURE1_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
56 mmVM_PRT_APERTURE2_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
57 mmVM_PRT_APERTURE3_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
60 static const u32 tonga_mgcg_cgcg_init
[] =
62 mmMC_MEM_POWER_LS
, 0xffffffff, 0x00000104
65 static const u32 golden_settings_fiji_a10
[] =
67 mmVM_PRT_APERTURE0_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
68 mmVM_PRT_APERTURE1_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
69 mmVM_PRT_APERTURE2_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
70 mmVM_PRT_APERTURE3_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
73 static const u32 fiji_mgcg_cgcg_init
[] =
75 mmMC_MEM_POWER_LS
, 0xffffffff, 0x00000104
78 static const u32 golden_settings_iceland_a11
[] =
80 mmVM_PRT_APERTURE0_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
81 mmVM_PRT_APERTURE1_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
82 mmVM_PRT_APERTURE2_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
83 mmVM_PRT_APERTURE3_LOW_ADDR
, 0x0fffffff, 0x0fffffff
86 static const u32 iceland_mgcg_cgcg_init
[] =
88 mmMC_MEM_POWER_LS
, 0xffffffff, 0x00000104
91 static const u32 cz_mgcg_cgcg_init
[] =
93 mmMC_MEM_POWER_LS
, 0xffffffff, 0x00000104
96 static const u32 stoney_mgcg_cgcg_init
[] =
98 mmMC_MEM_POWER_LS
, 0xffffffff, 0x00000104
102 static void gmc_v8_0_init_golden_registers(struct amdgpu_device
*adev
)
104 switch (adev
->asic_type
) {
106 amdgpu_program_register_sequence(adev
,
107 iceland_mgcg_cgcg_init
,
108 (const u32
)ARRAY_SIZE(iceland_mgcg_cgcg_init
));
109 amdgpu_program_register_sequence(adev
,
110 golden_settings_iceland_a11
,
111 (const u32
)ARRAY_SIZE(golden_settings_iceland_a11
));
114 amdgpu_program_register_sequence(adev
,
116 (const u32
)ARRAY_SIZE(fiji_mgcg_cgcg_init
));
117 amdgpu_program_register_sequence(adev
,
118 golden_settings_fiji_a10
,
119 (const u32
)ARRAY_SIZE(golden_settings_fiji_a10
));
122 amdgpu_program_register_sequence(adev
,
123 tonga_mgcg_cgcg_init
,
124 (const u32
)ARRAY_SIZE(tonga_mgcg_cgcg_init
));
125 amdgpu_program_register_sequence(adev
,
126 golden_settings_tonga_a11
,
127 (const u32
)ARRAY_SIZE(golden_settings_tonga_a11
));
130 amdgpu_program_register_sequence(adev
,
132 (const u32
)ARRAY_SIZE(cz_mgcg_cgcg_init
));
135 amdgpu_program_register_sequence(adev
,
136 stoney_mgcg_cgcg_init
,
137 (const u32
)ARRAY_SIZE(stoney_mgcg_cgcg_init
));
145 * gmc8_mc_wait_for_idle - wait for MC idle callback.
147 * @adev: amdgpu_device pointer
149 * Wait for the MC (memory controller) to be idle.
151 * Returns 0 if the MC is idle, -1 if not.
153 int gmc_v8_0_mc_wait_for_idle(struct amdgpu_device
*adev
)
158 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
160 tmp
= RREG32(mmSRBM_STATUS
) & (SRBM_STATUS__VMC_BUSY_MASK
|
161 SRBM_STATUS__MCB_BUSY_MASK
|
162 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK
|
163 SRBM_STATUS__MCC_BUSY_MASK
|
164 SRBM_STATUS__MCD_BUSY_MASK
|
165 SRBM_STATUS__VMC1_BUSY_MASK
);
173 void gmc_v8_0_mc_stop(struct amdgpu_device
*adev
,
174 struct amdgpu_mode_mc_save
*save
)
178 if (adev
->mode_info
.num_crtc
)
179 amdgpu_display_stop_mc_access(adev
, save
);
181 amdgpu_asic_wait_for_mc_idle(adev
);
183 blackout
= RREG32(mmMC_SHARED_BLACKOUT_CNTL
);
184 if (REG_GET_FIELD(blackout
, MC_SHARED_BLACKOUT_CNTL
, BLACKOUT_MODE
) != 1) {
185 /* Block CPU access */
186 WREG32(mmBIF_FB_EN
, 0);
187 /* blackout the MC */
188 blackout
= REG_SET_FIELD(blackout
,
189 MC_SHARED_BLACKOUT_CNTL
, BLACKOUT_MODE
, 1);
190 WREG32(mmMC_SHARED_BLACKOUT_CNTL
, blackout
);
192 /* wait for the MC to settle */
196 void gmc_v8_0_mc_resume(struct amdgpu_device
*adev
,
197 struct amdgpu_mode_mc_save
*save
)
201 /* unblackout the MC */
202 tmp
= RREG32(mmMC_SHARED_BLACKOUT_CNTL
);
203 tmp
= REG_SET_FIELD(tmp
, MC_SHARED_BLACKOUT_CNTL
, BLACKOUT_MODE
, 0);
204 WREG32(mmMC_SHARED_BLACKOUT_CNTL
, tmp
);
205 /* allow CPU access */
206 tmp
= REG_SET_FIELD(0, BIF_FB_EN
, FB_READ_EN
, 1);
207 tmp
= REG_SET_FIELD(tmp
, BIF_FB_EN
, FB_WRITE_EN
, 1);
208 WREG32(mmBIF_FB_EN
, tmp
);
210 if (adev
->mode_info
.num_crtc
)
211 amdgpu_display_resume_mc_access(adev
, save
);
215 * gmc_v8_0_init_microcode - load ucode images from disk
217 * @adev: amdgpu_device pointer
219 * Use the firmware interface to load the ucode images into
220 * the driver (not loaded into hw).
221 * Returns 0 on success, error on failure.
223 static int gmc_v8_0_init_microcode(struct amdgpu_device
*adev
)
225 const char *chip_name
;
231 switch (adev
->asic_type
) {
247 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_mc.bin", chip_name
);
248 err
= request_firmware(&adev
->mc
.fw
, fw_name
, adev
->dev
);
251 err
= amdgpu_ucode_validate(adev
->mc
.fw
);
256 "mc: Failed to load firmware \"%s\"\n",
258 release_firmware(adev
->mc
.fw
);
265 * gmc_v8_0_mc_load_microcode - load MC ucode into the hw
267 * @adev: amdgpu_device pointer
269 * Load the GDDR MC ucode into the hw (CIK).
270 * Returns 0 on success, error on failure.
272 static int gmc_v8_0_mc_load_microcode(struct amdgpu_device
*adev
)
274 const struct mc_firmware_header_v1_0
*hdr
;
275 const __le32
*fw_data
= NULL
;
276 const __le32
*io_mc_regs
= NULL
;
277 u32 running
, blackout
= 0;
278 int i
, ucode_size
, regs_size
;
283 hdr
= (const struct mc_firmware_header_v1_0
*)adev
->mc
.fw
->data
;
284 amdgpu_ucode_print_mc_hdr(&hdr
->header
);
286 adev
->mc
.fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
287 regs_size
= le32_to_cpu(hdr
->io_debug_size_bytes
) / (4 * 2);
288 io_mc_regs
= (const __le32
*)
289 (adev
->mc
.fw
->data
+ le32_to_cpu(hdr
->io_debug_array_offset_bytes
));
290 ucode_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
291 fw_data
= (const __le32
*)
292 (adev
->mc
.fw
->data
+ le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
294 running
= REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL
), MC_SEQ_SUP_CNTL
, RUN
);
298 blackout
= RREG32(mmMC_SHARED_BLACKOUT_CNTL
);
299 WREG32(mmMC_SHARED_BLACKOUT_CNTL
, blackout
| 1);
302 /* reset the engine and set to writable */
303 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000008);
304 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000010);
306 /* load mc io regs */
307 for (i
= 0; i
< regs_size
; i
++) {
308 WREG32(mmMC_SEQ_IO_DEBUG_INDEX
, le32_to_cpup(io_mc_regs
++));
309 WREG32(mmMC_SEQ_IO_DEBUG_DATA
, le32_to_cpup(io_mc_regs
++));
311 /* load the MC ucode */
312 for (i
= 0; i
< ucode_size
; i
++)
313 WREG32(mmMC_SEQ_SUP_PGM
, le32_to_cpup(fw_data
++));
315 /* put the engine back into the active state */
316 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000008);
317 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000004);
318 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000001);
320 /* wait for training to complete */
321 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
322 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL
),
323 MC_SEQ_TRAIN_WAKEUP_CNTL
, TRAIN_DONE_D0
))
327 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
328 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL
),
329 MC_SEQ_TRAIN_WAKEUP_CNTL
, TRAIN_DONE_D1
))
335 WREG32(mmMC_SHARED_BLACKOUT_CNTL
, blackout
);
341 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device
*adev
,
342 struct amdgpu_mc
*mc
)
344 if (mc
->mc_vram_size
> 0xFFC0000000ULL
) {
345 /* leave room for at least 1024M GTT */
346 dev_warn(adev
->dev
, "limiting VRAM\n");
347 mc
->real_vram_size
= 0xFFC0000000ULL
;
348 mc
->mc_vram_size
= 0xFFC0000000ULL
;
350 amdgpu_vram_location(adev
, &adev
->mc
, 0);
351 adev
->mc
.gtt_base_align
= 0;
352 amdgpu_gtt_location(adev
, mc
);
356 * gmc_v8_0_mc_program - program the GPU memory controller
358 * @adev: amdgpu_device pointer
360 * Set the location of vram, gart, and AGP in the GPU's
361 * physical address space (CIK).
363 static void gmc_v8_0_mc_program(struct amdgpu_device
*adev
)
365 struct amdgpu_mode_mc_save save
;
370 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x6) {
371 WREG32((0xb05 + j
), 0x00000000);
372 WREG32((0xb06 + j
), 0x00000000);
373 WREG32((0xb07 + j
), 0x00000000);
374 WREG32((0xb08 + j
), 0x00000000);
375 WREG32((0xb09 + j
), 0x00000000);
377 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL
, 0);
379 if (adev
->mode_info
.num_crtc
)
380 amdgpu_display_set_vga_render_state(adev
, false);
382 gmc_v8_0_mc_stop(adev
, &save
);
383 if (amdgpu_asic_wait_for_mc_idle(adev
)) {
384 dev_warn(adev
->dev
, "Wait for MC idle timedout !\n");
386 /* Update configuration */
387 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR
,
388 adev
->mc
.vram_start
>> 12);
389 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
390 adev
->mc
.vram_end
>> 12);
391 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
,
392 adev
->vram_scratch
.gpu_addr
>> 12);
393 tmp
= ((adev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
394 tmp
|= ((adev
->mc
.vram_start
>> 24) & 0xFFFF);
395 WREG32(mmMC_VM_FB_LOCATION
, tmp
);
396 /* XXX double check these! */
397 WREG32(mmHDP_NONSURFACE_BASE
, (adev
->mc
.vram_start
>> 8));
398 WREG32(mmHDP_NONSURFACE_INFO
, (2 << 7) | (1 << 30));
399 WREG32(mmHDP_NONSURFACE_SIZE
, 0x3FFFFFFF);
400 WREG32(mmMC_VM_AGP_BASE
, 0);
401 WREG32(mmMC_VM_AGP_TOP
, 0x0FFFFFFF);
402 WREG32(mmMC_VM_AGP_BOT
, 0x0FFFFFFF);
403 if (amdgpu_asic_wait_for_mc_idle(adev
)) {
404 dev_warn(adev
->dev
, "Wait for MC idle timedout !\n");
406 gmc_v8_0_mc_resume(adev
, &save
);
408 WREG32(mmBIF_FB_EN
, BIF_FB_EN__FB_READ_EN_MASK
| BIF_FB_EN__FB_WRITE_EN_MASK
);
410 tmp
= RREG32(mmHDP_MISC_CNTL
);
411 tmp
= REG_SET_FIELD(tmp
, HDP_MISC_CNTL
, FLUSH_INVALIDATE_CACHE
, 1);
412 WREG32(mmHDP_MISC_CNTL
, tmp
);
414 tmp
= RREG32(mmHDP_HOST_PATH_CNTL
);
415 WREG32(mmHDP_HOST_PATH_CNTL
, tmp
);
419 * gmc_v8_0_mc_init - initialize the memory controller driver params
421 * @adev: amdgpu_device pointer
423 * Look up the amount of vram, vram width, and decide how to place
424 * vram and gart within the GPU's physical address space (CIK).
425 * Returns 0 for success.
427 static int gmc_v8_0_mc_init(struct amdgpu_device
*adev
)
430 int chansize
, numchan
;
432 /* Get VRAM informations */
433 tmp
= RREG32(mmMC_ARB_RAMCFG
);
434 if (REG_GET_FIELD(tmp
, MC_ARB_RAMCFG
, CHANSIZE
)) {
439 tmp
= RREG32(mmMC_SHARED_CHMAP
);
440 switch (REG_GET_FIELD(tmp
, MC_SHARED_CHMAP
, NOOFCHAN
)) {
470 adev
->mc
.vram_width
= numchan
* chansize
;
471 /* Could aper size report 0 ? */
472 adev
->mc
.aper_base
= pci_resource_start(adev
->pdev
, 0);
473 adev
->mc
.aper_size
= pci_resource_len(adev
->pdev
, 0);
474 /* size in MB on si */
475 adev
->mc
.mc_vram_size
= RREG32(mmCONFIG_MEMSIZE
) * 1024ULL * 1024ULL;
476 adev
->mc
.real_vram_size
= RREG32(mmCONFIG_MEMSIZE
) * 1024ULL * 1024ULL;
477 adev
->mc
.visible_vram_size
= adev
->mc
.aper_size
;
479 /* unless the user had overridden it, set the gart
480 * size equal to the 1024 or vram, whichever is larger.
482 if (amdgpu_gart_size
== -1)
483 adev
->mc
.gtt_size
= max((1024ULL << 20), adev
->mc
.mc_vram_size
);
485 adev
->mc
.gtt_size
= (uint64_t)amdgpu_gart_size
<< 20;
487 gmc_v8_0_vram_gtt_location(adev
, &adev
->mc
);
494 * VMID 0 is the physical GPU addresses as used by the kernel.
495 * VMIDs 1-15 are used for userspace clients and are handled
496 * by the amdgpu vm/hsa code.
500 * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
502 * @adev: amdgpu_device pointer
503 * @vmid: vm instance to flush
505 * Flush the TLB for the requested page table (CIK).
507 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device
*adev
,
510 /* flush hdp cache */
511 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL
, 0);
513 /* bits 0-15 are the VM contexts0-15 */
514 WREG32(mmVM_INVALIDATE_REQUEST
, 1 << vmid
);
518 * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
520 * @adev: amdgpu_device pointer
521 * @cpu_pt_addr: cpu address of the page table
522 * @gpu_page_idx: entry in the page table to update
523 * @addr: dst addr to write into pte/pde
524 * @flags: access flags
526 * Update the page tables using the CPU.
528 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device
*adev
,
530 uint32_t gpu_page_idx
,
534 void __iomem
*ptr
= (void *)cpu_pt_addr
;
540 * 39:12 4k physical page base address
551 * 63:59 block fragment size
553 * 39:1 physical base address of PTE
554 * bits 5:1 must be 0.
557 value
= addr
& 0x000000FFFFFFF000ULL
;
559 writeq(value
, ptr
+ (gpu_page_idx
* 8));
565 * gmc_v8_0_set_fault_enable_default - update VM fault handling
567 * @adev: amdgpu_device pointer
568 * @value: true redirects VM faults to the default page
570 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device
*adev
,
575 tmp
= RREG32(mmVM_CONTEXT1_CNTL
);
576 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
577 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
578 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
579 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
580 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
581 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
582 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
583 VALID_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
584 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
585 READ_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
586 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
587 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
588 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
589 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
590 WREG32(mmVM_CONTEXT1_CNTL
, tmp
);
594 * gmc_v8_0_gart_enable - gart enable
596 * @adev: amdgpu_device pointer
598 * This sets up the TLBs, programs the page tables for VMID0,
599 * sets up the hw for VMIDs 1-15 which are allocated on
600 * demand, and sets up the global locations for the LDS, GDS,
601 * and GPUVM for FSA64 clients (CIK).
602 * Returns 0 for success, errors for failure.
604 static int gmc_v8_0_gart_enable(struct amdgpu_device
*adev
)
609 if (adev
->gart
.robj
== NULL
) {
610 dev_err(adev
->dev
, "No VRAM object for PCIE GART.\n");
613 r
= amdgpu_gart_table_vram_pin(adev
);
616 /* Setup TLB control */
617 tmp
= RREG32(mmMC_VM_MX_L1_TLB_CNTL
);
618 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, ENABLE_L1_TLB
, 1);
619 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, ENABLE_L1_FRAGMENT_PROCESSING
, 1);
620 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, SYSTEM_ACCESS_MODE
, 3);
621 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, ENABLE_ADVANCED_DRIVER_MODEL
, 1);
622 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, SYSTEM_APERTURE_UNMAPPED_ACCESS
, 0);
623 WREG32(mmMC_VM_MX_L1_TLB_CNTL
, tmp
);
625 tmp
= RREG32(mmVM_L2_CNTL
);
626 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, ENABLE_L2_CACHE
, 1);
627 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
, 1);
628 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
, 1);
629 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
, 1);
630 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, EFFECTIVE_L2_QUEUE_SIZE
, 7);
631 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, CONTEXT1_IDENTITY_ACCESS_MODE
, 1);
632 WREG32(mmVM_L2_CNTL
, tmp
);
633 tmp
= RREG32(mmVM_L2_CNTL2
);
634 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL2
, INVALIDATE_ALL_L1_TLBS
, 1);
635 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL2
, INVALIDATE_L2_CACHE
, 1);
636 WREG32(mmVM_L2_CNTL2
, tmp
);
637 tmp
= RREG32(mmVM_L2_CNTL3
);
638 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL3
, L2_CACHE_BIGK_ASSOCIATIVITY
, 1);
639 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL3
, BANK_SELECT
, 4);
640 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL3
, L2_CACHE_BIGK_FRAGMENT_SIZE
, 4);
641 WREG32(mmVM_L2_CNTL3
, tmp
);
642 /* XXX: set to enable PTE/PDE in system memory */
643 tmp
= RREG32(mmVM_L2_CNTL4
);
644 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL
, 0);
645 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED
, 0);
646 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP
, 0);
647 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL
, 0);
648 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED
, 0);
649 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP
, 0);
650 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL
, 0);
651 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED
, 0);
652 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP
, 0);
653 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL
, 0);
654 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED
, 0);
655 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP
, 0);
656 WREG32(mmVM_L2_CNTL4
, tmp
);
658 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR
, adev
->mc
.gtt_start
>> 12);
659 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR
, (adev
->mc
.gtt_end
>> 12) - 1);
660 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, adev
->gart
.table_addr
>> 12);
661 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
662 (u32
)(adev
->dummy_page
.addr
>> 12));
663 WREG32(mmVM_CONTEXT0_CNTL2
, 0);
664 tmp
= RREG32(mmVM_CONTEXT0_CNTL
);
665 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
, 1);
666 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT0_CNTL
, PAGE_TABLE_DEPTH
, 0);
667 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT0_CNTL
, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
668 WREG32(mmVM_CONTEXT0_CNTL
, tmp
);
670 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR
, 0);
671 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR
, 0);
672 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET
, 0);
674 /* empty context1-15 */
675 /* FIXME start with 4G, once using 2 level pt switch to full
678 /* set vm size, must be a multiple of 4 */
679 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR
, 0);
680 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR
, adev
->vm_manager
.max_pfn
- 1);
681 for (i
= 1; i
< 16; i
++) {
683 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ i
,
684 adev
->gart
.table_addr
>> 12);
686 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ i
- 8,
687 adev
->gart
.table_addr
>> 12);
690 /* enable context1-15 */
691 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR
,
692 (u32
)(adev
->dummy_page
.addr
>> 12));
693 WREG32(mmVM_CONTEXT1_CNTL2
, 4);
694 tmp
= RREG32(mmVM_CONTEXT1_CNTL
);
695 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, ENABLE_CONTEXT
, 1);
696 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, PAGE_TABLE_DEPTH
, 1);
697 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
698 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
699 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
700 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, VALID_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
701 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, READ_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
702 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
703 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
704 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, PAGE_TABLE_BLOCK_SIZE
,
705 amdgpu_vm_block_size
- 9);
706 WREG32(mmVM_CONTEXT1_CNTL
, tmp
);
707 if (amdgpu_vm_fault_stop
== AMDGPU_VM_FAULT_STOP_ALWAYS
)
708 gmc_v8_0_set_fault_enable_default(adev
, false);
710 gmc_v8_0_set_fault_enable_default(adev
, true);
712 gmc_v8_0_gart_flush_gpu_tlb(adev
, 0);
713 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
714 (unsigned)(adev
->mc
.gtt_size
>> 20),
715 (unsigned long long)adev
->gart
.table_addr
);
716 adev
->gart
.ready
= true;
720 static int gmc_v8_0_gart_init(struct amdgpu_device
*adev
)
724 if (adev
->gart
.robj
) {
725 WARN(1, "R600 PCIE GART already initialized\n");
728 /* Initialize common gart structure */
729 r
= amdgpu_gart_init(adev
);
732 adev
->gart
.table_size
= adev
->gart
.num_gpu_pages
* 8;
733 return amdgpu_gart_table_vram_alloc(adev
);
737 * gmc_v8_0_gart_disable - gart disable
739 * @adev: amdgpu_device pointer
741 * This disables all VM page table (CIK).
743 static void gmc_v8_0_gart_disable(struct amdgpu_device
*adev
)
747 /* Disable all tables */
748 WREG32(mmVM_CONTEXT0_CNTL
, 0);
749 WREG32(mmVM_CONTEXT1_CNTL
, 0);
750 /* Setup TLB control */
751 tmp
= RREG32(mmMC_VM_MX_L1_TLB_CNTL
);
752 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, ENABLE_L1_TLB
, 0);
753 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, ENABLE_L1_FRAGMENT_PROCESSING
, 0);
754 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, ENABLE_ADVANCED_DRIVER_MODEL
, 0);
755 WREG32(mmMC_VM_MX_L1_TLB_CNTL
, tmp
);
757 tmp
= RREG32(mmVM_L2_CNTL
);
758 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, ENABLE_L2_CACHE
, 0);
759 WREG32(mmVM_L2_CNTL
, tmp
);
760 WREG32(mmVM_L2_CNTL2
, 0);
761 amdgpu_gart_table_vram_unpin(adev
);
765 * gmc_v8_0_gart_fini - vm fini callback
767 * @adev: amdgpu_device pointer
769 * Tears down the driver GART/VM setup (CIK).
771 static void gmc_v8_0_gart_fini(struct amdgpu_device
*adev
)
773 amdgpu_gart_table_vram_free(adev
);
774 amdgpu_gart_fini(adev
);
779 * VMID 0 is the physical GPU addresses as used by the kernel.
780 * VMIDs 1-15 are used for userspace clients and are handled
781 * by the amdgpu vm/hsa code.
784 * gmc_v8_0_vm_init - cik vm init callback
786 * @adev: amdgpu_device pointer
788 * Inits cik specific vm parameters (number of VMs, base of vram for
790 * Returns 0 for success.
792 static int gmc_v8_0_vm_init(struct amdgpu_device
*adev
)
796 * VMID 0 is reserved for System
797 * amdgpu graphics/compute will use VMIDs 1-7
798 * amdkfd will use VMIDs 8-15
800 adev
->vm_manager
.nvm
= AMDGPU_NUM_OF_VMIDS
;
802 /* base offset of vram pages */
803 if (adev
->flags
& AMD_IS_APU
) {
804 u64 tmp
= RREG32(mmMC_VM_FB_OFFSET
);
806 adev
->vm_manager
.vram_base_offset
= tmp
;
808 adev
->vm_manager
.vram_base_offset
= 0;
814 * gmc_v8_0_vm_fini - cik vm fini callback
816 * @adev: amdgpu_device pointer
818 * Tear down any asic specific VM setup (CIK).
820 static void gmc_v8_0_vm_fini(struct amdgpu_device
*adev
)
825 * gmc_v8_0_vm_decode_fault - print human readable fault info
827 * @adev: amdgpu_device pointer
828 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
829 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
831 * Print human readable fault information (CIK).
833 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device
*adev
,
834 u32 status
, u32 addr
, u32 mc_client
)
837 u32 vmid
= REG_GET_FIELD(status
, VM_CONTEXT1_PROTECTION_FAULT_STATUS
, VMID
);
838 u32 protections
= REG_GET_FIELD(status
, VM_CONTEXT1_PROTECTION_FAULT_STATUS
,
840 char block
[5] = { mc_client
>> 24, (mc_client
>> 16) & 0xff,
841 (mc_client
>> 8) & 0xff, mc_client
& 0xff, 0 };
843 mc_id
= REG_GET_FIELD(status
, VM_CONTEXT1_PROTECTION_FAULT_STATUS
,
846 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
847 protections
, vmid
, addr
,
848 REG_GET_FIELD(status
, VM_CONTEXT1_PROTECTION_FAULT_STATUS
,
850 "write" : "read", block
, mc_client
, mc_id
);
853 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type
)
855 switch (mc_seq_vram_type
) {
856 case MC_SEQ_MISC0__MT__GDDR1
:
857 return AMDGPU_VRAM_TYPE_GDDR1
;
858 case MC_SEQ_MISC0__MT__DDR2
:
859 return AMDGPU_VRAM_TYPE_DDR2
;
860 case MC_SEQ_MISC0__MT__GDDR3
:
861 return AMDGPU_VRAM_TYPE_GDDR3
;
862 case MC_SEQ_MISC0__MT__GDDR4
:
863 return AMDGPU_VRAM_TYPE_GDDR4
;
864 case MC_SEQ_MISC0__MT__GDDR5
:
865 return AMDGPU_VRAM_TYPE_GDDR5
;
866 case MC_SEQ_MISC0__MT__HBM
:
867 return AMDGPU_VRAM_TYPE_HBM
;
868 case MC_SEQ_MISC0__MT__DDR3
:
869 return AMDGPU_VRAM_TYPE_DDR3
;
871 return AMDGPU_VRAM_TYPE_UNKNOWN
;
875 static int gmc_v8_0_early_init(void *handle
)
877 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
879 gmc_v8_0_set_gart_funcs(adev
);
880 gmc_v8_0_set_irq_funcs(adev
);
882 if (adev
->flags
& AMD_IS_APU
) {
883 adev
->mc
.vram_type
= AMDGPU_VRAM_TYPE_UNKNOWN
;
885 u32 tmp
= RREG32(mmMC_SEQ_MISC0
);
886 tmp
&= MC_SEQ_MISC0__MT__MASK
;
887 adev
->mc
.vram_type
= gmc_v8_0_convert_vram_type(tmp
);
893 static int gmc_v8_0_late_init(void *handle
)
895 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
897 return amdgpu_irq_get(adev
, &adev
->mc
.vm_fault
, 0);
900 static int gmc_v8_0_sw_init(void *handle
)
904 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
906 r
= amdgpu_gem_init(adev
);
910 r
= amdgpu_irq_add_id(adev
, 146, &adev
->mc
.vm_fault
);
914 r
= amdgpu_irq_add_id(adev
, 147, &adev
->mc
.vm_fault
);
918 /* Adjust VM size here.
919 * Currently set to 4GB ((1 << 20) 4k pages).
920 * Max GPUVM size for cayman and SI is 40 bits.
922 adev
->vm_manager
.max_pfn
= amdgpu_vm_size
<< 18;
924 /* Set the internal MC address mask
925 * This is the max address of the GPU's
926 * internal address space.
928 adev
->mc
.mc_mask
= 0xffffffffffULL
; /* 40 bit MC */
930 /* set DMA mask + need_dma32 flags.
931 * PCIE - can handle 40-bits.
932 * IGP - can handle 40-bits
933 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
935 adev
->need_dma32
= false;
936 dma_bits
= adev
->need_dma32
? 32 : 40;
937 r
= pci_set_dma_mask(adev
->pdev
, DMA_BIT_MASK(dma_bits
));
939 adev
->need_dma32
= true;
941 printk(KERN_WARNING
"amdgpu: No suitable DMA available.\n");
943 r
= pci_set_consistent_dma_mask(adev
->pdev
, DMA_BIT_MASK(dma_bits
));
945 pci_set_consistent_dma_mask(adev
->pdev
, DMA_BIT_MASK(32));
946 printk(KERN_WARNING
"amdgpu: No coherent DMA available.\n");
949 r
= gmc_v8_0_init_microcode(adev
);
951 DRM_ERROR("Failed to load mc firmware!\n");
955 r
= gmc_v8_0_mc_init(adev
);
960 r
= amdgpu_bo_init(adev
);
964 r
= gmc_v8_0_gart_init(adev
);
968 if (!adev
->vm_manager
.enabled
) {
969 r
= gmc_v8_0_vm_init(adev
);
971 dev_err(adev
->dev
, "vm manager initialization failed (%d).\n", r
);
974 adev
->vm_manager
.enabled
= true;
980 static int gmc_v8_0_sw_fini(void *handle
)
983 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
985 if (adev
->vm_manager
.enabled
) {
986 for (i
= 0; i
< AMDGPU_NUM_VM
; ++i
)
987 fence_put(adev
->vm_manager
.active
[i
]);
988 gmc_v8_0_vm_fini(adev
);
989 adev
->vm_manager
.enabled
= false;
991 gmc_v8_0_gart_fini(adev
);
992 amdgpu_gem_fini(adev
);
993 amdgpu_bo_fini(adev
);
998 static int gmc_v8_0_hw_init(void *handle
)
1001 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1003 gmc_v8_0_init_golden_registers(adev
);
1005 gmc_v8_0_mc_program(adev
);
1007 if (!(adev
->flags
& AMD_IS_APU
)) {
1008 r
= gmc_v8_0_mc_load_microcode(adev
);
1010 DRM_ERROR("Failed to load MC firmware!\n");
1015 r
= gmc_v8_0_gart_enable(adev
);
1022 static int gmc_v8_0_hw_fini(void *handle
)
1024 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1026 amdgpu_irq_put(adev
, &adev
->mc
.vm_fault
, 0);
1027 gmc_v8_0_gart_disable(adev
);
1032 static int gmc_v8_0_suspend(void *handle
)
1035 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1037 if (adev
->vm_manager
.enabled
) {
1038 for (i
= 0; i
< AMDGPU_NUM_VM
; ++i
)
1039 fence_put(adev
->vm_manager
.active
[i
]);
1040 gmc_v8_0_vm_fini(adev
);
1041 adev
->vm_manager
.enabled
= false;
1043 gmc_v8_0_hw_fini(adev
);
1048 static int gmc_v8_0_resume(void *handle
)
1051 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1053 r
= gmc_v8_0_hw_init(adev
);
1057 if (!adev
->vm_manager
.enabled
) {
1058 r
= gmc_v8_0_vm_init(adev
);
1060 dev_err(adev
->dev
, "vm manager initialization failed (%d).\n", r
);
1063 adev
->vm_manager
.enabled
= true;
1069 static bool gmc_v8_0_is_idle(void *handle
)
1071 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1072 u32 tmp
= RREG32(mmSRBM_STATUS
);
1074 if (tmp
& (SRBM_STATUS__MCB_BUSY_MASK
| SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK
|
1075 SRBM_STATUS__MCC_BUSY_MASK
| SRBM_STATUS__MCD_BUSY_MASK
| SRBM_STATUS__VMC_BUSY_MASK
))
1081 static int gmc_v8_0_wait_for_idle(void *handle
)
1085 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1087 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1088 /* read MC_STATUS */
1089 tmp
= RREG32(mmSRBM_STATUS
) & (SRBM_STATUS__MCB_BUSY_MASK
|
1090 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK
|
1091 SRBM_STATUS__MCC_BUSY_MASK
|
1092 SRBM_STATUS__MCD_BUSY_MASK
|
1093 SRBM_STATUS__VMC_BUSY_MASK
|
1094 SRBM_STATUS__VMC1_BUSY_MASK
);
1103 static void gmc_v8_0_print_status(void *handle
)
1106 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1108 dev_info(adev
->dev
, "GMC 8.x registers\n");
1109 dev_info(adev
->dev
, " SRBM_STATUS=0x%08X\n",
1110 RREG32(mmSRBM_STATUS
));
1111 dev_info(adev
->dev
, " SRBM_STATUS2=0x%08X\n",
1112 RREG32(mmSRBM_STATUS2
));
1114 dev_info(adev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1115 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR
));
1116 dev_info(adev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1117 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS
));
1118 dev_info(adev
->dev
, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
1119 RREG32(mmMC_VM_MX_L1_TLB_CNTL
));
1120 dev_info(adev
->dev
, " VM_L2_CNTL=0x%08X\n",
1121 RREG32(mmVM_L2_CNTL
));
1122 dev_info(adev
->dev
, " VM_L2_CNTL2=0x%08X\n",
1123 RREG32(mmVM_L2_CNTL2
));
1124 dev_info(adev
->dev
, " VM_L2_CNTL3=0x%08X\n",
1125 RREG32(mmVM_L2_CNTL3
));
1126 dev_info(adev
->dev
, " VM_L2_CNTL4=0x%08X\n",
1127 RREG32(mmVM_L2_CNTL4
));
1128 dev_info(adev
->dev
, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
1129 RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR
));
1130 dev_info(adev
->dev
, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
1131 RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR
));
1132 dev_info(adev
->dev
, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1133 RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
));
1134 dev_info(adev
->dev
, " VM_CONTEXT0_CNTL2=0x%08X\n",
1135 RREG32(mmVM_CONTEXT0_CNTL2
));
1136 dev_info(adev
->dev
, " VM_CONTEXT0_CNTL=0x%08X\n",
1137 RREG32(mmVM_CONTEXT0_CNTL
));
1138 dev_info(adev
->dev
, " VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR=0x%08X\n",
1139 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR
));
1140 dev_info(adev
->dev
, " VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR=0x%08X\n",
1141 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR
));
1142 dev_info(adev
->dev
, " mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET=0x%08X\n",
1143 RREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET
));
1144 dev_info(adev
->dev
, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
1145 RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR
));
1146 dev_info(adev
->dev
, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
1147 RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR
));
1148 dev_info(adev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1149 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR
));
1150 dev_info(adev
->dev
, " VM_CONTEXT1_CNTL2=0x%08X\n",
1151 RREG32(mmVM_CONTEXT1_CNTL2
));
1152 dev_info(adev
->dev
, " VM_CONTEXT1_CNTL=0x%08X\n",
1153 RREG32(mmVM_CONTEXT1_CNTL
));
1154 for (i
= 0; i
< 16; i
++) {
1156 dev_info(adev
->dev
, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1157 i
, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ i
));
1159 dev_info(adev
->dev
, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1160 i
, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ i
- 8));
1162 dev_info(adev
->dev
, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
1163 RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR
));
1164 dev_info(adev
->dev
, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
1165 RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR
));
1166 dev_info(adev
->dev
, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
1167 RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
));
1168 dev_info(adev
->dev
, " MC_VM_FB_LOCATION=0x%08X\n",
1169 RREG32(mmMC_VM_FB_LOCATION
));
1170 dev_info(adev
->dev
, " MC_VM_AGP_BASE=0x%08X\n",
1171 RREG32(mmMC_VM_AGP_BASE
));
1172 dev_info(adev
->dev
, " MC_VM_AGP_TOP=0x%08X\n",
1173 RREG32(mmMC_VM_AGP_TOP
));
1174 dev_info(adev
->dev
, " MC_VM_AGP_BOT=0x%08X\n",
1175 RREG32(mmMC_VM_AGP_BOT
));
1177 dev_info(adev
->dev
, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
1178 RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL
));
1179 dev_info(adev
->dev
, " HDP_NONSURFACE_BASE=0x%08X\n",
1180 RREG32(mmHDP_NONSURFACE_BASE
));
1181 dev_info(adev
->dev
, " HDP_NONSURFACE_INFO=0x%08X\n",
1182 RREG32(mmHDP_NONSURFACE_INFO
));
1183 dev_info(adev
->dev
, " HDP_NONSURFACE_SIZE=0x%08X\n",
1184 RREG32(mmHDP_NONSURFACE_SIZE
));
1185 dev_info(adev
->dev
, " HDP_MISC_CNTL=0x%08X\n",
1186 RREG32(mmHDP_MISC_CNTL
));
1187 dev_info(adev
->dev
, " HDP_HOST_PATH_CNTL=0x%08X\n",
1188 RREG32(mmHDP_HOST_PATH_CNTL
));
1190 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x6) {
1191 dev_info(adev
->dev
, " %d:\n", i
);
1192 dev_info(adev
->dev
, " 0x%04X=0x%08X\n",
1193 0xb05 + j
, RREG32(0xb05 + j
));
1194 dev_info(adev
->dev
, " 0x%04X=0x%08X\n",
1195 0xb06 + j
, RREG32(0xb06 + j
));
1196 dev_info(adev
->dev
, " 0x%04X=0x%08X\n",
1197 0xb07 + j
, RREG32(0xb07 + j
));
1198 dev_info(adev
->dev
, " 0x%04X=0x%08X\n",
1199 0xb08 + j
, RREG32(0xb08 + j
));
1200 dev_info(adev
->dev
, " 0x%04X=0x%08X\n",
1201 0xb09 + j
, RREG32(0xb09 + j
));
1204 dev_info(adev
->dev
, " BIF_FB_EN=0x%08X\n",
1205 RREG32(mmBIF_FB_EN
));
1208 static int gmc_v8_0_soft_reset(void *handle
)
1210 struct amdgpu_mode_mc_save save
;
1211 u32 srbm_soft_reset
= 0;
1212 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1213 u32 tmp
= RREG32(mmSRBM_STATUS
);
1215 if (tmp
& SRBM_STATUS__VMC_BUSY_MASK
)
1216 srbm_soft_reset
= REG_SET_FIELD(srbm_soft_reset
,
1217 SRBM_SOFT_RESET
, SOFT_RESET_VMC
, 1);
1219 if (tmp
& (SRBM_STATUS__MCB_BUSY_MASK
| SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK
|
1220 SRBM_STATUS__MCC_BUSY_MASK
| SRBM_STATUS__MCD_BUSY_MASK
)) {
1221 if (!(adev
->flags
& AMD_IS_APU
))
1222 srbm_soft_reset
= REG_SET_FIELD(srbm_soft_reset
,
1223 SRBM_SOFT_RESET
, SOFT_RESET_MC
, 1);
1226 if (srbm_soft_reset
) {
1227 gmc_v8_0_print_status((void *)adev
);
1229 gmc_v8_0_mc_stop(adev
, &save
);
1230 if (gmc_v8_0_wait_for_idle(adev
)) {
1231 dev_warn(adev
->dev
, "Wait for GMC idle timed out !\n");
1235 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1236 tmp
|= srbm_soft_reset
;
1237 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
1238 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1239 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1243 tmp
&= ~srbm_soft_reset
;
1244 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1245 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1247 /* Wait a little for things to settle down */
1250 gmc_v8_0_mc_resume(adev
, &save
);
1253 gmc_v8_0_print_status((void *)adev
);
1259 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device
*adev
,
1260 struct amdgpu_irq_src
*src
,
1262 enum amdgpu_interrupt_state state
)
1265 u32 bits
= (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1266 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1267 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1268 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1269 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1270 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1271 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
);
1274 case AMDGPU_IRQ_STATE_DISABLE
:
1275 /* system context */
1276 tmp
= RREG32(mmVM_CONTEXT0_CNTL
);
1278 WREG32(mmVM_CONTEXT0_CNTL
, tmp
);
1280 tmp
= RREG32(mmVM_CONTEXT1_CNTL
);
1282 WREG32(mmVM_CONTEXT1_CNTL
, tmp
);
1284 case AMDGPU_IRQ_STATE_ENABLE
:
1285 /* system context */
1286 tmp
= RREG32(mmVM_CONTEXT0_CNTL
);
1288 WREG32(mmVM_CONTEXT0_CNTL
, tmp
);
1290 tmp
= RREG32(mmVM_CONTEXT1_CNTL
);
1292 WREG32(mmVM_CONTEXT1_CNTL
, tmp
);
1301 static int gmc_v8_0_process_interrupt(struct amdgpu_device
*adev
,
1302 struct amdgpu_irq_src
*source
,
1303 struct amdgpu_iv_entry
*entry
)
1305 u32 addr
, status
, mc_client
;
1307 addr
= RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR
);
1308 status
= RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS
);
1309 mc_client
= RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT
);
1310 /* reset addr and status */
1311 WREG32_P(mmVM_CONTEXT1_CNTL2
, 1, ~1);
1313 if (!addr
&& !status
)
1316 if (amdgpu_vm_fault_stop
== AMDGPU_VM_FAULT_STOP_FIRST
)
1317 gmc_v8_0_set_fault_enable_default(adev
, false);
1319 dev_err(adev
->dev
, "GPU fault detected: %d 0x%08x\n",
1320 entry
->src_id
, entry
->src_data
);
1321 dev_err(adev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1323 dev_err(adev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1325 gmc_v8_0_vm_decode_fault(adev
, status
, addr
, mc_client
);
1330 static int gmc_v8_0_set_clockgating_state(void *handle
,
1331 enum amd_clockgating_state state
)
1336 static int gmc_v8_0_set_powergating_state(void *handle
,
1337 enum amd_powergating_state state
)
1342 const struct amd_ip_funcs gmc_v8_0_ip_funcs
= {
1343 .early_init
= gmc_v8_0_early_init
,
1344 .late_init
= gmc_v8_0_late_init
,
1345 .sw_init
= gmc_v8_0_sw_init
,
1346 .sw_fini
= gmc_v8_0_sw_fini
,
1347 .hw_init
= gmc_v8_0_hw_init
,
1348 .hw_fini
= gmc_v8_0_hw_fini
,
1349 .suspend
= gmc_v8_0_suspend
,
1350 .resume
= gmc_v8_0_resume
,
1351 .is_idle
= gmc_v8_0_is_idle
,
1352 .wait_for_idle
= gmc_v8_0_wait_for_idle
,
1353 .soft_reset
= gmc_v8_0_soft_reset
,
1354 .print_status
= gmc_v8_0_print_status
,
1355 .set_clockgating_state
= gmc_v8_0_set_clockgating_state
,
1356 .set_powergating_state
= gmc_v8_0_set_powergating_state
,
1359 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs
= {
1360 .flush_gpu_tlb
= gmc_v8_0_gart_flush_gpu_tlb
,
1361 .set_pte_pde
= gmc_v8_0_gart_set_pte_pde
,
1364 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs
= {
1365 .set
= gmc_v8_0_vm_fault_interrupt_state
,
1366 .process
= gmc_v8_0_process_interrupt
,
1369 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device
*adev
)
1371 if (adev
->gart
.gart_funcs
== NULL
)
1372 adev
->gart
.gart_funcs
= &gmc_v8_0_gart_funcs
;
1375 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device
*adev
)
1377 adev
->mc
.vm_fault
.num_types
= 1;
1378 adev
->mc
.vm_fault
.funcs
= &gmc_v8_0_irq_funcs
;