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Merge tag 'regmap-fix-v5.8-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / gmc_v9_0.c
1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/pci.h>
26
27 #include <drm/drm_cache.h>
28
29 #include "amdgpu.h"
30 #include "gmc_v9_0.h"
31 #include "amdgpu_atomfirmware.h"
32 #include "amdgpu_gem.h"
33
34 #include "hdp/hdp_4_0_offset.h"
35 #include "hdp/hdp_4_0_sh_mask.h"
36 #include "gc/gc_9_0_sh_mask.h"
37 #include "dce/dce_12_0_offset.h"
38 #include "dce/dce_12_0_sh_mask.h"
39 #include "vega10_enum.h"
40 #include "mmhub/mmhub_1_0_offset.h"
41 #include "athub/athub_1_0_sh_mask.h"
42 #include "athub/athub_1_0_offset.h"
43 #include "oss/osssys_4_0_offset.h"
44
45 #include "soc15.h"
46 #include "soc15d.h"
47 #include "soc15_common.h"
48 #include "umc/umc_6_0_sh_mask.h"
49
50 #include "gfxhub_v1_0.h"
51 #include "mmhub_v1_0.h"
52 #include "athub_v1_0.h"
53 #include "gfxhub_v1_1.h"
54 #include "mmhub_v9_4.h"
55 #include "umc_v6_1.h"
56 #include "umc_v6_0.h"
57
58 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
59
60 #include "amdgpu_ras.h"
61 #include "amdgpu_xgmi.h"
62
63 /* add these here since we already include dce12 headers and these are for DCN */
64 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
65 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
66 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
67 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
68 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
69 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
70
71 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
72 #define AMDGPU_NUM_OF_VMIDS 8
73
74 static const u32 golden_settings_vega10_hdp[] =
75 {
76 0xf64, 0x0fffffff, 0x00000000,
77 0xf65, 0x0fffffff, 0x00000000,
78 0xf66, 0x0fffffff, 0x00000000,
79 0xf67, 0x0fffffff, 0x00000000,
80 0xf68, 0x0fffffff, 0x00000000,
81 0xf6a, 0x0fffffff, 0x00000000,
82 0xf6b, 0x0fffffff, 0x00000000,
83 0xf6c, 0x0fffffff, 0x00000000,
84 0xf6d, 0x0fffffff, 0x00000000,
85 0xf6e, 0x0fffffff, 0x00000000,
86 };
87
88 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
89 {
90 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
91 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
92 };
93
94 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
95 {
96 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
97 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
98 };
99
100 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
101 (0x000143c0 + 0x00000000),
102 (0x000143c0 + 0x00000800),
103 (0x000143c0 + 0x00001000),
104 (0x000143c0 + 0x00001800),
105 (0x000543c0 + 0x00000000),
106 (0x000543c0 + 0x00000800),
107 (0x000543c0 + 0x00001000),
108 (0x000543c0 + 0x00001800),
109 (0x000943c0 + 0x00000000),
110 (0x000943c0 + 0x00000800),
111 (0x000943c0 + 0x00001000),
112 (0x000943c0 + 0x00001800),
113 (0x000d43c0 + 0x00000000),
114 (0x000d43c0 + 0x00000800),
115 (0x000d43c0 + 0x00001000),
116 (0x000d43c0 + 0x00001800),
117 (0x001143c0 + 0x00000000),
118 (0x001143c0 + 0x00000800),
119 (0x001143c0 + 0x00001000),
120 (0x001143c0 + 0x00001800),
121 (0x001543c0 + 0x00000000),
122 (0x001543c0 + 0x00000800),
123 (0x001543c0 + 0x00001000),
124 (0x001543c0 + 0x00001800),
125 (0x001943c0 + 0x00000000),
126 (0x001943c0 + 0x00000800),
127 (0x001943c0 + 0x00001000),
128 (0x001943c0 + 0x00001800),
129 (0x001d43c0 + 0x00000000),
130 (0x001d43c0 + 0x00000800),
131 (0x001d43c0 + 0x00001000),
132 (0x001d43c0 + 0x00001800),
133 };
134
135 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
136 (0x000143e0 + 0x00000000),
137 (0x000143e0 + 0x00000800),
138 (0x000143e0 + 0x00001000),
139 (0x000143e0 + 0x00001800),
140 (0x000543e0 + 0x00000000),
141 (0x000543e0 + 0x00000800),
142 (0x000543e0 + 0x00001000),
143 (0x000543e0 + 0x00001800),
144 (0x000943e0 + 0x00000000),
145 (0x000943e0 + 0x00000800),
146 (0x000943e0 + 0x00001000),
147 (0x000943e0 + 0x00001800),
148 (0x000d43e0 + 0x00000000),
149 (0x000d43e0 + 0x00000800),
150 (0x000d43e0 + 0x00001000),
151 (0x000d43e0 + 0x00001800),
152 (0x001143e0 + 0x00000000),
153 (0x001143e0 + 0x00000800),
154 (0x001143e0 + 0x00001000),
155 (0x001143e0 + 0x00001800),
156 (0x001543e0 + 0x00000000),
157 (0x001543e0 + 0x00000800),
158 (0x001543e0 + 0x00001000),
159 (0x001543e0 + 0x00001800),
160 (0x001943e0 + 0x00000000),
161 (0x001943e0 + 0x00000800),
162 (0x001943e0 + 0x00001000),
163 (0x001943e0 + 0x00001800),
164 (0x001d43e0 + 0x00000000),
165 (0x001d43e0 + 0x00000800),
166 (0x001d43e0 + 0x00001000),
167 (0x001d43e0 + 0x00001800),
168 };
169
170 static const uint32_t ecc_umc_mcumc_status_addrs[] = {
171 (0x000143c2 + 0x00000000),
172 (0x000143c2 + 0x00000800),
173 (0x000143c2 + 0x00001000),
174 (0x000143c2 + 0x00001800),
175 (0x000543c2 + 0x00000000),
176 (0x000543c2 + 0x00000800),
177 (0x000543c2 + 0x00001000),
178 (0x000543c2 + 0x00001800),
179 (0x000943c2 + 0x00000000),
180 (0x000943c2 + 0x00000800),
181 (0x000943c2 + 0x00001000),
182 (0x000943c2 + 0x00001800),
183 (0x000d43c2 + 0x00000000),
184 (0x000d43c2 + 0x00000800),
185 (0x000d43c2 + 0x00001000),
186 (0x000d43c2 + 0x00001800),
187 (0x001143c2 + 0x00000000),
188 (0x001143c2 + 0x00000800),
189 (0x001143c2 + 0x00001000),
190 (0x001143c2 + 0x00001800),
191 (0x001543c2 + 0x00000000),
192 (0x001543c2 + 0x00000800),
193 (0x001543c2 + 0x00001000),
194 (0x001543c2 + 0x00001800),
195 (0x001943c2 + 0x00000000),
196 (0x001943c2 + 0x00000800),
197 (0x001943c2 + 0x00001000),
198 (0x001943c2 + 0x00001800),
199 (0x001d43c2 + 0x00000000),
200 (0x001d43c2 + 0x00000800),
201 (0x001d43c2 + 0x00001000),
202 (0x001d43c2 + 0x00001800),
203 };
204
205 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
206 struct amdgpu_irq_src *src,
207 unsigned type,
208 enum amdgpu_interrupt_state state)
209 {
210 u32 bits, i, tmp, reg;
211
212 /* Devices newer then VEGA10/12 shall have these programming
213 sequences performed by PSP BL */
214 if (adev->asic_type >= CHIP_VEGA20)
215 return 0;
216
217 bits = 0x7f;
218
219 switch (state) {
220 case AMDGPU_IRQ_STATE_DISABLE:
221 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
222 reg = ecc_umc_mcumc_ctrl_addrs[i];
223 tmp = RREG32(reg);
224 tmp &= ~bits;
225 WREG32(reg, tmp);
226 }
227 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
228 reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
229 tmp = RREG32(reg);
230 tmp &= ~bits;
231 WREG32(reg, tmp);
232 }
233 break;
234 case AMDGPU_IRQ_STATE_ENABLE:
235 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
236 reg = ecc_umc_mcumc_ctrl_addrs[i];
237 tmp = RREG32(reg);
238 tmp |= bits;
239 WREG32(reg, tmp);
240 }
241 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
242 reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
243 tmp = RREG32(reg);
244 tmp |= bits;
245 WREG32(reg, tmp);
246 }
247 break;
248 default:
249 break;
250 }
251
252 return 0;
253 }
254
255 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
256 struct amdgpu_irq_src *src,
257 unsigned type,
258 enum amdgpu_interrupt_state state)
259 {
260 struct amdgpu_vmhub *hub;
261 u32 tmp, reg, bits, i, j;
262
263 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
264 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
265 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
266 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
267 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
268 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
269 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
270
271 switch (state) {
272 case AMDGPU_IRQ_STATE_DISABLE:
273 for (j = 0; j < adev->num_vmhubs; j++) {
274 hub = &adev->vmhub[j];
275 for (i = 0; i < 16; i++) {
276 reg = hub->vm_context0_cntl + i;
277 tmp = RREG32(reg);
278 tmp &= ~bits;
279 WREG32(reg, tmp);
280 }
281 }
282 break;
283 case AMDGPU_IRQ_STATE_ENABLE:
284 for (j = 0; j < adev->num_vmhubs; j++) {
285 hub = &adev->vmhub[j];
286 for (i = 0; i < 16; i++) {
287 reg = hub->vm_context0_cntl + i;
288 tmp = RREG32(reg);
289 tmp |= bits;
290 WREG32(reg, tmp);
291 }
292 }
293 default:
294 break;
295 }
296
297 return 0;
298 }
299
300 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
301 struct amdgpu_irq_src *source,
302 struct amdgpu_iv_entry *entry)
303 {
304 struct amdgpu_vmhub *hub;
305 bool retry_fault = !!(entry->src_data[1] & 0x80);
306 uint32_t status = 0;
307 u64 addr;
308 char hub_name[10];
309
310 addr = (u64)entry->src_data[0] << 12;
311 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
312
313 if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
314 entry->timestamp))
315 return 1; /* This also prevents sending it to KFD */
316
317 if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
318 snprintf(hub_name, sizeof(hub_name), "mmhub0");
319 hub = &adev->vmhub[AMDGPU_MMHUB_0];
320 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
321 snprintf(hub_name, sizeof(hub_name), "mmhub1");
322 hub = &adev->vmhub[AMDGPU_MMHUB_1];
323 } else {
324 snprintf(hub_name, sizeof(hub_name), "gfxhub0");
325 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
326 }
327
328 /* If it's the first fault for this address, process it normally */
329 if (retry_fault && !in_interrupt() &&
330 amdgpu_vm_handle_fault(adev, entry->pasid, addr))
331 return 1; /* This also prevents sending it to KFD */
332
333 if (!amdgpu_sriov_vf(adev)) {
334 /*
335 * Issue a dummy read to wait for the status register to
336 * be updated to avoid reading an incorrect value due to
337 * the new fast GRBM interface.
338 */
339 if (entry->vmid_src == AMDGPU_GFXHUB_0)
340 RREG32(hub->vm_l2_pro_fault_status);
341
342 status = RREG32(hub->vm_l2_pro_fault_status);
343 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
344 }
345
346 if (printk_ratelimit()) {
347 struct amdgpu_task_info task_info;
348
349 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
350 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
351
352 dev_err(adev->dev,
353 "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
354 "pasid:%u, for process %s pid %d thread %s pid %d)\n",
355 hub_name, retry_fault ? "retry" : "no-retry",
356 entry->src_id, entry->ring_id, entry->vmid,
357 entry->pasid, task_info.process_name, task_info.tgid,
358 task_info.task_name, task_info.pid);
359 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n",
360 addr, entry->client_id);
361 if (!amdgpu_sriov_vf(adev)) {
362 dev_err(adev->dev,
363 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
364 status);
365 dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
366 REG_GET_FIELD(status,
367 VM_L2_PROTECTION_FAULT_STATUS, CID));
368 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
369 REG_GET_FIELD(status,
370 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
371 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
372 REG_GET_FIELD(status,
373 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
374 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
375 REG_GET_FIELD(status,
376 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
377 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
378 REG_GET_FIELD(status,
379 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
380 dev_err(adev->dev, "\t RW: 0x%lx\n",
381 REG_GET_FIELD(status,
382 VM_L2_PROTECTION_FAULT_STATUS, RW));
383
384 }
385 }
386
387 return 0;
388 }
389
390 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
391 .set = gmc_v9_0_vm_fault_interrupt_state,
392 .process = gmc_v9_0_process_interrupt,
393 };
394
395
396 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
397 .set = gmc_v9_0_ecc_interrupt_state,
398 .process = amdgpu_umc_process_ecc_irq,
399 };
400
401 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
402 {
403 adev->gmc.vm_fault.num_types = 1;
404 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
405
406 if (!amdgpu_sriov_vf(adev)) {
407 adev->gmc.ecc_irq.num_types = 1;
408 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
409 }
410 }
411
412 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
413 uint32_t flush_type)
414 {
415 u32 req = 0;
416
417 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
418 PER_VMID_INVALIDATE_REQ, 1 << vmid);
419 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
420 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
421 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
422 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
423 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
424 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
425 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
426 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
427
428 return req;
429 }
430
431 /**
432 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
433 *
434 * @adev: amdgpu_device pointer
435 * @vmhub: vmhub type
436 *
437 */
438 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
439 uint32_t vmhub)
440 {
441 return ((vmhub == AMDGPU_MMHUB_0 ||
442 vmhub == AMDGPU_MMHUB_1) &&
443 (!amdgpu_sriov_vf(adev)) &&
444 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
445 (adev->apu_flags & AMD_APU_IS_PICASSO))));
446 }
447
448 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
449 uint8_t vmid, uint16_t *p_pasid)
450 {
451 uint32_t value;
452
453 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
454 + vmid);
455 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
456
457 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
458 }
459
460 /*
461 * GART
462 * VMID 0 is the physical GPU addresses as used by the kernel.
463 * VMIDs 1-15 are used for userspace clients and are handled
464 * by the amdgpu vm/hsa code.
465 */
466
467 /**
468 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
469 *
470 * @adev: amdgpu_device pointer
471 * @vmid: vm instance to flush
472 * @flush_type: the flush type
473 *
474 * Flush the TLB for the requested page table using certain type.
475 */
476 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
477 uint32_t vmhub, uint32_t flush_type)
478 {
479 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
480 const unsigned eng = 17;
481 u32 j, inv_req, inv_req2, tmp;
482 struct amdgpu_vmhub *hub;
483
484 BUG_ON(vmhub >= adev->num_vmhubs);
485
486 hub = &adev->vmhub[vmhub];
487 if (adev->gmc.xgmi.num_physical_nodes &&
488 adev->asic_type == CHIP_VEGA20) {
489 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
490 * heavy-weight TLB flush (type 2), which flushes
491 * both. Due to a race condition with concurrent
492 * memory accesses using the same TLB cache line, we
493 * still need a second TLB flush after this.
494 */
495 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2);
496 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type);
497 } else {
498 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
499 inv_req2 = 0;
500 }
501
502 /* This is necessary for a HW workaround under SRIOV as well
503 * as GFXOFF under bare metal
504 */
505 if (adev->gfx.kiq.ring.sched.ready &&
506 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
507 !adev->in_gpu_reset) {
508 uint32_t req = hub->vm_inv_eng0_req + eng;
509 uint32_t ack = hub->vm_inv_eng0_ack + eng;
510
511 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
512 1 << vmid);
513 return;
514 }
515
516 spin_lock(&adev->gmc.invalidate_lock);
517
518 /*
519 * It may lose gpuvm invalidate acknowldege state across power-gating
520 * off cycle, add semaphore acquire before invalidation and semaphore
521 * release after invalidation to avoid entering power gated state
522 * to WA the Issue
523 */
524
525 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
526 if (use_semaphore) {
527 for (j = 0; j < adev->usec_timeout; j++) {
528 /* a read return value of 1 means semaphore acuqire */
529 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
530 if (tmp & 0x1)
531 break;
532 udelay(1);
533 }
534
535 if (j >= adev->usec_timeout)
536 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
537 }
538
539 do {
540 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, inv_req);
541
542 /*
543 * Issue a dummy read to wait for the ACK register to
544 * be cleared to avoid a false ACK due to the new fast
545 * GRBM interface.
546 */
547 if (vmhub == AMDGPU_GFXHUB_0)
548 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
549
550 for (j = 0; j < adev->usec_timeout; j++) {
551 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
552 if (tmp & (1 << vmid))
553 break;
554 udelay(1);
555 }
556
557 inv_req = inv_req2;
558 inv_req2 = 0;
559 } while (inv_req);
560
561 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
562 if (use_semaphore)
563 /*
564 * add semaphore release after invalidation,
565 * write with 0 means semaphore release
566 */
567 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
568
569 spin_unlock(&adev->gmc.invalidate_lock);
570
571 if (j < adev->usec_timeout)
572 return;
573
574 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
575 }
576
577 /**
578 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
579 *
580 * @adev: amdgpu_device pointer
581 * @pasid: pasid to be flush
582 *
583 * Flush the TLB for the requested pasid.
584 */
585 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
586 uint16_t pasid, uint32_t flush_type,
587 bool all_hub)
588 {
589 int vmid, i;
590 signed long r;
591 uint32_t seq;
592 uint16_t queried_pasid;
593 bool ret;
594 struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
595 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
596
597 if (adev->in_gpu_reset)
598 return -EIO;
599
600 if (ring->sched.ready) {
601 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
602 * heavy-weight TLB flush (type 2), which flushes
603 * both. Due to a race condition with concurrent
604 * memory accesses using the same TLB cache line, we
605 * still need a second TLB flush after this.
606 */
607 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes &&
608 adev->asic_type == CHIP_VEGA20);
609 /* 2 dwords flush + 8 dwords fence */
610 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8;
611
612 if (vega20_xgmi_wa)
613 ndw += kiq->pmf->invalidate_tlbs_size;
614
615 spin_lock(&adev->gfx.kiq.ring_lock);
616 /* 2 dwords flush + 8 dwords fence */
617 amdgpu_ring_alloc(ring, ndw);
618 if (vega20_xgmi_wa)
619 kiq->pmf->kiq_invalidate_tlbs(ring,
620 pasid, 2, all_hub);
621 kiq->pmf->kiq_invalidate_tlbs(ring,
622 pasid, flush_type, all_hub);
623 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
624 if (r) {
625 amdgpu_ring_undo(ring);
626 spin_unlock(&adev->gfx.kiq.ring_lock);
627 return -ETIME;
628 }
629
630 amdgpu_ring_commit(ring);
631 spin_unlock(&adev->gfx.kiq.ring_lock);
632 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
633 if (r < 1) {
634 DRM_ERROR("wait for kiq fence error: %ld.\n", r);
635 return -ETIME;
636 }
637
638 return 0;
639 }
640
641 for (vmid = 1; vmid < 16; vmid++) {
642
643 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
644 &queried_pasid);
645 if (ret && queried_pasid == pasid) {
646 if (all_hub) {
647 for (i = 0; i < adev->num_vmhubs; i++)
648 gmc_v9_0_flush_gpu_tlb(adev, vmid,
649 i, flush_type);
650 } else {
651 gmc_v9_0_flush_gpu_tlb(adev, vmid,
652 AMDGPU_GFXHUB_0, flush_type);
653 }
654 break;
655 }
656 }
657
658 return 0;
659
660 }
661
662 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
663 unsigned vmid, uint64_t pd_addr)
664 {
665 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
666 struct amdgpu_device *adev = ring->adev;
667 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
668 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
669 unsigned eng = ring->vm_inv_eng;
670
671 /*
672 * It may lose gpuvm invalidate acknowldege state across power-gating
673 * off cycle, add semaphore acquire before invalidation and semaphore
674 * release after invalidation to avoid entering power gated state
675 * to WA the Issue
676 */
677
678 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
679 if (use_semaphore)
680 /* a read return value of 1 means semaphore acuqire */
681 amdgpu_ring_emit_reg_wait(ring,
682 hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
683
684 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
685 lower_32_bits(pd_addr));
686
687 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
688 upper_32_bits(pd_addr));
689
690 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
691 hub->vm_inv_eng0_ack + eng,
692 req, 1 << vmid);
693
694 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
695 if (use_semaphore)
696 /*
697 * add semaphore release after invalidation,
698 * write with 0 means semaphore release
699 */
700 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0);
701
702 return pd_addr;
703 }
704
705 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
706 unsigned pasid)
707 {
708 struct amdgpu_device *adev = ring->adev;
709 uint32_t reg;
710
711 /* Do nothing because there's no lut register for mmhub1. */
712 if (ring->funcs->vmhub == AMDGPU_MMHUB_1)
713 return;
714
715 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
716 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
717 else
718 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
719
720 amdgpu_ring_emit_wreg(ring, reg, pasid);
721 }
722
723 /*
724 * PTE format on VEGA 10:
725 * 63:59 reserved
726 * 58:57 mtype
727 * 56 F
728 * 55 L
729 * 54 P
730 * 53 SW
731 * 52 T
732 * 50:48 reserved
733 * 47:12 4k physical page base address
734 * 11:7 fragment
735 * 6 write
736 * 5 read
737 * 4 exe
738 * 3 Z
739 * 2 snooped
740 * 1 system
741 * 0 valid
742 *
743 * PDE format on VEGA 10:
744 * 63:59 block fragment size
745 * 58:55 reserved
746 * 54 P
747 * 53:48 reserved
748 * 47:6 physical base address of PD or PTE
749 * 5:3 reserved
750 * 2 C
751 * 1 system
752 * 0 valid
753 */
754
755 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
756
757 {
758 switch (flags) {
759 case AMDGPU_VM_MTYPE_DEFAULT:
760 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
761 case AMDGPU_VM_MTYPE_NC:
762 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
763 case AMDGPU_VM_MTYPE_WC:
764 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
765 case AMDGPU_VM_MTYPE_RW:
766 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
767 case AMDGPU_VM_MTYPE_CC:
768 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
769 case AMDGPU_VM_MTYPE_UC:
770 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
771 default:
772 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
773 }
774 }
775
776 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
777 uint64_t *addr, uint64_t *flags)
778 {
779 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
780 *addr = adev->vm_manager.vram_base_offset + *addr -
781 adev->gmc.vram_start;
782 BUG_ON(*addr & 0xFFFF00000000003FULL);
783
784 if (!adev->gmc.translate_further)
785 return;
786
787 if (level == AMDGPU_VM_PDB1) {
788 /* Set the block fragment size */
789 if (!(*flags & AMDGPU_PDE_PTE))
790 *flags |= AMDGPU_PDE_BFS(0x9);
791
792 } else if (level == AMDGPU_VM_PDB0) {
793 if (*flags & AMDGPU_PDE_PTE)
794 *flags &= ~AMDGPU_PDE_PTE;
795 else
796 *flags |= AMDGPU_PTE_TF;
797 }
798 }
799
800 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
801 struct amdgpu_bo_va_mapping *mapping,
802 uint64_t *flags)
803 {
804 *flags &= ~AMDGPU_PTE_EXECUTABLE;
805 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
806
807 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
808 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
809
810 if (mapping->flags & AMDGPU_PTE_PRT) {
811 *flags |= AMDGPU_PTE_PRT;
812 *flags &= ~AMDGPU_PTE_VALID;
813 }
814
815 if (adev->asic_type == CHIP_ARCTURUS &&
816 !(*flags & AMDGPU_PTE_SYSTEM) &&
817 mapping->bo_va->is_xgmi)
818 *flags |= AMDGPU_PTE_SNOOPED;
819 }
820
821 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
822 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
823 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
824 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
825 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
826 .map_mtype = gmc_v9_0_map_mtype,
827 .get_vm_pde = gmc_v9_0_get_vm_pde,
828 .get_vm_pte = gmc_v9_0_get_vm_pte
829 };
830
831 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
832 {
833 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
834 }
835
836 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
837 {
838 switch (adev->asic_type) {
839 case CHIP_VEGA10:
840 adev->umc.funcs = &umc_v6_0_funcs;
841 break;
842 case CHIP_VEGA20:
843 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
844 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
845 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
846 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
847 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
848 adev->umc.funcs = &umc_v6_1_funcs;
849 break;
850 case CHIP_ARCTURUS:
851 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
852 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
853 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
854 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
855 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
856 adev->umc.funcs = &umc_v6_1_funcs;
857 break;
858 default:
859 break;
860 }
861 }
862
863 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
864 {
865 switch (adev->asic_type) {
866 case CHIP_VEGA20:
867 adev->mmhub.funcs = &mmhub_v1_0_funcs;
868 break;
869 case CHIP_ARCTURUS:
870 adev->mmhub.funcs = &mmhub_v9_4_funcs;
871 break;
872 default:
873 break;
874 }
875 }
876
877 static int gmc_v9_0_early_init(void *handle)
878 {
879 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
880
881 gmc_v9_0_set_gmc_funcs(adev);
882 gmc_v9_0_set_irq_funcs(adev);
883 gmc_v9_0_set_umc_funcs(adev);
884 gmc_v9_0_set_mmhub_funcs(adev);
885
886 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
887 adev->gmc.shared_aperture_end =
888 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
889 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
890 adev->gmc.private_aperture_end =
891 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
892
893 return 0;
894 }
895
896 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
897 {
898
899 /*
900 * TODO:
901 * Currently there is a bug where some memory client outside
902 * of the driver writes to first 8M of VRAM on S3 resume,
903 * this overrides GART which by default gets placed in first 8M and
904 * causes VM_FAULTS once GTT is accessed.
905 * Keep the stolen memory reservation until the while this is not solved.
906 * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init
907 */
908 switch (adev->asic_type) {
909 case CHIP_VEGA10:
910 case CHIP_RAVEN:
911 case CHIP_ARCTURUS:
912 case CHIP_RENOIR:
913 return true;
914 case CHIP_VEGA12:
915 case CHIP_VEGA20:
916 default:
917 return false;
918 }
919 }
920
921 static int gmc_v9_0_late_init(void *handle)
922 {
923 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
924 int r;
925
926 if (!gmc_v9_0_keep_stolen_memory(adev))
927 amdgpu_bo_late_init(adev);
928
929 r = amdgpu_gmc_allocate_vm_inv_eng(adev);
930 if (r)
931 return r;
932 /* Check if ecc is available */
933 if (!amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) {
934 r = amdgpu_atomfirmware_mem_ecc_supported(adev);
935 if (!r) {
936 DRM_INFO("ECC is not present.\n");
937 if (adev->df.funcs->enable_ecc_force_par_wr_rmw)
938 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
939 } else
940 DRM_INFO("ECC is active.\n");
941
942 r = amdgpu_atomfirmware_sram_ecc_supported(adev);
943 if (!r)
944 DRM_INFO("SRAM ECC is not present.\n");
945 else
946 DRM_INFO("SRAM ECC is active.\n");
947 }
948
949 if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count)
950 adev->mmhub.funcs->reset_ras_error_count(adev);
951
952 r = amdgpu_gmc_ras_late_init(adev);
953 if (r)
954 return r;
955
956 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
957 }
958
959 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
960 struct amdgpu_gmc *mc)
961 {
962 u64 base = 0;
963
964 if (adev->asic_type == CHIP_ARCTURUS)
965 base = mmhub_v9_4_get_fb_location(adev);
966 else if (!amdgpu_sriov_vf(adev))
967 base = mmhub_v1_0_get_fb_location(adev);
968
969 /* add the xgmi offset of the physical node */
970 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
971 amdgpu_gmc_vram_location(adev, mc, base);
972 amdgpu_gmc_gart_location(adev, mc);
973 amdgpu_gmc_agp_location(adev, mc);
974 /* base offset of vram pages */
975 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
976
977 /* XXX: add the xgmi offset of the physical node? */
978 adev->vm_manager.vram_base_offset +=
979 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
980 }
981
982 /**
983 * gmc_v9_0_mc_init - initialize the memory controller driver params
984 *
985 * @adev: amdgpu_device pointer
986 *
987 * Look up the amount of vram, vram width, and decide how to place
988 * vram and gart within the GPU's physical address space.
989 * Returns 0 for success.
990 */
991 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
992 {
993 int r;
994
995 /* size in MB on si */
996 adev->gmc.mc_vram_size =
997 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
998 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
999
1000 if (!(adev->flags & AMD_IS_APU)) {
1001 r = amdgpu_device_resize_fb_bar(adev);
1002 if (r)
1003 return r;
1004 }
1005 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
1006 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
1007
1008 #ifdef CONFIG_X86_64
1009 if (adev->flags & AMD_IS_APU) {
1010 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);
1011 adev->gmc.aper_size = adev->gmc.real_vram_size;
1012 }
1013 #endif
1014 /* In case the PCI BAR is larger than the actual amount of vram */
1015 adev->gmc.visible_vram_size = adev->gmc.aper_size;
1016 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
1017 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
1018
1019 /* set the gart size */
1020 if (amdgpu_gart_size == -1) {
1021 switch (adev->asic_type) {
1022 case CHIP_VEGA10: /* all engines support GPUVM */
1023 case CHIP_VEGA12: /* all engines support GPUVM */
1024 case CHIP_VEGA20:
1025 case CHIP_ARCTURUS:
1026 default:
1027 adev->gmc.gart_size = 512ULL << 20;
1028 break;
1029 case CHIP_RAVEN: /* DCE SG support */
1030 case CHIP_RENOIR:
1031 adev->gmc.gart_size = 1024ULL << 20;
1032 break;
1033 }
1034 } else {
1035 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
1036 }
1037
1038 gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
1039
1040 return 0;
1041 }
1042
1043 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
1044 {
1045 int r;
1046
1047 if (adev->gart.bo) {
1048 WARN(1, "VEGA10 PCIE GART already initialized\n");
1049 return 0;
1050 }
1051 /* Initialize common gart structure */
1052 r = amdgpu_gart_init(adev);
1053 if (r)
1054 return r;
1055 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
1056 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
1057 AMDGPU_PTE_EXECUTABLE;
1058 return amdgpu_gart_table_vram_alloc(adev);
1059 }
1060
1061 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
1062 {
1063 u32 d1vga_control;
1064 unsigned size;
1065
1066 /*
1067 * TODO Remove once GART corruption is resolved
1068 * Check related code in gmc_v9_0_sw_fini
1069 * */
1070 if (gmc_v9_0_keep_stolen_memory(adev))
1071 return 9 * 1024 * 1024;
1072
1073 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
1074 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1075 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
1076 } else {
1077 u32 viewport;
1078
1079 switch (adev->asic_type) {
1080 case CHIP_RAVEN:
1081 case CHIP_RENOIR:
1082 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
1083 size = (REG_GET_FIELD(viewport,
1084 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1085 REG_GET_FIELD(viewport,
1086 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1087 4);
1088 break;
1089 case CHIP_VEGA10:
1090 case CHIP_VEGA12:
1091 case CHIP_VEGA20:
1092 default:
1093 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1094 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1095 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1096 4);
1097 break;
1098 }
1099 }
1100 /* return 0 if the pre-OS buffer uses up most of vram */
1101 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
1102 return 0;
1103
1104 return size;
1105 }
1106
1107 static int gmc_v9_0_sw_init(void *handle)
1108 {
1109 int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
1110 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1111
1112 gfxhub_v1_0_init(adev);
1113 if (adev->asic_type == CHIP_ARCTURUS)
1114 mmhub_v9_4_init(adev);
1115 else
1116 mmhub_v1_0_init(adev);
1117
1118 spin_lock_init(&adev->gmc.invalidate_lock);
1119
1120 r = amdgpu_atomfirmware_get_vram_info(adev,
1121 &vram_width, &vram_type, &vram_vendor);
1122 if (amdgpu_sriov_vf(adev))
1123 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
1124 * and DF related registers is not readable, seems hardcord is the
1125 * only way to set the correct vram_width
1126 */
1127 adev->gmc.vram_width = 2048;
1128 else if (amdgpu_emu_mode != 1)
1129 adev->gmc.vram_width = vram_width;
1130
1131 if (!adev->gmc.vram_width) {
1132 int chansize, numchan;
1133
1134 /* hbm memory channel size */
1135 if (adev->flags & AMD_IS_APU)
1136 chansize = 64;
1137 else
1138 chansize = 128;
1139
1140 numchan = adev->df.funcs->get_hbm_channel_number(adev);
1141 adev->gmc.vram_width = numchan * chansize;
1142 }
1143
1144 adev->gmc.vram_type = vram_type;
1145 adev->gmc.vram_vendor = vram_vendor;
1146 switch (adev->asic_type) {
1147 case CHIP_RAVEN:
1148 adev->num_vmhubs = 2;
1149
1150 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
1151 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1152 } else {
1153 /* vm_size is 128TB + 512GB for legacy 3-level page support */
1154 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
1155 adev->gmc.translate_further =
1156 adev->vm_manager.num_level > 1;
1157 }
1158 break;
1159 case CHIP_VEGA10:
1160 case CHIP_VEGA12:
1161 case CHIP_VEGA20:
1162 case CHIP_RENOIR:
1163 adev->num_vmhubs = 2;
1164
1165
1166 /*
1167 * To fulfill 4-level page support,
1168 * vm size is 256TB (48bit), maximum size of Vega10,
1169 * block size 512 (9bit)
1170 */
1171 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
1172 if (amdgpu_sriov_vf(adev))
1173 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
1174 else
1175 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1176 break;
1177 case CHIP_ARCTURUS:
1178 adev->num_vmhubs = 3;
1179
1180 /* Keep the vm size same with Vega20 */
1181 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1182 break;
1183 default:
1184 break;
1185 }
1186
1187 /* This interrupt is VMC page fault.*/
1188 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
1189 &adev->gmc.vm_fault);
1190 if (r)
1191 return r;
1192
1193 if (adev->asic_type == CHIP_ARCTURUS) {
1194 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
1195 &adev->gmc.vm_fault);
1196 if (r)
1197 return r;
1198 }
1199
1200 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
1201 &adev->gmc.vm_fault);
1202
1203 if (r)
1204 return r;
1205
1206 if (!amdgpu_sriov_vf(adev)) {
1207 /* interrupt sent to DF. */
1208 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
1209 &adev->gmc.ecc_irq);
1210 if (r)
1211 return r;
1212 }
1213
1214 /* Set the internal MC address mask
1215 * This is the max address of the GPU's
1216 * internal address space.
1217 */
1218 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
1219
1220 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
1221 if (r) {
1222 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
1223 return r;
1224 }
1225 adev->need_swiotlb = drm_need_swiotlb(44);
1226
1227 if (adev->gmc.xgmi.supported) {
1228 r = gfxhub_v1_1_get_xgmi_info(adev);
1229 if (r)
1230 return r;
1231 }
1232
1233 r = gmc_v9_0_mc_init(adev);
1234 if (r)
1235 return r;
1236
1237 adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev);
1238
1239 /* Memory manager */
1240 r = amdgpu_bo_init(adev);
1241 if (r)
1242 return r;
1243
1244 r = gmc_v9_0_gart_init(adev);
1245 if (r)
1246 return r;
1247
1248 /*
1249 * number of VMs
1250 * VMID 0 is reserved for System
1251 * amdgpu graphics/compute will use VMIDs 1-7
1252 * amdkfd will use VMIDs 8-15
1253 */
1254 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
1255 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
1256 adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS;
1257
1258 amdgpu_vm_manager_init(adev);
1259
1260 return 0;
1261 }
1262
1263 static int gmc_v9_0_sw_fini(void *handle)
1264 {
1265 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1266 void *stolen_vga_buf;
1267
1268 amdgpu_gmc_ras_fini(adev);
1269 amdgpu_gem_force_release(adev);
1270 amdgpu_vm_manager_fini(adev);
1271
1272 if (gmc_v9_0_keep_stolen_memory(adev))
1273 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
1274
1275 amdgpu_gart_table_vram_free(adev);
1276 amdgpu_bo_fini(adev);
1277 amdgpu_gart_fini(adev);
1278
1279 return 0;
1280 }
1281
1282 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1283 {
1284
1285 switch (adev->asic_type) {
1286 case CHIP_VEGA10:
1287 if (amdgpu_sriov_vf(adev))
1288 break;
1289 /* fall through */
1290 case CHIP_VEGA20:
1291 soc15_program_register_sequence(adev,
1292 golden_settings_mmhub_1_0_0,
1293 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1294 soc15_program_register_sequence(adev,
1295 golden_settings_athub_1_0_0,
1296 ARRAY_SIZE(golden_settings_athub_1_0_0));
1297 break;
1298 case CHIP_VEGA12:
1299 break;
1300 case CHIP_RAVEN:
1301 /* TODO for renoir */
1302 soc15_program_register_sequence(adev,
1303 golden_settings_athub_1_0_0,
1304 ARRAY_SIZE(golden_settings_athub_1_0_0));
1305 break;
1306 default:
1307 break;
1308 }
1309 }
1310
1311 /**
1312 * gmc_v9_0_restore_registers - restores regs
1313 *
1314 * @adev: amdgpu_device pointer
1315 *
1316 * This restores register values, saved at suspend.
1317 */
1318 static void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
1319 {
1320 if (adev->asic_type == CHIP_RAVEN)
1321 WREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
1322 }
1323
1324 /**
1325 * gmc_v9_0_gart_enable - gart enable
1326 *
1327 * @adev: amdgpu_device pointer
1328 */
1329 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1330 {
1331 int r;
1332
1333 if (adev->gart.bo == NULL) {
1334 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1335 return -EINVAL;
1336 }
1337 r = amdgpu_gart_table_vram_pin(adev);
1338 if (r)
1339 return r;
1340
1341 r = gfxhub_v1_0_gart_enable(adev);
1342 if (r)
1343 return r;
1344
1345 if (adev->asic_type == CHIP_ARCTURUS)
1346 r = mmhub_v9_4_gart_enable(adev);
1347 else
1348 r = mmhub_v1_0_gart_enable(adev);
1349 if (r)
1350 return r;
1351
1352 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1353 (unsigned)(adev->gmc.gart_size >> 20),
1354 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1355 adev->gart.ready = true;
1356 return 0;
1357 }
1358
1359 static int gmc_v9_0_hw_init(void *handle)
1360 {
1361 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1362 bool value;
1363 int r, i;
1364 u32 tmp;
1365
1366 /* The sequence of these two function calls matters.*/
1367 gmc_v9_0_init_golden_registers(adev);
1368
1369 if (adev->mode_info.num_crtc) {
1370 if (adev->asic_type != CHIP_ARCTURUS) {
1371 /* Lockout access through VGA aperture*/
1372 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1373
1374 /* disable VGA render */
1375 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1376 }
1377 }
1378
1379 amdgpu_device_program_register_sequence(adev,
1380 golden_settings_vega10_hdp,
1381 ARRAY_SIZE(golden_settings_vega10_hdp));
1382
1383 switch (adev->asic_type) {
1384 case CHIP_RAVEN:
1385 /* TODO for renoir */
1386 mmhub_v1_0_update_power_gating(adev, true);
1387 break;
1388 case CHIP_ARCTURUS:
1389 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
1390 break;
1391 default:
1392 break;
1393 }
1394
1395 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
1396
1397 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
1398 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
1399
1400 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
1401 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
1402
1403 /* After HDP is initialized, flush HDP.*/
1404 adev->nbio.funcs->hdp_flush(adev, NULL);
1405
1406 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1407 value = false;
1408 else
1409 value = true;
1410
1411 if (!amdgpu_sriov_vf(adev)) {
1412 gfxhub_v1_0_set_fault_enable_default(adev, value);
1413 if (adev->asic_type == CHIP_ARCTURUS)
1414 mmhub_v9_4_set_fault_enable_default(adev, value);
1415 else
1416 mmhub_v1_0_set_fault_enable_default(adev, value);
1417 }
1418 for (i = 0; i < adev->num_vmhubs; ++i)
1419 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
1420
1421 if (adev->umc.funcs && adev->umc.funcs->init_registers)
1422 adev->umc.funcs->init_registers(adev);
1423
1424 r = gmc_v9_0_gart_enable(adev);
1425
1426 return r;
1427 }
1428
1429 /**
1430 * gmc_v9_0_save_registers - saves regs
1431 *
1432 * @adev: amdgpu_device pointer
1433 *
1434 * This saves potential register values that should be
1435 * restored upon resume
1436 */
1437 static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
1438 {
1439 if (adev->asic_type == CHIP_RAVEN)
1440 adev->gmc.sdpif_register = RREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
1441 }
1442
1443 /**
1444 * gmc_v9_0_gart_disable - gart disable
1445 *
1446 * @adev: amdgpu_device pointer
1447 *
1448 * This disables all VM page table.
1449 */
1450 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1451 {
1452 gfxhub_v1_0_gart_disable(adev);
1453 if (adev->asic_type == CHIP_ARCTURUS)
1454 mmhub_v9_4_gart_disable(adev);
1455 else
1456 mmhub_v1_0_gart_disable(adev);
1457 amdgpu_gart_table_vram_unpin(adev);
1458 }
1459
1460 static int gmc_v9_0_hw_fini(void *handle)
1461 {
1462 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1463
1464 if (amdgpu_sriov_vf(adev)) {
1465 /* full access mode, so don't touch any GMC register */
1466 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1467 return 0;
1468 }
1469
1470 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1471 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1472 gmc_v9_0_gart_disable(adev);
1473
1474 return 0;
1475 }
1476
1477 static int gmc_v9_0_suspend(void *handle)
1478 {
1479 int r;
1480 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1481
1482 r = gmc_v9_0_hw_fini(adev);
1483 if (r)
1484 return r;
1485
1486 gmc_v9_0_save_registers(adev);
1487
1488 return 0;
1489 }
1490
1491 static int gmc_v9_0_resume(void *handle)
1492 {
1493 int r;
1494 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1495
1496 gmc_v9_0_restore_registers(adev);
1497 r = gmc_v9_0_hw_init(adev);
1498 if (r)
1499 return r;
1500
1501 amdgpu_vmid_reset_all(adev);
1502
1503 return 0;
1504 }
1505
1506 static bool gmc_v9_0_is_idle(void *handle)
1507 {
1508 /* MC is always ready in GMC v9.*/
1509 return true;
1510 }
1511
1512 static int gmc_v9_0_wait_for_idle(void *handle)
1513 {
1514 /* There is no need to wait for MC idle in GMC v9.*/
1515 return 0;
1516 }
1517
1518 static int gmc_v9_0_soft_reset(void *handle)
1519 {
1520 /* XXX for emulation.*/
1521 return 0;
1522 }
1523
1524 static int gmc_v9_0_set_clockgating_state(void *handle,
1525 enum amd_clockgating_state state)
1526 {
1527 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1528
1529 if (adev->asic_type == CHIP_ARCTURUS)
1530 mmhub_v9_4_set_clockgating(adev, state);
1531 else
1532 mmhub_v1_0_set_clockgating(adev, state);
1533
1534 athub_v1_0_set_clockgating(adev, state);
1535
1536 return 0;
1537 }
1538
1539 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1540 {
1541 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1542
1543 if (adev->asic_type == CHIP_ARCTURUS)
1544 mmhub_v9_4_get_clockgating(adev, flags);
1545 else
1546 mmhub_v1_0_get_clockgating(adev, flags);
1547
1548 athub_v1_0_get_clockgating(adev, flags);
1549 }
1550
1551 static int gmc_v9_0_set_powergating_state(void *handle,
1552 enum amd_powergating_state state)
1553 {
1554 return 0;
1555 }
1556
1557 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1558 .name = "gmc_v9_0",
1559 .early_init = gmc_v9_0_early_init,
1560 .late_init = gmc_v9_0_late_init,
1561 .sw_init = gmc_v9_0_sw_init,
1562 .sw_fini = gmc_v9_0_sw_fini,
1563 .hw_init = gmc_v9_0_hw_init,
1564 .hw_fini = gmc_v9_0_hw_fini,
1565 .suspend = gmc_v9_0_suspend,
1566 .resume = gmc_v9_0_resume,
1567 .is_idle = gmc_v9_0_is_idle,
1568 .wait_for_idle = gmc_v9_0_wait_for_idle,
1569 .soft_reset = gmc_v9_0_soft_reset,
1570 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1571 .set_powergating_state = gmc_v9_0_set_powergating_state,
1572 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1573 };
1574
1575 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1576 {
1577 .type = AMD_IP_BLOCK_TYPE_GMC,
1578 .major = 9,
1579 .minor = 0,
1580 .rev = 0,
1581 .funcs = &gmc_v9_0_ip_funcs,
1582 };
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