drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __MXGPU_AI_H__
  25 #define __MXGPU_AI_H__
  26
  27 #define AI_MAILBOX_POLL_ACK_TIMEDOUT    500
  28 #define AI_MAILBOX_POLL_MSG_TIMEDOUT    12000
  29 #define AI_MAILBOX_POLL_FLR_TIMEDOUT    5000
  30
  31 enum idh_request {
  32         IDH_REQ_GPU_INIT_ACCESS = 1,
  33         IDH_REL_GPU_INIT_ACCESS,
  34         IDH_REQ_GPU_FINI_ACCESS,
  35         IDH_REL_GPU_FINI_ACCESS,
  36         IDH_REQ_GPU_RESET_ACCESS,
  37
  38         IDH_LOG_VF_ERROR       = 200,
  39 };
  40
  41 enum idh_event {
  42         IDH_CLR_MSG_BUF = 0,
  43         IDH_READY_TO_ACCESS_GPU,
  44         IDH_FLR_NOTIFICATION,
  45         IDH_FLR_NOTIFICATION_CMPL,
  46         IDH_SUCCESS,
  47         IDH_FAIL,
  48         IDH_QUERY_ALIVE,
  49
  50         IDH_TEXT_MESSAGE = 255,
  51 };
  52
  53 extern const struct amdgpu_virt_ops xgpu_ai_virt_ops;
  54
  55 void xgpu_ai_mailbox_set_irq_funcs(struct amdgpu_device *adev);
  56 int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev);
  57 int xgpu_ai_mailbox_get_irq(struct amdgpu_device *adev);
  58 void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev);
  59
  60 #define AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4
  61 #define AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 + 1
  62
  63 #endif