2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
28 #include "amdgpu_atombios.h"
29 #include "amdgpu_ih.h"
30 #include "amdgpu_uvd.h"
31 #include "amdgpu_vce.h"
32 #include "amdgpu_ucode.h"
33 #include "amdgpu_psp.h"
34 #include "amdgpu_smu.h"
38 #include "gc/gc_10_1_0_offset.h"
39 #include "gc/gc_10_1_0_sh_mask.h"
40 #include "hdp/hdp_5_0_0_offset.h"
41 #include "hdp/hdp_5_0_0_sh_mask.h"
44 #include "soc15_common.h"
45 #include "gmc_v10_0.h"
46 #include "gfxhub_v2_0.h"
47 #include "mmhub_v2_0.h"
49 #include "navi10_ih.h"
50 #include "gfx_v10_0.h"
51 #include "sdma_v5_0.h"
53 #include "dce_virtual.h"
54 #include "mes_v10_1.h"
56 static const struct amd_ip_funcs nv_common_ip_funcs
;
59 * Indirect registers accessor
61 static u32
nv_pcie_rreg(struct amdgpu_device
*adev
, u32 reg
)
63 unsigned long flags
, address
, data
;
65 address
= adev
->nbio_funcs
->get_pcie_index_offset(adev
);
66 data
= adev
->nbio_funcs
->get_pcie_data_offset(adev
);
68 spin_lock_irqsave(&adev
->pcie_idx_lock
, flags
);
70 (void)RREG32(address
);
72 spin_unlock_irqrestore(&adev
->pcie_idx_lock
, flags
);
76 static void nv_pcie_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
78 unsigned long flags
, address
, data
;
80 address
= adev
->nbio_funcs
->get_pcie_index_offset(adev
);
81 data
= adev
->nbio_funcs
->get_pcie_data_offset(adev
);
83 spin_lock_irqsave(&adev
->pcie_idx_lock
, flags
);
85 (void)RREG32(address
);
88 spin_unlock_irqrestore(&adev
->pcie_idx_lock
, flags
);
91 static u32
nv_didt_rreg(struct amdgpu_device
*adev
, u32 reg
)
93 unsigned long flags
, address
, data
;
96 address
= SOC15_REG_OFFSET(GC
, 0, mmDIDT_IND_INDEX
);
97 data
= SOC15_REG_OFFSET(GC
, 0, mmDIDT_IND_DATA
);
99 spin_lock_irqsave(&adev
->didt_idx_lock
, flags
);
100 WREG32(address
, (reg
));
102 spin_unlock_irqrestore(&adev
->didt_idx_lock
, flags
);
106 static void nv_didt_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
108 unsigned long flags
, address
, data
;
110 address
= SOC15_REG_OFFSET(GC
, 0, mmDIDT_IND_INDEX
);
111 data
= SOC15_REG_OFFSET(GC
, 0, mmDIDT_IND_DATA
);
113 spin_lock_irqsave(&adev
->didt_idx_lock
, flags
);
114 WREG32(address
, (reg
));
116 spin_unlock_irqrestore(&adev
->didt_idx_lock
, flags
);
119 static u32
nv_get_config_memsize(struct amdgpu_device
*adev
)
121 return adev
->nbio_funcs
->get_memsize(adev
);
124 static u32
nv_get_xclk(struct amdgpu_device
*adev
)
126 return adev
->clock
.spll
.reference_freq
;
130 void nv_grbm_select(struct amdgpu_device
*adev
,
131 u32 me
, u32 pipe
, u32 queue
, u32 vmid
)
133 u32 grbm_gfx_cntl
= 0;
134 grbm_gfx_cntl
= REG_SET_FIELD(grbm_gfx_cntl
, GRBM_GFX_CNTL
, PIPEID
, pipe
);
135 grbm_gfx_cntl
= REG_SET_FIELD(grbm_gfx_cntl
, GRBM_GFX_CNTL
, MEID
, me
);
136 grbm_gfx_cntl
= REG_SET_FIELD(grbm_gfx_cntl
, GRBM_GFX_CNTL
, VMID
, vmid
);
137 grbm_gfx_cntl
= REG_SET_FIELD(grbm_gfx_cntl
, GRBM_GFX_CNTL
, QUEUEID
, queue
);
139 WREG32(SOC15_REG_OFFSET(GC
, 0, mmGRBM_GFX_CNTL
), grbm_gfx_cntl
);
142 static void nv_vga_set_state(struct amdgpu_device
*adev
, bool state
)
147 static bool nv_read_disabled_bios(struct amdgpu_device
*adev
)
153 static bool nv_read_bios_from_rom(struct amdgpu_device
*adev
,
154 u8
*bios
, u32 length_bytes
)
156 /* TODO: will implement it when SMU header is available */
160 static struct soc15_allowed_register_entry nv_allowed_read_registers
[] = {
161 { SOC15_REG_ENTRY(GC
, 0, mmGRBM_STATUS
)},
162 { SOC15_REG_ENTRY(GC
, 0, mmGRBM_STATUS2
)},
163 { SOC15_REG_ENTRY(GC
, 0, mmGRBM_STATUS_SE0
)},
164 { SOC15_REG_ENTRY(GC
, 0, mmGRBM_STATUS_SE1
)},
165 { SOC15_REG_ENTRY(GC
, 0, mmGRBM_STATUS_SE2
)},
166 { SOC15_REG_ENTRY(GC
, 0, mmGRBM_STATUS_SE3
)},
167 #if 0 /* TODO: will set it when SDMA header is available */
168 { SOC15_REG_ENTRY(SDMA0
, 0, mmSDMA0_STATUS_REG
)},
169 { SOC15_REG_ENTRY(SDMA1
, 0, mmSDMA1_STATUS_REG
)},
171 { SOC15_REG_ENTRY(GC
, 0, mmCP_STAT
)},
172 { SOC15_REG_ENTRY(GC
, 0, mmCP_STALLED_STAT1
)},
173 { SOC15_REG_ENTRY(GC
, 0, mmCP_STALLED_STAT2
)},
174 { SOC15_REG_ENTRY(GC
, 0, mmCP_STALLED_STAT3
)},
175 { SOC15_REG_ENTRY(GC
, 0, mmCP_CPF_BUSY_STAT
)},
176 { SOC15_REG_ENTRY(GC
, 0, mmCP_CPF_STALLED_STAT1
)},
177 { SOC15_REG_ENTRY(GC
, 0, mmCP_CPF_STATUS
)},
178 { SOC15_REG_ENTRY(GC
, 0, mmCP_CPC_STALLED_STAT1
)},
179 { SOC15_REG_ENTRY(GC
, 0, mmCP_CPC_STATUS
)},
180 { SOC15_REG_ENTRY(GC
, 0, mmGB_ADDR_CONFIG
)},
183 static uint32_t nv_read_indexed_register(struct amdgpu_device
*adev
, u32 se_num
,
184 u32 sh_num
, u32 reg_offset
)
188 mutex_lock(&adev
->grbm_idx_mutex
);
189 if (se_num
!= 0xffffffff || sh_num
!= 0xffffffff)
190 amdgpu_gfx_select_se_sh(adev
, se_num
, sh_num
, 0xffffffff);
192 val
= RREG32(reg_offset
);
194 if (se_num
!= 0xffffffff || sh_num
!= 0xffffffff)
195 amdgpu_gfx_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
196 mutex_unlock(&adev
->grbm_idx_mutex
);
200 static uint32_t nv_get_register_value(struct amdgpu_device
*adev
,
201 bool indexed
, u32 se_num
,
202 u32 sh_num
, u32 reg_offset
)
205 return nv_read_indexed_register(adev
, se_num
, sh_num
, reg_offset
);
207 if (reg_offset
== SOC15_REG_OFFSET(GC
, 0, mmGB_ADDR_CONFIG
))
208 return adev
->gfx
.config
.gb_addr_config
;
209 return RREG32(reg_offset
);
213 static int nv_read_register(struct amdgpu_device
*adev
, u32 se_num
,
214 u32 sh_num
, u32 reg_offset
, u32
*value
)
217 struct soc15_allowed_register_entry
*en
;
220 for (i
= 0; i
< ARRAY_SIZE(nv_allowed_read_registers
); i
++) {
221 en
= &nv_allowed_read_registers
[i
];
223 (adev
->reg_offset
[en
->hwip
][en
->inst
][en
->seg
] + en
->reg_offset
))
226 *value
= nv_get_register_value(adev
,
227 nv_allowed_read_registers
[i
].grbm_indexed
,
228 se_num
, sh_num
, reg_offset
);
235 static void nv_gpu_pci_config_reset(struct amdgpu_device
*adev
)
239 dev_info(adev
->dev
, "GPU pci config reset\n");
242 pci_clear_master(adev
->pdev
);
244 amdgpu_pci_config_reset(adev
);
248 /* wait for asic to come out of reset */
249 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
250 u32 memsize
= nbio_v2_3_get_memsize(adev
);
251 if (memsize
!= 0xffffffff)
259 static int nv_asic_mode1_reset(struct amdgpu_device
*adev
)
264 amdgpu_atombios_scratch_regs_engine_hung(adev
, true);
266 dev_info(adev
->dev
, "GPU mode1 reset\n");
269 pci_clear_master(adev
->pdev
);
271 pci_save_state(adev
->pdev
);
273 ret
= psp_gpu_reset(adev
);
275 dev_err(adev
->dev
, "GPU mode1 reset failed\n");
277 pci_restore_state(adev
->pdev
);
279 /* wait for asic to come out of reset */
280 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
281 u32 memsize
= adev
->nbio_funcs
->get_memsize(adev
);
283 if (memsize
!= 0xffffffff)
288 amdgpu_atombios_scratch_regs_engine_hung(adev
, false);
292 static int nv_asic_reset(struct amdgpu_device
*adev
)
295 /* FIXME: it doesn't work since vega10 */
297 amdgpu_atombios_scratch_regs_engine_hung(adev
, true);
299 nv_gpu_pci_config_reset(adev
);
301 amdgpu_atombios_scratch_regs_engine_hung(adev
, false);
304 struct smu_context
*smu
= &adev
->smu
;
306 if (smu_baco_is_support(smu
))
307 ret
= smu_baco_reset(smu
);
309 ret
= nv_asic_mode1_reset(adev
);
314 static int nv_set_uvd_clocks(struct amdgpu_device
*adev
, u32 vclk
, u32 dclk
)
320 static int nv_set_vce_clocks(struct amdgpu_device
*adev
, u32 evclk
, u32 ecclk
)
326 static void nv_pcie_gen3_enable(struct amdgpu_device
*adev
)
328 if (pci_is_root_bus(adev
->pdev
->bus
))
331 if (amdgpu_pcie_gen2
== 0)
334 if (!(adev
->pm
.pcie_gen_mask
& (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2
|
335 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3
)))
341 static void nv_program_aspm(struct amdgpu_device
*adev
)
344 if (amdgpu_aspm
== 0)
350 static void nv_enable_doorbell_aperture(struct amdgpu_device
*adev
,
353 adev
->nbio_funcs
->enable_doorbell_aperture(adev
, enable
);
354 adev
->nbio_funcs
->enable_doorbell_selfring_aperture(adev
, enable
);
357 static const struct amdgpu_ip_block_version nv_common_ip_block
=
359 .type
= AMD_IP_BLOCK_TYPE_COMMON
,
363 .funcs
= &nv_common_ip_funcs
,
366 int nv_set_ip_blocks(struct amdgpu_device
*adev
)
368 /* Set IP register base before any HW register access */
369 switch (adev
->asic_type
) {
371 navi10_reg_base_init(adev
);
377 adev
->nbio_funcs
= &nbio_v2_3_funcs
;
379 adev
->nbio_funcs
->detect_hw_virt(adev
);
381 switch (adev
->asic_type
) {
383 amdgpu_device_ip_block_add(adev
, &nv_common_ip_block
);
384 amdgpu_device_ip_block_add(adev
, &gmc_v10_0_ip_block
);
385 amdgpu_device_ip_block_add(adev
, &navi10_ih_ip_block
);
386 amdgpu_device_ip_block_add(adev
, &psp_v11_0_ip_block
);
387 if (adev
->firmware
.load_type
== AMDGPU_FW_LOAD_PSP
&&
388 is_support_sw_smu(adev
))
389 amdgpu_device_ip_block_add(adev
, &smu_v11_0_ip_block
);
390 if (adev
->enable_virtual_display
|| amdgpu_sriov_vf(adev
))
391 amdgpu_device_ip_block_add(adev
, &dce_virtual_ip_block
);
392 #if defined(CONFIG_DRM_AMD_DC)
393 else if (amdgpu_device_has_dc_support(adev
))
394 amdgpu_device_ip_block_add(adev
, &dm_ip_block
);
396 amdgpu_device_ip_block_add(adev
, &gfx_v10_0_ip_block
);
397 amdgpu_device_ip_block_add(adev
, &sdma_v5_0_ip_block
);
398 if (adev
->firmware
.load_type
== AMDGPU_FW_LOAD_DIRECT
&&
399 is_support_sw_smu(adev
))
400 amdgpu_device_ip_block_add(adev
, &smu_v11_0_ip_block
);
401 amdgpu_device_ip_block_add(adev
, &vcn_v2_0_ip_block
);
402 if (adev
->enable_mes
)
403 amdgpu_device_ip_block_add(adev
, &mes_v10_1_ip_block
);
412 static uint32_t nv_get_rev_id(struct amdgpu_device
*adev
)
414 return adev
->nbio_funcs
->get_rev_id(adev
);
417 static void nv_flush_hdp(struct amdgpu_device
*adev
, struct amdgpu_ring
*ring
)
419 adev
->nbio_funcs
->hdp_flush(adev
, ring
);
422 static void nv_invalidate_hdp(struct amdgpu_device
*adev
,
423 struct amdgpu_ring
*ring
)
425 if (!ring
|| !ring
->funcs
->emit_wreg
) {
426 WREG32_SOC15_NO_KIQ(NBIO
, 0, mmHDP_READ_CACHE_INVALIDATE
, 1);
428 amdgpu_ring_emit_wreg(ring
, SOC15_REG_OFFSET(
429 HDP
, 0, mmHDP_READ_CACHE_INVALIDATE
), 1);
433 static bool nv_need_full_reset(struct amdgpu_device
*adev
)
438 static void nv_get_pcie_usage(struct amdgpu_device
*adev
,
445 static bool nv_need_reset_on_init(struct amdgpu_device
*adev
)
450 if (adev
->flags
& AMD_IS_APU
)
453 /* Check sOS sign of life register to confirm sys driver and sOS
454 * are already been loaded.
456 sol_reg
= RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_81
);
460 /* TODO: re-enable it when mode1 reset is functional */
464 static void nv_init_doorbell_index(struct amdgpu_device
*adev
)
466 adev
->doorbell_index
.kiq
= AMDGPU_NAVI10_DOORBELL_KIQ
;
467 adev
->doorbell_index
.mec_ring0
= AMDGPU_NAVI10_DOORBELL_MEC_RING0
;
468 adev
->doorbell_index
.mec_ring1
= AMDGPU_NAVI10_DOORBELL_MEC_RING1
;
469 adev
->doorbell_index
.mec_ring2
= AMDGPU_NAVI10_DOORBELL_MEC_RING2
;
470 adev
->doorbell_index
.mec_ring3
= AMDGPU_NAVI10_DOORBELL_MEC_RING3
;
471 adev
->doorbell_index
.mec_ring4
= AMDGPU_NAVI10_DOORBELL_MEC_RING4
;
472 adev
->doorbell_index
.mec_ring5
= AMDGPU_NAVI10_DOORBELL_MEC_RING5
;
473 adev
->doorbell_index
.mec_ring6
= AMDGPU_NAVI10_DOORBELL_MEC_RING6
;
474 adev
->doorbell_index
.mec_ring7
= AMDGPU_NAVI10_DOORBELL_MEC_RING7
;
475 adev
->doorbell_index
.userqueue_start
= AMDGPU_NAVI10_DOORBELL_USERQUEUE_START
;
476 adev
->doorbell_index
.userqueue_end
= AMDGPU_NAVI10_DOORBELL_USERQUEUE_END
;
477 adev
->doorbell_index
.gfx_ring0
= AMDGPU_NAVI10_DOORBELL_GFX_RING0
;
478 adev
->doorbell_index
.gfx_ring1
= AMDGPU_NAVI10_DOORBELL_GFX_RING1
;
479 adev
->doorbell_index
.sdma_engine
[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0
;
480 adev
->doorbell_index
.sdma_engine
[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1
;
481 adev
->doorbell_index
.ih
= AMDGPU_NAVI10_DOORBELL_IH
;
482 adev
->doorbell_index
.vcn
.vcn_ring0_1
= AMDGPU_NAVI10_DOORBELL64_VCN0_1
;
483 adev
->doorbell_index
.vcn
.vcn_ring2_3
= AMDGPU_NAVI10_DOORBELL64_VCN2_3
;
484 adev
->doorbell_index
.vcn
.vcn_ring4_5
= AMDGPU_NAVI10_DOORBELL64_VCN4_5
;
485 adev
->doorbell_index
.vcn
.vcn_ring6_7
= AMDGPU_NAVI10_DOORBELL64_VCN6_7
;
486 adev
->doorbell_index
.first_non_cp
= AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP
;
487 adev
->doorbell_index
.last_non_cp
= AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP
;
489 adev
->doorbell_index
.max_assignment
= AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT
<< 1;
490 adev
->doorbell_index
.sdma_doorbell_range
= 20;
493 static const struct amdgpu_asic_funcs nv_asic_funcs
=
495 .read_disabled_bios
= &nv_read_disabled_bios
,
496 .read_bios_from_rom
= &nv_read_bios_from_rom
,
497 .read_register
= &nv_read_register
,
498 .reset
= &nv_asic_reset
,
499 .set_vga_state
= &nv_vga_set_state
,
500 .get_xclk
= &nv_get_xclk
,
501 .set_uvd_clocks
= &nv_set_uvd_clocks
,
502 .set_vce_clocks
= &nv_set_vce_clocks
,
503 .get_config_memsize
= &nv_get_config_memsize
,
504 .flush_hdp
= &nv_flush_hdp
,
505 .invalidate_hdp
= &nv_invalidate_hdp
,
506 .init_doorbell_index
= &nv_init_doorbell_index
,
507 .need_full_reset
= &nv_need_full_reset
,
508 .get_pcie_usage
= &nv_get_pcie_usage
,
509 .need_reset_on_init
= &nv_need_reset_on_init
,
512 static int nv_common_early_init(void *handle
)
514 bool psp_enabled
= false;
515 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
517 adev
->smc_rreg
= NULL
;
518 adev
->smc_wreg
= NULL
;
519 adev
->pcie_rreg
= &nv_pcie_rreg
;
520 adev
->pcie_wreg
= &nv_pcie_wreg
;
522 /* TODO: will add them during VCN v2 implementation */
523 adev
->uvd_ctx_rreg
= NULL
;
524 adev
->uvd_ctx_wreg
= NULL
;
526 adev
->didt_rreg
= &nv_didt_rreg
;
527 adev
->didt_wreg
= &nv_didt_wreg
;
529 adev
->asic_funcs
= &nv_asic_funcs
;
531 if (amdgpu_device_ip_get_ip_block(adev
, AMD_IP_BLOCK_TYPE_PSP
) &&
532 (amdgpu_ip_block_mask
& (1 << AMD_IP_BLOCK_TYPE_PSP
)))
535 adev
->rev_id
= nv_get_rev_id(adev
);
536 adev
->external_rev_id
= 0xff;
537 switch (adev
->asic_type
) {
539 adev
->cg_flags
= AMD_CG_SUPPORT_GFX_MGCG
|
540 AMD_CG_SUPPORT_GFX_CGCG
|
541 AMD_CG_SUPPORT_IH_CG
|
542 AMD_CG_SUPPORT_HDP_MGCG
|
543 AMD_CG_SUPPORT_HDP_LS
|
544 AMD_CG_SUPPORT_SDMA_MGCG
|
545 AMD_CG_SUPPORT_SDMA_LS
|
546 AMD_CG_SUPPORT_MC_MGCG
|
547 AMD_CG_SUPPORT_MC_LS
|
548 AMD_CG_SUPPORT_ATHUB_MGCG
|
549 AMD_CG_SUPPORT_ATHUB_LS
|
550 AMD_CG_SUPPORT_VCN_MGCG
|
551 AMD_CG_SUPPORT_BIF_MGCG
|
552 AMD_CG_SUPPORT_BIF_LS
;
553 adev
->pg_flags
= AMD_PG_SUPPORT_VCN
|
554 AMD_PG_SUPPORT_VCN_DPG
|
555 AMD_PG_SUPPORT_ATHUB
;
556 adev
->external_rev_id
= adev
->rev_id
+ 0x1;
559 /* FIXME: not supported yet */
566 static int nv_common_late_init(void *handle
)
571 static int nv_common_sw_init(void *handle
)
576 static int nv_common_sw_fini(void *handle
)
581 static int nv_common_hw_init(void *handle
)
583 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
585 /* enable pcie gen2/3 link */
586 nv_pcie_gen3_enable(adev
);
588 nv_program_aspm(adev
);
589 /* setup nbio registers */
590 adev
->nbio_funcs
->init_registers(adev
);
591 /* enable the doorbell aperture */
592 nv_enable_doorbell_aperture(adev
, true);
597 static int nv_common_hw_fini(void *handle
)
599 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
601 /* disable the doorbell aperture */
602 nv_enable_doorbell_aperture(adev
, false);
607 static int nv_common_suspend(void *handle
)
609 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
611 return nv_common_hw_fini(adev
);
614 static int nv_common_resume(void *handle
)
616 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
618 return nv_common_hw_init(adev
);
621 static bool nv_common_is_idle(void *handle
)
626 static int nv_common_wait_for_idle(void *handle
)
631 static int nv_common_soft_reset(void *handle
)
636 static void nv_update_hdp_mem_power_gating(struct amdgpu_device
*adev
,
639 uint32_t hdp_clk_cntl
, hdp_clk_cntl1
;
640 uint32_t hdp_mem_pwr_cntl
;
642 if (!(adev
->cg_flags
& (AMD_CG_SUPPORT_HDP_LS
|
643 AMD_CG_SUPPORT_HDP_DS
|
644 AMD_CG_SUPPORT_HDP_SD
)))
647 hdp_clk_cntl
= hdp_clk_cntl1
= RREG32_SOC15(HDP
, 0, mmHDP_CLK_CNTL
);
648 hdp_mem_pwr_cntl
= RREG32_SOC15(HDP
, 0, mmHDP_MEM_POWER_CTRL
);
650 /* Before doing clock/power mode switch,
651 * forced on IPH & RC clock */
652 hdp_clk_cntl
= REG_SET_FIELD(hdp_clk_cntl
, HDP_CLK_CNTL
,
653 IPH_MEM_CLK_SOFT_OVERRIDE
, 1);
654 hdp_clk_cntl
= REG_SET_FIELD(hdp_clk_cntl
, HDP_CLK_CNTL
,
655 RC_MEM_CLK_SOFT_OVERRIDE
, 1);
656 WREG32_SOC15(HDP
, 0, mmHDP_CLK_CNTL
, hdp_clk_cntl
);
658 /* HDP 5.0 doesn't support dynamic power mode switch,
659 * disable clock and power gating before any changing */
660 hdp_mem_pwr_cntl
= REG_SET_FIELD(hdp_mem_pwr_cntl
, HDP_MEM_POWER_CTRL
,
661 IPH_MEM_POWER_CTRL_EN
, 0);
662 hdp_mem_pwr_cntl
= REG_SET_FIELD(hdp_mem_pwr_cntl
, HDP_MEM_POWER_CTRL
,
663 IPH_MEM_POWER_LS_EN
, 0);
664 hdp_mem_pwr_cntl
= REG_SET_FIELD(hdp_mem_pwr_cntl
, HDP_MEM_POWER_CTRL
,
665 IPH_MEM_POWER_DS_EN
, 0);
666 hdp_mem_pwr_cntl
= REG_SET_FIELD(hdp_mem_pwr_cntl
, HDP_MEM_POWER_CTRL
,
667 IPH_MEM_POWER_SD_EN
, 0);
668 hdp_mem_pwr_cntl
= REG_SET_FIELD(hdp_mem_pwr_cntl
, HDP_MEM_POWER_CTRL
,
669 RC_MEM_POWER_CTRL_EN
, 0);
670 hdp_mem_pwr_cntl
= REG_SET_FIELD(hdp_mem_pwr_cntl
, HDP_MEM_POWER_CTRL
,
671 RC_MEM_POWER_LS_EN
, 0);
672 hdp_mem_pwr_cntl
= REG_SET_FIELD(hdp_mem_pwr_cntl
, HDP_MEM_POWER_CTRL
,
673 RC_MEM_POWER_DS_EN
, 0);
674 hdp_mem_pwr_cntl
= REG_SET_FIELD(hdp_mem_pwr_cntl
, HDP_MEM_POWER_CTRL
,
675 RC_MEM_POWER_SD_EN
, 0);
676 WREG32_SOC15(HDP
, 0, mmHDP_MEM_POWER_CTRL
, hdp_mem_pwr_cntl
);
678 /* only one clock gating mode (LS/DS/SD) can be enabled */
679 if (adev
->cg_flags
& AMD_CG_SUPPORT_HDP_LS
) {
680 hdp_mem_pwr_cntl
= REG_SET_FIELD(hdp_mem_pwr_cntl
,
682 IPH_MEM_POWER_LS_EN
, enable
);
683 hdp_mem_pwr_cntl
= REG_SET_FIELD(hdp_mem_pwr_cntl
,
685 RC_MEM_POWER_LS_EN
, enable
);
686 } else if (adev
->cg_flags
& AMD_CG_SUPPORT_HDP_DS
) {
687 hdp_mem_pwr_cntl
= REG_SET_FIELD(hdp_mem_pwr_cntl
,
689 IPH_MEM_POWER_DS_EN
, enable
);
690 hdp_mem_pwr_cntl
= REG_SET_FIELD(hdp_mem_pwr_cntl
,
692 RC_MEM_POWER_DS_EN
, enable
);
693 } else if (adev
->cg_flags
& AMD_CG_SUPPORT_HDP_SD
) {
694 hdp_mem_pwr_cntl
= REG_SET_FIELD(hdp_mem_pwr_cntl
,
696 IPH_MEM_POWER_SD_EN
, enable
);
697 /* RC should not use shut down mode, fallback to ds */
698 hdp_mem_pwr_cntl
= REG_SET_FIELD(hdp_mem_pwr_cntl
,
700 RC_MEM_POWER_DS_EN
, enable
);
703 WREG32_SOC15(HDP
, 0, mmHDP_MEM_POWER_CTRL
, hdp_mem_pwr_cntl
);
705 /* restore IPH & RC clock override after clock/power mode changing */
706 WREG32_SOC15(HDP
, 0, mmHDP_CLK_CNTL
, hdp_clk_cntl1
);
709 static void nv_update_hdp_clock_gating(struct amdgpu_device
*adev
,
712 uint32_t hdp_clk_cntl
;
714 if (!(adev
->cg_flags
& AMD_CG_SUPPORT_HDP_MGCG
))
717 hdp_clk_cntl
= RREG32_SOC15(HDP
, 0, mmHDP_CLK_CNTL
);
722 (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK
|
723 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK
|
724 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK
|
725 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK
|
726 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK
|
727 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK
);
729 hdp_clk_cntl
|= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK
|
730 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK
|
731 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK
|
732 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK
|
733 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK
|
734 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK
;
737 WREG32_SOC15(HDP
, 0, mmHDP_CLK_CNTL
, hdp_clk_cntl
);
740 static int nv_common_set_clockgating_state(void *handle
,
741 enum amd_clockgating_state state
)
743 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
745 if (amdgpu_sriov_vf(adev
))
748 switch (adev
->asic_type
) {
750 adev
->nbio_funcs
->update_medium_grain_clock_gating(adev
,
751 state
== AMD_CG_STATE_GATE
? true : false);
752 adev
->nbio_funcs
->update_medium_grain_light_sleep(adev
,
753 state
== AMD_CG_STATE_GATE
? true : false);
754 nv_update_hdp_mem_power_gating(adev
,
755 state
== AMD_CG_STATE_GATE
? true : false);
756 nv_update_hdp_clock_gating(adev
,
757 state
== AMD_CG_STATE_GATE
? true : false);
765 static int nv_common_set_powergating_state(void *handle
,
766 enum amd_powergating_state state
)
772 static void nv_common_get_clockgating_state(void *handle
, u32
*flags
)
774 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
777 if (amdgpu_sriov_vf(adev
))
780 adev
->nbio_funcs
->get_clockgating_state(adev
, flags
);
782 /* AMD_CG_SUPPORT_HDP_MGCG */
783 tmp
= RREG32_SOC15(HDP
, 0, mmHDP_CLK_CNTL
);
784 if (!(tmp
& (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK
|
785 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK
|
786 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK
|
787 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK
|
788 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK
|
789 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK
)))
790 *flags
|= AMD_CG_SUPPORT_HDP_MGCG
;
792 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
793 tmp
= RREG32_SOC15(HDP
, 0, mmHDP_MEM_POWER_CTRL
);
794 if (tmp
& HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK
)
795 *flags
|= AMD_CG_SUPPORT_HDP_LS
;
796 else if (tmp
& HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK
)
797 *flags
|= AMD_CG_SUPPORT_HDP_DS
;
798 else if (tmp
& HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK
)
799 *flags
|= AMD_CG_SUPPORT_HDP_SD
;
804 static const struct amd_ip_funcs nv_common_ip_funcs
= {
806 .early_init
= nv_common_early_init
,
807 .late_init
= nv_common_late_init
,
808 .sw_init
= nv_common_sw_init
,
809 .sw_fini
= nv_common_sw_fini
,
810 .hw_init
= nv_common_hw_init
,
811 .hw_fini
= nv_common_hw_fini
,
812 .suspend
= nv_common_suspend
,
813 .resume
= nv_common_resume
,
814 .is_idle
= nv_common_is_idle
,
815 .wait_for_idle
= nv_common_wait_for_idle
,
816 .soft_reset
= nv_common_soft_reset
,
817 .set_clockgating_state
= nv_common_set_clockgating_state
,
818 .set_powergating_state
= nv_common_set_powergating_state
,
819 .get_clockgating_state
= nv_common_get_clockgating_state
,