2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
31 #include "amdgpu_psp.h"
32 #include "amdgpu_ucode.h"
33 #include "soc15_common.h"
34 #include "psp_v10_0.h"
36 #include "mp/mp_10_0_offset.h"
37 #include "gc/gc_9_1_offset.h"
38 #include "sdma0/sdma0_4_1_offset.h"
40 MODULE_FIRMWARE("amdgpu/raven_asd.bin");
41 MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
42 MODULE_FIRMWARE("amdgpu/raven2_asd.bin");
44 static int psp_v10_0_init_microcode(struct psp_context
*psp
)
46 struct amdgpu_device
*adev
= psp
->adev
;
47 const char *chip_name
;
50 const struct psp_firmware_header_v1_0
*hdr
;
54 switch (adev
->asic_type
) {
56 if (adev
->rev_id
>= 0x8)
58 else if (adev
->pdev
->device
== 0x15d8)
59 chip_name
= "picasso";
66 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_asd.bin", chip_name
);
67 err
= request_firmware(&adev
->psp
.asd_fw
, fw_name
, adev
->dev
);
71 err
= amdgpu_ucode_validate(adev
->psp
.asd_fw
);
75 hdr
= (const struct psp_firmware_header_v1_0
*)adev
->psp
.asd_fw
->data
;
76 adev
->psp
.asd_fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
77 adev
->psp
.asd_feature_version
= le32_to_cpu(hdr
->ucode_feature_version
);
78 adev
->psp
.asd_ucode_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
);
79 adev
->psp
.asd_start_addr
= (uint8_t *)hdr
+
80 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
);
86 "psp v10.0: Failed to load firmware \"%s\"\n",
88 release_firmware(adev
->psp
.asd_fw
);
89 adev
->psp
.asd_fw
= NULL
;
95 static int psp_v10_0_ring_init(struct psp_context
*psp
,
96 enum psp_ring_type ring_type
)
99 struct psp_ring
*ring
;
100 struct amdgpu_device
*adev
= psp
->adev
;
102 ring
= &psp
->km_ring
;
104 ring
->ring_type
= ring_type
;
106 /* allocate 4k Page of Local Frame Buffer memory for ring */
107 ring
->ring_size
= 0x1000;
108 ret
= amdgpu_bo_create_kernel(adev
, ring
->ring_size
, PAGE_SIZE
,
109 AMDGPU_GEM_DOMAIN_VRAM
,
110 &adev
->firmware
.rbuf
,
111 &ring
->ring_mem_mc_addr
,
112 (void **)&ring
->ring_mem
);
121 static int psp_v10_0_ring_create(struct psp_context
*psp
,
122 enum psp_ring_type ring_type
)
125 unsigned int psp_ring_reg
= 0;
126 struct psp_ring
*ring
= &psp
->km_ring
;
127 struct amdgpu_device
*adev
= psp
->adev
;
129 /* Write low address of the ring to C2PMSG_69 */
130 psp_ring_reg
= lower_32_bits(ring
->ring_mem_mc_addr
);
131 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_69
, psp_ring_reg
);
132 /* Write high address of the ring to C2PMSG_70 */
133 psp_ring_reg
= upper_32_bits(ring
->ring_mem_mc_addr
);
134 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_70
, psp_ring_reg
);
135 /* Write size of ring to C2PMSG_71 */
136 psp_ring_reg
= ring
->ring_size
;
137 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_71
, psp_ring_reg
);
138 /* Write the ring initialization command to C2PMSG_64 */
139 psp_ring_reg
= ring_type
;
140 psp_ring_reg
= psp_ring_reg
<< 16;
141 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_64
, psp_ring_reg
);
143 /* There might be handshake issue with hardware which needs delay */
146 /* Wait for response flag (bit 31) in C2PMSG_64 */
147 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_64
),
148 0x80000000, 0x8000FFFF, false);
153 static int psp_v10_0_ring_stop(struct psp_context
*psp
,
154 enum psp_ring_type ring_type
)
157 unsigned int psp_ring_reg
= 0;
158 struct amdgpu_device
*adev
= psp
->adev
;
160 /* Write the ring destroy command to C2PMSG_64 */
161 psp_ring_reg
= 3 << 16;
162 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_64
, psp_ring_reg
);
164 /* There might be handshake issue with hardware which needs delay */
167 /* Wait for response flag (bit 31) in C2PMSG_64 */
168 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_64
),
169 0x80000000, 0x80000000, false);
174 static int psp_v10_0_ring_destroy(struct psp_context
*psp
,
175 enum psp_ring_type ring_type
)
178 struct psp_ring
*ring
= &psp
->km_ring
;
179 struct amdgpu_device
*adev
= psp
->adev
;
181 ret
= psp_v10_0_ring_stop(psp
, ring_type
);
183 DRM_ERROR("Fail to stop psp ring\n");
185 amdgpu_bo_free_kernel(&adev
->firmware
.rbuf
,
186 &ring
->ring_mem_mc_addr
,
187 (void **)&ring
->ring_mem
);
192 static int psp_v10_0_cmd_submit(struct psp_context
*psp
,
193 struct amdgpu_firmware_info
*ucode
,
194 uint64_t cmd_buf_mc_addr
, uint64_t fence_mc_addr
,
197 unsigned int psp_write_ptr_reg
= 0;
198 struct psp_gfx_rb_frame
* write_frame
= psp
->km_ring
.ring_mem
;
199 struct psp_ring
*ring
= &psp
->km_ring
;
200 struct psp_gfx_rb_frame
*ring_buffer_start
= ring
->ring_mem
;
201 struct psp_gfx_rb_frame
*ring_buffer_end
= ring_buffer_start
+
202 ring
->ring_size
/ sizeof(struct psp_gfx_rb_frame
) - 1;
203 struct amdgpu_device
*adev
= psp
->adev
;
204 uint32_t ring_size_dw
= ring
->ring_size
/ 4;
205 uint32_t rb_frame_size_dw
= sizeof(struct psp_gfx_rb_frame
) / 4;
207 /* KM (GPCOM) prepare write pointer */
208 psp_write_ptr_reg
= RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_67
);
210 /* Update KM RB frame pointer to new frame */
211 if ((psp_write_ptr_reg
% ring_size_dw
) == 0)
212 write_frame
= ring_buffer_start
;
214 write_frame
= ring_buffer_start
+ (psp_write_ptr_reg
/ rb_frame_size_dw
);
215 /* Check invalid write_frame ptr address */
216 if ((write_frame
< ring_buffer_start
) || (ring_buffer_end
< write_frame
)) {
217 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
218 ring_buffer_start
, ring_buffer_end
, write_frame
);
219 DRM_ERROR("write_frame is pointing to address out of bounds\n");
223 /* Initialize KM RB frame */
224 memset(write_frame
, 0, sizeof(struct psp_gfx_rb_frame
));
226 /* Update KM RB frame */
227 write_frame
->cmd_buf_addr_hi
= upper_32_bits(cmd_buf_mc_addr
);
228 write_frame
->cmd_buf_addr_lo
= lower_32_bits(cmd_buf_mc_addr
);
229 write_frame
->fence_addr_hi
= upper_32_bits(fence_mc_addr
);
230 write_frame
->fence_addr_lo
= lower_32_bits(fence_mc_addr
);
231 write_frame
->fence_value
= index
;
233 /* Update the write Pointer in DWORDs */
234 psp_write_ptr_reg
= (psp_write_ptr_reg
+ rb_frame_size_dw
) % ring_size_dw
;
235 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_67
, psp_write_ptr_reg
);
241 psp_v10_0_sram_map(struct amdgpu_device
*adev
,
242 unsigned int *sram_offset
, unsigned int *sram_addr_reg_offset
,
243 unsigned int *sram_data_reg_offset
,
244 enum AMDGPU_UCODE_ID ucode_id
)
249 /* TODO: needs to confirm */
251 case AMDGPU_UCODE_ID_SMC
:
253 *sram_addr_reg_offset
= 0;
254 *sram_data_reg_offset
= 0;
258 case AMDGPU_UCODE_ID_CP_CE
:
260 *sram_addr_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_CE_UCODE_ADDR
);
261 *sram_data_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_CE_UCODE_DATA
);
264 case AMDGPU_UCODE_ID_CP_PFP
:
266 *sram_addr_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_PFP_UCODE_ADDR
);
267 *sram_data_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_PFP_UCODE_DATA
);
270 case AMDGPU_UCODE_ID_CP_ME
:
272 *sram_addr_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_HYP_ME_UCODE_ADDR
);
273 *sram_data_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_HYP_ME_UCODE_DATA
);
276 case AMDGPU_UCODE_ID_CP_MEC1
:
277 *sram_offset
= 0x10000;
278 *sram_addr_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_MEC_ME1_UCODE_ADDR
);
279 *sram_data_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_MEC_ME1_UCODE_DATA
);
282 case AMDGPU_UCODE_ID_CP_MEC2
:
283 *sram_offset
= 0x10000;
284 *sram_addr_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_HYP_MEC2_UCODE_ADDR
);
285 *sram_data_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_HYP_MEC2_UCODE_DATA
);
288 case AMDGPU_UCODE_ID_RLC_G
:
289 *sram_offset
= 0x2000;
290 *sram_addr_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmRLC_GPM_UCODE_ADDR
);
291 *sram_data_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmRLC_GPM_UCODE_DATA
);
294 case AMDGPU_UCODE_ID_SDMA0
:
296 *sram_addr_reg_offset
= SOC15_REG_OFFSET(SDMA0
, 0, mmSDMA0_UCODE_ADDR
);
297 *sram_data_reg_offset
= SOC15_REG_OFFSET(SDMA0
, 0, mmSDMA0_UCODE_DATA
);
300 /* TODO: needs to confirm */
302 case AMDGPU_UCODE_ID_SDMA1
:
304 *sram_addr_reg_offset
= ;
307 case AMDGPU_UCODE_ID_UVD
:
309 *sram_addr_reg_offset
= ;
312 case AMDGPU_UCODE_ID_VCE
:
314 *sram_addr_reg_offset
= ;
318 case AMDGPU_UCODE_ID_MAXIMUM
:
327 static bool psp_v10_0_compare_sram_data(struct psp_context
*psp
,
328 struct amdgpu_firmware_info
*ucode
,
329 enum AMDGPU_UCODE_ID ucode_type
)
332 unsigned int fw_sram_reg_val
= 0;
333 unsigned int fw_sram_addr_reg_offset
= 0;
334 unsigned int fw_sram_data_reg_offset
= 0;
335 unsigned int ucode_size
;
336 uint32_t *ucode_mem
= NULL
;
337 struct amdgpu_device
*adev
= psp
->adev
;
339 err
= psp_v10_0_sram_map(adev
, &fw_sram_reg_val
, &fw_sram_addr_reg_offset
,
340 &fw_sram_data_reg_offset
, ucode_type
);
344 WREG32(fw_sram_addr_reg_offset
, fw_sram_reg_val
);
346 ucode_size
= ucode
->ucode_size
;
347 ucode_mem
= (uint32_t *)ucode
->kaddr
;
348 while (!ucode_size
) {
349 fw_sram_reg_val
= RREG32(fw_sram_data_reg_offset
);
351 if (*ucode_mem
!= fw_sram_reg_val
)
363 static int psp_v10_0_mode1_reset(struct psp_context
*psp
)
365 DRM_INFO("psp mode 1 reset not supported now! \n");
369 static const struct psp_funcs psp_v10_0_funcs
= {
370 .init_microcode
= psp_v10_0_init_microcode
,
371 .ring_init
= psp_v10_0_ring_init
,
372 .ring_create
= psp_v10_0_ring_create
,
373 .ring_stop
= psp_v10_0_ring_stop
,
374 .ring_destroy
= psp_v10_0_ring_destroy
,
375 .cmd_submit
= psp_v10_0_cmd_submit
,
376 .compare_sram_data
= psp_v10_0_compare_sram_data
,
377 .mode1_reset
= psp_v10_0_mode1_reset
,
380 void psp_v10_0_set_psp_funcs(struct psp_context
*psp
)
382 psp
->funcs
= &psp_v10_0_funcs
;