2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
25 #include "amdgpu_psp.h"
26 #include "amdgpu_ucode.h"
27 #include "soc15_common.h"
28 #include "psp_v11_0.h"
30 #include "mp/mp_11_0_offset.h"
31 #include "mp/mp_11_0_sh_mask.h"
32 #include "gc/gc_9_0_offset.h"
33 #include "sdma0/sdma0_4_0_offset.h"
34 #include "nbio/nbio_7_4_offset.h"
36 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
37 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
38 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
41 #define smnMP1_FIRMWARE_FLAGS 0x3010024
44 psp_v11_0_get_fw_type(struct amdgpu_firmware_info
*ucode
, enum psp_gfx_fw_type
*type
)
46 switch (ucode
->ucode_id
) {
47 case AMDGPU_UCODE_ID_SDMA0
:
48 *type
= GFX_FW_TYPE_SDMA0
;
50 case AMDGPU_UCODE_ID_SDMA1
:
51 *type
= GFX_FW_TYPE_SDMA1
;
53 case AMDGPU_UCODE_ID_CP_CE
:
54 *type
= GFX_FW_TYPE_CP_CE
;
56 case AMDGPU_UCODE_ID_CP_PFP
:
57 *type
= GFX_FW_TYPE_CP_PFP
;
59 case AMDGPU_UCODE_ID_CP_ME
:
60 *type
= GFX_FW_TYPE_CP_ME
;
62 case AMDGPU_UCODE_ID_CP_MEC1
:
63 *type
= GFX_FW_TYPE_CP_MEC
;
65 case AMDGPU_UCODE_ID_CP_MEC1_JT
:
66 *type
= GFX_FW_TYPE_CP_MEC_ME1
;
68 case AMDGPU_UCODE_ID_CP_MEC2
:
69 *type
= GFX_FW_TYPE_CP_MEC
;
71 case AMDGPU_UCODE_ID_CP_MEC2_JT
:
72 *type
= GFX_FW_TYPE_CP_MEC_ME2
;
74 case AMDGPU_UCODE_ID_RLC_G
:
75 *type
= GFX_FW_TYPE_RLC_G
;
77 case AMDGPU_UCODE_ID_SMC
:
78 *type
= GFX_FW_TYPE_SMU
;
80 case AMDGPU_UCODE_ID_UVD
:
81 *type
= GFX_FW_TYPE_UVD
;
83 case AMDGPU_UCODE_ID_VCE
:
84 *type
= GFX_FW_TYPE_VCE
;
86 case AMDGPU_UCODE_ID_UVD1
:
87 *type
= GFX_FW_TYPE_UVD1
;
89 case AMDGPU_UCODE_ID_MAXIMUM
:
97 static int psp_v11_0_init_microcode(struct psp_context
*psp
)
99 struct amdgpu_device
*adev
= psp
->adev
;
100 const char *chip_name
;
103 const struct psp_firmware_header_v1_0
*sos_hdr
;
104 const struct psp_firmware_header_v1_0
*asd_hdr
;
105 const struct ta_firmware_header_v1_0
*ta_hdr
;
109 switch (adev
->asic_type
) {
111 chip_name
= "vega20";
117 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_sos.bin", chip_name
);
118 err
= request_firmware(&adev
->psp
.sos_fw
, fw_name
, adev
->dev
);
122 err
= amdgpu_ucode_validate(adev
->psp
.sos_fw
);
126 sos_hdr
= (const struct psp_firmware_header_v1_0
*)adev
->psp
.sos_fw
->data
;
127 adev
->psp
.sos_fw_version
= le32_to_cpu(sos_hdr
->header
.ucode_version
);
128 adev
->psp
.sos_feature_version
= le32_to_cpu(sos_hdr
->ucode_feature_version
);
129 adev
->psp
.sos_bin_size
= le32_to_cpu(sos_hdr
->sos_size_bytes
);
130 adev
->psp
.sys_bin_size
= le32_to_cpu(sos_hdr
->header
.ucode_size_bytes
) -
131 le32_to_cpu(sos_hdr
->sos_size_bytes
);
132 adev
->psp
.sys_start_addr
= (uint8_t *)sos_hdr
+
133 le32_to_cpu(sos_hdr
->header
.ucode_array_offset_bytes
);
134 adev
->psp
.sos_start_addr
= (uint8_t *)adev
->psp
.sys_start_addr
+
135 le32_to_cpu(sos_hdr
->sos_offset_bytes
);
137 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_asd.bin", chip_name
);
138 err
= request_firmware(&adev
->psp
.asd_fw
, fw_name
, adev
->dev
);
142 err
= amdgpu_ucode_validate(adev
->psp
.asd_fw
);
146 asd_hdr
= (const struct psp_firmware_header_v1_0
*)adev
->psp
.asd_fw
->data
;
147 adev
->psp
.asd_fw_version
= le32_to_cpu(asd_hdr
->header
.ucode_version
);
148 adev
->psp
.asd_feature_version
= le32_to_cpu(asd_hdr
->ucode_feature_version
);
149 adev
->psp
.asd_ucode_size
= le32_to_cpu(asd_hdr
->header
.ucode_size_bytes
);
150 adev
->psp
.asd_start_addr
= (uint8_t *)asd_hdr
+
151 le32_to_cpu(asd_hdr
->header
.ucode_array_offset_bytes
);
153 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_ta.bin", chip_name
);
154 err
= request_firmware(&adev
->psp
.ta_fw
, fw_name
, adev
->dev
);
156 release_firmware(adev
->psp
.ta_fw
);
157 adev
->psp
.ta_fw
= NULL
;
159 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name
);
161 err
= amdgpu_ucode_validate(adev
->psp
.ta_fw
);
165 ta_hdr
= (const struct ta_firmware_header_v1_0
*)adev
->psp
.ta_fw
->data
;
166 adev
->psp
.ta_xgmi_ucode_version
= le32_to_cpu(ta_hdr
->ta_xgmi_ucode_version
);
167 adev
->psp
.ta_xgmi_ucode_size
= le32_to_cpu(ta_hdr
->ta_xgmi_size_bytes
);
168 adev
->psp
.ta_xgmi_start_addr
= (uint8_t *)ta_hdr
+
169 le32_to_cpu(ta_hdr
->header
.ucode_array_offset_bytes
);
175 release_firmware(adev
->psp
.ta_fw
);
176 adev
->psp
.ta_fw
= NULL
;
178 release_firmware(adev
->psp
.asd_fw
);
179 adev
->psp
.asd_fw
= NULL
;
182 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name
);
183 release_firmware(adev
->psp
.sos_fw
);
184 adev
->psp
.sos_fw
= NULL
;
189 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context
*psp
)
192 uint32_t psp_gfxdrv_command_reg
= 0;
193 struct amdgpu_device
*adev
= psp
->adev
;
196 /* Check sOS sign of life register to confirm sys driver and sOS
197 * are already been loaded.
199 sol_reg
= RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_81
);
201 psp
->sos_fw_version
= RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_58
);
202 printk("sos fw version = 0x%x.\n", psp
->sos_fw_version
);
206 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
207 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_35
),
208 0x80000000, 0x80000000, false);
212 memset(psp
->fw_pri_buf
, 0, PSP_1_MEG
);
214 /* Copy PSP System Driver binary to memory */
215 memcpy(psp
->fw_pri_buf
, psp
->sys_start_addr
, psp
->sys_bin_size
);
217 /* Provide the sys driver to bootloader */
218 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_36
,
219 (uint32_t)(psp
->fw_pri_mc_addr
>> 20));
220 psp_gfxdrv_command_reg
= 1 << 16;
221 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_35
,
222 psp_gfxdrv_command_reg
);
224 /* there might be handshake issue with hardware which needs delay */
227 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_35
),
228 0x80000000, 0x80000000, false);
233 static int psp_v11_0_bootloader_load_sos(struct psp_context
*psp
)
236 unsigned int psp_gfxdrv_command_reg
= 0;
237 struct amdgpu_device
*adev
= psp
->adev
;
240 /* Check sOS sign of life register to confirm sys driver and sOS
241 * are already been loaded.
243 sol_reg
= RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_81
);
247 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
248 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_35
),
249 0x80000000, 0x80000000, false);
253 memset(psp
->fw_pri_buf
, 0, PSP_1_MEG
);
255 /* Copy Secure OS binary to PSP memory */
256 memcpy(psp
->fw_pri_buf
, psp
->sos_start_addr
, psp
->sos_bin_size
);
258 /* Provide the PSP secure OS to bootloader */
259 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_36
,
260 (uint32_t)(psp
->fw_pri_mc_addr
>> 20));
261 psp_gfxdrv_command_reg
= 2 << 16;
262 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_35
,
263 psp_gfxdrv_command_reg
);
265 /* there might be handshake issue with hardware which needs delay */
267 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_81
),
268 RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_81
),
274 static int psp_v11_0_prep_cmd_buf(struct amdgpu_firmware_info
*ucode
,
275 struct psp_gfx_cmd_resp
*cmd
)
278 uint64_t fw_mem_mc_addr
= ucode
->mc_addr
;
280 memset(cmd
, 0, sizeof(struct psp_gfx_cmd_resp
));
282 cmd
->cmd_id
= GFX_CMD_ID_LOAD_IP_FW
;
283 cmd
->cmd
.cmd_load_ip_fw
.fw_phy_addr_lo
= lower_32_bits(fw_mem_mc_addr
);
284 cmd
->cmd
.cmd_load_ip_fw
.fw_phy_addr_hi
= upper_32_bits(fw_mem_mc_addr
);
285 cmd
->cmd
.cmd_load_ip_fw
.fw_size
= ucode
->ucode_size
;
287 ret
= psp_v11_0_get_fw_type(ucode
, &cmd
->cmd
.cmd_load_ip_fw
.fw_type
);
289 DRM_ERROR("Unknown firmware type\n");
294 static int psp_v11_0_ring_init(struct psp_context
*psp
,
295 enum psp_ring_type ring_type
)
298 struct psp_ring
*ring
;
299 struct amdgpu_device
*adev
= psp
->adev
;
301 ring
= &psp
->km_ring
;
303 ring
->ring_type
= ring_type
;
305 /* allocate 4k Page of Local Frame Buffer memory for ring */
306 ring
->ring_size
= 0x1000;
307 ret
= amdgpu_bo_create_kernel(adev
, ring
->ring_size
, PAGE_SIZE
,
308 AMDGPU_GEM_DOMAIN_VRAM
,
309 &adev
->firmware
.rbuf
,
310 &ring
->ring_mem_mc_addr
,
311 (void **)&ring
->ring_mem
);
320 static bool psp_v11_0_support_vmr_ring(struct psp_context
*psp
)
322 if (amdgpu_sriov_vf(psp
->adev
) && psp
->sos_fw_version
> 0x80045)
327 static int psp_v11_0_ring_create(struct psp_context
*psp
,
328 enum psp_ring_type ring_type
)
331 unsigned int psp_ring_reg
= 0;
332 struct psp_ring
*ring
= &psp
->km_ring
;
333 struct amdgpu_device
*adev
= psp
->adev
;
335 if (psp_v11_0_support_vmr_ring(psp
)) {
336 /* Write low address of the ring to C2PMSG_102 */
337 psp_ring_reg
= lower_32_bits(ring
->ring_mem_mc_addr
);
338 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_102
, psp_ring_reg
);
339 /* Write high address of the ring to C2PMSG_103 */
340 psp_ring_reg
= upper_32_bits(ring
->ring_mem_mc_addr
);
341 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_103
, psp_ring_reg
);
343 /* Write the ring initialization command to C2PMSG_101 */
344 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_101
,
345 GFX_CTRL_CMD_ID_INIT_GPCOM_RING
);
347 /* there might be handshake issue with hardware which needs delay */
350 /* Wait for response flag (bit 31) in C2PMSG_101 */
351 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_101
),
352 0x80000000, 0x8000FFFF, false);
355 /* Write low address of the ring to C2PMSG_69 */
356 psp_ring_reg
= lower_32_bits(ring
->ring_mem_mc_addr
);
357 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_69
, psp_ring_reg
);
358 /* Write high address of the ring to C2PMSG_70 */
359 psp_ring_reg
= upper_32_bits(ring
->ring_mem_mc_addr
);
360 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_70
, psp_ring_reg
);
361 /* Write size of ring to C2PMSG_71 */
362 psp_ring_reg
= ring
->ring_size
;
363 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_71
, psp_ring_reg
);
364 /* Write the ring initialization command to C2PMSG_64 */
365 psp_ring_reg
= ring_type
;
366 psp_ring_reg
= psp_ring_reg
<< 16;
367 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_64
, psp_ring_reg
);
369 /* there might be handshake issue with hardware which needs delay */
372 /* Wait for response flag (bit 31) in C2PMSG_64 */
373 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_64
),
374 0x80000000, 0x8000FFFF, false);
380 static int psp_v11_0_ring_stop(struct psp_context
*psp
,
381 enum psp_ring_type ring_type
)
384 struct amdgpu_device
*adev
= psp
->adev
;
386 /* Write the ring destroy command*/
387 if (psp_v11_0_support_vmr_ring(psp
))
388 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_101
,
389 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING
);
391 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_64
,
392 GFX_CTRL_CMD_ID_DESTROY_RINGS
);
394 /* there might be handshake issue with hardware which needs delay */
397 /* Wait for response flag (bit 31) */
398 if (psp_v11_0_support_vmr_ring(psp
))
399 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_101
),
400 0x80000000, 0x80000000, false);
402 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_64
),
403 0x80000000, 0x80000000, false);
408 static int psp_v11_0_ring_destroy(struct psp_context
*psp
,
409 enum psp_ring_type ring_type
)
412 struct psp_ring
*ring
= &psp
->km_ring
;
413 struct amdgpu_device
*adev
= psp
->adev
;
415 ret
= psp_v11_0_ring_stop(psp
, ring_type
);
417 DRM_ERROR("Fail to stop psp ring\n");
419 amdgpu_bo_free_kernel(&adev
->firmware
.rbuf
,
420 &ring
->ring_mem_mc_addr
,
421 (void **)&ring
->ring_mem
);
426 static int psp_v11_0_cmd_submit(struct psp_context
*psp
,
427 struct amdgpu_firmware_info
*ucode
,
428 uint64_t cmd_buf_mc_addr
, uint64_t fence_mc_addr
,
431 unsigned int psp_write_ptr_reg
= 0;
432 struct psp_gfx_rb_frame
*write_frame
= psp
->km_ring
.ring_mem
;
433 struct psp_ring
*ring
= &psp
->km_ring
;
434 struct psp_gfx_rb_frame
*ring_buffer_start
= ring
->ring_mem
;
435 struct psp_gfx_rb_frame
*ring_buffer_end
= ring_buffer_start
+
436 ring
->ring_size
/ sizeof(struct psp_gfx_rb_frame
) - 1;
437 struct amdgpu_device
*adev
= psp
->adev
;
438 uint32_t ring_size_dw
= ring
->ring_size
/ 4;
439 uint32_t rb_frame_size_dw
= sizeof(struct psp_gfx_rb_frame
) / 4;
441 /* KM (GPCOM) prepare write pointer */
442 if (psp_v11_0_support_vmr_ring(psp
))
443 psp_write_ptr_reg
= RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_102
);
445 psp_write_ptr_reg
= RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_67
);
447 /* Update KM RB frame pointer to new frame */
448 /* write_frame ptr increments by size of rb_frame in bytes */
449 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
450 if ((psp_write_ptr_reg
% ring_size_dw
) == 0)
451 write_frame
= ring_buffer_start
;
453 write_frame
= ring_buffer_start
+ (psp_write_ptr_reg
/ rb_frame_size_dw
);
454 /* Check invalid write_frame ptr address */
455 if ((write_frame
< ring_buffer_start
) || (ring_buffer_end
< write_frame
)) {
456 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
457 ring_buffer_start
, ring_buffer_end
, write_frame
);
458 DRM_ERROR("write_frame is pointing to address out of bounds\n");
462 /* Initialize KM RB frame */
463 memset(write_frame
, 0, sizeof(struct psp_gfx_rb_frame
));
465 /* Update KM RB frame */
466 write_frame
->cmd_buf_addr_hi
= upper_32_bits(cmd_buf_mc_addr
);
467 write_frame
->cmd_buf_addr_lo
= lower_32_bits(cmd_buf_mc_addr
);
468 write_frame
->fence_addr_hi
= upper_32_bits(fence_mc_addr
);
469 write_frame
->fence_addr_lo
= lower_32_bits(fence_mc_addr
);
470 write_frame
->fence_value
= index
;
472 /* Update the write Pointer in DWORDs */
473 psp_write_ptr_reg
= (psp_write_ptr_reg
+ rb_frame_size_dw
) % ring_size_dw
;
474 if (psp_v11_0_support_vmr_ring(psp
)) {
475 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_102
, psp_write_ptr_reg
);
476 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_101
, GFX_CTRL_CMD_ID_CONSUME_CMD
);
478 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_67
, psp_write_ptr_reg
);
484 psp_v11_0_sram_map(struct amdgpu_device
*adev
,
485 unsigned int *sram_offset
, unsigned int *sram_addr_reg_offset
,
486 unsigned int *sram_data_reg_offset
,
487 enum AMDGPU_UCODE_ID ucode_id
)
492 /* TODO: needs to confirm */
494 case AMDGPU_UCODE_ID_SMC
:
496 *sram_addr_reg_offset
= 0;
497 *sram_data_reg_offset
= 0;
501 case AMDGPU_UCODE_ID_CP_CE
:
503 *sram_addr_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_CE_UCODE_ADDR
);
504 *sram_data_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_CE_UCODE_DATA
);
507 case AMDGPU_UCODE_ID_CP_PFP
:
509 *sram_addr_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_PFP_UCODE_ADDR
);
510 *sram_data_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_PFP_UCODE_DATA
);
513 case AMDGPU_UCODE_ID_CP_ME
:
515 *sram_addr_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_HYP_ME_UCODE_ADDR
);
516 *sram_data_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_HYP_ME_UCODE_DATA
);
519 case AMDGPU_UCODE_ID_CP_MEC1
:
520 *sram_offset
= 0x10000;
521 *sram_addr_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_MEC_ME1_UCODE_ADDR
);
522 *sram_data_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_MEC_ME1_UCODE_DATA
);
525 case AMDGPU_UCODE_ID_CP_MEC2
:
526 *sram_offset
= 0x10000;
527 *sram_addr_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_HYP_MEC2_UCODE_ADDR
);
528 *sram_data_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_HYP_MEC2_UCODE_DATA
);
531 case AMDGPU_UCODE_ID_RLC_G
:
532 *sram_offset
= 0x2000;
533 *sram_addr_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmRLC_GPM_UCODE_ADDR
);
534 *sram_data_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmRLC_GPM_UCODE_DATA
);
537 case AMDGPU_UCODE_ID_SDMA0
:
539 *sram_addr_reg_offset
= SOC15_REG_OFFSET(SDMA0
, 0, mmSDMA0_UCODE_ADDR
);
540 *sram_data_reg_offset
= SOC15_REG_OFFSET(SDMA0
, 0, mmSDMA0_UCODE_DATA
);
543 /* TODO: needs to confirm */
545 case AMDGPU_UCODE_ID_SDMA1
:
547 *sram_addr_reg_offset
= ;
550 case AMDGPU_UCODE_ID_UVD
:
552 *sram_addr_reg_offset
= ;
555 case AMDGPU_UCODE_ID_VCE
:
557 *sram_addr_reg_offset
= ;
561 case AMDGPU_UCODE_ID_MAXIMUM
:
570 static bool psp_v11_0_compare_sram_data(struct psp_context
*psp
,
571 struct amdgpu_firmware_info
*ucode
,
572 enum AMDGPU_UCODE_ID ucode_type
)
575 unsigned int fw_sram_reg_val
= 0;
576 unsigned int fw_sram_addr_reg_offset
= 0;
577 unsigned int fw_sram_data_reg_offset
= 0;
578 unsigned int ucode_size
;
579 uint32_t *ucode_mem
= NULL
;
580 struct amdgpu_device
*adev
= psp
->adev
;
582 err
= psp_v11_0_sram_map(adev
, &fw_sram_reg_val
, &fw_sram_addr_reg_offset
,
583 &fw_sram_data_reg_offset
, ucode_type
);
587 WREG32(fw_sram_addr_reg_offset
, fw_sram_reg_val
);
589 ucode_size
= ucode
->ucode_size
;
590 ucode_mem
= (uint32_t *)ucode
->kaddr
;
592 fw_sram_reg_val
= RREG32(fw_sram_data_reg_offset
);
594 if (*ucode_mem
!= fw_sram_reg_val
)
605 static int psp_v11_0_mode1_reset(struct psp_context
*psp
)
609 struct amdgpu_device
*adev
= psp
->adev
;
611 offset
= SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_64
);
613 ret
= psp_wait_for(psp
, offset
, 0x80000000, 0x8000FFFF, false);
616 DRM_INFO("psp is not working correctly before mode1 reset!\n");
620 /*send the mode 1 reset command*/
621 WREG32(offset
, GFX_CTRL_CMD_ID_MODE1_RST
);
625 offset
= SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_33
);
627 ret
= psp_wait_for(psp
, offset
, 0x80000000, 0x80000000, false);
630 DRM_INFO("psp mode 1 reset failed!\n");
634 DRM_INFO("psp mode1 reset succeed \n");
639 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready.
640 * For now, return success and hack the hive_id so high level code can
643 static int psp_v11_0_xgmi_get_topology_info(struct psp_context
*psp
,
644 int number_devices
, struct psp_xgmi_topology_info
*topology
)
646 struct ta_xgmi_shared_memory
*xgmi_cmd
;
647 struct ta_xgmi_cmd_get_topology_info_input
*topology_info_input
;
648 struct ta_xgmi_cmd_get_topology_info_output
*topology_info_output
;
652 if (!topology
|| topology
->num_nodes
> TA_XGMI__MAX_CONNECTED_NODES
)
655 xgmi_cmd
= (struct ta_xgmi_shared_memory
*)psp
->xgmi_context
.xgmi_shared_buf
;
656 memset(xgmi_cmd
, 0, sizeof(struct ta_xgmi_shared_memory
));
658 /* Fill in the shared memory with topology information as input */
659 topology_info_input
= &xgmi_cmd
->xgmi_in_message
.get_topology_info
;
660 xgmi_cmd
->cmd_id
= TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO
;
661 topology_info_input
->num_nodes
= number_devices
;
663 for (i
= 0; i
< topology_info_input
->num_nodes
; i
++) {
664 topology_info_input
->nodes
[i
].node_id
= topology
->nodes
[i
].node_id
;
665 topology_info_input
->nodes
[i
].num_hops
= topology
->nodes
[i
].num_hops
;
666 topology_info_input
->nodes
[i
].is_sharing_enabled
= topology
->nodes
[i
].is_sharing_enabled
;
667 topology_info_input
->nodes
[i
].sdma_engine
= topology
->nodes
[i
].sdma_engine
;
670 /* Invoke xgmi ta to get the topology information */
671 ret
= psp_xgmi_invoke(psp
, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO
);
675 /* Read the output topology information from the shared memory */
676 topology_info_output
= &xgmi_cmd
->xgmi_out_message
.get_topology_info
;
677 topology
->num_nodes
= xgmi_cmd
->xgmi_out_message
.get_topology_info
.num_nodes
;
678 for (i
= 0; i
< topology
->num_nodes
; i
++) {
679 topology
->nodes
[i
].node_id
= topology_info_output
->nodes
[i
].node_id
;
680 topology
->nodes
[i
].num_hops
= topology_info_output
->nodes
[i
].num_hops
;
681 topology
->nodes
[i
].is_sharing_enabled
= topology_info_output
->nodes
[i
].is_sharing_enabled
;
682 topology
->nodes
[i
].sdma_engine
= topology_info_output
->nodes
[i
].sdma_engine
;
688 static int psp_v11_0_xgmi_set_topology_info(struct psp_context
*psp
,
689 int number_devices
, struct psp_xgmi_topology_info
*topology
)
691 struct ta_xgmi_shared_memory
*xgmi_cmd
;
692 struct ta_xgmi_cmd_get_topology_info_input
*topology_info_input
;
695 if (!topology
|| topology
->num_nodes
> TA_XGMI__MAX_CONNECTED_NODES
)
698 xgmi_cmd
= (struct ta_xgmi_shared_memory
*)psp
->xgmi_context
.xgmi_shared_buf
;
699 memset(xgmi_cmd
, 0, sizeof(struct ta_xgmi_shared_memory
));
701 topology_info_input
= &xgmi_cmd
->xgmi_in_message
.get_topology_info
;
702 xgmi_cmd
->cmd_id
= TA_COMMAND_XGMI__SET_TOPOLOGY_INFO
;
703 topology_info_input
->num_nodes
= number_devices
;
705 for (i
= 0; i
< topology_info_input
->num_nodes
; i
++) {
706 topology_info_input
->nodes
[i
].node_id
= topology
->nodes
[i
].node_id
;
707 topology_info_input
->nodes
[i
].num_hops
= topology
->nodes
[i
].num_hops
;
708 topology_info_input
->nodes
[i
].is_sharing_enabled
= topology
->nodes
[i
].is_sharing_enabled
;
709 topology_info_input
->nodes
[i
].sdma_engine
= topology
->nodes
[i
].sdma_engine
;
712 /* Invoke xgmi ta to set topology information */
713 return psp_xgmi_invoke(psp
, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO
);
716 static int psp_v11_0_xgmi_get_hive_id(struct psp_context
*psp
, uint64_t *hive_id
)
718 struct ta_xgmi_shared_memory
*xgmi_cmd
;
721 xgmi_cmd
= (struct ta_xgmi_shared_memory
*)psp
->xgmi_context
.xgmi_shared_buf
;
722 memset(xgmi_cmd
, 0, sizeof(struct ta_xgmi_shared_memory
));
724 xgmi_cmd
->cmd_id
= TA_COMMAND_XGMI__GET_HIVE_ID
;
726 /* Invoke xgmi ta to get hive id */
727 ret
= psp_xgmi_invoke(psp
, xgmi_cmd
->cmd_id
);
731 *hive_id
= xgmi_cmd
->xgmi_out_message
.get_hive_id
.hive_id
;
736 static int psp_v11_0_xgmi_get_node_id(struct psp_context
*psp
, uint64_t *node_id
)
738 struct ta_xgmi_shared_memory
*xgmi_cmd
;
741 xgmi_cmd
= (struct ta_xgmi_shared_memory
*)psp
->xgmi_context
.xgmi_shared_buf
;
742 memset(xgmi_cmd
, 0, sizeof(struct ta_xgmi_shared_memory
));
744 xgmi_cmd
->cmd_id
= TA_COMMAND_XGMI__GET_NODE_ID
;
746 /* Invoke xgmi ta to get the node id */
747 ret
= psp_xgmi_invoke(psp
, xgmi_cmd
->cmd_id
);
751 *node_id
= xgmi_cmd
->xgmi_out_message
.get_node_id
.node_id
;
756 static const struct psp_funcs psp_v11_0_funcs
= {
757 .init_microcode
= psp_v11_0_init_microcode
,
758 .bootloader_load_sysdrv
= psp_v11_0_bootloader_load_sysdrv
,
759 .bootloader_load_sos
= psp_v11_0_bootloader_load_sos
,
760 .prep_cmd_buf
= psp_v11_0_prep_cmd_buf
,
761 .ring_init
= psp_v11_0_ring_init
,
762 .ring_create
= psp_v11_0_ring_create
,
763 .ring_stop
= psp_v11_0_ring_stop
,
764 .ring_destroy
= psp_v11_0_ring_destroy
,
765 .cmd_submit
= psp_v11_0_cmd_submit
,
766 .compare_sram_data
= psp_v11_0_compare_sram_data
,
767 .mode1_reset
= psp_v11_0_mode1_reset
,
768 .xgmi_get_topology_info
= psp_v11_0_xgmi_get_topology_info
,
769 .xgmi_set_topology_info
= psp_v11_0_xgmi_set_topology_info
,
770 .xgmi_get_hive_id
= psp_v11_0_xgmi_get_hive_id
,
771 .xgmi_get_node_id
= psp_v11_0_xgmi_get_node_id
,
772 .support_vmr_ring
= psp_v11_0_support_vmr_ring
,
775 void psp_v11_0_set_psp_funcs(struct psp_context
*psp
)
777 psp
->funcs
= &psp_v11_0_funcs
;