2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
25 #include "amdgpu_psp.h"
26 #include "amdgpu_ucode.h"
27 #include "soc15_common.h"
28 #include "psp_v11_0.h"
30 #include "mp/mp_11_0_offset.h"
31 #include "mp/mp_11_0_sh_mask.h"
32 #include "gc/gc_9_0_offset.h"
33 #include "sdma0/sdma0_4_0_offset.h"
34 #include "nbio/nbio_7_4_offset.h"
36 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
37 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
38 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
41 #define smnMP1_FIRMWARE_FLAGS 0x3010024
44 psp_v11_0_get_fw_type(struct amdgpu_firmware_info
*ucode
, enum psp_gfx_fw_type
*type
)
46 switch (ucode
->ucode_id
) {
47 case AMDGPU_UCODE_ID_SDMA0
:
48 *type
= GFX_FW_TYPE_SDMA0
;
50 case AMDGPU_UCODE_ID_SDMA1
:
51 *type
= GFX_FW_TYPE_SDMA1
;
53 case AMDGPU_UCODE_ID_CP_CE
:
54 *type
= GFX_FW_TYPE_CP_CE
;
56 case AMDGPU_UCODE_ID_CP_PFP
:
57 *type
= GFX_FW_TYPE_CP_PFP
;
59 case AMDGPU_UCODE_ID_CP_ME
:
60 *type
= GFX_FW_TYPE_CP_ME
;
62 case AMDGPU_UCODE_ID_CP_MEC1
:
63 *type
= GFX_FW_TYPE_CP_MEC
;
65 case AMDGPU_UCODE_ID_CP_MEC1_JT
:
66 *type
= GFX_FW_TYPE_CP_MEC_ME1
;
68 case AMDGPU_UCODE_ID_CP_MEC2
:
69 *type
= GFX_FW_TYPE_CP_MEC
;
71 case AMDGPU_UCODE_ID_CP_MEC2_JT
:
72 *type
= GFX_FW_TYPE_CP_MEC_ME2
;
74 case AMDGPU_UCODE_ID_RLC_G
:
75 *type
= GFX_FW_TYPE_RLC_G
;
77 case AMDGPU_UCODE_ID_SMC
:
78 *type
= GFX_FW_TYPE_SMU
;
80 case AMDGPU_UCODE_ID_UVD
:
81 *type
= GFX_FW_TYPE_UVD
;
83 case AMDGPU_UCODE_ID_VCE
:
84 *type
= GFX_FW_TYPE_VCE
;
86 case AMDGPU_UCODE_ID_UVD1
:
87 *type
= GFX_FW_TYPE_UVD1
;
89 case AMDGPU_UCODE_ID_MAXIMUM
:
97 static int psp_v11_0_init_microcode(struct psp_context
*psp
)
99 struct amdgpu_device
*adev
= psp
->adev
;
100 const char *chip_name
;
103 const struct psp_firmware_header_v1_0
*sos_hdr
;
104 const struct psp_firmware_header_v1_0
*asd_hdr
;
105 const struct ta_firmware_header_v1_0
*ta_hdr
;
109 switch (adev
->asic_type
) {
111 chip_name
= "vega20";
117 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_sos.bin", chip_name
);
118 err
= request_firmware(&adev
->psp
.sos_fw
, fw_name
, adev
->dev
);
122 err
= amdgpu_ucode_validate(adev
->psp
.sos_fw
);
126 sos_hdr
= (const struct psp_firmware_header_v1_0
*)adev
->psp
.sos_fw
->data
;
127 adev
->psp
.sos_fw_version
= le32_to_cpu(sos_hdr
->header
.ucode_version
);
128 adev
->psp
.sos_feature_version
= le32_to_cpu(sos_hdr
->ucode_feature_version
);
129 adev
->psp
.sos_bin_size
= le32_to_cpu(sos_hdr
->sos_size_bytes
);
130 adev
->psp
.sys_bin_size
= le32_to_cpu(sos_hdr
->header
.ucode_size_bytes
) -
131 le32_to_cpu(sos_hdr
->sos_size_bytes
);
132 adev
->psp
.sys_start_addr
= (uint8_t *)sos_hdr
+
133 le32_to_cpu(sos_hdr
->header
.ucode_array_offset_bytes
);
134 adev
->psp
.sos_start_addr
= (uint8_t *)adev
->psp
.sys_start_addr
+
135 le32_to_cpu(sos_hdr
->sos_offset_bytes
);
137 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_asd.bin", chip_name
);
138 err
= request_firmware(&adev
->psp
.asd_fw
, fw_name
, adev
->dev
);
142 err
= amdgpu_ucode_validate(adev
->psp
.asd_fw
);
146 asd_hdr
= (const struct psp_firmware_header_v1_0
*)adev
->psp
.asd_fw
->data
;
147 adev
->psp
.asd_fw_version
= le32_to_cpu(asd_hdr
->header
.ucode_version
);
148 adev
->psp
.asd_feature_version
= le32_to_cpu(asd_hdr
->ucode_feature_version
);
149 adev
->psp
.asd_ucode_size
= le32_to_cpu(asd_hdr
->header
.ucode_size_bytes
);
150 adev
->psp
.asd_start_addr
= (uint8_t *)asd_hdr
+
151 le32_to_cpu(asd_hdr
->header
.ucode_array_offset_bytes
);
153 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_ta.bin", chip_name
);
154 err
= request_firmware(&adev
->psp
.ta_fw
, fw_name
, adev
->dev
);
158 err
= amdgpu_ucode_validate(adev
->psp
.ta_fw
);
162 ta_hdr
= (const struct ta_firmware_header_v1_0
*)adev
->psp
.ta_fw
->data
;
163 adev
->psp
.ta_xgmi_ucode_version
= le32_to_cpu(ta_hdr
->ta_xgmi_ucode_version
);
164 adev
->psp
.ta_xgmi_ucode_size
= le32_to_cpu(ta_hdr
->ta_xgmi_size_bytes
);
165 adev
->psp
.ta_xgmi_start_addr
= (uint8_t *)ta_hdr
+
166 le32_to_cpu(ta_hdr
->header
.ucode_array_offset_bytes
);
171 release_firmware(adev
->psp
.ta_fw
);
172 adev
->psp
.ta_fw
= NULL
;
174 release_firmware(adev
->psp
.asd_fw
);
175 adev
->psp
.asd_fw
= NULL
;
178 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name
);
179 release_firmware(adev
->psp
.sos_fw
);
180 adev
->psp
.sos_fw
= NULL
;
185 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context
*psp
)
188 uint32_t psp_gfxdrv_command_reg
= 0;
189 struct amdgpu_device
*adev
= psp
->adev
;
192 /* Check sOS sign of life register to confirm sys driver and sOS
193 * are already been loaded.
195 sol_reg
= RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_81
);
197 psp
->sos_fw_version
= RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_58
);
198 printk("sos fw version = 0x%x.\n", psp
->sos_fw_version
);
202 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
203 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_35
),
204 0x80000000, 0x80000000, false);
208 memset(psp
->fw_pri_buf
, 0, PSP_1_MEG
);
210 /* Copy PSP System Driver binary to memory */
211 memcpy(psp
->fw_pri_buf
, psp
->sys_start_addr
, psp
->sys_bin_size
);
213 /* Provide the sys driver to bootloader */
214 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_36
,
215 (uint32_t)(psp
->fw_pri_mc_addr
>> 20));
216 psp_gfxdrv_command_reg
= 1 << 16;
217 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_35
,
218 psp_gfxdrv_command_reg
);
220 /* there might be handshake issue with hardware which needs delay */
223 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_35
),
224 0x80000000, 0x80000000, false);
229 static int psp_v11_0_bootloader_load_sos(struct psp_context
*psp
)
232 unsigned int psp_gfxdrv_command_reg
= 0;
233 struct amdgpu_device
*adev
= psp
->adev
;
236 /* Check sOS sign of life register to confirm sys driver and sOS
237 * are already been loaded.
239 sol_reg
= RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_81
);
243 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
244 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_35
),
245 0x80000000, 0x80000000, false);
249 memset(psp
->fw_pri_buf
, 0, PSP_1_MEG
);
251 /* Copy Secure OS binary to PSP memory */
252 memcpy(psp
->fw_pri_buf
, psp
->sos_start_addr
, psp
->sos_bin_size
);
254 /* Provide the PSP secure OS to bootloader */
255 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_36
,
256 (uint32_t)(psp
->fw_pri_mc_addr
>> 20));
257 psp_gfxdrv_command_reg
= 2 << 16;
258 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_35
,
259 psp_gfxdrv_command_reg
);
261 /* there might be handshake issue with hardware which needs delay */
263 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_81
),
264 RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_81
),
270 static int psp_v11_0_prep_cmd_buf(struct amdgpu_firmware_info
*ucode
,
271 struct psp_gfx_cmd_resp
*cmd
)
274 uint64_t fw_mem_mc_addr
= ucode
->mc_addr
;
276 memset(cmd
, 0, sizeof(struct psp_gfx_cmd_resp
));
278 cmd
->cmd_id
= GFX_CMD_ID_LOAD_IP_FW
;
279 cmd
->cmd
.cmd_load_ip_fw
.fw_phy_addr_lo
= lower_32_bits(fw_mem_mc_addr
);
280 cmd
->cmd
.cmd_load_ip_fw
.fw_phy_addr_hi
= upper_32_bits(fw_mem_mc_addr
);
281 cmd
->cmd
.cmd_load_ip_fw
.fw_size
= ucode
->ucode_size
;
283 ret
= psp_v11_0_get_fw_type(ucode
, &cmd
->cmd
.cmd_load_ip_fw
.fw_type
);
285 DRM_ERROR("Unknown firmware type\n");
290 static int psp_v11_0_ring_init(struct psp_context
*psp
,
291 enum psp_ring_type ring_type
)
294 struct psp_ring
*ring
;
295 struct amdgpu_device
*adev
= psp
->adev
;
297 ring
= &psp
->km_ring
;
299 ring
->ring_type
= ring_type
;
301 /* allocate 4k Page of Local Frame Buffer memory for ring */
302 ring
->ring_size
= 0x1000;
303 ret
= amdgpu_bo_create_kernel(adev
, ring
->ring_size
, PAGE_SIZE
,
304 AMDGPU_GEM_DOMAIN_VRAM
,
305 &adev
->firmware
.rbuf
,
306 &ring
->ring_mem_mc_addr
,
307 (void **)&ring
->ring_mem
);
316 static bool psp_v11_0_support_vmr_ring(struct psp_context
*psp
)
318 if (amdgpu_sriov_vf(psp
->adev
) && psp
->sos_fw_version
> 0x80045)
323 static int psp_v11_0_ring_create(struct psp_context
*psp
,
324 enum psp_ring_type ring_type
)
327 unsigned int psp_ring_reg
= 0;
328 struct psp_ring
*ring
= &psp
->km_ring
;
329 struct amdgpu_device
*adev
= psp
->adev
;
331 if (psp_v11_0_support_vmr_ring(psp
)) {
332 /* Write low address of the ring to C2PMSG_102 */
333 psp_ring_reg
= lower_32_bits(ring
->ring_mem_mc_addr
);
334 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_102
, psp_ring_reg
);
335 /* Write high address of the ring to C2PMSG_103 */
336 psp_ring_reg
= upper_32_bits(ring
->ring_mem_mc_addr
);
337 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_103
, psp_ring_reg
);
339 /* Write the ring initialization command to C2PMSG_101 */
340 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_101
,
341 GFX_CTRL_CMD_ID_INIT_GPCOM_RING
);
343 /* there might be handshake issue with hardware which needs delay */
346 /* Wait for response flag (bit 31) in C2PMSG_101 */
347 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_101
),
348 0x80000000, 0x8000FFFF, false);
351 /* Write low address of the ring to C2PMSG_69 */
352 psp_ring_reg
= lower_32_bits(ring
->ring_mem_mc_addr
);
353 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_69
, psp_ring_reg
);
354 /* Write high address of the ring to C2PMSG_70 */
355 psp_ring_reg
= upper_32_bits(ring
->ring_mem_mc_addr
);
356 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_70
, psp_ring_reg
);
357 /* Write size of ring to C2PMSG_71 */
358 psp_ring_reg
= ring
->ring_size
;
359 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_71
, psp_ring_reg
);
360 /* Write the ring initialization command to C2PMSG_64 */
361 psp_ring_reg
= ring_type
;
362 psp_ring_reg
= psp_ring_reg
<< 16;
363 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_64
, psp_ring_reg
);
365 /* there might be handshake issue with hardware which needs delay */
368 /* Wait for response flag (bit 31) in C2PMSG_64 */
369 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_64
),
370 0x80000000, 0x8000FFFF, false);
376 static int psp_v11_0_ring_stop(struct psp_context
*psp
,
377 enum psp_ring_type ring_type
)
380 struct amdgpu_device
*adev
= psp
->adev
;
382 /* Write the ring destroy command*/
383 if (psp_v11_0_support_vmr_ring(psp
))
384 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_101
,
385 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING
);
387 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_64
,
388 GFX_CTRL_CMD_ID_DESTROY_RINGS
);
390 /* there might be handshake issue with hardware which needs delay */
393 /* Wait for response flag (bit 31) */
394 if (psp_v11_0_support_vmr_ring(psp
))
395 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_101
),
396 0x80000000, 0x80000000, false);
398 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_64
),
399 0x80000000, 0x80000000, false);
404 static int psp_v11_0_ring_destroy(struct psp_context
*psp
,
405 enum psp_ring_type ring_type
)
408 struct psp_ring
*ring
= &psp
->km_ring
;
409 struct amdgpu_device
*adev
= psp
->adev
;
411 ret
= psp_v11_0_ring_stop(psp
, ring_type
);
413 DRM_ERROR("Fail to stop psp ring\n");
415 amdgpu_bo_free_kernel(&adev
->firmware
.rbuf
,
416 &ring
->ring_mem_mc_addr
,
417 (void **)&ring
->ring_mem
);
422 static int psp_v11_0_cmd_submit(struct psp_context
*psp
,
423 struct amdgpu_firmware_info
*ucode
,
424 uint64_t cmd_buf_mc_addr
, uint64_t fence_mc_addr
,
427 unsigned int psp_write_ptr_reg
= 0;
428 struct psp_gfx_rb_frame
*write_frame
= psp
->km_ring
.ring_mem
;
429 struct psp_ring
*ring
= &psp
->km_ring
;
430 struct psp_gfx_rb_frame
*ring_buffer_start
= ring
->ring_mem
;
431 struct psp_gfx_rb_frame
*ring_buffer_end
= ring_buffer_start
+
432 ring
->ring_size
/ sizeof(struct psp_gfx_rb_frame
) - 1;
433 struct amdgpu_device
*adev
= psp
->adev
;
434 uint32_t ring_size_dw
= ring
->ring_size
/ 4;
435 uint32_t rb_frame_size_dw
= sizeof(struct psp_gfx_rb_frame
) / 4;
437 /* KM (GPCOM) prepare write pointer */
438 if (psp_v11_0_support_vmr_ring(psp
))
439 psp_write_ptr_reg
= RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_102
);
441 psp_write_ptr_reg
= RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_67
);
443 /* Update KM RB frame pointer to new frame */
444 /* write_frame ptr increments by size of rb_frame in bytes */
445 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
446 if ((psp_write_ptr_reg
% ring_size_dw
) == 0)
447 write_frame
= ring_buffer_start
;
449 write_frame
= ring_buffer_start
+ (psp_write_ptr_reg
/ rb_frame_size_dw
);
450 /* Check invalid write_frame ptr address */
451 if ((write_frame
< ring_buffer_start
) || (ring_buffer_end
< write_frame
)) {
452 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
453 ring_buffer_start
, ring_buffer_end
, write_frame
);
454 DRM_ERROR("write_frame is pointing to address out of bounds\n");
458 /* Initialize KM RB frame */
459 memset(write_frame
, 0, sizeof(struct psp_gfx_rb_frame
));
461 /* Update KM RB frame */
462 write_frame
->cmd_buf_addr_hi
= upper_32_bits(cmd_buf_mc_addr
);
463 write_frame
->cmd_buf_addr_lo
= lower_32_bits(cmd_buf_mc_addr
);
464 write_frame
->fence_addr_hi
= upper_32_bits(fence_mc_addr
);
465 write_frame
->fence_addr_lo
= lower_32_bits(fence_mc_addr
);
466 write_frame
->fence_value
= index
;
468 /* Update the write Pointer in DWORDs */
469 psp_write_ptr_reg
= (psp_write_ptr_reg
+ rb_frame_size_dw
) % ring_size_dw
;
470 if (psp_v11_0_support_vmr_ring(psp
)) {
471 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_102
, psp_write_ptr_reg
);
472 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_101
, GFX_CTRL_CMD_ID_CONSUME_CMD
);
474 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_67
, psp_write_ptr_reg
);
480 psp_v11_0_sram_map(struct amdgpu_device
*adev
,
481 unsigned int *sram_offset
, unsigned int *sram_addr_reg_offset
,
482 unsigned int *sram_data_reg_offset
,
483 enum AMDGPU_UCODE_ID ucode_id
)
488 /* TODO: needs to confirm */
490 case AMDGPU_UCODE_ID_SMC
:
492 *sram_addr_reg_offset
= 0;
493 *sram_data_reg_offset
= 0;
497 case AMDGPU_UCODE_ID_CP_CE
:
499 *sram_addr_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_CE_UCODE_ADDR
);
500 *sram_data_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_CE_UCODE_DATA
);
503 case AMDGPU_UCODE_ID_CP_PFP
:
505 *sram_addr_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_PFP_UCODE_ADDR
);
506 *sram_data_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_PFP_UCODE_DATA
);
509 case AMDGPU_UCODE_ID_CP_ME
:
511 *sram_addr_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_HYP_ME_UCODE_ADDR
);
512 *sram_data_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_HYP_ME_UCODE_DATA
);
515 case AMDGPU_UCODE_ID_CP_MEC1
:
516 *sram_offset
= 0x10000;
517 *sram_addr_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_MEC_ME1_UCODE_ADDR
);
518 *sram_data_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_MEC_ME1_UCODE_DATA
);
521 case AMDGPU_UCODE_ID_CP_MEC2
:
522 *sram_offset
= 0x10000;
523 *sram_addr_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_HYP_MEC2_UCODE_ADDR
);
524 *sram_data_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmCP_HYP_MEC2_UCODE_DATA
);
527 case AMDGPU_UCODE_ID_RLC_G
:
528 *sram_offset
= 0x2000;
529 *sram_addr_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmRLC_GPM_UCODE_ADDR
);
530 *sram_data_reg_offset
= SOC15_REG_OFFSET(GC
, 0, mmRLC_GPM_UCODE_DATA
);
533 case AMDGPU_UCODE_ID_SDMA0
:
535 *sram_addr_reg_offset
= SOC15_REG_OFFSET(SDMA0
, 0, mmSDMA0_UCODE_ADDR
);
536 *sram_data_reg_offset
= SOC15_REG_OFFSET(SDMA0
, 0, mmSDMA0_UCODE_DATA
);
539 /* TODO: needs to confirm */
541 case AMDGPU_UCODE_ID_SDMA1
:
543 *sram_addr_reg_offset
= ;
546 case AMDGPU_UCODE_ID_UVD
:
548 *sram_addr_reg_offset
= ;
551 case AMDGPU_UCODE_ID_VCE
:
553 *sram_addr_reg_offset
= ;
557 case AMDGPU_UCODE_ID_MAXIMUM
:
566 static bool psp_v11_0_compare_sram_data(struct psp_context
*psp
,
567 struct amdgpu_firmware_info
*ucode
,
568 enum AMDGPU_UCODE_ID ucode_type
)
571 unsigned int fw_sram_reg_val
= 0;
572 unsigned int fw_sram_addr_reg_offset
= 0;
573 unsigned int fw_sram_data_reg_offset
= 0;
574 unsigned int ucode_size
;
575 uint32_t *ucode_mem
= NULL
;
576 struct amdgpu_device
*adev
= psp
->adev
;
578 err
= psp_v11_0_sram_map(adev
, &fw_sram_reg_val
, &fw_sram_addr_reg_offset
,
579 &fw_sram_data_reg_offset
, ucode_type
);
583 WREG32(fw_sram_addr_reg_offset
, fw_sram_reg_val
);
585 ucode_size
= ucode
->ucode_size
;
586 ucode_mem
= (uint32_t *)ucode
->kaddr
;
588 fw_sram_reg_val
= RREG32(fw_sram_data_reg_offset
);
590 if (*ucode_mem
!= fw_sram_reg_val
)
601 static int psp_v11_0_mode1_reset(struct psp_context
*psp
)
605 struct amdgpu_device
*adev
= psp
->adev
;
607 offset
= SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_64
);
609 ret
= psp_wait_for(psp
, offset
, 0x80000000, 0x8000FFFF, false);
612 DRM_INFO("psp is not working correctly before mode1 reset!\n");
616 /*send the mode 1 reset command*/
617 WREG32(offset
, GFX_CTRL_CMD_ID_MODE1_RST
);
621 offset
= SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_33
);
623 ret
= psp_wait_for(psp
, offset
, 0x80000000, 0x80000000, false);
626 DRM_INFO("psp mode 1 reset failed!\n");
630 DRM_INFO("psp mode1 reset succeed \n");
635 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready.
636 * For now, return success and hack the hive_id so high level code can
639 static int psp_v11_0_xgmi_get_topology_info(struct psp_context
*psp
,
640 int number_devices
, struct psp_xgmi_topology_info
*topology
)
642 struct ta_xgmi_shared_memory
*xgmi_cmd
;
643 struct ta_xgmi_cmd_get_topology_info_input
*topology_info_input
;
644 struct ta_xgmi_cmd_get_topology_info_output
*topology_info_output
;
648 if (!topology
|| topology
->num_nodes
> TA_XGMI__MAX_CONNECTED_NODES
)
651 xgmi_cmd
= (struct ta_xgmi_shared_memory
*)psp
->xgmi_context
.xgmi_shared_buf
;
652 memset(xgmi_cmd
, 0, sizeof(struct ta_xgmi_shared_memory
));
654 /* Fill in the shared memory with topology information as input */
655 topology_info_input
= &xgmi_cmd
->xgmi_in_message
.get_topology_info
;
656 xgmi_cmd
->cmd_id
= TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO
;
657 topology_info_input
->num_nodes
= number_devices
;
659 for (i
= 0; i
< topology_info_input
->num_nodes
; i
++) {
660 topology_info_input
->nodes
[i
].node_id
= topology
->nodes
[i
].node_id
;
661 topology_info_input
->nodes
[i
].num_hops
= topology
->nodes
[i
].num_hops
;
662 topology_info_input
->nodes
[i
].is_sharing_enabled
= topology
->nodes
[i
].is_sharing_enabled
;
663 topology_info_input
->nodes
[i
].sdma_engine
= topology
->nodes
[i
].sdma_engine
;
666 /* Invoke xgmi ta to get the topology information */
667 ret
= psp_xgmi_invoke(psp
, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO
);
671 /* Read the output topology information from the shared memory */
672 topology_info_output
= &xgmi_cmd
->xgmi_out_message
.get_topology_info
;
673 topology
->num_nodes
= xgmi_cmd
->xgmi_out_message
.get_topology_info
.num_nodes
;
674 for (i
= 0; i
< topology
->num_nodes
; i
++) {
675 topology
->nodes
[i
].node_id
= topology_info_output
->nodes
[i
].node_id
;
676 topology
->nodes
[i
].num_hops
= topology_info_output
->nodes
[i
].num_hops
;
677 topology
->nodes
[i
].is_sharing_enabled
= topology_info_output
->nodes
[i
].is_sharing_enabled
;
678 topology
->nodes
[i
].sdma_engine
= topology_info_output
->nodes
[i
].sdma_engine
;
684 static int psp_v11_0_xgmi_set_topology_info(struct psp_context
*psp
,
685 int number_devices
, struct psp_xgmi_topology_info
*topology
)
687 struct ta_xgmi_shared_memory
*xgmi_cmd
;
688 struct ta_xgmi_cmd_get_topology_info_input
*topology_info_input
;
691 if (!topology
|| topology
->num_nodes
> TA_XGMI__MAX_CONNECTED_NODES
)
694 xgmi_cmd
= (struct ta_xgmi_shared_memory
*)psp
->xgmi_context
.xgmi_shared_buf
;
695 memset(xgmi_cmd
, 0, sizeof(struct ta_xgmi_shared_memory
));
697 topology_info_input
= &xgmi_cmd
->xgmi_in_message
.get_topology_info
;
698 xgmi_cmd
->cmd_id
= TA_COMMAND_XGMI__SET_TOPOLOGY_INFO
;
699 topology_info_input
->num_nodes
= number_devices
;
701 for (i
= 0; i
< topology_info_input
->num_nodes
; i
++) {
702 topology_info_input
->nodes
[i
].node_id
= topology
->nodes
[i
].node_id
;
703 topology_info_input
->nodes
[i
].num_hops
= topology
->nodes
[i
].num_hops
;
704 topology_info_input
->nodes
[i
].is_sharing_enabled
= topology
->nodes
[i
].is_sharing_enabled
;
705 topology_info_input
->nodes
[i
].sdma_engine
= topology
->nodes
[i
].sdma_engine
;
708 /* Invoke xgmi ta to set topology information */
709 return psp_xgmi_invoke(psp
, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO
);
712 static int psp_v11_0_xgmi_get_hive_id(struct psp_context
*psp
, uint64_t *hive_id
)
714 struct ta_xgmi_shared_memory
*xgmi_cmd
;
717 xgmi_cmd
= (struct ta_xgmi_shared_memory
*)psp
->xgmi_context
.xgmi_shared_buf
;
718 memset(xgmi_cmd
, 0, sizeof(struct ta_xgmi_shared_memory
));
720 xgmi_cmd
->cmd_id
= TA_COMMAND_XGMI__GET_HIVE_ID
;
722 /* Invoke xgmi ta to get hive id */
723 ret
= psp_xgmi_invoke(psp
, xgmi_cmd
->cmd_id
);
727 *hive_id
= xgmi_cmd
->xgmi_out_message
.get_hive_id
.hive_id
;
732 static int psp_v11_0_xgmi_get_node_id(struct psp_context
*psp
, uint64_t *node_id
)
734 struct ta_xgmi_shared_memory
*xgmi_cmd
;
737 xgmi_cmd
= (struct ta_xgmi_shared_memory
*)psp
->xgmi_context
.xgmi_shared_buf
;
738 memset(xgmi_cmd
, 0, sizeof(struct ta_xgmi_shared_memory
));
740 xgmi_cmd
->cmd_id
= TA_COMMAND_XGMI__GET_NODE_ID
;
742 /* Invoke xgmi ta to get the node id */
743 ret
= psp_xgmi_invoke(psp
, xgmi_cmd
->cmd_id
);
747 *node_id
= xgmi_cmd
->xgmi_out_message
.get_node_id
.node_id
;
752 static const struct psp_funcs psp_v11_0_funcs
= {
753 .init_microcode
= psp_v11_0_init_microcode
,
754 .bootloader_load_sysdrv
= psp_v11_0_bootloader_load_sysdrv
,
755 .bootloader_load_sos
= psp_v11_0_bootloader_load_sos
,
756 .prep_cmd_buf
= psp_v11_0_prep_cmd_buf
,
757 .ring_init
= psp_v11_0_ring_init
,
758 .ring_create
= psp_v11_0_ring_create
,
759 .ring_stop
= psp_v11_0_ring_stop
,
760 .ring_destroy
= psp_v11_0_ring_destroy
,
761 .cmd_submit
= psp_v11_0_cmd_submit
,
762 .compare_sram_data
= psp_v11_0_compare_sram_data
,
763 .mode1_reset
= psp_v11_0_mode1_reset
,
764 .xgmi_get_topology_info
= psp_v11_0_xgmi_get_topology_info
,
765 .xgmi_set_topology_info
= psp_v11_0_xgmi_set_topology_info
,
766 .xgmi_get_hive_id
= psp_v11_0_xgmi_get_hive_id
,
767 .xgmi_get_node_id
= psp_v11_0_xgmi_get_node_id
,
768 .support_vmr_ring
= psp_v11_0_support_vmr_ring
,
771 void psp_v11_0_set_psp_funcs(struct psp_context
*psp
)
773 psp
->funcs
= &psp_v11_0_funcs
;