2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/vmalloc.h>
28 #include "amdgpu_psp.h"
29 #include "amdgpu_ras.h"
30 #include "amdgpu_ucode.h"
31 #include "soc15_common.h"
32 #include "psp_v11_0.h"
34 #include "mp/mp_11_0_offset.h"
35 #include "mp/mp_11_0_sh_mask.h"
36 #include "gc/gc_9_0_offset.h"
37 #include "sdma0/sdma0_4_0_offset.h"
38 #include "nbio/nbio_7_4_offset.h"
40 #include "oss/osssys_4_0_offset.h"
41 #include "oss/osssys_4_0_sh_mask.h"
43 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
44 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
45 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
46 MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
47 MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
48 MODULE_FIRMWARE("amdgpu/navi10_ta.bin");
49 MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
50 MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
51 MODULE_FIRMWARE("amdgpu/navi14_ta.bin");
52 MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
53 MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
54 MODULE_FIRMWARE("amdgpu/navi12_ta.bin");
55 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
56 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
57 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
60 #define smnMP1_FIRMWARE_FLAGS 0x3010024
61 /* navi10 reg offset define */
62 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61
63 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62
64 #define mmSDMA0_UCODE_ADDR_NV10 0x5880
65 #define mmSDMA0_UCODE_DATA_NV10 0x5881
66 /* memory training timeout define */
67 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000
69 /* For large FW files the time to complete can be very long */
70 #define USBC_PD_POLLING_LIMIT_S 240
72 static int psp_v11_0_init_microcode(struct psp_context
*psp
)
74 struct amdgpu_device
*adev
= psp
->adev
;
75 const char *chip_name
;
78 const struct ta_firmware_header_v1_0
*ta_hdr
;
82 switch (adev
->asic_type
) {
96 chip_name
= "arcturus";
102 err
= psp_init_sos_microcode(psp
, chip_name
);
106 err
= psp_init_asd_microcode(psp
, chip_name
);
110 switch (adev
->asic_type
) {
113 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_ta.bin", chip_name
);
114 err
= request_firmware(&adev
->psp
.ta_fw
, fw_name
, adev
->dev
);
116 release_firmware(adev
->psp
.ta_fw
);
117 adev
->psp
.ta_fw
= NULL
;
119 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name
);
121 err
= amdgpu_ucode_validate(adev
->psp
.ta_fw
);
125 ta_hdr
= (const struct ta_firmware_header_v1_0
*)adev
->psp
.ta_fw
->data
;
126 adev
->psp
.ta_xgmi_ucode_version
= le32_to_cpu(ta_hdr
->ta_xgmi_ucode_version
);
127 adev
->psp
.ta_xgmi_ucode_size
= le32_to_cpu(ta_hdr
->ta_xgmi_size_bytes
);
128 adev
->psp
.ta_xgmi_start_addr
= (uint8_t *)ta_hdr
+
129 le32_to_cpu(ta_hdr
->header
.ucode_array_offset_bytes
);
130 adev
->psp
.ta_fw_version
= le32_to_cpu(ta_hdr
->header
.ucode_version
);
131 adev
->psp
.ta_ras_ucode_version
= le32_to_cpu(ta_hdr
->ta_ras_ucode_version
);
132 adev
->psp
.ta_ras_ucode_size
= le32_to_cpu(ta_hdr
->ta_ras_size_bytes
);
133 adev
->psp
.ta_ras_start_addr
= (uint8_t *)adev
->psp
.ta_xgmi_start_addr
+
134 le32_to_cpu(ta_hdr
->ta_ras_offset_bytes
);
140 if (amdgpu_sriov_vf(adev
))
142 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_ta.bin", chip_name
);
143 err
= request_firmware(&adev
->psp
.ta_fw
, fw_name
, adev
->dev
);
145 release_firmware(adev
->psp
.ta_fw
);
146 adev
->psp
.ta_fw
= NULL
;
148 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name
);
150 err
= amdgpu_ucode_validate(adev
->psp
.ta_fw
);
154 ta_hdr
= (const struct ta_firmware_header_v1_0
*)adev
->psp
.ta_fw
->data
;
155 adev
->psp
.ta_hdcp_ucode_version
= le32_to_cpu(ta_hdr
->ta_hdcp_ucode_version
);
156 adev
->psp
.ta_hdcp_ucode_size
= le32_to_cpu(ta_hdr
->ta_hdcp_size_bytes
);
157 adev
->psp
.ta_hdcp_start_addr
= (uint8_t *)ta_hdr
+
158 le32_to_cpu(ta_hdr
->header
.ucode_array_offset_bytes
);
160 adev
->psp
.ta_fw_version
= le32_to_cpu(ta_hdr
->header
.ucode_version
);
162 adev
->psp
.ta_dtm_ucode_version
= le32_to_cpu(ta_hdr
->ta_dtm_ucode_version
);
163 adev
->psp
.ta_dtm_ucode_size
= le32_to_cpu(ta_hdr
->ta_dtm_size_bytes
);
164 adev
->psp
.ta_dtm_start_addr
= (uint8_t *)adev
->psp
.ta_hdcp_start_addr
+
165 le32_to_cpu(ta_hdr
->ta_dtm_offset_bytes
);
175 release_firmware(adev
->psp
.ta_fw
);
176 adev
->psp
.ta_fw
= NULL
;
180 int psp_v11_0_wait_for_bootloader(struct psp_context
*psp
)
182 struct amdgpu_device
*adev
= psp
->adev
;
187 for (retry_loop
= 0; retry_loop
< 10; retry_loop
++) {
188 /* Wait for bootloader to signify that is
189 ready having bit 31 of C2PMSG_35 set to 1 */
190 ret
= psp_wait_for(psp
,
191 SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_35
),
203 static bool psp_v11_0_is_sos_alive(struct psp_context
*psp
)
205 struct amdgpu_device
*adev
= psp
->adev
;
208 sol_reg
= RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_81
);
210 return sol_reg
!= 0x0;
213 static int psp_v11_0_bootloader_load_kdb(struct psp_context
*psp
)
216 uint32_t psp_gfxdrv_command_reg
= 0;
217 struct amdgpu_device
*adev
= psp
->adev
;
219 /* Check tOS sign of life register to confirm sys driver and sOS
220 * are already been loaded.
222 if (psp_v11_0_is_sos_alive(psp
))
225 ret
= psp_v11_0_wait_for_bootloader(psp
);
229 memset(psp
->fw_pri_buf
, 0, PSP_1_MEG
);
231 /* Copy PSP KDB binary to memory */
232 memcpy(psp
->fw_pri_buf
, psp
->kdb_start_addr
, psp
->kdb_bin_size
);
234 /* Provide the PSP KDB to bootloader */
235 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_36
,
236 (uint32_t)(psp
->fw_pri_mc_addr
>> 20));
237 psp_gfxdrv_command_reg
= PSP_BL__LOAD_KEY_DATABASE
;
238 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_35
,
239 psp_gfxdrv_command_reg
);
241 ret
= psp_v11_0_wait_for_bootloader(psp
);
246 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context
*psp
)
249 uint32_t psp_gfxdrv_command_reg
= 0;
250 struct amdgpu_device
*adev
= psp
->adev
;
252 /* Check sOS sign of life register to confirm sys driver and sOS
253 * are already been loaded.
255 if (psp_v11_0_is_sos_alive(psp
))
258 ret
= psp_v11_0_wait_for_bootloader(psp
);
262 memset(psp
->fw_pri_buf
, 0, PSP_1_MEG
);
264 /* Copy PSP System Driver binary to memory */
265 memcpy(psp
->fw_pri_buf
, psp
->sys_start_addr
, psp
->sys_bin_size
);
267 /* Provide the sys driver to bootloader */
268 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_36
,
269 (uint32_t)(psp
->fw_pri_mc_addr
>> 20));
270 psp_gfxdrv_command_reg
= PSP_BL__LOAD_SYSDRV
;
271 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_35
,
272 psp_gfxdrv_command_reg
);
274 /* there might be handshake issue with hardware which needs delay */
277 ret
= psp_v11_0_wait_for_bootloader(psp
);
282 static int psp_v11_0_bootloader_load_sos(struct psp_context
*psp
)
285 unsigned int psp_gfxdrv_command_reg
= 0;
286 struct amdgpu_device
*adev
= psp
->adev
;
288 /* Check sOS sign of life register to confirm sys driver and sOS
289 * are already been loaded.
291 if (psp_v11_0_is_sos_alive(psp
))
294 ret
= psp_v11_0_wait_for_bootloader(psp
);
298 memset(psp
->fw_pri_buf
, 0, PSP_1_MEG
);
300 /* Copy Secure OS binary to PSP memory */
301 memcpy(psp
->fw_pri_buf
, psp
->sos_start_addr
, psp
->sos_bin_size
);
303 /* Provide the PSP secure OS to bootloader */
304 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_36
,
305 (uint32_t)(psp
->fw_pri_mc_addr
>> 20));
306 psp_gfxdrv_command_reg
= PSP_BL__LOAD_SOSDRV
;
307 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_35
,
308 psp_gfxdrv_command_reg
);
310 /* there might be handshake issue with hardware which needs delay */
312 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_81
),
313 RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_81
),
319 static void psp_v11_0_reroute_ih(struct psp_context
*psp
)
321 struct amdgpu_device
*adev
= psp
->adev
;
324 /* Change IH ring for VMC */
325 tmp
= REG_SET_FIELD(0, IH_CLIENT_CFG_DATA
, CREDIT_RETURN_ADDR
, 0x1244b);
326 tmp
= REG_SET_FIELD(tmp
, IH_CLIENT_CFG_DATA
, CLIENT_TYPE
, 1);
327 tmp
= REG_SET_FIELD(tmp
, IH_CLIENT_CFG_DATA
, RING_ID
, 1);
329 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_69
, 3);
330 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_70
, tmp
);
331 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_64
, GFX_CTRL_CMD_ID_GBR_IH_SET
);
334 psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_64
),
335 0x80000000, 0x8000FFFF, false);
337 /* Change IH ring for UMC */
338 tmp
= REG_SET_FIELD(0, IH_CLIENT_CFG_DATA
, CREDIT_RETURN_ADDR
, 0x1216b);
339 tmp
= REG_SET_FIELD(tmp
, IH_CLIENT_CFG_DATA
, RING_ID
, 1);
341 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_69
, 4);
342 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_70
, tmp
);
343 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_64
, GFX_CTRL_CMD_ID_GBR_IH_SET
);
346 psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_64
),
347 0x80000000, 0x8000FFFF, false);
350 static int psp_v11_0_ring_init(struct psp_context
*psp
,
351 enum psp_ring_type ring_type
)
354 struct psp_ring
*ring
;
355 struct amdgpu_device
*adev
= psp
->adev
;
357 if (!amdgpu_sriov_vf(adev
))
358 psp_v11_0_reroute_ih(psp
);
360 ring
= &psp
->km_ring
;
362 ring
->ring_type
= ring_type
;
364 /* allocate 4k Page of Local Frame Buffer memory for ring */
365 ring
->ring_size
= 0x1000;
366 ret
= amdgpu_bo_create_kernel(adev
, ring
->ring_size
, PAGE_SIZE
,
367 AMDGPU_GEM_DOMAIN_VRAM
,
368 &adev
->firmware
.rbuf
,
369 &ring
->ring_mem_mc_addr
,
370 (void **)&ring
->ring_mem
);
379 static int psp_v11_0_ring_stop(struct psp_context
*psp
,
380 enum psp_ring_type ring_type
)
383 struct amdgpu_device
*adev
= psp
->adev
;
385 /* Write the ring destroy command*/
386 if (amdgpu_sriov_vf(adev
))
387 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_101
,
388 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING
);
390 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_64
,
391 GFX_CTRL_CMD_ID_DESTROY_RINGS
);
393 /* there might be handshake issue with hardware which needs delay */
396 /* Wait for response flag (bit 31) */
397 if (amdgpu_sriov_vf(adev
))
398 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_101
),
399 0x80000000, 0x80000000, false);
401 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_64
),
402 0x80000000, 0x80000000, false);
407 static int psp_v11_0_ring_create(struct psp_context
*psp
,
408 enum psp_ring_type ring_type
)
411 unsigned int psp_ring_reg
= 0;
412 struct psp_ring
*ring
= &psp
->km_ring
;
413 struct amdgpu_device
*adev
= psp
->adev
;
415 if (amdgpu_sriov_vf(adev
)) {
416 ret
= psp_v11_0_ring_stop(psp
, ring_type
);
418 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");
422 /* Write low address of the ring to C2PMSG_102 */
423 psp_ring_reg
= lower_32_bits(ring
->ring_mem_mc_addr
);
424 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_102
, psp_ring_reg
);
425 /* Write high address of the ring to C2PMSG_103 */
426 psp_ring_reg
= upper_32_bits(ring
->ring_mem_mc_addr
);
427 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_103
, psp_ring_reg
);
429 /* Write the ring initialization command to C2PMSG_101 */
430 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_101
,
431 GFX_CTRL_CMD_ID_INIT_GPCOM_RING
);
433 /* there might be handshake issue with hardware which needs delay */
436 /* Wait for response flag (bit 31) in C2PMSG_101 */
437 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_101
),
438 0x80000000, 0x8000FFFF, false);
441 /* Wait for sOS ready for ring creation */
442 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_64
),
443 0x80000000, 0x80000000, false);
445 DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
449 /* Write low address of the ring to C2PMSG_69 */
450 psp_ring_reg
= lower_32_bits(ring
->ring_mem_mc_addr
);
451 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_69
, psp_ring_reg
);
452 /* Write high address of the ring to C2PMSG_70 */
453 psp_ring_reg
= upper_32_bits(ring
->ring_mem_mc_addr
);
454 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_70
, psp_ring_reg
);
455 /* Write size of ring to C2PMSG_71 */
456 psp_ring_reg
= ring
->ring_size
;
457 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_71
, psp_ring_reg
);
458 /* Write the ring initialization command to C2PMSG_64 */
459 psp_ring_reg
= ring_type
;
460 psp_ring_reg
= psp_ring_reg
<< 16;
461 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_64
, psp_ring_reg
);
463 /* there might be handshake issue with hardware which needs delay */
466 /* Wait for response flag (bit 31) in C2PMSG_64 */
467 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_64
),
468 0x80000000, 0x8000FFFF, false);
475 static int psp_v11_0_ring_destroy(struct psp_context
*psp
,
476 enum psp_ring_type ring_type
)
479 struct psp_ring
*ring
= &psp
->km_ring
;
480 struct amdgpu_device
*adev
= psp
->adev
;
482 ret
= psp_v11_0_ring_stop(psp
, ring_type
);
484 DRM_ERROR("Fail to stop psp ring\n");
486 amdgpu_bo_free_kernel(&adev
->firmware
.rbuf
,
487 &ring
->ring_mem_mc_addr
,
488 (void **)&ring
->ring_mem
);
493 static int psp_v11_0_mode1_reset(struct psp_context
*psp
)
497 struct amdgpu_device
*adev
= psp
->adev
;
499 offset
= SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_64
);
501 ret
= psp_wait_for(psp
, offset
, 0x80000000, 0x8000FFFF, false);
504 DRM_INFO("psp is not working correctly before mode1 reset!\n");
508 /*send the mode 1 reset command*/
509 WREG32(offset
, GFX_CTRL_CMD_ID_MODE1_RST
);
513 offset
= SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_33
);
515 ret
= psp_wait_for(psp
, offset
, 0x80000000, 0x80000000, false);
518 DRM_INFO("psp mode 1 reset failed!\n");
522 DRM_INFO("psp mode1 reset succeed \n");
527 static int psp_v11_0_memory_training_send_msg(struct psp_context
*psp
, int msg
)
533 struct amdgpu_device
*adev
= psp
->adev
;
535 data_32
= (psp
->mem_train_ctx
.c2p_train_data_offset
>> 20);
536 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_36
, data_32
);
537 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_35
, msg
);
539 max_wait
= MEM_TRAIN_SEND_MSG_TIMEOUT_US
/ adev
->usec_timeout
;
540 for (i
= 0; i
< max_wait
; i
++) {
541 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_35
),
542 0x80000000, 0x80000000, false);
551 DRM_DEBUG("training %s %s, cost %d @ %d ms\n",
552 (msg
== PSP_BL__DRAM_SHORT_TRAIN
) ? "short" : "long",
553 (ret
== 0) ? "succeed" : "failed",
554 i
, adev
->usec_timeout
/1000);
558 static void psp_v11_0_memory_training_fini(struct psp_context
*psp
)
560 struct psp_memory_training_context
*ctx
= &psp
->mem_train_ctx
;
562 ctx
->init
= PSP_MEM_TRAIN_NOT_SUPPORT
;
563 kfree(ctx
->sys_cache
);
564 ctx
->sys_cache
= NULL
;
567 static int psp_v11_0_memory_training_init(struct psp_context
*psp
)
570 struct psp_memory_training_context
*ctx
= &psp
->mem_train_ctx
;
572 if (ctx
->init
!= PSP_MEM_TRAIN_RESERVE_SUCCESS
) {
573 DRM_DEBUG("memory training is not supported!\n");
577 ctx
->sys_cache
= kzalloc(ctx
->train_data_size
, GFP_KERNEL
);
578 if (ctx
->sys_cache
== NULL
) {
579 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
584 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
585 ctx
->train_data_size
,
586 ctx
->p2c_train_data_offset
,
587 ctx
->c2p_train_data_offset
);
588 ctx
->init
= PSP_MEM_TRAIN_INIT_SUCCESS
;
592 psp_v11_0_memory_training_fini(psp
);
597 * save and restore proces
599 static int psp_v11_0_memory_training(struct psp_context
*psp
, uint32_t ops
)
601 struct psp_memory_training_context
*ctx
= &psp
->mem_train_ctx
;
602 uint32_t *pcache
= (uint32_t*)ctx
->sys_cache
;
603 struct amdgpu_device
*adev
= psp
->adev
;
604 uint32_t p2c_header
[4];
609 if (ctx
->init
== PSP_MEM_TRAIN_NOT_SUPPORT
) {
610 DRM_DEBUG("Memory training is not supported.\n");
612 } else if (ctx
->init
!= PSP_MEM_TRAIN_INIT_SUCCESS
) {
613 DRM_ERROR("Memory training initialization failure.\n");
617 if (psp_v11_0_is_sos_alive(psp
)) {
618 DRM_DEBUG("SOS is alive, skip memory training.\n");
622 amdgpu_device_vram_access(adev
, ctx
->p2c_train_data_offset
, p2c_header
, sizeof(p2c_header
), false);
623 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
624 pcache
[0], pcache
[1], pcache
[2], pcache
[3],
625 p2c_header
[0], p2c_header
[1], p2c_header
[2], p2c_header
[3]);
627 if (ops
& PSP_MEM_TRAIN_SEND_SHORT_MSG
) {
628 DRM_DEBUG("Short training depends on restore.\n");
629 ops
|= PSP_MEM_TRAIN_RESTORE
;
632 if ((ops
& PSP_MEM_TRAIN_RESTORE
) &&
633 pcache
[0] != MEM_TRAIN_SYSTEM_SIGNATURE
) {
634 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n");
635 ops
|= PSP_MEM_TRAIN_SAVE
;
638 if (p2c_header
[0] == MEM_TRAIN_SYSTEM_SIGNATURE
&&
639 !(pcache
[0] == MEM_TRAIN_SYSTEM_SIGNATURE
&&
640 pcache
[3] == p2c_header
[3])) {
641 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
642 ops
|= PSP_MEM_TRAIN_SAVE
;
645 if ((ops
& PSP_MEM_TRAIN_SAVE
) &&
646 p2c_header
[0] != MEM_TRAIN_SYSTEM_SIGNATURE
) {
647 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n");
648 ops
|= PSP_MEM_TRAIN_SEND_LONG_MSG
;
651 if (ops
& PSP_MEM_TRAIN_SEND_LONG_MSG
) {
652 ops
&= ~PSP_MEM_TRAIN_SEND_SHORT_MSG
;
653 ops
|= PSP_MEM_TRAIN_SAVE
;
656 DRM_DEBUG("Memory training ops:%x.\n", ops
);
658 if (ops
& PSP_MEM_TRAIN_SEND_LONG_MSG
) {
660 * Long traing will encroach certain mount of bottom VRAM,
661 * saving the content of this bottom VRAM to system memory
662 * before training, and restoring it after training to avoid
665 sz
= GDDR6_MEM_TRAINING_ENCROACHED_SIZE
;
667 if (adev
->gmc
.visible_vram_size
< sz
|| !adev
->mman
.aper_base_kaddr
) {
668 DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
669 adev
->gmc
.visible_vram_size
,
670 adev
->mman
.aper_base_kaddr
);
676 DRM_ERROR("failed to allocate system memory.\n");
680 memcpy_fromio(buf
, adev
->mman
.aper_base_kaddr
, sz
);
681 ret
= psp_v11_0_memory_training_send_msg(psp
, PSP_BL__DRAM_LONG_TRAIN
);
683 DRM_ERROR("Send long training msg failed.\n");
688 memcpy_toio(adev
->mman
.aper_base_kaddr
, buf
, sz
);
689 adev
->nbio
.funcs
->hdp_flush(adev
, NULL
);
693 if (ops
& PSP_MEM_TRAIN_SAVE
) {
694 amdgpu_device_vram_access(psp
->adev
, ctx
->p2c_train_data_offset
, ctx
->sys_cache
, ctx
->train_data_size
, false);
697 if (ops
& PSP_MEM_TRAIN_RESTORE
) {
698 amdgpu_device_vram_access(psp
->adev
, ctx
->c2p_train_data_offset
, ctx
->sys_cache
, ctx
->train_data_size
, true);
701 if (ops
& PSP_MEM_TRAIN_SEND_SHORT_MSG
) {
702 ret
= psp_v11_0_memory_training_send_msg(psp
, (amdgpu_force_long_training
> 0) ?
703 PSP_BL__DRAM_LONG_TRAIN
: PSP_BL__DRAM_SHORT_TRAIN
);
705 DRM_ERROR("send training msg failed.\n");
713 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context
*psp
)
716 struct amdgpu_device
*adev
= psp
->adev
;
718 if (amdgpu_sriov_vf(adev
))
719 data
= RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_102
);
721 data
= RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_67
);
726 static void psp_v11_0_ring_set_wptr(struct psp_context
*psp
, uint32_t value
)
728 struct amdgpu_device
*adev
= psp
->adev
;
730 if (amdgpu_sriov_vf(adev
)) {
731 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_102
, value
);
732 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_101
, GFX_CTRL_CMD_ID_CONSUME_CMD
);
734 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_67
, value
);
737 static int psp_v11_0_load_usbc_pd_fw(struct psp_context
*psp
, dma_addr_t dma_addr
)
739 struct amdgpu_device
*adev
= psp
->adev
;
743 /* Write lower 32-bit address of the PD Controller FW */
744 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_36
, lower_32_bits(dma_addr
));
745 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_35
),
746 0x80000000, 0x80000000, false);
750 /* Fireup interrupt so PSP can pick up the lower address */
751 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_35
, 0x800000);
752 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_35
),
753 0x80000000, 0x80000000, false);
757 reg_status
= RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_35
);
759 if ((reg_status
& 0xFFFF) != 0) {
760 DRM_ERROR("Lower address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %02x...\n",
761 reg_status
& 0xFFFF);
765 /* Write upper 32-bit address of the PD Controller FW */
766 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_36
, upper_32_bits(dma_addr
));
768 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_35
),
769 0x80000000, 0x80000000, false);
773 /* Fireup interrupt so PSP can pick up the upper address */
774 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_35
, 0x4000000);
776 /* FW load takes very long time */
779 reg_status
= RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_35
);
781 if (reg_status
& 0x80000000)
784 } while (++i
< USBC_PD_POLLING_LIMIT_S
);
789 if ((reg_status
& 0xFFFF) != 0) {
790 DRM_ERROR("Upper address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = x%04x\n",
791 reg_status
& 0xFFFF);
798 static int psp_v11_0_read_usbc_pd_fw(struct psp_context
*psp
, uint32_t *fw_ver
)
800 struct amdgpu_device
*adev
= psp
->adev
;
803 WREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_35
, C2PMSG_CMD_GFX_USB_PD_FW_VER
);
805 ret
= psp_wait_for(psp
, SOC15_REG_OFFSET(MP0
, 0, mmMP0_SMN_C2PMSG_35
),
806 0x80000000, 0x80000000, false);
808 *fw_ver
= RREG32_SOC15(MP0
, 0, mmMP0_SMN_C2PMSG_36
);
813 static const struct psp_funcs psp_v11_0_funcs
= {
814 .init_microcode
= psp_v11_0_init_microcode
,
815 .bootloader_load_kdb
= psp_v11_0_bootloader_load_kdb
,
816 .bootloader_load_sysdrv
= psp_v11_0_bootloader_load_sysdrv
,
817 .bootloader_load_sos
= psp_v11_0_bootloader_load_sos
,
818 .ring_init
= psp_v11_0_ring_init
,
819 .ring_create
= psp_v11_0_ring_create
,
820 .ring_stop
= psp_v11_0_ring_stop
,
821 .ring_destroy
= psp_v11_0_ring_destroy
,
822 .mode1_reset
= psp_v11_0_mode1_reset
,
823 .mem_training_init
= psp_v11_0_memory_training_init
,
824 .mem_training_fini
= psp_v11_0_memory_training_fini
,
825 .mem_training
= psp_v11_0_memory_training
,
826 .ring_get_wptr
= psp_v11_0_ring_get_wptr
,
827 .ring_set_wptr
= psp_v11_0_ring_set_wptr
,
828 .load_usbc_pd_fw
= psp_v11_0_load_usbc_pd_fw
,
829 .read_usbc_pd_fw
= psp_v11_0_read_usbc_pd_fw
832 void psp_v11_0_set_psp_funcs(struct psp_context
*psp
)
834 psp
->funcs
= &psp_v11_0_funcs
;