2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "oss/oss_3_0_d.h"
33 #include "oss/oss_3_0_sh_mask.h"
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
38 #include "gca/gfx_8_0_d.h"
39 #include "gca/gfx_8_0_enum.h"
40 #include "gca/gfx_8_0_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
45 #include "tonga_sdma_pkt_open.h"
47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device
*adev
);
48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device
*adev
);
49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device
*adev
);
50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device
*adev
);
52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
58 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
59 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
60 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
61 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
62 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
63 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin");
64 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin");
67 static const u32 sdma_offsets
[SDMA_MAX_INSTANCE
] =
69 SDMA0_REGISTER_OFFSET
,
73 static const u32 golden_settings_tonga_a11
[] =
75 mmSDMA0_CHICKEN_BITS
, 0xfc910007, 0x00810007,
76 mmSDMA0_CLK_CTRL
, 0xff000fff, 0x00000000,
77 mmSDMA0_GFX_IB_CNTL
, 0x800f0111, 0x00000100,
78 mmSDMA0_RLC0_IB_CNTL
, 0x800f0111, 0x00000100,
79 mmSDMA0_RLC1_IB_CNTL
, 0x800f0111, 0x00000100,
80 mmSDMA1_CHICKEN_BITS
, 0xfc910007, 0x00810007,
81 mmSDMA1_CLK_CTRL
, 0xff000fff, 0x00000000,
82 mmSDMA1_GFX_IB_CNTL
, 0x800f0111, 0x00000100,
83 mmSDMA1_RLC0_IB_CNTL
, 0x800f0111, 0x00000100,
84 mmSDMA1_RLC1_IB_CNTL
, 0x800f0111, 0x00000100,
87 static const u32 tonga_mgcg_cgcg_init
[] =
89 mmSDMA0_CLK_CTRL
, 0xff000ff0, 0x00000100,
90 mmSDMA1_CLK_CTRL
, 0xff000ff0, 0x00000100
93 static const u32 golden_settings_fiji_a10
[] =
95 mmSDMA0_CHICKEN_BITS
, 0xfc910007, 0x00810007,
96 mmSDMA0_GFX_IB_CNTL
, 0x800f0111, 0x00000100,
97 mmSDMA0_RLC0_IB_CNTL
, 0x800f0111, 0x00000100,
98 mmSDMA0_RLC1_IB_CNTL
, 0x800f0111, 0x00000100,
99 mmSDMA1_CHICKEN_BITS
, 0xfc910007, 0x00810007,
100 mmSDMA1_GFX_IB_CNTL
, 0x800f0111, 0x00000100,
101 mmSDMA1_RLC0_IB_CNTL
, 0x800f0111, 0x00000100,
102 mmSDMA1_RLC1_IB_CNTL
, 0x800f0111, 0x00000100,
105 static const u32 fiji_mgcg_cgcg_init
[] =
107 mmSDMA0_CLK_CTRL
, 0xff000ff0, 0x00000100,
108 mmSDMA1_CLK_CTRL
, 0xff000ff0, 0x00000100
111 static const u32 golden_settings_polaris11_a11
[] =
113 mmSDMA0_CHICKEN_BITS
, 0xfc910007, 0x00810007,
114 mmSDMA0_CLK_CTRL
, 0xff000fff, 0x00000000,
115 mmSDMA0_GFX_IB_CNTL
, 0x800f0111, 0x00000100,
116 mmSDMA0_RLC0_IB_CNTL
, 0x800f0111, 0x00000100,
117 mmSDMA0_RLC1_IB_CNTL
, 0x800f0111, 0x00000100,
118 mmSDMA1_CHICKEN_BITS
, 0xfc910007, 0x00810007,
119 mmSDMA1_CLK_CTRL
, 0xff000fff, 0x00000000,
120 mmSDMA1_GFX_IB_CNTL
, 0x800f0111, 0x00000100,
121 mmSDMA1_RLC0_IB_CNTL
, 0x800f0111, 0x00000100,
122 mmSDMA1_RLC1_IB_CNTL
, 0x800f0111, 0x00000100,
125 static const u32 golden_settings_polaris10_a11
[] =
127 mmSDMA0_CHICKEN_BITS
, 0xfc910007, 0x00810007,
128 mmSDMA0_CLK_CTRL
, 0xff000fff, 0x00000000,
129 mmSDMA0_GFX_IB_CNTL
, 0x800f0111, 0x00000100,
130 mmSDMA0_RLC0_IB_CNTL
, 0x800f0111, 0x00000100,
131 mmSDMA0_RLC1_IB_CNTL
, 0x800f0111, 0x00000100,
132 mmSDMA1_CHICKEN_BITS
, 0xfc910007, 0x00810007,
133 mmSDMA1_CLK_CTRL
, 0xff000fff, 0x00000000,
134 mmSDMA1_GFX_IB_CNTL
, 0x800f0111, 0x00000100,
135 mmSDMA1_RLC0_IB_CNTL
, 0x800f0111, 0x00000100,
136 mmSDMA1_RLC1_IB_CNTL
, 0x800f0111, 0x00000100,
139 static const u32 cz_golden_settings_a11
[] =
141 mmSDMA0_CHICKEN_BITS
, 0xfc910007, 0x00810007,
142 mmSDMA0_CLK_CTRL
, 0xff000fff, 0x00000000,
143 mmSDMA0_GFX_IB_CNTL
, 0x00000100, 0x00000100,
144 mmSDMA0_POWER_CNTL
, 0x00000800, 0x0003c800,
145 mmSDMA0_RLC0_IB_CNTL
, 0x00000100, 0x00000100,
146 mmSDMA0_RLC1_IB_CNTL
, 0x00000100, 0x00000100,
147 mmSDMA1_CHICKEN_BITS
, 0xfc910007, 0x00810007,
148 mmSDMA1_CLK_CTRL
, 0xff000fff, 0x00000000,
149 mmSDMA1_GFX_IB_CNTL
, 0x00000100, 0x00000100,
150 mmSDMA1_POWER_CNTL
, 0x00000800, 0x0003c800,
151 mmSDMA1_RLC0_IB_CNTL
, 0x00000100, 0x00000100,
152 mmSDMA1_RLC1_IB_CNTL
, 0x00000100, 0x00000100,
155 static const u32 cz_mgcg_cgcg_init
[] =
157 mmSDMA0_CLK_CTRL
, 0xff000ff0, 0x00000100,
158 mmSDMA1_CLK_CTRL
, 0xff000ff0, 0x00000100
161 static const u32 stoney_golden_settings_a11
[] =
163 mmSDMA0_GFX_IB_CNTL
, 0x00000100, 0x00000100,
164 mmSDMA0_POWER_CNTL
, 0x00000800, 0x0003c800,
165 mmSDMA0_RLC0_IB_CNTL
, 0x00000100, 0x00000100,
166 mmSDMA0_RLC1_IB_CNTL
, 0x00000100, 0x00000100,
169 static const u32 stoney_mgcg_cgcg_init
[] =
171 mmSDMA0_CLK_CTRL
, 0xffffffff, 0x00000100,
176 * Starting with CIK, the GPU has new asynchronous
177 * DMA engines. These engines are used for compute
178 * and gfx. There are two DMA engines (SDMA0, SDMA1)
179 * and each one supports 1 ring buffer used for gfx
180 * and 2 queues used for compute.
182 * The programming model is very similar to the CP
183 * (ring buffer, IBs, etc.), but sDMA has it's own
184 * packet format that is different from the PM4 format
185 * used by the CP. sDMA supports copying data, writing
186 * embedded data, solid fills, and a number of other
187 * things. It also has support for tiling/detiling of
191 static void sdma_v3_0_init_golden_registers(struct amdgpu_device
*adev
)
193 switch (adev
->asic_type
) {
195 amdgpu_program_register_sequence(adev
,
197 (const u32
)ARRAY_SIZE(fiji_mgcg_cgcg_init
));
198 amdgpu_program_register_sequence(adev
,
199 golden_settings_fiji_a10
,
200 (const u32
)ARRAY_SIZE(golden_settings_fiji_a10
));
203 amdgpu_program_register_sequence(adev
,
204 tonga_mgcg_cgcg_init
,
205 (const u32
)ARRAY_SIZE(tonga_mgcg_cgcg_init
));
206 amdgpu_program_register_sequence(adev
,
207 golden_settings_tonga_a11
,
208 (const u32
)ARRAY_SIZE(golden_settings_tonga_a11
));
212 amdgpu_program_register_sequence(adev
,
213 golden_settings_polaris11_a11
,
214 (const u32
)ARRAY_SIZE(golden_settings_polaris11_a11
));
217 amdgpu_program_register_sequence(adev
,
218 golden_settings_polaris10_a11
,
219 (const u32
)ARRAY_SIZE(golden_settings_polaris10_a11
));
222 amdgpu_program_register_sequence(adev
,
224 (const u32
)ARRAY_SIZE(cz_mgcg_cgcg_init
));
225 amdgpu_program_register_sequence(adev
,
226 cz_golden_settings_a11
,
227 (const u32
)ARRAY_SIZE(cz_golden_settings_a11
));
230 amdgpu_program_register_sequence(adev
,
231 stoney_mgcg_cgcg_init
,
232 (const u32
)ARRAY_SIZE(stoney_mgcg_cgcg_init
));
233 amdgpu_program_register_sequence(adev
,
234 stoney_golden_settings_a11
,
235 (const u32
)ARRAY_SIZE(stoney_golden_settings_a11
));
242 static void sdma_v3_0_free_microcode(struct amdgpu_device
*adev
)
245 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
246 release_firmware(adev
->sdma
.instance
[i
].fw
);
247 adev
->sdma
.instance
[i
].fw
= NULL
;
252 * sdma_v3_0_init_microcode - load ucode images from disk
254 * @adev: amdgpu_device pointer
256 * Use the firmware interface to load the ucode images into
257 * the driver (not loaded into hw).
258 * Returns 0 on success, error on failure.
260 static int sdma_v3_0_init_microcode(struct amdgpu_device
*adev
)
262 const char *chip_name
;
265 struct amdgpu_firmware_info
*info
= NULL
;
266 const struct common_firmware_header
*header
= NULL
;
267 const struct sdma_firmware_header_v1_0
*hdr
;
271 switch (adev
->asic_type
) {
279 chip_name
= "polaris11";
282 chip_name
= "polaris10";
285 chip_name
= "polaris12";
288 chip_name
= "carrizo";
291 chip_name
= "stoney";
296 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
298 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_sdma.bin", chip_name
);
300 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_sdma1.bin", chip_name
);
301 err
= request_firmware(&adev
->sdma
.instance
[i
].fw
, fw_name
, adev
->dev
);
304 err
= amdgpu_ucode_validate(adev
->sdma
.instance
[i
].fw
);
307 hdr
= (const struct sdma_firmware_header_v1_0
*)adev
->sdma
.instance
[i
].fw
->data
;
308 adev
->sdma
.instance
[i
].fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
309 adev
->sdma
.instance
[i
].feature_version
= le32_to_cpu(hdr
->ucode_feature_version
);
310 if (adev
->sdma
.instance
[i
].feature_version
>= 20)
311 adev
->sdma
.instance
[i
].burst_nop
= true;
313 if (adev
->firmware
.load_type
== AMDGPU_FW_LOAD_SMU
) {
314 info
= &adev
->firmware
.ucode
[AMDGPU_UCODE_ID_SDMA0
+ i
];
315 info
->ucode_id
= AMDGPU_UCODE_ID_SDMA0
+ i
;
316 info
->fw
= adev
->sdma
.instance
[i
].fw
;
317 header
= (const struct common_firmware_header
*)info
->fw
->data
;
318 adev
->firmware
.fw_size
+=
319 ALIGN(le32_to_cpu(header
->ucode_size_bytes
), PAGE_SIZE
);
324 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name
);
325 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
326 release_firmware(adev
->sdma
.instance
[i
].fw
);
327 adev
->sdma
.instance
[i
].fw
= NULL
;
334 * sdma_v3_0_ring_get_rptr - get the current read pointer
336 * @ring: amdgpu ring pointer
338 * Get the current rptr from the hardware (VI+).
340 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring
*ring
)
342 /* XXX check if swapping is necessary on BE */
343 return ring
->adev
->wb
.wb
[ring
->rptr_offs
] >> 2;
347 * sdma_v3_0_ring_get_wptr - get the current write pointer
349 * @ring: amdgpu ring pointer
351 * Get the current wptr from the hardware (VI+).
353 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring
*ring
)
355 struct amdgpu_device
*adev
= ring
->adev
;
358 if (ring
->use_doorbell
) {
359 /* XXX check if swapping is necessary on BE */
360 wptr
= ring
->adev
->wb
.wb
[ring
->wptr_offs
] >> 2;
362 int me
= (ring
== &ring
->adev
->sdma
.instance
[0].ring
) ? 0 : 1;
364 wptr
= RREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
]) >> 2;
371 * sdma_v3_0_ring_set_wptr - commit the write pointer
373 * @ring: amdgpu ring pointer
375 * Write the wptr back to the hardware (VI+).
377 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring
*ring
)
379 struct amdgpu_device
*adev
= ring
->adev
;
381 if (ring
->use_doorbell
) {
382 u32
*wb
= (u32
*)&adev
->wb
.wb
[ring
->wptr_offs
];
384 /* XXX check if swapping is necessary on BE */
385 WRITE_ONCE(*wb
, (lower_32_bits(ring
->wptr
) << 2));
386 WDOORBELL32(ring
->doorbell_index
, lower_32_bits(ring
->wptr
) << 2);
388 int me
= (ring
== &ring
->adev
->sdma
.instance
[0].ring
) ? 0 : 1;
390 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
], lower_32_bits(ring
->wptr
) << 2);
394 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring
*ring
, uint32_t count
)
396 struct amdgpu_sdma_instance
*sdma
= amdgpu_get_sdma_instance(ring
);
399 for (i
= 0; i
< count
; i
++)
400 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
401 amdgpu_ring_write(ring
, ring
->funcs
->nop
|
402 SDMA_PKT_NOP_HEADER_COUNT(count
- 1));
404 amdgpu_ring_write(ring
, ring
->funcs
->nop
);
408 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
410 * @ring: amdgpu ring pointer
411 * @ib: IB object to schedule
413 * Schedule an IB in the DMA ring (VI).
415 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring
*ring
,
416 struct amdgpu_ib
*ib
,
417 unsigned vm_id
, bool ctx_switch
)
419 u32 vmid
= vm_id
& 0xf;
421 /* IB packet must end on a 8 DW boundary */
422 sdma_v3_0_ring_insert_nop(ring
, (10 - (lower_32_bits(ring
->wptr
) & 7)) % 8);
424 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT
) |
425 SDMA_PKT_INDIRECT_HEADER_VMID(vmid
));
426 /* base must be 32 byte aligned */
427 amdgpu_ring_write(ring
, lower_32_bits(ib
->gpu_addr
) & 0xffffffe0);
428 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
));
429 amdgpu_ring_write(ring
, ib
->length_dw
);
430 amdgpu_ring_write(ring
, 0);
431 amdgpu_ring_write(ring
, 0);
436 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
438 * @ring: amdgpu ring pointer
440 * Emit an hdp flush packet on the requested DMA ring.
442 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring
*ring
)
444 u32 ref_and_mask
= 0;
446 if (ring
== &ring
->adev
->sdma
.instance
[0].ring
)
447 ref_and_mask
= REG_SET_FIELD(ref_and_mask
, GPU_HDP_FLUSH_DONE
, SDMA0
, 1);
449 ref_and_mask
= REG_SET_FIELD(ref_and_mask
, GPU_HDP_FLUSH_DONE
, SDMA1
, 1);
451 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM
) |
452 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
453 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
454 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_DONE
<< 2);
455 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_REQ
<< 2);
456 amdgpu_ring_write(ring
, ref_and_mask
); /* reference */
457 amdgpu_ring_write(ring
, ref_and_mask
); /* mask */
458 amdgpu_ring_write(ring
, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
459 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
462 static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring
*ring
)
464 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE
) |
465 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
466 amdgpu_ring_write(ring
, mmHDP_DEBUG0
);
467 amdgpu_ring_write(ring
, 1);
471 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
473 * @ring: amdgpu ring pointer
474 * @fence: amdgpu fence object
476 * Add a DMA fence packet to the ring to write
477 * the fence seq number and DMA trap packet to generate
478 * an interrupt if needed (VI).
480 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
, u64 seq
,
483 bool write64bit
= flags
& AMDGPU_FENCE_FLAG_64BIT
;
484 /* write the fence */
485 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE
));
486 amdgpu_ring_write(ring
, lower_32_bits(addr
));
487 amdgpu_ring_write(ring
, upper_32_bits(addr
));
488 amdgpu_ring_write(ring
, lower_32_bits(seq
));
490 /* optionally write high bits as well */
493 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE
));
494 amdgpu_ring_write(ring
, lower_32_bits(addr
));
495 amdgpu_ring_write(ring
, upper_32_bits(addr
));
496 amdgpu_ring_write(ring
, upper_32_bits(seq
));
499 /* generate an interrupt */
500 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP
));
501 amdgpu_ring_write(ring
, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
505 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
507 * @adev: amdgpu_device pointer
509 * Stop the gfx async dma ring buffers (VI).
511 static void sdma_v3_0_gfx_stop(struct amdgpu_device
*adev
)
513 struct amdgpu_ring
*sdma0
= &adev
->sdma
.instance
[0].ring
;
514 struct amdgpu_ring
*sdma1
= &adev
->sdma
.instance
[1].ring
;
515 u32 rb_cntl
, ib_cntl
;
518 if ((adev
->mman
.buffer_funcs_ring
== sdma0
) ||
519 (adev
->mman
.buffer_funcs_ring
== sdma1
))
520 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.visible_vram_size
);
522 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
523 rb_cntl
= RREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
]);
524 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_ENABLE
, 0);
525 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
526 ib_cntl
= RREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
]);
527 ib_cntl
= REG_SET_FIELD(ib_cntl
, SDMA0_GFX_IB_CNTL
, IB_ENABLE
, 0);
528 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], ib_cntl
);
530 sdma0
->ready
= false;
531 sdma1
->ready
= false;
535 * sdma_v3_0_rlc_stop - stop the compute async dma engines
537 * @adev: amdgpu_device pointer
539 * Stop the compute async dma queues (VI).
541 static void sdma_v3_0_rlc_stop(struct amdgpu_device
*adev
)
547 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
549 * @adev: amdgpu_device pointer
550 * @enable: enable/disable the DMA MEs context switch.
552 * Halt or unhalt the async dma engines context switch (VI).
554 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device
*adev
, bool enable
)
556 u32 f32_cntl
, phase_quantum
= 0;
559 if (amdgpu_sdma_phase_quantum
) {
560 unsigned value
= amdgpu_sdma_phase_quantum
;
563 while (value
> (SDMA0_PHASE0_QUANTUM__VALUE_MASK
>>
564 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT
)) {
565 value
= (value
+ 1) >> 1;
568 if (unit
> (SDMA0_PHASE0_QUANTUM__UNIT_MASK
>>
569 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT
)) {
570 value
= (SDMA0_PHASE0_QUANTUM__VALUE_MASK
>>
571 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT
);
572 unit
= (SDMA0_PHASE0_QUANTUM__UNIT_MASK
>>
573 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT
);
575 "clamping sdma_phase_quantum to %uK clock cycles\n",
579 value
<< SDMA0_PHASE0_QUANTUM__VALUE__SHIFT
|
580 unit
<< SDMA0_PHASE0_QUANTUM__UNIT__SHIFT
;
583 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
584 f32_cntl
= RREG32(mmSDMA0_CNTL
+ sdma_offsets
[i
]);
586 f32_cntl
= REG_SET_FIELD(f32_cntl
, SDMA0_CNTL
,
587 AUTO_CTXSW_ENABLE
, 1);
588 f32_cntl
= REG_SET_FIELD(f32_cntl
, SDMA0_CNTL
,
590 if (amdgpu_sdma_phase_quantum
) {
591 WREG32(mmSDMA0_PHASE0_QUANTUM
+ sdma_offsets
[i
],
593 WREG32(mmSDMA0_PHASE1_QUANTUM
+ sdma_offsets
[i
],
597 f32_cntl
= REG_SET_FIELD(f32_cntl
, SDMA0_CNTL
,
598 AUTO_CTXSW_ENABLE
, 0);
599 f32_cntl
= REG_SET_FIELD(f32_cntl
, SDMA0_CNTL
,
603 WREG32(mmSDMA0_CNTL
+ sdma_offsets
[i
], f32_cntl
);
608 * sdma_v3_0_enable - stop the async dma engines
610 * @adev: amdgpu_device pointer
611 * @enable: enable/disable the DMA MEs.
613 * Halt or unhalt the async dma engines (VI).
615 static void sdma_v3_0_enable(struct amdgpu_device
*adev
, bool enable
)
621 sdma_v3_0_gfx_stop(adev
);
622 sdma_v3_0_rlc_stop(adev
);
625 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
626 f32_cntl
= RREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
]);
628 f32_cntl
= REG_SET_FIELD(f32_cntl
, SDMA0_F32_CNTL
, HALT
, 0);
630 f32_cntl
= REG_SET_FIELD(f32_cntl
, SDMA0_F32_CNTL
, HALT
, 1);
631 WREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
], f32_cntl
);
636 * sdma_v3_0_gfx_resume - setup and start the async dma engines
638 * @adev: amdgpu_device pointer
640 * Set up the gfx DMA ring buffers and enable them (VI).
641 * Returns 0 for success, error for failure.
643 static int sdma_v3_0_gfx_resume(struct amdgpu_device
*adev
)
645 struct amdgpu_ring
*ring
;
646 u32 rb_cntl
, ib_cntl
, wptr_poll_cntl
;
653 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
654 ring
= &adev
->sdma
.instance
[i
].ring
;
655 amdgpu_ring_clear_ring(ring
);
656 wb_offset
= (ring
->rptr_offs
* 4);
658 mutex_lock(&adev
->srbm_mutex
);
659 for (j
= 0; j
< 16; j
++) {
660 vi_srbm_select(adev
, 0, 0, 0, j
);
662 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR
+ sdma_offsets
[i
], 0);
663 WREG32(mmSDMA0_GFX_APE1_CNTL
+ sdma_offsets
[i
], 0);
665 vi_srbm_select(adev
, 0, 0, 0, 0);
666 mutex_unlock(&adev
->srbm_mutex
);
668 WREG32(mmSDMA0_TILING_CONFIG
+ sdma_offsets
[i
],
669 adev
->gfx
.config
.gb_addr_config
& 0x70);
671 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
+ sdma_offsets
[i
], 0);
673 /* Set ring buffer size in dwords */
674 rb_bufsz
= order_base_2(ring
->ring_size
/ 4);
675 rb_cntl
= RREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
]);
676 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_SIZE
, rb_bufsz
);
678 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_SWAP_ENABLE
, 1);
679 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
,
680 RPTR_WRITEBACK_SWAP_ENABLE
, 1);
682 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
684 /* Initialize the ring buffer's read and write pointers */
686 WREG32(mmSDMA0_GFX_RB_RPTR
+ sdma_offsets
[i
], 0);
687 sdma_v3_0_ring_set_wptr(ring
);
688 WREG32(mmSDMA0_GFX_IB_RPTR
+ sdma_offsets
[i
], 0);
689 WREG32(mmSDMA0_GFX_IB_OFFSET
+ sdma_offsets
[i
], 0);
691 /* set the wb address whether it's enabled or not */
692 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI
+ sdma_offsets
[i
],
693 upper_32_bits(adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFF);
694 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO
+ sdma_offsets
[i
],
695 lower_32_bits(adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFC);
697 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RPTR_WRITEBACK_ENABLE
, 1);
699 WREG32(mmSDMA0_GFX_RB_BASE
+ sdma_offsets
[i
], ring
->gpu_addr
>> 8);
700 WREG32(mmSDMA0_GFX_RB_BASE_HI
+ sdma_offsets
[i
], ring
->gpu_addr
>> 40);
702 doorbell
= RREG32(mmSDMA0_GFX_DOORBELL
+ sdma_offsets
[i
]);
704 if (ring
->use_doorbell
) {
705 doorbell
= REG_SET_FIELD(doorbell
, SDMA0_GFX_DOORBELL
,
706 OFFSET
, ring
->doorbell_index
);
707 doorbell
= REG_SET_FIELD(doorbell
, SDMA0_GFX_DOORBELL
, ENABLE
, 1);
709 doorbell
= REG_SET_FIELD(doorbell
, SDMA0_GFX_DOORBELL
, ENABLE
, 0);
711 WREG32(mmSDMA0_GFX_DOORBELL
+ sdma_offsets
[i
], doorbell
);
713 /* setup the wptr shadow polling */
714 wptr_gpu_addr
= adev
->wb
.gpu_addr
+ (ring
->wptr_offs
* 4);
716 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO
+ sdma_offsets
[i
],
717 lower_32_bits(wptr_gpu_addr
));
718 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI
+ sdma_offsets
[i
],
719 upper_32_bits(wptr_gpu_addr
));
720 wptr_poll_cntl
= RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL
+ sdma_offsets
[i
]);
721 if (amdgpu_sriov_vf(adev
))
722 wptr_poll_cntl
= REG_SET_FIELD(wptr_poll_cntl
, SDMA0_GFX_RB_WPTR_POLL_CNTL
, F32_POLL_ENABLE
, 1);
724 wptr_poll_cntl
= REG_SET_FIELD(wptr_poll_cntl
, SDMA0_GFX_RB_WPTR_POLL_CNTL
, F32_POLL_ENABLE
, 0);
725 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL
+ sdma_offsets
[i
], wptr_poll_cntl
);
728 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_ENABLE
, 1);
729 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
731 ib_cntl
= RREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
]);
732 ib_cntl
= REG_SET_FIELD(ib_cntl
, SDMA0_GFX_IB_CNTL
, IB_ENABLE
, 1);
734 ib_cntl
= REG_SET_FIELD(ib_cntl
, SDMA0_GFX_IB_CNTL
, IB_SWAP_ENABLE
, 1);
737 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], ib_cntl
);
743 sdma_v3_0_enable(adev
, true);
744 /* enable sdma ring preemption */
745 sdma_v3_0_ctx_switch_enable(adev
, true);
747 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
748 ring
= &adev
->sdma
.instance
[i
].ring
;
749 r
= amdgpu_ring_test_ring(ring
);
755 if (adev
->mman
.buffer_funcs_ring
== ring
)
756 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.real_vram_size
);
763 * sdma_v3_0_rlc_resume - setup and start the async dma engines
765 * @adev: amdgpu_device pointer
767 * Set up the compute DMA queues and enable them (VI).
768 * Returns 0 for success, error for failure.
770 static int sdma_v3_0_rlc_resume(struct amdgpu_device
*adev
)
777 * sdma_v3_0_load_microcode - load the sDMA ME ucode
779 * @adev: amdgpu_device pointer
781 * Loads the sDMA0/1 ucode.
782 * Returns 0 for success, -EINVAL if the ucode is not available.
784 static int sdma_v3_0_load_microcode(struct amdgpu_device
*adev
)
786 const struct sdma_firmware_header_v1_0
*hdr
;
787 const __le32
*fw_data
;
792 sdma_v3_0_enable(adev
, false);
794 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
795 if (!adev
->sdma
.instance
[i
].fw
)
797 hdr
= (const struct sdma_firmware_header_v1_0
*)adev
->sdma
.instance
[i
].fw
->data
;
798 amdgpu_ucode_print_sdma_hdr(&hdr
->header
);
799 fw_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
800 fw_data
= (const __le32
*)
801 (adev
->sdma
.instance
[i
].fw
->data
+
802 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
803 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], 0);
804 for (j
= 0; j
< fw_size
; j
++)
805 WREG32(mmSDMA0_UCODE_DATA
+ sdma_offsets
[i
], le32_to_cpup(fw_data
++));
806 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], adev
->sdma
.instance
[i
].fw_version
);
813 * sdma_v3_0_start - setup and start the async dma engines
815 * @adev: amdgpu_device pointer
817 * Set up the DMA engines and enable them (VI).
818 * Returns 0 for success, error for failure.
820 static int sdma_v3_0_start(struct amdgpu_device
*adev
)
824 if (adev
->firmware
.load_type
== AMDGPU_FW_LOAD_DIRECT
) {
825 r
= sdma_v3_0_load_microcode(adev
);
830 /* disable sdma engine before programing it */
831 sdma_v3_0_ctx_switch_enable(adev
, false);
832 sdma_v3_0_enable(adev
, false);
834 /* start the gfx rings and rlc compute queues */
835 r
= sdma_v3_0_gfx_resume(adev
);
838 r
= sdma_v3_0_rlc_resume(adev
);
846 * sdma_v3_0_ring_test_ring - simple async dma engine test
848 * @ring: amdgpu_ring structure holding ring information
850 * Test the DMA engine by writing using it to write an
851 * value to memory. (VI).
852 * Returns 0 for success, error for failure.
854 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring
*ring
)
856 struct amdgpu_device
*adev
= ring
->adev
;
863 r
= amdgpu_wb_get(adev
, &index
);
865 dev_err(adev
->dev
, "(%d) failed to allocate wb slot\n", r
);
869 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
871 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
873 r
= amdgpu_ring_alloc(ring
, 5);
875 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring
->idx
, r
);
876 amdgpu_wb_free(adev
, index
);
880 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
881 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR
));
882 amdgpu_ring_write(ring
, lower_32_bits(gpu_addr
));
883 amdgpu_ring_write(ring
, upper_32_bits(gpu_addr
));
884 amdgpu_ring_write(ring
, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
885 amdgpu_ring_write(ring
, 0xDEADBEEF);
886 amdgpu_ring_commit(ring
);
888 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
889 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
890 if (tmp
== 0xDEADBEEF)
895 if (i
< adev
->usec_timeout
) {
896 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring
->idx
, i
);
898 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
902 amdgpu_wb_free(adev
, index
);
908 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
910 * @ring: amdgpu_ring structure holding ring information
912 * Test a simple IB in the DMA ring (VI).
913 * Returns 0 on success, error on failure.
915 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring
*ring
, long timeout
)
917 struct amdgpu_device
*adev
= ring
->adev
;
919 struct dma_fence
*f
= NULL
;
925 r
= amdgpu_wb_get(adev
, &index
);
927 dev_err(adev
->dev
, "(%ld) failed to allocate wb slot\n", r
);
931 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
933 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
934 memset(&ib
, 0, sizeof(ib
));
935 r
= amdgpu_ib_get(adev
, NULL
, 256, &ib
);
937 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r
);
941 ib
.ptr
[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
942 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR
);
943 ib
.ptr
[1] = lower_32_bits(gpu_addr
);
944 ib
.ptr
[2] = upper_32_bits(gpu_addr
);
945 ib
.ptr
[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
946 ib
.ptr
[4] = 0xDEADBEEF;
947 ib
.ptr
[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
);
948 ib
.ptr
[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
);
949 ib
.ptr
[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
);
952 r
= amdgpu_ib_schedule(ring
, 1, &ib
, NULL
, &f
);
956 r
= dma_fence_wait_timeout(f
, false, timeout
);
958 DRM_ERROR("amdgpu: IB test timed out\n");
962 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r
);
965 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
966 if (tmp
== 0xDEADBEEF) {
967 DRM_DEBUG("ib test on ring %d succeeded\n", ring
->idx
);
970 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp
);
974 amdgpu_ib_free(adev
, &ib
, NULL
);
977 amdgpu_wb_free(adev
, index
);
982 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
984 * @ib: indirect buffer to fill with commands
985 * @pe: addr of the page entry
986 * @src: src addr to copy from
987 * @count: number of page entries to update
989 * Update PTEs by copying them from the GART using sDMA (CIK).
991 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib
*ib
,
992 uint64_t pe
, uint64_t src
,
995 unsigned bytes
= count
* 8;
997 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY
) |
998 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR
);
999 ib
->ptr
[ib
->length_dw
++] = bytes
;
1000 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
1001 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src
);
1002 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src
);
1003 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
);
1004 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
1008 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
1010 * @ib: indirect buffer to fill with commands
1011 * @pe: addr of the page entry
1012 * @value: dst addr to write into pe
1013 * @count: number of page entries to update
1014 * @incr: increase next addr by incr bytes
1016 * Update PTEs by writing them manually using sDMA (CIK).
1018 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib
*ib
, uint64_t pe
,
1019 uint64_t value
, unsigned count
,
1022 unsigned ndw
= count
* 2;
1024 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
1025 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR
);
1026 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
);
1027 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
1028 ib
->ptr
[ib
->length_dw
++] = ndw
;
1029 for (; ndw
> 0; ndw
-= 2) {
1030 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(value
);
1031 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
1037 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
1039 * @ib: indirect buffer to fill with commands
1040 * @pe: addr of the page entry
1041 * @addr: dst addr to write into pe
1042 * @count: number of page entries to update
1043 * @incr: increase next addr by incr bytes
1044 * @flags: access flags
1046 * Update the page tables using sDMA (CIK).
1048 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib
*ib
, uint64_t pe
,
1049 uint64_t addr
, unsigned count
,
1050 uint32_t incr
, uint64_t flags
)
1052 /* for physically contiguous pages (vram) */
1053 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE
);
1054 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
); /* dst addr */
1055 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
1056 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(flags
); /* mask */
1057 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(flags
);
1058 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(addr
); /* value */
1059 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(addr
);
1060 ib
->ptr
[ib
->length_dw
++] = incr
; /* increment size */
1061 ib
->ptr
[ib
->length_dw
++] = 0;
1062 ib
->ptr
[ib
->length_dw
++] = count
; /* number of entries */
1066 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1068 * @ib: indirect buffer to fill with padding
1071 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
)
1073 struct amdgpu_sdma_instance
*sdma
= amdgpu_get_sdma_instance(ring
);
1077 pad_count
= (8 - (ib
->length_dw
& 0x7)) % 8;
1078 for (i
= 0; i
< pad_count
; i
++)
1079 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
1080 ib
->ptr
[ib
->length_dw
++] =
1081 SDMA_PKT_HEADER_OP(SDMA_OP_NOP
) |
1082 SDMA_PKT_NOP_HEADER_COUNT(pad_count
- 1);
1084 ib
->ptr
[ib
->length_dw
++] =
1085 SDMA_PKT_HEADER_OP(SDMA_OP_NOP
);
1089 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1091 * @ring: amdgpu_ring pointer
1093 * Make sure all previous operations are completed (CIK).
1095 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring
*ring
)
1097 uint32_t seq
= ring
->fence_drv
.sync_seq
;
1098 uint64_t addr
= ring
->fence_drv
.gpu_addr
;
1101 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM
) |
1102 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1103 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1104 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1105 amdgpu_ring_write(ring
, addr
& 0xfffffffc);
1106 amdgpu_ring_write(ring
, upper_32_bits(addr
) & 0xffffffff);
1107 amdgpu_ring_write(ring
, seq
); /* reference */
1108 amdgpu_ring_write(ring
, 0xfffffff); /* mask */
1109 amdgpu_ring_write(ring
, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1110 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1114 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1116 * @ring: amdgpu_ring pointer
1117 * @vm: amdgpu_vm pointer
1119 * Update the page table base and flush the VM TLB
1122 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring
*ring
,
1123 unsigned vm_id
, uint64_t pd_addr
)
1125 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE
) |
1126 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1128 amdgpu_ring_write(ring
, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ vm_id
));
1130 amdgpu_ring_write(ring
, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ vm_id
- 8));
1132 amdgpu_ring_write(ring
, pd_addr
>> 12);
1135 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE
) |
1136 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1137 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
);
1138 amdgpu_ring_write(ring
, 1 << vm_id
);
1140 /* wait for flush */
1141 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM
) |
1142 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1143 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1144 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
<< 2);
1145 amdgpu_ring_write(ring
, 0);
1146 amdgpu_ring_write(ring
, 0); /* reference */
1147 amdgpu_ring_write(ring
, 0); /* mask */
1148 amdgpu_ring_write(ring
, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1149 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1152 static int sdma_v3_0_early_init(void *handle
)
1154 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1156 switch (adev
->asic_type
) {
1158 adev
->sdma
.num_instances
= 1;
1161 adev
->sdma
.num_instances
= SDMA_MAX_INSTANCE
;
1165 sdma_v3_0_set_ring_funcs(adev
);
1166 sdma_v3_0_set_buffer_funcs(adev
);
1167 sdma_v3_0_set_vm_pte_funcs(adev
);
1168 sdma_v3_0_set_irq_funcs(adev
);
1173 static int sdma_v3_0_sw_init(void *handle
)
1175 struct amdgpu_ring
*ring
;
1177 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1179 /* SDMA trap event */
1180 r
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_LEGACY
, 224,
1181 &adev
->sdma
.trap_irq
);
1185 /* SDMA Privileged inst */
1186 r
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_LEGACY
, 241,
1187 &adev
->sdma
.illegal_inst_irq
);
1191 /* SDMA Privileged inst */
1192 r
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_LEGACY
, 247,
1193 &adev
->sdma
.illegal_inst_irq
);
1197 r
= sdma_v3_0_init_microcode(adev
);
1199 DRM_ERROR("Failed to load sdma firmware!\n");
1203 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1204 ring
= &adev
->sdma
.instance
[i
].ring
;
1205 ring
->ring_obj
= NULL
;
1206 ring
->use_doorbell
= true;
1207 ring
->doorbell_index
= (i
== 0) ?
1208 AMDGPU_DOORBELL_sDMA_ENGINE0
: AMDGPU_DOORBELL_sDMA_ENGINE1
;
1210 sprintf(ring
->name
, "sdma%d", i
);
1211 r
= amdgpu_ring_init(adev
, ring
, 1024,
1212 &adev
->sdma
.trap_irq
,
1214 AMDGPU_SDMA_IRQ_TRAP0
:
1215 AMDGPU_SDMA_IRQ_TRAP1
);
1223 static int sdma_v3_0_sw_fini(void *handle
)
1225 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1228 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1229 amdgpu_ring_fini(&adev
->sdma
.instance
[i
].ring
);
1231 sdma_v3_0_free_microcode(adev
);
1235 static int sdma_v3_0_hw_init(void *handle
)
1238 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1240 sdma_v3_0_init_golden_registers(adev
);
1242 r
= sdma_v3_0_start(adev
);
1249 static int sdma_v3_0_hw_fini(void *handle
)
1251 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1253 sdma_v3_0_ctx_switch_enable(adev
, false);
1254 sdma_v3_0_enable(adev
, false);
1259 static int sdma_v3_0_suspend(void *handle
)
1261 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1263 return sdma_v3_0_hw_fini(adev
);
1266 static int sdma_v3_0_resume(void *handle
)
1268 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1270 return sdma_v3_0_hw_init(adev
);
1273 static bool sdma_v3_0_is_idle(void *handle
)
1275 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1276 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1278 if (tmp
& (SRBM_STATUS2__SDMA_BUSY_MASK
|
1279 SRBM_STATUS2__SDMA1_BUSY_MASK
))
1285 static int sdma_v3_0_wait_for_idle(void *handle
)
1289 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1291 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1292 tmp
= RREG32(mmSRBM_STATUS2
) & (SRBM_STATUS2__SDMA_BUSY_MASK
|
1293 SRBM_STATUS2__SDMA1_BUSY_MASK
);
1302 static bool sdma_v3_0_check_soft_reset(void *handle
)
1304 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1305 u32 srbm_soft_reset
= 0;
1306 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1308 if ((tmp
& SRBM_STATUS2__SDMA_BUSY_MASK
) ||
1309 (tmp
& SRBM_STATUS2__SDMA1_BUSY_MASK
)) {
1310 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK
;
1311 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK
;
1314 if (srbm_soft_reset
) {
1315 adev
->sdma
.srbm_soft_reset
= srbm_soft_reset
;
1318 adev
->sdma
.srbm_soft_reset
= 0;
1323 static int sdma_v3_0_pre_soft_reset(void *handle
)
1325 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1326 u32 srbm_soft_reset
= 0;
1328 if (!adev
->sdma
.srbm_soft_reset
)
1331 srbm_soft_reset
= adev
->sdma
.srbm_soft_reset
;
1333 if (REG_GET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_SDMA
) ||
1334 REG_GET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_SDMA1
)) {
1335 sdma_v3_0_ctx_switch_enable(adev
, false);
1336 sdma_v3_0_enable(adev
, false);
1342 static int sdma_v3_0_post_soft_reset(void *handle
)
1344 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1345 u32 srbm_soft_reset
= 0;
1347 if (!adev
->sdma
.srbm_soft_reset
)
1350 srbm_soft_reset
= adev
->sdma
.srbm_soft_reset
;
1352 if (REG_GET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_SDMA
) ||
1353 REG_GET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_SDMA1
)) {
1354 sdma_v3_0_gfx_resume(adev
);
1355 sdma_v3_0_rlc_resume(adev
);
1361 static int sdma_v3_0_soft_reset(void *handle
)
1363 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1364 u32 srbm_soft_reset
= 0;
1367 if (!adev
->sdma
.srbm_soft_reset
)
1370 srbm_soft_reset
= adev
->sdma
.srbm_soft_reset
;
1372 if (srbm_soft_reset
) {
1373 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1374 tmp
|= srbm_soft_reset
;
1375 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
1376 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1377 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1381 tmp
&= ~srbm_soft_reset
;
1382 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1383 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1385 /* Wait a little for things to settle down */
1392 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device
*adev
,
1393 struct amdgpu_irq_src
*source
,
1395 enum amdgpu_interrupt_state state
)
1400 case AMDGPU_SDMA_IRQ_TRAP0
:
1402 case AMDGPU_IRQ_STATE_DISABLE
:
1403 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1404 sdma_cntl
= REG_SET_FIELD(sdma_cntl
, SDMA0_CNTL
, TRAP_ENABLE
, 0);
1405 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1407 case AMDGPU_IRQ_STATE_ENABLE
:
1408 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1409 sdma_cntl
= REG_SET_FIELD(sdma_cntl
, SDMA0_CNTL
, TRAP_ENABLE
, 1);
1410 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1416 case AMDGPU_SDMA_IRQ_TRAP1
:
1418 case AMDGPU_IRQ_STATE_DISABLE
:
1419 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1420 sdma_cntl
= REG_SET_FIELD(sdma_cntl
, SDMA0_CNTL
, TRAP_ENABLE
, 0);
1421 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1423 case AMDGPU_IRQ_STATE_ENABLE
:
1424 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1425 sdma_cntl
= REG_SET_FIELD(sdma_cntl
, SDMA0_CNTL
, TRAP_ENABLE
, 1);
1426 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1438 static int sdma_v3_0_process_trap_irq(struct amdgpu_device
*adev
,
1439 struct amdgpu_irq_src
*source
,
1440 struct amdgpu_iv_entry
*entry
)
1442 u8 instance_id
, queue_id
;
1444 instance_id
= (entry
->ring_id
& 0x3) >> 0;
1445 queue_id
= (entry
->ring_id
& 0xc) >> 2;
1446 DRM_DEBUG("IH: SDMA trap\n");
1447 switch (instance_id
) {
1451 amdgpu_fence_process(&adev
->sdma
.instance
[0].ring
);
1464 amdgpu_fence_process(&adev
->sdma
.instance
[1].ring
);
1478 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device
*adev
,
1479 struct amdgpu_irq_src
*source
,
1480 struct amdgpu_iv_entry
*entry
)
1482 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1483 schedule_work(&adev
->reset_work
);
1487 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1488 struct amdgpu_device
*adev
,
1491 uint32_t temp
, data
;
1494 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_SDMA_MGCG
)) {
1495 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1496 temp
= data
= RREG32(mmSDMA0_CLK_CTRL
+ sdma_offsets
[i
]);
1497 data
&= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK
|
1498 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK
|
1499 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK
|
1500 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK
|
1501 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK
|
1502 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK
|
1503 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK
|
1504 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK
);
1506 WREG32(mmSDMA0_CLK_CTRL
+ sdma_offsets
[i
], data
);
1509 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1510 temp
= data
= RREG32(mmSDMA0_CLK_CTRL
+ sdma_offsets
[i
]);
1511 data
|= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK
|
1512 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK
|
1513 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK
|
1514 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK
|
1515 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK
|
1516 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK
|
1517 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK
|
1518 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK
;
1521 WREG32(mmSDMA0_CLK_CTRL
+ sdma_offsets
[i
], data
);
1526 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1527 struct amdgpu_device
*adev
,
1530 uint32_t temp
, data
;
1533 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_SDMA_LS
)) {
1534 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1535 temp
= data
= RREG32(mmSDMA0_POWER_CNTL
+ sdma_offsets
[i
]);
1536 data
|= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK
;
1539 WREG32(mmSDMA0_POWER_CNTL
+ sdma_offsets
[i
], data
);
1542 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1543 temp
= data
= RREG32(mmSDMA0_POWER_CNTL
+ sdma_offsets
[i
]);
1544 data
&= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK
;
1547 WREG32(mmSDMA0_POWER_CNTL
+ sdma_offsets
[i
], data
);
1552 static int sdma_v3_0_set_clockgating_state(void *handle
,
1553 enum amd_clockgating_state state
)
1555 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1557 if (amdgpu_sriov_vf(adev
))
1560 switch (adev
->asic_type
) {
1564 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev
,
1565 state
== AMD_CG_STATE_GATE
);
1566 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev
,
1567 state
== AMD_CG_STATE_GATE
);
1575 static int sdma_v3_0_set_powergating_state(void *handle
,
1576 enum amd_powergating_state state
)
1581 static void sdma_v3_0_get_clockgating_state(void *handle
, u32
*flags
)
1583 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1586 if (amdgpu_sriov_vf(adev
))
1589 /* AMD_CG_SUPPORT_SDMA_MGCG */
1590 data
= RREG32(mmSDMA0_CLK_CTRL
+ sdma_offsets
[0]);
1591 if (!(data
& SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK
))
1592 *flags
|= AMD_CG_SUPPORT_SDMA_MGCG
;
1594 /* AMD_CG_SUPPORT_SDMA_LS */
1595 data
= RREG32(mmSDMA0_POWER_CNTL
+ sdma_offsets
[0]);
1596 if (data
& SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK
)
1597 *flags
|= AMD_CG_SUPPORT_SDMA_LS
;
1600 static const struct amd_ip_funcs sdma_v3_0_ip_funcs
= {
1601 .name
= "sdma_v3_0",
1602 .early_init
= sdma_v3_0_early_init
,
1604 .sw_init
= sdma_v3_0_sw_init
,
1605 .sw_fini
= sdma_v3_0_sw_fini
,
1606 .hw_init
= sdma_v3_0_hw_init
,
1607 .hw_fini
= sdma_v3_0_hw_fini
,
1608 .suspend
= sdma_v3_0_suspend
,
1609 .resume
= sdma_v3_0_resume
,
1610 .is_idle
= sdma_v3_0_is_idle
,
1611 .wait_for_idle
= sdma_v3_0_wait_for_idle
,
1612 .check_soft_reset
= sdma_v3_0_check_soft_reset
,
1613 .pre_soft_reset
= sdma_v3_0_pre_soft_reset
,
1614 .post_soft_reset
= sdma_v3_0_post_soft_reset
,
1615 .soft_reset
= sdma_v3_0_soft_reset
,
1616 .set_clockgating_state
= sdma_v3_0_set_clockgating_state
,
1617 .set_powergating_state
= sdma_v3_0_set_powergating_state
,
1618 .get_clockgating_state
= sdma_v3_0_get_clockgating_state
,
1621 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs
= {
1622 .type
= AMDGPU_RING_TYPE_SDMA
,
1624 .nop
= SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
),
1625 .support_64bit_ptrs
= false,
1626 .get_rptr
= sdma_v3_0_ring_get_rptr
,
1627 .get_wptr
= sdma_v3_0_ring_get_wptr
,
1628 .set_wptr
= sdma_v3_0_ring_set_wptr
,
1630 6 + /* sdma_v3_0_ring_emit_hdp_flush */
1631 3 + /* sdma_v3_0_ring_emit_hdp_invalidate */
1632 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
1633 12 + /* sdma_v3_0_ring_emit_vm_flush */
1634 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
1635 .emit_ib_size
= 7 + 6, /* sdma_v3_0_ring_emit_ib */
1636 .emit_ib
= sdma_v3_0_ring_emit_ib
,
1637 .emit_fence
= sdma_v3_0_ring_emit_fence
,
1638 .emit_pipeline_sync
= sdma_v3_0_ring_emit_pipeline_sync
,
1639 .emit_vm_flush
= sdma_v3_0_ring_emit_vm_flush
,
1640 .emit_hdp_flush
= sdma_v3_0_ring_emit_hdp_flush
,
1641 .emit_hdp_invalidate
= sdma_v3_0_ring_emit_hdp_invalidate
,
1642 .test_ring
= sdma_v3_0_ring_test_ring
,
1643 .test_ib
= sdma_v3_0_ring_test_ib
,
1644 .insert_nop
= sdma_v3_0_ring_insert_nop
,
1645 .pad_ib
= sdma_v3_0_ring_pad_ib
,
1648 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device
*adev
)
1652 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1653 adev
->sdma
.instance
[i
].ring
.funcs
= &sdma_v3_0_ring_funcs
;
1656 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs
= {
1657 .set
= sdma_v3_0_set_trap_irq_state
,
1658 .process
= sdma_v3_0_process_trap_irq
,
1661 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs
= {
1662 .process
= sdma_v3_0_process_illegal_inst_irq
,
1665 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device
*adev
)
1667 adev
->sdma
.trap_irq
.num_types
= AMDGPU_SDMA_IRQ_LAST
;
1668 adev
->sdma
.trap_irq
.funcs
= &sdma_v3_0_trap_irq_funcs
;
1669 adev
->sdma
.illegal_inst_irq
.funcs
= &sdma_v3_0_illegal_inst_irq_funcs
;
1673 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1675 * @ring: amdgpu_ring structure holding ring information
1676 * @src_offset: src GPU address
1677 * @dst_offset: dst GPU address
1678 * @byte_count: number of bytes to xfer
1680 * Copy GPU buffers using the DMA engine (VI).
1681 * Used by the amdgpu ttm implementation to move pages if
1682 * registered as the asic copy callback.
1684 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib
*ib
,
1685 uint64_t src_offset
,
1686 uint64_t dst_offset
,
1687 uint32_t byte_count
)
1689 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY
) |
1690 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR
);
1691 ib
->ptr
[ib
->length_dw
++] = byte_count
;
1692 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
1693 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src_offset
);
1694 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src_offset
);
1695 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1696 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1700 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1702 * @ring: amdgpu_ring structure holding ring information
1703 * @src_data: value to write to buffer
1704 * @dst_offset: dst GPU address
1705 * @byte_count: number of bytes to xfer
1707 * Fill GPU buffers using the DMA engine (VI).
1709 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib
*ib
,
1711 uint64_t dst_offset
,
1712 uint32_t byte_count
)
1714 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL
);
1715 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1716 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1717 ib
->ptr
[ib
->length_dw
++] = src_data
;
1718 ib
->ptr
[ib
->length_dw
++] = byte_count
;
1721 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs
= {
1722 .copy_max_bytes
= 0x3fffe0, /* not 0x3fffff due to HW limitation */
1724 .emit_copy_buffer
= sdma_v3_0_emit_copy_buffer
,
1726 .fill_max_bytes
= 0x3fffe0, /* not 0x3fffff due to HW limitation */
1728 .emit_fill_buffer
= sdma_v3_0_emit_fill_buffer
,
1731 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device
*adev
)
1733 if (adev
->mman
.buffer_funcs
== NULL
) {
1734 adev
->mman
.buffer_funcs
= &sdma_v3_0_buffer_funcs
;
1735 adev
->mman
.buffer_funcs_ring
= &adev
->sdma
.instance
[0].ring
;
1739 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs
= {
1740 .copy_pte_num_dw
= 7,
1741 .copy_pte
= sdma_v3_0_vm_copy_pte
,
1743 .write_pte
= sdma_v3_0_vm_write_pte
,
1745 /* not 0x3fffff due to HW limitation */
1746 .set_max_nums_pte_pde
= 0x3fffe0 >> 3,
1747 .set_pte_pde_num_dw
= 10,
1748 .set_pte_pde
= sdma_v3_0_vm_set_pte_pde
,
1751 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device
*adev
)
1755 if (adev
->vm_manager
.vm_pte_funcs
== NULL
) {
1756 adev
->vm_manager
.vm_pte_funcs
= &sdma_v3_0_vm_pte_funcs
;
1757 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1758 adev
->vm_manager
.vm_pte_rings
[i
] =
1759 &adev
->sdma
.instance
[i
].ring
;
1761 adev
->vm_manager
.vm_pte_num_rings
= adev
->sdma
.num_instances
;
1765 const struct amdgpu_ip_block_version sdma_v3_0_ip_block
=
1767 .type
= AMD_IP_BLOCK_TYPE_SDMA
,
1771 .funcs
= &sdma_v3_0_ip_funcs
,
1774 const struct amdgpu_ip_block_version sdma_v3_1_ip_block
=
1776 .type
= AMD_IP_BLOCK_TYPE_SDMA
,
1780 .funcs
= &sdma_v3_0_ip_funcs
,