2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
33 #include "gc/gc_10_1_0_offset.h"
34 #include "gc/gc_10_1_0_sh_mask.h"
35 #include "hdp/hdp_5_0_0_offset.h"
36 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
37 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
39 #include "soc15_common.h"
41 #include "navi10_sdma_pkt_open.h"
42 #include "nbio_v2_3.h"
43 #include "sdma_v5_0.h"
45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
54 #define SDMA1_REG_OFFSET 0x600
55 #define SDMA0_HYP_DEC_REG_START 0x5880
56 #define SDMA0_HYP_DEC_REG_END 0x5893
57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
59 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device
*adev
);
60 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device
*adev
);
61 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device
*adev
);
62 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device
*adev
);
64 static const struct soc15_reg_golden golden_settings_sdma_5
[] = {
65 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_CHICKEN_BITS
, 0xffbf1f0f, 0x03ab0107),
66 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
67 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
68 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
69 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
70 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
71 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
72 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
73 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
74 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
75 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
76 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_UTCL1_PAGE
, 0x00ffffff, 0x000c5c00),
77 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_CHICKEN_BITS
, 0xffbf1f0f, 0x03ab0107),
78 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
79 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
80 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
81 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
82 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
83 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
84 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
85 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
86 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
87 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
88 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_UTCL1_PAGE
, 0x00ffffff, 0x000c5c00)
91 static const struct soc15_reg_golden golden_settings_sdma_5_sriov
[] = {
92 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
93 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
94 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
95 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
96 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
97 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
98 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
99 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
100 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
101 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
102 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
103 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
104 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
105 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
106 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
107 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
108 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
109 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
110 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
111 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
114 static const struct soc15_reg_golden golden_settings_sdma_nv10
[] = {
115 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL
, 0x0000fff0, 0x00403000),
116 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL
, 0x0000fff0, 0x00403000),
119 static const struct soc15_reg_golden golden_settings_sdma_nv14
[] = {
120 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
121 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
124 static const struct soc15_reg_golden golden_settings_sdma_nv12
[] = {
125 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
126 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
129 static u32
sdma_v5_0_get_reg_offset(struct amdgpu_device
*adev
, u32 instance
, u32 internal_offset
)
133 if (internal_offset
>= SDMA0_HYP_DEC_REG_START
&&
134 internal_offset
<= SDMA0_HYP_DEC_REG_END
) {
135 base
= adev
->reg_offset
[GC_HWIP
][0][1];
137 internal_offset
+= SDMA1_HYP_DEC_REG_OFFSET
;
139 base
= adev
->reg_offset
[GC_HWIP
][0][0];
141 internal_offset
+= SDMA1_REG_OFFSET
;
144 return base
+ internal_offset
;
147 static void sdma_v5_0_init_golden_registers(struct amdgpu_device
*adev
)
149 switch (adev
->asic_type
) {
151 soc15_program_register_sequence(adev
,
152 golden_settings_sdma_5
,
153 (const u32
)ARRAY_SIZE(golden_settings_sdma_5
));
154 soc15_program_register_sequence(adev
,
155 golden_settings_sdma_nv10
,
156 (const u32
)ARRAY_SIZE(golden_settings_sdma_nv10
));
159 soc15_program_register_sequence(adev
,
160 golden_settings_sdma_5
,
161 (const u32
)ARRAY_SIZE(golden_settings_sdma_5
));
162 soc15_program_register_sequence(adev
,
163 golden_settings_sdma_nv14
,
164 (const u32
)ARRAY_SIZE(golden_settings_sdma_nv14
));
167 if (amdgpu_sriov_vf(adev
))
168 soc15_program_register_sequence(adev
,
169 golden_settings_sdma_5_sriov
,
170 (const u32
)ARRAY_SIZE(golden_settings_sdma_5_sriov
));
172 soc15_program_register_sequence(adev
,
173 golden_settings_sdma_5
,
174 (const u32
)ARRAY_SIZE(golden_settings_sdma_5
));
175 soc15_program_register_sequence(adev
,
176 golden_settings_sdma_nv12
,
177 (const u32
)ARRAY_SIZE(golden_settings_sdma_nv12
));
185 * sdma_v5_0_init_microcode - load ucode images from disk
187 * @adev: amdgpu_device pointer
189 * Use the firmware interface to load the ucode images into
190 * the driver (not loaded into hw).
191 * Returns 0 on success, error on failure.
194 // emulation only, won't work on real chip
195 // navi10 real chip need to use PSP to load firmware
196 static int sdma_v5_0_init_microcode(struct amdgpu_device
*adev
)
198 const char *chip_name
;
201 struct amdgpu_firmware_info
*info
= NULL
;
202 const struct common_firmware_header
*header
= NULL
;
203 const struct sdma_firmware_header_v1_0
*hdr
;
207 switch (adev
->asic_type
) {
209 chip_name
= "navi10";
212 chip_name
= "navi14";
215 chip_name
= "navi12";
221 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
223 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_sdma.bin", chip_name
);
225 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_sdma1.bin", chip_name
);
226 err
= request_firmware(&adev
->sdma
.instance
[i
].fw
, fw_name
, adev
->dev
);
229 err
= amdgpu_ucode_validate(adev
->sdma
.instance
[i
].fw
);
232 hdr
= (const struct sdma_firmware_header_v1_0
*)adev
->sdma
.instance
[i
].fw
->data
;
233 adev
->sdma
.instance
[i
].fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
234 adev
->sdma
.instance
[i
].feature_version
= le32_to_cpu(hdr
->ucode_feature_version
);
235 if (adev
->sdma
.instance
[i
].feature_version
>= 20)
236 adev
->sdma
.instance
[i
].burst_nop
= true;
237 DRM_DEBUG("psp_load == '%s'\n",
238 adev
->firmware
.load_type
== AMDGPU_FW_LOAD_PSP
? "true" : "false");
240 if (adev
->firmware
.load_type
== AMDGPU_FW_LOAD_PSP
) {
241 info
= &adev
->firmware
.ucode
[AMDGPU_UCODE_ID_SDMA0
+ i
];
242 info
->ucode_id
= AMDGPU_UCODE_ID_SDMA0
+ i
;
243 info
->fw
= adev
->sdma
.instance
[i
].fw
;
244 header
= (const struct common_firmware_header
*)info
->fw
->data
;
245 adev
->firmware
.fw_size
+=
246 ALIGN(le32_to_cpu(header
->ucode_size_bytes
), PAGE_SIZE
);
251 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name
);
252 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
253 release_firmware(adev
->sdma
.instance
[i
].fw
);
254 adev
->sdma
.instance
[i
].fw
= NULL
;
260 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring
*ring
)
264 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE
));
265 amdgpu_ring_write(ring
, lower_32_bits(ring
->cond_exe_gpu_addr
));
266 amdgpu_ring_write(ring
, upper_32_bits(ring
->cond_exe_gpu_addr
));
267 amdgpu_ring_write(ring
, 1);
268 ret
= ring
->wptr
& ring
->buf_mask
;/* this is the offset we need patch later */
269 amdgpu_ring_write(ring
, 0x55aa55aa);/* insert dummy here and patch it later */
274 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring
*ring
,
279 BUG_ON(offset
> ring
->buf_mask
);
280 BUG_ON(ring
->ring
[offset
] != 0x55aa55aa);
282 cur
= (ring
->wptr
- 1) & ring
->buf_mask
;
284 ring
->ring
[offset
] = cur
- offset
;
286 ring
->ring
[offset
] = (ring
->buf_mask
+ 1) - offset
+ cur
;
290 * sdma_v5_0_ring_get_rptr - get the current read pointer
292 * @ring: amdgpu ring pointer
294 * Get the current rptr from the hardware (NAVI10+).
296 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring
*ring
)
300 /* XXX check if swapping is necessary on BE */
301 rptr
= ((u64
*)&ring
->adev
->wb
.wb
[ring
->rptr_offs
]);
303 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr
);
304 return ((*rptr
) >> 2);
308 * sdma_v5_0_ring_get_wptr - get the current write pointer
310 * @ring: amdgpu ring pointer
312 * Get the current wptr from the hardware (NAVI10+).
314 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring
*ring
)
316 struct amdgpu_device
*adev
= ring
->adev
;
318 uint64_t local_wptr
= 0;
320 if (ring
->use_doorbell
) {
321 /* XXX check if swapping is necessary on BE */
322 wptr
= ((u64
*)&adev
->wb
.wb
[ring
->wptr_offs
]);
323 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr
);
324 *wptr
= (*wptr
) >> 2;
325 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr
);
330 lowbit
= RREG32(sdma_v5_0_get_reg_offset(adev
, ring
->me
, mmSDMA0_GFX_RB_WPTR
)) >> 2;
331 highbit
= RREG32(sdma_v5_0_get_reg_offset(adev
, ring
->me
, mmSDMA0_GFX_RB_WPTR_HI
)) >> 2;
333 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
334 ring
->me
, highbit
, lowbit
);
336 *wptr
= (*wptr
) << 32;
344 * sdma_v5_0_ring_set_wptr - commit the write pointer
346 * @ring: amdgpu ring pointer
348 * Write the wptr back to the hardware (NAVI10+).
350 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring
*ring
)
352 struct amdgpu_device
*adev
= ring
->adev
;
354 DRM_DEBUG("Setting write pointer\n");
355 if (ring
->use_doorbell
) {
356 DRM_DEBUG("Using doorbell -- "
357 "wptr_offs == 0x%08x "
358 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
359 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
361 lower_32_bits(ring
->wptr
<< 2),
362 upper_32_bits(ring
->wptr
<< 2));
363 /* XXX check if swapping is necessary on BE */
364 adev
->wb
.wb
[ring
->wptr_offs
] = lower_32_bits(ring
->wptr
<< 2);
365 adev
->wb
.wb
[ring
->wptr_offs
+ 1] = upper_32_bits(ring
->wptr
<< 2);
366 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
367 ring
->doorbell_index
, ring
->wptr
<< 2);
368 WDOORBELL64(ring
->doorbell_index
, ring
->wptr
<< 2);
370 DRM_DEBUG("Not using doorbell -- "
371 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
372 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
374 lower_32_bits(ring
->wptr
<< 2),
376 upper_32_bits(ring
->wptr
<< 2));
377 WREG32(sdma_v5_0_get_reg_offset(adev
, ring
->me
, mmSDMA0_GFX_RB_WPTR
),
378 lower_32_bits(ring
->wptr
<< 2));
379 WREG32(sdma_v5_0_get_reg_offset(adev
, ring
->me
, mmSDMA0_GFX_RB_WPTR_HI
),
380 upper_32_bits(ring
->wptr
<< 2));
384 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring
*ring
, uint32_t count
)
386 struct amdgpu_sdma_instance
*sdma
= amdgpu_sdma_get_instance_from_ring(ring
);
389 for (i
= 0; i
< count
; i
++)
390 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
391 amdgpu_ring_write(ring
, ring
->funcs
->nop
|
392 SDMA_PKT_NOP_HEADER_COUNT(count
- 1));
394 amdgpu_ring_write(ring
, ring
->funcs
->nop
);
398 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
400 * @ring: amdgpu ring pointer
401 * @ib: IB object to schedule
403 * Schedule an IB in the DMA ring (NAVI10).
405 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring
*ring
,
406 struct amdgpu_job
*job
,
407 struct amdgpu_ib
*ib
,
410 unsigned vmid
= AMDGPU_JOB_GET_VMID(job
);
411 uint64_t csa_mc_addr
= amdgpu_sdma_get_csa_mc_addr(ring
, vmid
);
413 /* Invalidate L2, because if we don't do it, we might get stale cache
414 * lines from previous IBs.
416 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ
));
417 amdgpu_ring_write(ring
, 0);
418 amdgpu_ring_write(ring
, (SDMA_GCR_GL2_INV
|
421 SDMA_GCR_GLM_WB
) << 16);
422 amdgpu_ring_write(ring
, 0xffffff80);
423 amdgpu_ring_write(ring
, 0xffff);
425 /* An IB packet must end on a 8 DW boundary--the next dword
426 * must be on a 8-dword boundary. Our IB packet below is 6
427 * dwords long, thus add x number of NOPs, such that, in
428 * modular arithmetic,
429 * wptr + 6 + x = 8k, k >= 0, which in C is,
430 * (wptr + 6 + x) % 8 = 0.
431 * The expression below, is a solution of x.
433 sdma_v5_0_ring_insert_nop(ring
, (2 - lower_32_bits(ring
->wptr
)) & 7);
435 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT
) |
436 SDMA_PKT_INDIRECT_HEADER_VMID(vmid
& 0xf));
437 /* base must be 32 byte aligned */
438 amdgpu_ring_write(ring
, lower_32_bits(ib
->gpu_addr
) & 0xffffffe0);
439 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
));
440 amdgpu_ring_write(ring
, ib
->length_dw
);
441 amdgpu_ring_write(ring
, lower_32_bits(csa_mc_addr
));
442 amdgpu_ring_write(ring
, upper_32_bits(csa_mc_addr
));
446 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
448 * @ring: amdgpu ring pointer
450 * Emit an hdp flush packet on the requested DMA ring.
452 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring
*ring
)
454 struct amdgpu_device
*adev
= ring
->adev
;
455 u32 ref_and_mask
= 0;
456 const struct nbio_hdp_flush_reg
*nbio_hf_reg
= adev
->nbio
.hdp_flush_reg
;
459 ref_and_mask
= nbio_hf_reg
->ref_and_mask_sdma0
;
461 ref_and_mask
= nbio_hf_reg
->ref_and_mask_sdma1
;
463 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM
) |
464 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
465 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
466 amdgpu_ring_write(ring
, (adev
->nbio
.funcs
->get_hdp_flush_done_offset(adev
)) << 2);
467 amdgpu_ring_write(ring
, (adev
->nbio
.funcs
->get_hdp_flush_req_offset(adev
)) << 2);
468 amdgpu_ring_write(ring
, ref_and_mask
); /* reference */
469 amdgpu_ring_write(ring
, ref_and_mask
); /* mask */
470 amdgpu_ring_write(ring
, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
471 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
475 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
477 * @ring: amdgpu ring pointer
478 * @fence: amdgpu fence object
480 * Add a DMA fence packet to the ring to write
481 * the fence seq number and DMA trap packet to generate
482 * an interrupt if needed (NAVI10).
484 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
, u64 seq
,
487 struct amdgpu_device
*adev
= ring
->adev
;
488 bool write64bit
= flags
& AMDGPU_FENCE_FLAG_64BIT
;
489 /* write the fence */
490 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE
) |
491 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
492 /* zero in first two bits */
494 amdgpu_ring_write(ring
, lower_32_bits(addr
));
495 amdgpu_ring_write(ring
, upper_32_bits(addr
));
496 amdgpu_ring_write(ring
, lower_32_bits(seq
));
498 /* optionally write high bits as well */
501 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE
) |
502 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
503 /* zero in first two bits */
505 amdgpu_ring_write(ring
, lower_32_bits(addr
));
506 amdgpu_ring_write(ring
, upper_32_bits(addr
));
507 amdgpu_ring_write(ring
, upper_32_bits(seq
));
510 /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
511 if ((flags
& AMDGPU_FENCE_FLAG_INT
) && adev
->pdev
->device
!= 0x50) {
512 /* generate an interrupt */
513 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP
));
514 amdgpu_ring_write(ring
, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
520 * sdma_v5_0_gfx_stop - stop the gfx async dma engines
522 * @adev: amdgpu_device pointer
524 * Stop the gfx async dma ring buffers (NAVI10).
526 static void sdma_v5_0_gfx_stop(struct amdgpu_device
*adev
)
528 struct amdgpu_ring
*sdma0
= &adev
->sdma
.instance
[0].ring
;
529 struct amdgpu_ring
*sdma1
= &adev
->sdma
.instance
[1].ring
;
530 u32 rb_cntl
, ib_cntl
;
533 if ((adev
->mman
.buffer_funcs_ring
== sdma0
) ||
534 (adev
->mman
.buffer_funcs_ring
== sdma1
))
535 amdgpu_ttm_set_buffer_funcs_status(adev
, false);
537 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
538 rb_cntl
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_CNTL
));
539 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_ENABLE
, 0);
540 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_CNTL
), rb_cntl
);
541 ib_cntl
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_IB_CNTL
));
542 ib_cntl
= REG_SET_FIELD(ib_cntl
, SDMA0_GFX_IB_CNTL
, IB_ENABLE
, 0);
543 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_IB_CNTL
), ib_cntl
);
548 * sdma_v5_0_rlc_stop - stop the compute async dma engines
550 * @adev: amdgpu_device pointer
552 * Stop the compute async dma queues (NAVI10).
554 static void sdma_v5_0_rlc_stop(struct amdgpu_device
*adev
)
560 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
562 * @adev: amdgpu_device pointer
563 * @enable: enable/disable the DMA MEs context switch.
565 * Halt or unhalt the async dma engines context switch (NAVI10).
567 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device
*adev
, bool enable
)
569 u32 f32_cntl
= 0, phase_quantum
= 0;
572 if (amdgpu_sdma_phase_quantum
) {
573 unsigned value
= amdgpu_sdma_phase_quantum
;
576 while (value
> (SDMA0_PHASE0_QUANTUM__VALUE_MASK
>>
577 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT
)) {
578 value
= (value
+ 1) >> 1;
581 if (unit
> (SDMA0_PHASE0_QUANTUM__UNIT_MASK
>>
582 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT
)) {
583 value
= (SDMA0_PHASE0_QUANTUM__VALUE_MASK
>>
584 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT
);
585 unit
= (SDMA0_PHASE0_QUANTUM__UNIT_MASK
>>
586 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT
);
588 "clamping sdma_phase_quantum to %uK clock cycles\n",
592 value
<< SDMA0_PHASE0_QUANTUM__VALUE__SHIFT
|
593 unit
<< SDMA0_PHASE0_QUANTUM__UNIT__SHIFT
;
596 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
597 if (!amdgpu_sriov_vf(adev
)) {
598 f32_cntl
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_CNTL
));
599 f32_cntl
= REG_SET_FIELD(f32_cntl
, SDMA0_CNTL
,
600 AUTO_CTXSW_ENABLE
, enable
? 1 : 0);
603 if (enable
&& amdgpu_sdma_phase_quantum
) {
604 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_PHASE0_QUANTUM
),
606 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_PHASE1_QUANTUM
),
608 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_PHASE2_QUANTUM
),
611 if (!amdgpu_sriov_vf(adev
))
612 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_CNTL
), f32_cntl
);
618 * sdma_v5_0_enable - stop the async dma engines
620 * @adev: amdgpu_device pointer
621 * @enable: enable/disable the DMA MEs.
623 * Halt or unhalt the async dma engines (NAVI10).
625 static void sdma_v5_0_enable(struct amdgpu_device
*adev
, bool enable
)
630 if (enable
== false) {
631 sdma_v5_0_gfx_stop(adev
);
632 sdma_v5_0_rlc_stop(adev
);
635 if (amdgpu_sriov_vf(adev
))
638 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
639 f32_cntl
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_F32_CNTL
));
640 f32_cntl
= REG_SET_FIELD(f32_cntl
, SDMA0_F32_CNTL
, HALT
, enable
? 0 : 1);
641 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_F32_CNTL
), f32_cntl
);
646 * sdma_v5_0_gfx_resume - setup and start the async dma engines
648 * @adev: amdgpu_device pointer
650 * Set up the gfx DMA ring buffers and enable them (NAVI10).
651 * Returns 0 for success, error for failure.
653 static int sdma_v5_0_gfx_resume(struct amdgpu_device
*adev
)
655 struct amdgpu_ring
*ring
;
656 u32 rb_cntl
, ib_cntl
;
666 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
667 ring
= &adev
->sdma
.instance
[i
].ring
;
668 wb_offset
= (ring
->rptr_offs
* 4);
670 if (!amdgpu_sriov_vf(adev
))
671 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
), 0);
673 /* Set ring buffer size in dwords */
674 rb_bufsz
= order_base_2(ring
->ring_size
/ 4);
675 rb_cntl
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_CNTL
));
676 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_SIZE
, rb_bufsz
);
678 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_SWAP_ENABLE
, 1);
679 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
,
680 RPTR_WRITEBACK_SWAP_ENABLE
, 1);
682 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_CNTL
), rb_cntl
);
684 /* Initialize the ring buffer's read and write pointers */
685 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_RPTR
), 0);
686 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_RPTR_HI
), 0);
687 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_WPTR
), 0);
688 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_WPTR_HI
), 0);
690 /* setup the wptr shadow polling */
691 wptr_gpu_addr
= adev
->wb
.gpu_addr
+ (ring
->wptr_offs
* 4);
692 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO
),
693 lower_32_bits(wptr_gpu_addr
));
694 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI
),
695 upper_32_bits(wptr_gpu_addr
));
696 wptr_poll_cntl
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
,
697 mmSDMA0_GFX_RB_WPTR_POLL_CNTL
));
698 wptr_poll_cntl
= REG_SET_FIELD(wptr_poll_cntl
,
699 SDMA0_GFX_RB_WPTR_POLL_CNTL
,
701 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_WPTR_POLL_CNTL
),
704 /* set the wb address whether it's enabled or not */
705 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_RPTR_ADDR_HI
),
706 upper_32_bits(adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFF);
707 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_RPTR_ADDR_LO
),
708 lower_32_bits(adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFC);
710 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RPTR_WRITEBACK_ENABLE
, 1);
712 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_BASE
), ring
->gpu_addr
>> 8);
713 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_BASE_HI
), ring
->gpu_addr
>> 40);
717 /* before programing wptr to a less value, need set minor_ptr_update first */
718 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_MINOR_PTR_UPDATE
), 1);
720 if (!amdgpu_sriov_vf(adev
)) { /* only bare-metal use register write for wptr */
721 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_WPTR
), lower_32_bits(ring
->wptr
) << 2);
722 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_WPTR_HI
), upper_32_bits(ring
->wptr
) << 2);
725 doorbell
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_DOORBELL
));
726 doorbell_offset
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_DOORBELL_OFFSET
));
728 if (ring
->use_doorbell
) {
729 doorbell
= REG_SET_FIELD(doorbell
, SDMA0_GFX_DOORBELL
, ENABLE
, 1);
730 doorbell_offset
= REG_SET_FIELD(doorbell_offset
, SDMA0_GFX_DOORBELL_OFFSET
,
731 OFFSET
, ring
->doorbell_index
);
733 doorbell
= REG_SET_FIELD(doorbell
, SDMA0_GFX_DOORBELL
, ENABLE
, 0);
735 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_DOORBELL
), doorbell
);
736 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_DOORBELL_OFFSET
), doorbell_offset
);
738 adev
->nbio
.funcs
->sdma_doorbell_range(adev
, i
, ring
->use_doorbell
,
739 ring
->doorbell_index
, 20);
741 if (amdgpu_sriov_vf(adev
))
742 sdma_v5_0_ring_set_wptr(ring
);
744 /* set minor_ptr_update to 0 after wptr programed */
745 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_MINOR_PTR_UPDATE
), 0);
747 if (!amdgpu_sriov_vf(adev
)) {
748 /* set utc l1 enable flag always to 1 */
749 temp
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_CNTL
));
750 temp
= REG_SET_FIELD(temp
, SDMA0_CNTL
, UTC_L1_ENABLE
, 1);
753 temp
= REG_SET_FIELD(temp
, SDMA0_CNTL
, MIDCMD_PREEMPT_ENABLE
, 1);
754 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_CNTL
), temp
);
756 /* Set up RESP_MODE to non-copy addresses */
757 temp
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_UTCL1_CNTL
));
758 temp
= REG_SET_FIELD(temp
, SDMA0_UTCL1_CNTL
, RESP_MODE
, 3);
759 temp
= REG_SET_FIELD(temp
, SDMA0_UTCL1_CNTL
, REDO_DELAY
, 9);
760 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_UTCL1_CNTL
), temp
);
762 /* program default cache read and write policy */
763 temp
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_UTCL1_PAGE
));
764 /* clean read policy and write policy bits */
766 temp
|= ((CACHE_READ_POLICY_L2__DEFAULT
<< 12) | (CACHE_WRITE_POLICY_L2__DEFAULT
<< 14));
767 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_UTCL1_PAGE
), temp
);
770 if (!amdgpu_sriov_vf(adev
)) {
772 temp
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_F32_CNTL
));
773 temp
= REG_SET_FIELD(temp
, SDMA0_F32_CNTL
, HALT
, 0);
774 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_F32_CNTL
), temp
);
778 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_ENABLE
, 1);
779 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_CNTL
), rb_cntl
);
781 ib_cntl
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_IB_CNTL
));
782 ib_cntl
= REG_SET_FIELD(ib_cntl
, SDMA0_GFX_IB_CNTL
, IB_ENABLE
, 1);
784 ib_cntl
= REG_SET_FIELD(ib_cntl
, SDMA0_GFX_IB_CNTL
, IB_SWAP_ENABLE
, 1);
787 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_IB_CNTL
), ib_cntl
);
789 ring
->sched
.ready
= true;
791 if (amdgpu_sriov_vf(adev
)) { /* bare-metal sequence doesn't need below to lines */
792 sdma_v5_0_ctx_switch_enable(adev
, true);
793 sdma_v5_0_enable(adev
, true);
796 r
= amdgpu_ring_test_helper(ring
);
800 if (adev
->mman
.buffer_funcs_ring
== ring
)
801 amdgpu_ttm_set_buffer_funcs_status(adev
, true);
808 * sdma_v5_0_rlc_resume - setup and start the async dma engines
810 * @adev: amdgpu_device pointer
812 * Set up the compute DMA queues and enable them (NAVI10).
813 * Returns 0 for success, error for failure.
815 static int sdma_v5_0_rlc_resume(struct amdgpu_device
*adev
)
821 * sdma_v5_0_load_microcode - load the sDMA ME ucode
823 * @adev: amdgpu_device pointer
825 * Loads the sDMA0/1 ucode.
826 * Returns 0 for success, -EINVAL if the ucode is not available.
828 static int sdma_v5_0_load_microcode(struct amdgpu_device
*adev
)
830 const struct sdma_firmware_header_v1_0
*hdr
;
831 const __le32
*fw_data
;
836 sdma_v5_0_enable(adev
, false);
838 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
839 if (!adev
->sdma
.instance
[i
].fw
)
842 hdr
= (const struct sdma_firmware_header_v1_0
*)adev
->sdma
.instance
[i
].fw
->data
;
843 amdgpu_ucode_print_sdma_hdr(&hdr
->header
);
844 fw_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
846 fw_data
= (const __le32
*)
847 (adev
->sdma
.instance
[i
].fw
->data
+
848 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
850 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_UCODE_ADDR
), 0);
852 for (j
= 0; j
< fw_size
; j
++) {
853 if (amdgpu_emu_mode
== 1 && j
% 500 == 0)
855 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_UCODE_DATA
), le32_to_cpup(fw_data
++));
858 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_UCODE_ADDR
), adev
->sdma
.instance
[i
].fw_version
);
865 * sdma_v5_0_start - setup and start the async dma engines
867 * @adev: amdgpu_device pointer
869 * Set up the DMA engines and enable them (NAVI10).
870 * Returns 0 for success, error for failure.
872 static int sdma_v5_0_start(struct amdgpu_device
*adev
)
876 if (amdgpu_sriov_vf(adev
)) {
877 sdma_v5_0_ctx_switch_enable(adev
, false);
878 sdma_v5_0_enable(adev
, false);
880 /* set RB registers */
881 r
= sdma_v5_0_gfx_resume(adev
);
885 if (adev
->firmware
.load_type
== AMDGPU_FW_LOAD_DIRECT
) {
886 r
= sdma_v5_0_load_microcode(adev
);
890 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
891 if (amdgpu_emu_mode
== 1 && adev
->pdev
->device
== 0x4d)
896 sdma_v5_0_enable(adev
, true);
897 /* enable sdma ring preemption */
898 sdma_v5_0_ctx_switch_enable(adev
, true);
900 /* start the gfx rings and rlc compute queues */
901 r
= sdma_v5_0_gfx_resume(adev
);
904 r
= sdma_v5_0_rlc_resume(adev
);
910 * sdma_v5_0_ring_test_ring - simple async dma engine test
912 * @ring: amdgpu_ring structure holding ring information
914 * Test the DMA engine by writing using it to write an
915 * value to memory. (NAVI10).
916 * Returns 0 for success, error for failure.
918 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring
*ring
)
920 struct amdgpu_device
*adev
= ring
->adev
;
927 r
= amdgpu_device_wb_get(adev
, &index
);
929 dev_err(adev
->dev
, "(%d) failed to allocate wb slot\n", r
);
933 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
935 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
937 r
= amdgpu_ring_alloc(ring
, 5);
939 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring
->idx
, r
);
940 amdgpu_device_wb_free(adev
, index
);
944 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
945 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR
));
946 amdgpu_ring_write(ring
, lower_32_bits(gpu_addr
));
947 amdgpu_ring_write(ring
, upper_32_bits(gpu_addr
));
948 amdgpu_ring_write(ring
, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
949 amdgpu_ring_write(ring
, 0xDEADBEEF);
950 amdgpu_ring_commit(ring
);
952 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
953 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
954 if (tmp
== 0xDEADBEEF)
956 if (amdgpu_emu_mode
== 1)
962 if (i
>= adev
->usec_timeout
)
965 amdgpu_device_wb_free(adev
, index
);
971 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
973 * @ring: amdgpu_ring structure holding ring information
975 * Test a simple IB in the DMA ring (NAVI10).
976 * Returns 0 on success, error on failure.
978 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring
*ring
, long timeout
)
980 struct amdgpu_device
*adev
= ring
->adev
;
982 struct dma_fence
*f
= NULL
;
988 r
= amdgpu_device_wb_get(adev
, &index
);
990 dev_err(adev
->dev
, "(%ld) failed to allocate wb slot\n", r
);
994 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
996 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
997 memset(&ib
, 0, sizeof(ib
));
998 r
= amdgpu_ib_get(adev
, NULL
, 256,
999 AMDGPU_IB_POOL_DIRECT
, &ib
);
1001 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r
);
1005 ib
.ptr
[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
1006 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR
);
1007 ib
.ptr
[1] = lower_32_bits(gpu_addr
);
1008 ib
.ptr
[2] = upper_32_bits(gpu_addr
);
1009 ib
.ptr
[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1010 ib
.ptr
[4] = 0xDEADBEEF;
1011 ib
.ptr
[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
);
1012 ib
.ptr
[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
);
1013 ib
.ptr
[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
);
1016 r
= amdgpu_ib_schedule(ring
, 1, &ib
, NULL
, &f
);
1020 r
= dma_fence_wait_timeout(f
, false, timeout
);
1022 DRM_ERROR("amdgpu: IB test timed out\n");
1026 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r
);
1029 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
1030 if (tmp
== 0xDEADBEEF)
1036 amdgpu_ib_free(adev
, &ib
, NULL
);
1039 amdgpu_device_wb_free(adev
, index
);
1045 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1047 * @ib: indirect buffer to fill with commands
1048 * @pe: addr of the page entry
1049 * @src: src addr to copy from
1050 * @count: number of page entries to update
1052 * Update PTEs by copying them from the GART using sDMA (NAVI10).
1054 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib
*ib
,
1055 uint64_t pe
, uint64_t src
,
1058 unsigned bytes
= count
* 8;
1060 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY
) |
1061 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR
);
1062 ib
->ptr
[ib
->length_dw
++] = bytes
- 1;
1063 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
1064 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src
);
1065 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src
);
1066 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
);
1067 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
1072 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1074 * @ib: indirect buffer to fill with commands
1075 * @pe: addr of the page entry
1076 * @addr: dst addr to write into pe
1077 * @count: number of page entries to update
1078 * @incr: increase next addr by incr bytes
1079 * @flags: access flags
1081 * Update PTEs by writing them manually using sDMA (NAVI10).
1083 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib
*ib
, uint64_t pe
,
1084 uint64_t value
, unsigned count
,
1087 unsigned ndw
= count
* 2;
1089 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
1090 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR
);
1091 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
);
1092 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
1093 ib
->ptr
[ib
->length_dw
++] = ndw
- 1;
1094 for (; ndw
> 0; ndw
-= 2) {
1095 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(value
);
1096 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
1102 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1104 * @ib: indirect buffer to fill with commands
1105 * @pe: addr of the page entry
1106 * @addr: dst addr to write into pe
1107 * @count: number of page entries to update
1108 * @incr: increase next addr by incr bytes
1109 * @flags: access flags
1111 * Update the page tables using sDMA (NAVI10).
1113 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib
*ib
,
1115 uint64_t addr
, unsigned count
,
1116 uint32_t incr
, uint64_t flags
)
1118 /* for physically contiguous pages (vram) */
1119 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE
);
1120 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
); /* dst addr */
1121 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
1122 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(flags
); /* mask */
1123 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(flags
);
1124 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(addr
); /* value */
1125 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(addr
);
1126 ib
->ptr
[ib
->length_dw
++] = incr
; /* increment size */
1127 ib
->ptr
[ib
->length_dw
++] = 0;
1128 ib
->ptr
[ib
->length_dw
++] = count
- 1; /* number of entries */
1132 * sdma_v5_0_ring_pad_ib - pad the IB
1133 * @ib: indirect buffer to fill with padding
1135 * Pad the IB with NOPs to a boundary multiple of 8.
1137 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
)
1139 struct amdgpu_sdma_instance
*sdma
= amdgpu_sdma_get_instance_from_ring(ring
);
1143 pad_count
= (-ib
->length_dw
) & 0x7;
1144 for (i
= 0; i
< pad_count
; i
++)
1145 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
1146 ib
->ptr
[ib
->length_dw
++] =
1147 SDMA_PKT_HEADER_OP(SDMA_OP_NOP
) |
1148 SDMA_PKT_NOP_HEADER_COUNT(pad_count
- 1);
1150 ib
->ptr
[ib
->length_dw
++] =
1151 SDMA_PKT_HEADER_OP(SDMA_OP_NOP
);
1156 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1158 * @ring: amdgpu_ring pointer
1160 * Make sure all previous operations are completed (CIK).
1162 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring
*ring
)
1164 uint32_t seq
= ring
->fence_drv
.sync_seq
;
1165 uint64_t addr
= ring
->fence_drv
.gpu_addr
;
1168 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM
) |
1169 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1170 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1171 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1172 amdgpu_ring_write(ring
, addr
& 0xfffffffc);
1173 amdgpu_ring_write(ring
, upper_32_bits(addr
) & 0xffffffff);
1174 amdgpu_ring_write(ring
, seq
); /* reference */
1175 amdgpu_ring_write(ring
, 0xffffffff); /* mask */
1176 amdgpu_ring_write(ring
, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1177 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1182 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1184 * @ring: amdgpu_ring pointer
1185 * @vm: amdgpu_vm pointer
1187 * Update the page table base and flush the VM TLB
1188 * using sDMA (NAVI10).
1190 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring
*ring
,
1191 unsigned vmid
, uint64_t pd_addr
)
1193 amdgpu_gmc_emit_flush_gpu_tlb(ring
, vmid
, pd_addr
);
1196 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring
*ring
,
1197 uint32_t reg
, uint32_t val
)
1199 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE
) |
1200 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1201 amdgpu_ring_write(ring
, reg
);
1202 amdgpu_ring_write(ring
, val
);
1205 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring
*ring
, uint32_t reg
,
1206 uint32_t val
, uint32_t mask
)
1208 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM
) |
1209 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1210 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1211 amdgpu_ring_write(ring
, reg
<< 2);
1212 amdgpu_ring_write(ring
, 0);
1213 amdgpu_ring_write(ring
, val
); /* reference */
1214 amdgpu_ring_write(ring
, mask
); /* mask */
1215 amdgpu_ring_write(ring
, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1216 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1219 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring
*ring
,
1220 uint32_t reg0
, uint32_t reg1
,
1221 uint32_t ref
, uint32_t mask
)
1223 amdgpu_ring_emit_wreg(ring
, reg0
, ref
);
1224 /* wait for a cycle to reset vm_inv_eng*_ack */
1225 amdgpu_ring_emit_reg_wait(ring
, reg0
, 0, 0);
1226 amdgpu_ring_emit_reg_wait(ring
, reg1
, mask
, mask
);
1229 static int sdma_v5_0_early_init(void *handle
)
1231 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1233 adev
->sdma
.num_instances
= 2;
1235 sdma_v5_0_set_ring_funcs(adev
);
1236 sdma_v5_0_set_buffer_funcs(adev
);
1237 sdma_v5_0_set_vm_pte_funcs(adev
);
1238 sdma_v5_0_set_irq_funcs(adev
);
1244 static int sdma_v5_0_sw_init(void *handle
)
1246 struct amdgpu_ring
*ring
;
1248 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1250 /* SDMA trap event */
1251 r
= amdgpu_irq_add_id(adev
, SOC15_IH_CLIENTID_SDMA0
,
1252 SDMA0_5_0__SRCID__SDMA_TRAP
,
1253 &adev
->sdma
.trap_irq
);
1257 /* SDMA trap event */
1258 r
= amdgpu_irq_add_id(adev
, SOC15_IH_CLIENTID_SDMA1
,
1259 SDMA1_5_0__SRCID__SDMA_TRAP
,
1260 &adev
->sdma
.trap_irq
);
1264 r
= sdma_v5_0_init_microcode(adev
);
1266 DRM_ERROR("Failed to load sdma firmware!\n");
1270 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1271 ring
= &adev
->sdma
.instance
[i
].ring
;
1272 ring
->ring_obj
= NULL
;
1273 ring
->use_doorbell
= true;
1275 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i
,
1276 ring
->use_doorbell
?"true":"false");
1278 ring
->doorbell_index
= (i
== 0) ?
1279 (adev
->doorbell_index
.sdma_engine
[0] << 1) //get DWORD offset
1280 : (adev
->doorbell_index
.sdma_engine
[1] << 1); // get DWORD offset
1282 sprintf(ring
->name
, "sdma%d", i
);
1283 r
= amdgpu_ring_init(adev
, ring
, 1024,
1284 &adev
->sdma
.trap_irq
,
1286 AMDGPU_SDMA_IRQ_INSTANCE0
:
1287 AMDGPU_SDMA_IRQ_INSTANCE1
,
1288 AMDGPU_RING_PRIO_DEFAULT
);
1296 static int sdma_v5_0_sw_fini(void *handle
)
1298 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1301 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1302 amdgpu_ring_fini(&adev
->sdma
.instance
[i
].ring
);
1307 static int sdma_v5_0_hw_init(void *handle
)
1310 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1312 sdma_v5_0_init_golden_registers(adev
);
1314 r
= sdma_v5_0_start(adev
);
1319 static int sdma_v5_0_hw_fini(void *handle
)
1321 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1323 if (amdgpu_sriov_vf(adev
))
1326 sdma_v5_0_ctx_switch_enable(adev
, false);
1327 sdma_v5_0_enable(adev
, false);
1332 static int sdma_v5_0_suspend(void *handle
)
1334 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1336 return sdma_v5_0_hw_fini(adev
);
1339 static int sdma_v5_0_resume(void *handle
)
1341 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1343 return sdma_v5_0_hw_init(adev
);
1346 static bool sdma_v5_0_is_idle(void *handle
)
1348 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1351 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1352 u32 tmp
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_STATUS_REG
));
1354 if (!(tmp
& SDMA0_STATUS_REG__IDLE_MASK
))
1361 static int sdma_v5_0_wait_for_idle(void *handle
)
1365 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1367 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1368 sdma0
= RREG32(sdma_v5_0_get_reg_offset(adev
, 0, mmSDMA0_STATUS_REG
));
1369 sdma1
= RREG32(sdma_v5_0_get_reg_offset(adev
, 1, mmSDMA0_STATUS_REG
));
1371 if (sdma0
& sdma1
& SDMA0_STATUS_REG__IDLE_MASK
)
1378 static int sdma_v5_0_soft_reset(void *handle
)
1385 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring
*ring
)
1388 struct amdgpu_device
*adev
= ring
->adev
;
1390 u64 sdma_gfx_preempt
;
1392 amdgpu_sdma_get_index_from_ring(ring
, &index
);
1394 sdma_gfx_preempt
= mmSDMA0_GFX_PREEMPT
;
1396 sdma_gfx_preempt
= mmSDMA1_GFX_PREEMPT
;
1398 /* assert preemption condition */
1399 amdgpu_ring_set_preempt_cond_exec(ring
, false);
1401 /* emit the trailing fence */
1402 ring
->trail_seq
+= 1;
1403 amdgpu_ring_alloc(ring
, 10);
1404 sdma_v5_0_ring_emit_fence(ring
, ring
->trail_fence_gpu_addr
,
1405 ring
->trail_seq
, 0);
1406 amdgpu_ring_commit(ring
);
1408 /* assert IB preemption */
1409 WREG32(sdma_gfx_preempt
, 1);
1411 /* poll the trailing fence */
1412 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1413 if (ring
->trail_seq
==
1414 le32_to_cpu(*(ring
->trail_fence_cpu_addr
)))
1419 if (i
>= adev
->usec_timeout
) {
1421 DRM_ERROR("ring %d failed to be preempted\n", ring
->idx
);
1424 /* deassert IB preemption */
1425 WREG32(sdma_gfx_preempt
, 0);
1427 /* deassert the preemption condition */
1428 amdgpu_ring_set_preempt_cond_exec(ring
, true);
1432 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device
*adev
,
1433 struct amdgpu_irq_src
*source
,
1435 enum amdgpu_interrupt_state state
)
1439 if (!amdgpu_sriov_vf(adev
)) {
1440 u32 reg_offset
= (type
== AMDGPU_SDMA_IRQ_INSTANCE0
) ?
1441 sdma_v5_0_get_reg_offset(adev
, 0, mmSDMA0_CNTL
) :
1442 sdma_v5_0_get_reg_offset(adev
, 1, mmSDMA0_CNTL
);
1444 sdma_cntl
= RREG32(reg_offset
);
1445 sdma_cntl
= REG_SET_FIELD(sdma_cntl
, SDMA0_CNTL
, TRAP_ENABLE
,
1446 state
== AMDGPU_IRQ_STATE_ENABLE
? 1 : 0);
1447 WREG32(reg_offset
, sdma_cntl
);
1453 static int sdma_v5_0_process_trap_irq(struct amdgpu_device
*adev
,
1454 struct amdgpu_irq_src
*source
,
1455 struct amdgpu_iv_entry
*entry
)
1457 DRM_DEBUG("IH: SDMA trap\n");
1458 switch (entry
->client_id
) {
1459 case SOC15_IH_CLIENTID_SDMA0
:
1460 switch (entry
->ring_id
) {
1462 amdgpu_fence_process(&adev
->sdma
.instance
[0].ring
);
1475 case SOC15_IH_CLIENTID_SDMA1
:
1476 switch (entry
->ring_id
) {
1478 amdgpu_fence_process(&adev
->sdma
.instance
[1].ring
);
1495 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device
*adev
,
1496 struct amdgpu_irq_src
*source
,
1497 struct amdgpu_iv_entry
*entry
)
1502 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device
*adev
,
1508 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1509 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_SDMA_MGCG
)) {
1510 /* Enable sdma clock gating */
1511 def
= data
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_CLK_CTRL
));
1512 data
&= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK
|
1513 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK
|
1514 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK
|
1515 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK
|
1516 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK
|
1517 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK
|
1518 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK
|
1519 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK
);
1521 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_CLK_CTRL
), data
);
1523 /* Disable sdma clock gating */
1524 def
= data
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_CLK_CTRL
));
1525 data
|= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK
|
1526 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK
|
1527 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK
|
1528 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK
|
1529 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK
|
1530 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK
|
1531 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK
|
1532 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK
);
1534 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_CLK_CTRL
), data
);
1539 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device
*adev
,
1545 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1546 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_SDMA_LS
)) {
1547 /* Enable sdma mem light sleep */
1548 def
= data
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_POWER_CNTL
));
1549 data
|= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK
;
1551 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_POWER_CNTL
), data
);
1554 /* Disable sdma mem light sleep */
1555 def
= data
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_POWER_CNTL
));
1556 data
&= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK
;
1558 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_POWER_CNTL
), data
);
1564 static int sdma_v5_0_set_clockgating_state(void *handle
,
1565 enum amd_clockgating_state state
)
1567 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1569 if (amdgpu_sriov_vf(adev
))
1572 switch (adev
->asic_type
) {
1576 sdma_v5_0_update_medium_grain_clock_gating(adev
,
1577 state
== AMD_CG_STATE_GATE
);
1578 sdma_v5_0_update_medium_grain_light_sleep(adev
,
1579 state
== AMD_CG_STATE_GATE
);
1588 static int sdma_v5_0_set_powergating_state(void *handle
,
1589 enum amd_powergating_state state
)
1594 static void sdma_v5_0_get_clockgating_state(void *handle
, u32
*flags
)
1596 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1599 if (amdgpu_sriov_vf(adev
))
1602 /* AMD_CG_SUPPORT_SDMA_MGCG */
1603 data
= RREG32(sdma_v5_0_get_reg_offset(adev
, 0, mmSDMA0_CLK_CTRL
));
1604 if (!(data
& SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK
))
1605 *flags
|= AMD_CG_SUPPORT_SDMA_MGCG
;
1607 /* AMD_CG_SUPPORT_SDMA_LS */
1608 data
= RREG32(sdma_v5_0_get_reg_offset(adev
, 0, mmSDMA0_POWER_CNTL
));
1609 if (data
& SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK
)
1610 *flags
|= AMD_CG_SUPPORT_SDMA_LS
;
1613 const struct amd_ip_funcs sdma_v5_0_ip_funcs
= {
1614 .name
= "sdma_v5_0",
1615 .early_init
= sdma_v5_0_early_init
,
1617 .sw_init
= sdma_v5_0_sw_init
,
1618 .sw_fini
= sdma_v5_0_sw_fini
,
1619 .hw_init
= sdma_v5_0_hw_init
,
1620 .hw_fini
= sdma_v5_0_hw_fini
,
1621 .suspend
= sdma_v5_0_suspend
,
1622 .resume
= sdma_v5_0_resume
,
1623 .is_idle
= sdma_v5_0_is_idle
,
1624 .wait_for_idle
= sdma_v5_0_wait_for_idle
,
1625 .soft_reset
= sdma_v5_0_soft_reset
,
1626 .set_clockgating_state
= sdma_v5_0_set_clockgating_state
,
1627 .set_powergating_state
= sdma_v5_0_set_powergating_state
,
1628 .get_clockgating_state
= sdma_v5_0_get_clockgating_state
,
1631 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs
= {
1632 .type
= AMDGPU_RING_TYPE_SDMA
,
1634 .nop
= SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
),
1635 .support_64bit_ptrs
= true,
1636 .vmhub
= AMDGPU_GFXHUB_0
,
1637 .get_rptr
= sdma_v5_0_ring_get_rptr
,
1638 .get_wptr
= sdma_v5_0_ring_get_wptr
,
1639 .set_wptr
= sdma_v5_0_ring_set_wptr
,
1641 5 + /* sdma_v5_0_ring_init_cond_exec */
1642 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1643 3 + /* hdp_invalidate */
1644 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1645 /* sdma_v5_0_ring_emit_vm_flush */
1646 SOC15_FLUSH_GPU_TLB_NUM_WREG
* 3 +
1647 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT
* 6 * 2 +
1648 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1649 .emit_ib_size
= 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1650 .emit_ib
= sdma_v5_0_ring_emit_ib
,
1651 .emit_fence
= sdma_v5_0_ring_emit_fence
,
1652 .emit_pipeline_sync
= sdma_v5_0_ring_emit_pipeline_sync
,
1653 .emit_vm_flush
= sdma_v5_0_ring_emit_vm_flush
,
1654 .emit_hdp_flush
= sdma_v5_0_ring_emit_hdp_flush
,
1655 .test_ring
= sdma_v5_0_ring_test_ring
,
1656 .test_ib
= sdma_v5_0_ring_test_ib
,
1657 .insert_nop
= sdma_v5_0_ring_insert_nop
,
1658 .pad_ib
= sdma_v5_0_ring_pad_ib
,
1659 .emit_wreg
= sdma_v5_0_ring_emit_wreg
,
1660 .emit_reg_wait
= sdma_v5_0_ring_emit_reg_wait
,
1661 .emit_reg_write_reg_wait
= sdma_v5_0_ring_emit_reg_write_reg_wait
,
1662 .init_cond_exec
= sdma_v5_0_ring_init_cond_exec
,
1663 .patch_cond_exec
= sdma_v5_0_ring_patch_cond_exec
,
1664 .preempt_ib
= sdma_v5_0_ring_preempt_ib
,
1667 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device
*adev
)
1671 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1672 adev
->sdma
.instance
[i
].ring
.funcs
= &sdma_v5_0_ring_funcs
;
1673 adev
->sdma
.instance
[i
].ring
.me
= i
;
1677 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs
= {
1678 .set
= sdma_v5_0_set_trap_irq_state
,
1679 .process
= sdma_v5_0_process_trap_irq
,
1682 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs
= {
1683 .process
= sdma_v5_0_process_illegal_inst_irq
,
1686 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device
*adev
)
1688 adev
->sdma
.trap_irq
.num_types
= AMDGPU_SDMA_IRQ_INSTANCE0
+
1689 adev
->sdma
.num_instances
;
1690 adev
->sdma
.trap_irq
.funcs
= &sdma_v5_0_trap_irq_funcs
;
1691 adev
->sdma
.illegal_inst_irq
.funcs
= &sdma_v5_0_illegal_inst_irq_funcs
;
1695 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1697 * @ring: amdgpu_ring structure holding ring information
1698 * @src_offset: src GPU address
1699 * @dst_offset: dst GPU address
1700 * @byte_count: number of bytes to xfer
1702 * Copy GPU buffers using the DMA engine (NAVI10).
1703 * Used by the amdgpu ttm implementation to move pages if
1704 * registered as the asic copy callback.
1706 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib
*ib
,
1707 uint64_t src_offset
,
1708 uint64_t dst_offset
,
1709 uint32_t byte_count
,
1712 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY
) |
1713 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR
) |
1714 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz
? 1 : 0);
1715 ib
->ptr
[ib
->length_dw
++] = byte_count
- 1;
1716 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
1717 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src_offset
);
1718 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src_offset
);
1719 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1720 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1724 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1726 * @ring: amdgpu_ring structure holding ring information
1727 * @src_data: value to write to buffer
1728 * @dst_offset: dst GPU address
1729 * @byte_count: number of bytes to xfer
1731 * Fill GPU buffers using the DMA engine (NAVI10).
1733 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib
*ib
,
1735 uint64_t dst_offset
,
1736 uint32_t byte_count
)
1738 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL
);
1739 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1740 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1741 ib
->ptr
[ib
->length_dw
++] = src_data
;
1742 ib
->ptr
[ib
->length_dw
++] = byte_count
- 1;
1745 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs
= {
1746 .copy_max_bytes
= 0x400000,
1748 .emit_copy_buffer
= sdma_v5_0_emit_copy_buffer
,
1750 .fill_max_bytes
= 0x400000,
1752 .emit_fill_buffer
= sdma_v5_0_emit_fill_buffer
,
1755 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device
*adev
)
1757 if (adev
->mman
.buffer_funcs
== NULL
) {
1758 adev
->mman
.buffer_funcs
= &sdma_v5_0_buffer_funcs
;
1759 adev
->mman
.buffer_funcs_ring
= &adev
->sdma
.instance
[0].ring
;
1763 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs
= {
1764 .copy_pte_num_dw
= 7,
1765 .copy_pte
= sdma_v5_0_vm_copy_pte
,
1766 .write_pte
= sdma_v5_0_vm_write_pte
,
1767 .set_pte_pde
= sdma_v5_0_vm_set_pte_pde
,
1770 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device
*adev
)
1774 if (adev
->vm_manager
.vm_pte_funcs
== NULL
) {
1775 adev
->vm_manager
.vm_pte_funcs
= &sdma_v5_0_vm_pte_funcs
;
1776 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1777 adev
->vm_manager
.vm_pte_scheds
[i
] =
1778 &adev
->sdma
.instance
[i
].ring
.sched
;
1780 adev
->vm_manager
.vm_pte_num_scheds
= adev
->sdma
.num_instances
;
1784 const struct amdgpu_ip_block_version sdma_v5_0_ip_block
= {
1785 .type
= AMD_IP_BLOCK_TYPE_SDMA
,
1789 .funcs
= &sdma_v5_0_ip_funcs
,