2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
30 #include "gc/gc_10_1_0_offset.h"
31 #include "gc/gc_10_1_0_sh_mask.h"
32 #include "hdp/hdp_5_0_0_offset.h"
33 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
34 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
36 #include "soc15_common.h"
38 #include "navi10_sdma_pkt_open.h"
39 #include "nbio_v2_3.h"
40 #include "sdma_v5_0.h"
42 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
43 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
45 #define SDMA1_REG_OFFSET 0x600
46 #define SDMA0_HYP_DEC_REG_START 0x5880
47 #define SDMA0_HYP_DEC_REG_END 0x5893
48 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
50 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device
*adev
);
51 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device
*adev
);
52 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device
*adev
);
53 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device
*adev
);
55 static const struct soc15_reg_golden golden_settings_sdma_5
[] = {
56 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_CHICKEN_BITS
, 0xffbf1f0f, 0x03ab0107),
57 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
58 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
59 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
60 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
61 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
62 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL
, 0x0000fff0, 0x00403000),
63 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
64 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
65 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
66 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
67 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA0_UTCL1_PAGE
, 0x00ffffff, 0x000c5c00),
68 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_CHICKEN_BITS
, 0xffbf1f0f, 0x03ab0107),
69 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
70 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
71 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
72 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
73 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
74 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL
, 0x0000fff0, 0x00403000),
75 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
76 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
77 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
78 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL
, 0xfffffff7, 0x00403000),
79 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSDMA1_UTCL1_PAGE
, 0x00ffffff, 0x000c5c00)
82 static const struct soc15_reg_golden golden_settings_sdma_nv10
[] = {
85 static u32
sdma_v5_0_get_reg_offset(struct amdgpu_device
*adev
, u32 instance
, u32 internal_offset
)
89 if (internal_offset
>= SDMA0_HYP_DEC_REG_START
&&
90 internal_offset
<= SDMA0_HYP_DEC_REG_END
) {
91 base
= adev
->reg_offset
[GC_HWIP
][0][1];
93 internal_offset
+= SDMA1_HYP_DEC_REG_OFFSET
;
95 base
= adev
->reg_offset
[GC_HWIP
][0][0];
97 internal_offset
+= SDMA1_REG_OFFSET
;
100 return base
+ internal_offset
;
103 static void sdma_v5_0_init_golden_registers(struct amdgpu_device
*adev
)
105 switch (adev
->asic_type
) {
107 soc15_program_register_sequence(adev
,
108 golden_settings_sdma_5
,
109 (const u32
)ARRAY_SIZE(golden_settings_sdma_5
));
110 soc15_program_register_sequence(adev
,
111 golden_settings_sdma_nv10
,
112 (const u32
)ARRAY_SIZE(golden_settings_sdma_nv10
));
120 * sdma_v5_0_init_microcode - load ucode images from disk
122 * @adev: amdgpu_device pointer
124 * Use the firmware interface to load the ucode images into
125 * the driver (not loaded into hw).
126 * Returns 0 on success, error on failure.
129 // emulation only, won't work on real chip
130 // navi10 real chip need to use PSP to load firmware
131 static int sdma_v5_0_init_microcode(struct amdgpu_device
*adev
)
133 const char *chip_name
;
136 struct amdgpu_firmware_info
*info
= NULL
;
137 const struct common_firmware_header
*header
= NULL
;
138 const struct sdma_firmware_header_v1_0
*hdr
;
142 switch (adev
->asic_type
) {
144 chip_name
= "navi10";
150 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
152 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_sdma.bin", chip_name
);
154 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_sdma1.bin", chip_name
);
155 err
= request_firmware(&adev
->sdma
.instance
[i
].fw
, fw_name
, adev
->dev
);
158 err
= amdgpu_ucode_validate(adev
->sdma
.instance
[i
].fw
);
161 hdr
= (const struct sdma_firmware_header_v1_0
*)adev
->sdma
.instance
[i
].fw
->data
;
162 adev
->sdma
.instance
[i
].fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
163 adev
->sdma
.instance
[i
].feature_version
= le32_to_cpu(hdr
->ucode_feature_version
);
164 if (adev
->sdma
.instance
[i
].feature_version
>= 20)
165 adev
->sdma
.instance
[i
].burst_nop
= true;
166 DRM_DEBUG("psp_load == '%s'\n",
167 adev
->firmware
.load_type
== AMDGPU_FW_LOAD_PSP
? "true" : "false");
169 if (adev
->firmware
.load_type
== AMDGPU_FW_LOAD_PSP
) {
170 info
= &adev
->firmware
.ucode
[AMDGPU_UCODE_ID_SDMA0
+ i
];
171 info
->ucode_id
= AMDGPU_UCODE_ID_SDMA0
+ i
;
172 info
->fw
= adev
->sdma
.instance
[i
].fw
;
173 header
= (const struct common_firmware_header
*)info
->fw
->data
;
174 adev
->firmware
.fw_size
+=
175 ALIGN(le32_to_cpu(header
->ucode_size_bytes
), PAGE_SIZE
);
180 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name
);
181 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
182 release_firmware(adev
->sdma
.instance
[i
].fw
);
183 adev
->sdma
.instance
[i
].fw
= NULL
;
189 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring
*ring
)
193 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE
));
194 amdgpu_ring_write(ring
, lower_32_bits(ring
->cond_exe_gpu_addr
));
195 amdgpu_ring_write(ring
, upper_32_bits(ring
->cond_exe_gpu_addr
));
196 amdgpu_ring_write(ring
, 1);
197 ret
= ring
->wptr
& ring
->buf_mask
;/* this is the offset we need patch later */
198 amdgpu_ring_write(ring
, 0x55aa55aa);/* insert dummy here and patch it later */
203 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring
*ring
,
208 BUG_ON(offset
> ring
->buf_mask
);
209 BUG_ON(ring
->ring
[offset
] != 0x55aa55aa);
211 cur
= (ring
->wptr
- 1) & ring
->buf_mask
;
213 ring
->ring
[offset
] = cur
- offset
;
215 ring
->ring
[offset
] = (ring
->buf_mask
+ 1) - offset
+ cur
;
219 * sdma_v5_0_ring_get_rptr - get the current read pointer
221 * @ring: amdgpu ring pointer
223 * Get the current rptr from the hardware (NAVI10+).
225 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring
*ring
)
229 /* XXX check if swapping is necessary on BE */
230 rptr
= ((u64
*)&ring
->adev
->wb
.wb
[ring
->rptr_offs
]);
232 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr
);
233 return ((*rptr
) >> 2);
237 * sdma_v5_0_ring_get_wptr - get the current write pointer
239 * @ring: amdgpu ring pointer
241 * Get the current wptr from the hardware (NAVI10+).
243 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring
*ring
)
245 struct amdgpu_device
*adev
= ring
->adev
;
247 uint64_t local_wptr
= 0;
249 if (ring
->use_doorbell
) {
250 /* XXX check if swapping is necessary on BE */
251 wptr
= ((u64
*)&adev
->wb
.wb
[ring
->wptr_offs
]);
252 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr
);
253 *wptr
= (*wptr
) >> 2;
254 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr
);
259 lowbit
= RREG32(sdma_v5_0_get_reg_offset(adev
, ring
->me
, mmSDMA0_GFX_RB_WPTR
)) >> 2;
260 highbit
= RREG32(sdma_v5_0_get_reg_offset(adev
, ring
->me
, mmSDMA0_GFX_RB_WPTR_HI
)) >> 2;
262 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
263 ring
->me
, highbit
, lowbit
);
265 *wptr
= (*wptr
) << 32;
273 * sdma_v5_0_ring_set_wptr - commit the write pointer
275 * @ring: amdgpu ring pointer
277 * Write the wptr back to the hardware (NAVI10+).
279 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring
*ring
)
281 struct amdgpu_device
*adev
= ring
->adev
;
283 DRM_DEBUG("Setting write pointer\n");
284 if (ring
->use_doorbell
) {
285 DRM_DEBUG("Using doorbell -- "
286 "wptr_offs == 0x%08x "
287 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
288 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
290 lower_32_bits(ring
->wptr
<< 2),
291 upper_32_bits(ring
->wptr
<< 2));
292 /* XXX check if swapping is necessary on BE */
293 adev
->wb
.wb
[ring
->wptr_offs
] = lower_32_bits(ring
->wptr
<< 2);
294 adev
->wb
.wb
[ring
->wptr_offs
+ 1] = upper_32_bits(ring
->wptr
<< 2);
295 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
296 ring
->doorbell_index
, ring
->wptr
<< 2);
297 WDOORBELL64(ring
->doorbell_index
, ring
->wptr
<< 2);
299 DRM_DEBUG("Not using doorbell -- "
300 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
301 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
303 lower_32_bits(ring
->wptr
<< 2),
305 upper_32_bits(ring
->wptr
<< 2));
306 WREG32(sdma_v5_0_get_reg_offset(adev
, ring
->me
, mmSDMA0_GFX_RB_WPTR
),
307 lower_32_bits(ring
->wptr
<< 2));
308 WREG32(sdma_v5_0_get_reg_offset(adev
, ring
->me
, mmSDMA0_GFX_RB_WPTR_HI
),
309 upper_32_bits(ring
->wptr
<< 2));
313 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring
*ring
, uint32_t count
)
315 struct amdgpu_sdma_instance
*sdma
= amdgpu_sdma_get_instance_from_ring(ring
);
318 for (i
= 0; i
< count
; i
++)
319 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
320 amdgpu_ring_write(ring
, ring
->funcs
->nop
|
321 SDMA_PKT_NOP_HEADER_COUNT(count
- 1));
323 amdgpu_ring_write(ring
, ring
->funcs
->nop
);
327 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
329 * @ring: amdgpu ring pointer
330 * @ib: IB object to schedule
332 * Schedule an IB in the DMA ring (NAVI10).
334 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring
*ring
,
335 struct amdgpu_job
*job
,
336 struct amdgpu_ib
*ib
,
339 unsigned vmid
= AMDGPU_JOB_GET_VMID(job
);
340 uint64_t csa_mc_addr
= amdgpu_sdma_get_csa_mc_addr(ring
, vmid
);
342 /* IB packet must end on a 8 DW boundary */
343 sdma_v5_0_ring_insert_nop(ring
, (10 - (lower_32_bits(ring
->wptr
) & 7)) % 8);
345 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT
) |
346 SDMA_PKT_INDIRECT_HEADER_VMID(vmid
& 0xf));
347 /* base must be 32 byte aligned */
348 amdgpu_ring_write(ring
, lower_32_bits(ib
->gpu_addr
) & 0xffffffe0);
349 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
));
350 amdgpu_ring_write(ring
, ib
->length_dw
);
351 amdgpu_ring_write(ring
, lower_32_bits(csa_mc_addr
));
352 amdgpu_ring_write(ring
, upper_32_bits(csa_mc_addr
));
356 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
358 * @ring: amdgpu ring pointer
360 * Emit an hdp flush packet on the requested DMA ring.
362 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring
*ring
)
364 struct amdgpu_device
*adev
= ring
->adev
;
365 u32 ref_and_mask
= 0;
366 const struct nbio_hdp_flush_reg
*nbio_hf_reg
= adev
->nbio_funcs
->hdp_flush_reg
;
369 ref_and_mask
= nbio_hf_reg
->ref_and_mask_sdma0
;
371 ref_and_mask
= nbio_hf_reg
->ref_and_mask_sdma1
;
373 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM
) |
374 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
375 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
376 amdgpu_ring_write(ring
, (adev
->nbio_funcs
->get_hdp_flush_done_offset(adev
)) << 2);
377 amdgpu_ring_write(ring
, (adev
->nbio_funcs
->get_hdp_flush_req_offset(adev
)) << 2);
378 amdgpu_ring_write(ring
, ref_and_mask
); /* reference */
379 amdgpu_ring_write(ring
, ref_and_mask
); /* mask */
380 amdgpu_ring_write(ring
, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
381 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
385 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
387 * @ring: amdgpu ring pointer
388 * @fence: amdgpu fence object
390 * Add a DMA fence packet to the ring to write
391 * the fence seq number and DMA trap packet to generate
392 * an interrupt if needed (NAVI10).
394 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
, u64 seq
,
397 struct amdgpu_device
*adev
= ring
->adev
;
398 bool write64bit
= flags
& AMDGPU_FENCE_FLAG_64BIT
;
399 /* write the fence */
400 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE
) |
401 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
402 /* zero in first two bits */
404 amdgpu_ring_write(ring
, lower_32_bits(addr
));
405 amdgpu_ring_write(ring
, upper_32_bits(addr
));
406 amdgpu_ring_write(ring
, lower_32_bits(seq
));
408 /* optionally write high bits as well */
411 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE
) |
412 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
413 /* zero in first two bits */
415 amdgpu_ring_write(ring
, lower_32_bits(addr
));
416 amdgpu_ring_write(ring
, upper_32_bits(addr
));
417 amdgpu_ring_write(ring
, upper_32_bits(seq
));
420 /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
421 if ((flags
& AMDGPU_FENCE_FLAG_INT
) && adev
->pdev
->device
!= 0x50) {
422 /* generate an interrupt */
423 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP
));
424 amdgpu_ring_write(ring
, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
430 * sdma_v5_0_gfx_stop - stop the gfx async dma engines
432 * @adev: amdgpu_device pointer
434 * Stop the gfx async dma ring buffers (NAVI10).
436 static void sdma_v5_0_gfx_stop(struct amdgpu_device
*adev
)
438 struct amdgpu_ring
*sdma0
= &adev
->sdma
.instance
[0].ring
;
439 struct amdgpu_ring
*sdma1
= &adev
->sdma
.instance
[1].ring
;
440 u32 rb_cntl
, ib_cntl
;
443 if ((adev
->mman
.buffer_funcs_ring
== sdma0
) ||
444 (adev
->mman
.buffer_funcs_ring
== sdma1
))
445 amdgpu_ttm_set_buffer_funcs_status(adev
, false);
447 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
448 rb_cntl
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_CNTL
));
449 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_ENABLE
, 0);
450 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_CNTL
), rb_cntl
);
451 ib_cntl
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_IB_CNTL
));
452 ib_cntl
= REG_SET_FIELD(ib_cntl
, SDMA0_GFX_IB_CNTL
, IB_ENABLE
, 0);
453 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_IB_CNTL
), ib_cntl
);
456 sdma0
->sched
.ready
= false;
457 sdma1
->sched
.ready
= false;
461 * sdma_v5_0_rlc_stop - stop the compute async dma engines
463 * @adev: amdgpu_device pointer
465 * Stop the compute async dma queues (NAVI10).
467 static void sdma_v5_0_rlc_stop(struct amdgpu_device
*adev
)
473 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
475 * @adev: amdgpu_device pointer
476 * @enable: enable/disable the DMA MEs context switch.
478 * Halt or unhalt the async dma engines context switch (NAVI10).
480 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device
*adev
, bool enable
)
482 u32 f32_cntl
, phase_quantum
= 0;
485 if (amdgpu_sdma_phase_quantum
) {
486 unsigned value
= amdgpu_sdma_phase_quantum
;
489 while (value
> (SDMA0_PHASE0_QUANTUM__VALUE_MASK
>>
490 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT
)) {
491 value
= (value
+ 1) >> 1;
494 if (unit
> (SDMA0_PHASE0_QUANTUM__UNIT_MASK
>>
495 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT
)) {
496 value
= (SDMA0_PHASE0_QUANTUM__VALUE_MASK
>>
497 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT
);
498 unit
= (SDMA0_PHASE0_QUANTUM__UNIT_MASK
>>
499 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT
);
501 "clamping sdma_phase_quantum to %uK clock cycles\n",
505 value
<< SDMA0_PHASE0_QUANTUM__VALUE__SHIFT
|
506 unit
<< SDMA0_PHASE0_QUANTUM__UNIT__SHIFT
;
509 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
510 f32_cntl
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_CNTL
));
511 f32_cntl
= REG_SET_FIELD(f32_cntl
, SDMA0_CNTL
,
512 AUTO_CTXSW_ENABLE
, enable
? 1 : 0);
513 if (enable
&& amdgpu_sdma_phase_quantum
) {
514 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_PHASE0_QUANTUM
),
516 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_PHASE1_QUANTUM
),
518 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_PHASE2_QUANTUM
),
521 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_CNTL
), f32_cntl
);
527 * sdma_v5_0_enable - stop the async dma engines
529 * @adev: amdgpu_device pointer
530 * @enable: enable/disable the DMA MEs.
532 * Halt or unhalt the async dma engines (NAVI10).
534 static void sdma_v5_0_enable(struct amdgpu_device
*adev
, bool enable
)
539 if (enable
== false) {
540 sdma_v5_0_gfx_stop(adev
);
541 sdma_v5_0_rlc_stop(adev
);
544 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
545 f32_cntl
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_F32_CNTL
));
546 f32_cntl
= REG_SET_FIELD(f32_cntl
, SDMA0_F32_CNTL
, HALT
, enable
? 0 : 1);
547 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_F32_CNTL
), f32_cntl
);
552 * sdma_v5_0_gfx_resume - setup and start the async dma engines
554 * @adev: amdgpu_device pointer
556 * Set up the gfx DMA ring buffers and enable them (NAVI10).
557 * Returns 0 for success, error for failure.
559 static int sdma_v5_0_gfx_resume(struct amdgpu_device
*adev
)
561 struct amdgpu_ring
*ring
;
562 u32 rb_cntl
, ib_cntl
;
572 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
573 ring
= &adev
->sdma
.instance
[i
].ring
;
574 wb_offset
= (ring
->rptr_offs
* 4);
576 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
), 0);
578 /* Set ring buffer size in dwords */
579 rb_bufsz
= order_base_2(ring
->ring_size
/ 4);
580 rb_cntl
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_CNTL
));
581 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_SIZE
, rb_bufsz
);
583 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_SWAP_ENABLE
, 1);
584 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
,
585 RPTR_WRITEBACK_SWAP_ENABLE
, 1);
587 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_CNTL
), rb_cntl
);
589 /* Initialize the ring buffer's read and write pointers */
590 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_RPTR
), 0);
591 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_RPTR_HI
), 0);
592 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_WPTR
), 0);
593 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_WPTR_HI
), 0);
595 /* setup the wptr shadow polling */
596 wptr_gpu_addr
= adev
->wb
.gpu_addr
+ (ring
->wptr_offs
* 4);
597 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO
),
598 lower_32_bits(wptr_gpu_addr
));
599 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI
),
600 upper_32_bits(wptr_gpu_addr
));
601 wptr_poll_cntl
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
,
602 mmSDMA0_GFX_RB_WPTR_POLL_CNTL
));
603 wptr_poll_cntl
= REG_SET_FIELD(wptr_poll_cntl
,
604 SDMA0_GFX_RB_WPTR_POLL_CNTL
,
606 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_WPTR_POLL_CNTL
),
609 /* set the wb address whether it's enabled or not */
610 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_RPTR_ADDR_HI
),
611 upper_32_bits(adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFF);
612 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_RPTR_ADDR_LO
),
613 lower_32_bits(adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFC);
615 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RPTR_WRITEBACK_ENABLE
, 1);
617 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_BASE
), ring
->gpu_addr
>> 8);
618 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_BASE_HI
), ring
->gpu_addr
>> 40);
622 /* before programing wptr to a less value, need set minor_ptr_update first */
623 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_MINOR_PTR_UPDATE
), 1);
625 if (!amdgpu_sriov_vf(adev
)) { /* only bare-metal use register write for wptr */
626 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_WPTR
), lower_32_bits(ring
->wptr
) << 2);
627 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_WPTR_HI
), upper_32_bits(ring
->wptr
) << 2);
630 doorbell
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_DOORBELL
));
631 doorbell_offset
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_DOORBELL_OFFSET
));
633 if (ring
->use_doorbell
) {
634 doorbell
= REG_SET_FIELD(doorbell
, SDMA0_GFX_DOORBELL
, ENABLE
, 1);
635 doorbell_offset
= REG_SET_FIELD(doorbell_offset
, SDMA0_GFX_DOORBELL_OFFSET
,
636 OFFSET
, ring
->doorbell_index
);
638 doorbell
= REG_SET_FIELD(doorbell
, SDMA0_GFX_DOORBELL
, ENABLE
, 0);
640 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_DOORBELL
), doorbell
);
641 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_DOORBELL_OFFSET
), doorbell_offset
);
643 adev
->nbio_funcs
->sdma_doorbell_range(adev
, i
, ring
->use_doorbell
,
644 ring
->doorbell_index
, 20);
646 if (amdgpu_sriov_vf(adev
))
647 sdma_v5_0_ring_set_wptr(ring
);
649 /* set minor_ptr_update to 0 after wptr programed */
650 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_MINOR_PTR_UPDATE
), 0);
652 /* set utc l1 enable flag always to 1 */
653 temp
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_CNTL
));
654 temp
= REG_SET_FIELD(temp
, SDMA0_CNTL
, UTC_L1_ENABLE
, 1);
657 temp
= REG_SET_FIELD(temp
, SDMA0_CNTL
, MIDCMD_PREEMPT_ENABLE
, 1);
658 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_CNTL
), temp
);
660 /* Set up RESP_MODE to non-copy addresses */
661 temp
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_UTCL1_CNTL
));
662 temp
= REG_SET_FIELD(temp
, SDMA0_UTCL1_CNTL
, RESP_MODE
, 3);
663 temp
= REG_SET_FIELD(temp
, SDMA0_UTCL1_CNTL
, REDO_DELAY
, 9);
664 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_UTCL1_CNTL
), temp
);
666 /* program default cache read and write policy */
667 temp
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_UTCL1_PAGE
));
668 /* clean read policy and write policy bits */
670 temp
|= ((CACHE_READ_POLICY_L2__DEFAULT
<< 12) | (CACHE_WRITE_POLICY_L2__DEFAULT
<< 14));
671 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_UTCL1_PAGE
), temp
);
673 if (!amdgpu_sriov_vf(adev
)) {
675 temp
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_F32_CNTL
));
676 temp
= REG_SET_FIELD(temp
, SDMA0_F32_CNTL
, HALT
, 0);
677 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_F32_CNTL
), temp
);
681 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_ENABLE
, 1);
682 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_RB_CNTL
), rb_cntl
);
684 ib_cntl
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_IB_CNTL
));
685 ib_cntl
= REG_SET_FIELD(ib_cntl
, SDMA0_GFX_IB_CNTL
, IB_ENABLE
, 1);
687 ib_cntl
= REG_SET_FIELD(ib_cntl
, SDMA0_GFX_IB_CNTL
, IB_SWAP_ENABLE
, 1);
690 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_GFX_IB_CNTL
), ib_cntl
);
692 ring
->sched
.ready
= true;
694 if (amdgpu_sriov_vf(adev
)) { /* bare-metal sequence doesn't need below to lines */
695 sdma_v5_0_ctx_switch_enable(adev
, true);
696 sdma_v5_0_enable(adev
, true);
699 r
= amdgpu_ring_test_ring(ring
);
701 ring
->sched
.ready
= false;
705 if (adev
->mman
.buffer_funcs_ring
== ring
)
706 amdgpu_ttm_set_buffer_funcs_status(adev
, true);
713 * sdma_v5_0_rlc_resume - setup and start the async dma engines
715 * @adev: amdgpu_device pointer
717 * Set up the compute DMA queues and enable them (NAVI10).
718 * Returns 0 for success, error for failure.
720 static int sdma_v5_0_rlc_resume(struct amdgpu_device
*adev
)
726 * sdma_v5_0_load_microcode - load the sDMA ME ucode
728 * @adev: amdgpu_device pointer
730 * Loads the sDMA0/1 ucode.
731 * Returns 0 for success, -EINVAL if the ucode is not available.
733 static int sdma_v5_0_load_microcode(struct amdgpu_device
*adev
)
735 const struct sdma_firmware_header_v1_0
*hdr
;
736 const __le32
*fw_data
;
741 sdma_v5_0_enable(adev
, false);
743 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
744 if (!adev
->sdma
.instance
[i
].fw
)
747 hdr
= (const struct sdma_firmware_header_v1_0
*)adev
->sdma
.instance
[i
].fw
->data
;
748 amdgpu_ucode_print_sdma_hdr(&hdr
->header
);
749 fw_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
751 fw_data
= (const __le32
*)
752 (adev
->sdma
.instance
[i
].fw
->data
+
753 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
755 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_UCODE_ADDR
), 0);
757 for (j
= 0; j
< fw_size
; j
++) {
758 if (amdgpu_emu_mode
== 1 && j
% 500 == 0)
760 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_UCODE_DATA
), le32_to_cpup(fw_data
++));
763 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_UCODE_ADDR
), adev
->sdma
.instance
[i
].fw_version
);
770 * sdma_v5_0_start - setup and start the async dma engines
772 * @adev: amdgpu_device pointer
774 * Set up the DMA engines and enable them (NAVI10).
775 * Returns 0 for success, error for failure.
777 static int sdma_v5_0_start(struct amdgpu_device
*adev
)
781 if (amdgpu_sriov_vf(adev
)) {
782 sdma_v5_0_ctx_switch_enable(adev
, false);
783 sdma_v5_0_enable(adev
, false);
785 /* set RB registers */
786 r
= sdma_v5_0_gfx_resume(adev
);
790 if (adev
->firmware
.load_type
== AMDGPU_FW_LOAD_DIRECT
) {
791 r
= sdma_v5_0_load_microcode(adev
);
795 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
796 if (amdgpu_emu_mode
== 1 && adev
->pdev
->device
== 0x4d)
801 sdma_v5_0_enable(adev
, true);
802 /* enable sdma ring preemption */
803 sdma_v5_0_ctx_switch_enable(adev
, true);
805 /* start the gfx rings and rlc compute queues */
806 r
= sdma_v5_0_gfx_resume(adev
);
809 r
= sdma_v5_0_rlc_resume(adev
);
815 * sdma_v5_0_ring_test_ring - simple async dma engine test
817 * @ring: amdgpu_ring structure holding ring information
819 * Test the DMA engine by writing using it to write an
820 * value to memory. (NAVI10).
821 * Returns 0 for success, error for failure.
823 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring
*ring
)
825 struct amdgpu_device
*adev
= ring
->adev
;
832 r
= amdgpu_device_wb_get(adev
, &index
);
834 dev_err(adev
->dev
, "(%d) failed to allocate wb slot\n", r
);
838 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
840 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
842 r
= amdgpu_ring_alloc(ring
, 5);
844 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring
->idx
, r
);
845 amdgpu_device_wb_free(adev
, index
);
849 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
850 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR
));
851 amdgpu_ring_write(ring
, lower_32_bits(gpu_addr
));
852 amdgpu_ring_write(ring
, upper_32_bits(gpu_addr
));
853 amdgpu_ring_write(ring
, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
854 amdgpu_ring_write(ring
, 0xDEADBEEF);
855 amdgpu_ring_commit(ring
);
857 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
858 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
859 if (tmp
== 0xDEADBEEF)
861 if (amdgpu_emu_mode
== 1)
867 if (i
< adev
->usec_timeout
) {
868 if (amdgpu_emu_mode
== 1)
869 DRM_INFO("ring test on %d succeeded in %d msecs\n", ring
->idx
, i
);
871 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring
->idx
, i
);
873 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
877 amdgpu_device_wb_free(adev
, index
);
883 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
885 * @ring: amdgpu_ring structure holding ring information
887 * Test a simple IB in the DMA ring (NAVI10).
888 * Returns 0 on success, error on failure.
890 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring
*ring
, long timeout
)
892 struct amdgpu_device
*adev
= ring
->adev
;
894 struct dma_fence
*f
= NULL
;
900 r
= amdgpu_device_wb_get(adev
, &index
);
902 dev_err(adev
->dev
, "(%ld) failed to allocate wb slot\n", r
);
906 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
908 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
909 memset(&ib
, 0, sizeof(ib
));
910 r
= amdgpu_ib_get(adev
, NULL
, 256, &ib
);
912 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r
);
916 ib
.ptr
[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
917 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR
);
918 ib
.ptr
[1] = lower_32_bits(gpu_addr
);
919 ib
.ptr
[2] = upper_32_bits(gpu_addr
);
920 ib
.ptr
[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
921 ib
.ptr
[4] = 0xDEADBEEF;
922 ib
.ptr
[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
);
923 ib
.ptr
[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
);
924 ib
.ptr
[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
);
927 r
= amdgpu_ib_schedule(ring
, 1, &ib
, NULL
, &f
);
931 r
= dma_fence_wait_timeout(f
, false, timeout
);
933 DRM_ERROR("amdgpu: IB test timed out\n");
937 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r
);
940 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
941 if (tmp
== 0xDEADBEEF) {
942 DRM_INFO("ib test on ring %d succeeded\n", ring
->idx
);
945 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp
);
950 amdgpu_ib_free(adev
, &ib
, NULL
);
953 amdgpu_device_wb_free(adev
, index
);
959 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
961 * @ib: indirect buffer to fill with commands
962 * @pe: addr of the page entry
963 * @src: src addr to copy from
964 * @count: number of page entries to update
966 * Update PTEs by copying them from the GART using sDMA (NAVI10).
968 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib
*ib
,
969 uint64_t pe
, uint64_t src
,
972 unsigned bytes
= count
* 8;
974 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY
) |
975 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR
);
976 ib
->ptr
[ib
->length_dw
++] = bytes
- 1;
977 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
978 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src
);
979 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src
);
980 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
);
981 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
986 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
988 * @ib: indirect buffer to fill with commands
989 * @pe: addr of the page entry
990 * @addr: dst addr to write into pe
991 * @count: number of page entries to update
992 * @incr: increase next addr by incr bytes
993 * @flags: access flags
995 * Update PTEs by writing them manually using sDMA (NAVI10).
997 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib
*ib
, uint64_t pe
,
998 uint64_t value
, unsigned count
,
1001 unsigned ndw
= count
* 2;
1003 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
1004 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR
);
1005 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
);
1006 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
1007 ib
->ptr
[ib
->length_dw
++] = ndw
- 1;
1008 for (; ndw
> 0; ndw
-= 2) {
1009 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(value
);
1010 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
1016 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1018 * @ib: indirect buffer to fill with commands
1019 * @pe: addr of the page entry
1020 * @addr: dst addr to write into pe
1021 * @count: number of page entries to update
1022 * @incr: increase next addr by incr bytes
1023 * @flags: access flags
1025 * Update the page tables using sDMA (NAVI10).
1027 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib
*ib
,
1029 uint64_t addr
, unsigned count
,
1030 uint32_t incr
, uint64_t flags
)
1032 /* for physically contiguous pages (vram) */
1033 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE
);
1034 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
); /* dst addr */
1035 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
1036 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(flags
); /* mask */
1037 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(flags
);
1038 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(addr
); /* value */
1039 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(addr
);
1040 ib
->ptr
[ib
->length_dw
++] = incr
; /* increment size */
1041 ib
->ptr
[ib
->length_dw
++] = 0;
1042 ib
->ptr
[ib
->length_dw
++] = count
- 1; /* number of entries */
1046 * sdma_v5_0_ring_pad_ib - pad the IB to the required number of dw
1048 * @ib: indirect buffer to fill with padding
1051 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
)
1053 struct amdgpu_sdma_instance
*sdma
= amdgpu_sdma_get_instance_from_ring(ring
);
1057 pad_count
= (8 - (ib
->length_dw
& 0x7)) % 8;
1058 for (i
= 0; i
< pad_count
; i
++)
1059 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
1060 ib
->ptr
[ib
->length_dw
++] =
1061 SDMA_PKT_HEADER_OP(SDMA_OP_NOP
) |
1062 SDMA_PKT_NOP_HEADER_COUNT(pad_count
- 1);
1064 ib
->ptr
[ib
->length_dw
++] =
1065 SDMA_PKT_HEADER_OP(SDMA_OP_NOP
);
1070 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1072 * @ring: amdgpu_ring pointer
1074 * Make sure all previous operations are completed (CIK).
1076 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring
*ring
)
1078 uint32_t seq
= ring
->fence_drv
.sync_seq
;
1079 uint64_t addr
= ring
->fence_drv
.gpu_addr
;
1082 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM
) |
1083 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1084 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1085 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1086 amdgpu_ring_write(ring
, addr
& 0xfffffffc);
1087 amdgpu_ring_write(ring
, upper_32_bits(addr
) & 0xffffffff);
1088 amdgpu_ring_write(ring
, seq
); /* reference */
1089 amdgpu_ring_write(ring
, 0xfffffff); /* mask */
1090 amdgpu_ring_write(ring
, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1091 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1096 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1098 * @ring: amdgpu_ring pointer
1099 * @vm: amdgpu_vm pointer
1101 * Update the page table base and flush the VM TLB
1102 * using sDMA (NAVI10).
1104 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring
*ring
,
1105 unsigned vmid
, uint64_t pd_addr
)
1107 amdgpu_gmc_emit_flush_gpu_tlb(ring
, vmid
, pd_addr
);
1110 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring
*ring
,
1111 uint32_t reg
, uint32_t val
)
1113 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE
) |
1114 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1115 amdgpu_ring_write(ring
, reg
);
1116 amdgpu_ring_write(ring
, val
);
1119 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring
*ring
, uint32_t reg
,
1120 uint32_t val
, uint32_t mask
)
1122 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM
) |
1123 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1124 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1125 amdgpu_ring_write(ring
, reg
<< 2);
1126 amdgpu_ring_write(ring
, 0);
1127 amdgpu_ring_write(ring
, val
); /* reference */
1128 amdgpu_ring_write(ring
, mask
); /* mask */
1129 amdgpu_ring_write(ring
, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1130 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1133 static int sdma_v5_0_early_init(void *handle
)
1135 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1137 adev
->sdma
.num_instances
= 2;
1139 sdma_v5_0_set_ring_funcs(adev
);
1140 sdma_v5_0_set_buffer_funcs(adev
);
1141 sdma_v5_0_set_vm_pte_funcs(adev
);
1142 sdma_v5_0_set_irq_funcs(adev
);
1148 static int sdma_v5_0_sw_init(void *handle
)
1150 struct amdgpu_ring
*ring
;
1152 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1154 /* SDMA trap event */
1155 r
= amdgpu_irq_add_id(adev
, SOC15_IH_CLIENTID_SDMA0
,
1156 SDMA0_5_0__SRCID__SDMA_TRAP
,
1157 &adev
->sdma
.trap_irq
);
1161 /* SDMA trap event */
1162 r
= amdgpu_irq_add_id(adev
, SOC15_IH_CLIENTID_SDMA1
,
1163 SDMA1_5_0__SRCID__SDMA_TRAP
,
1164 &adev
->sdma
.trap_irq
);
1168 r
= sdma_v5_0_init_microcode(adev
);
1170 DRM_ERROR("Failed to load sdma firmware!\n");
1174 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1175 ring
= &adev
->sdma
.instance
[i
].ring
;
1176 ring
->ring_obj
= NULL
;
1177 ring
->use_doorbell
= true;
1179 DRM_INFO("use_doorbell being set to: [%s]\n",
1180 ring
->use_doorbell
?"true":"false");
1182 ring
->doorbell_index
= (i
== 0) ?
1183 (adev
->doorbell_index
.sdma_engine
[0] << 1) //get DWORD offset
1184 : (adev
->doorbell_index
.sdma_engine
[1] << 1); // get DWORD offset
1186 sprintf(ring
->name
, "sdma%d", i
);
1187 r
= amdgpu_ring_init(adev
, ring
, 1024,
1188 &adev
->sdma
.trap_irq
,
1190 AMDGPU_SDMA_IRQ_INSTANCE0
:
1191 AMDGPU_SDMA_IRQ_INSTANCE1
);
1199 static int sdma_v5_0_sw_fini(void *handle
)
1201 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1204 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1205 amdgpu_ring_fini(&adev
->sdma
.instance
[i
].ring
);
1210 static int sdma_v5_0_hw_init(void *handle
)
1213 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1215 sdma_v5_0_init_golden_registers(adev
);
1217 r
= sdma_v5_0_start(adev
);
1222 static int sdma_v5_0_hw_fini(void *handle
)
1224 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1226 if (amdgpu_sriov_vf(adev
))
1229 sdma_v5_0_ctx_switch_enable(adev
, false);
1230 sdma_v5_0_enable(adev
, false);
1235 static int sdma_v5_0_suspend(void *handle
)
1237 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1239 return sdma_v5_0_hw_fini(adev
);
1242 static int sdma_v5_0_resume(void *handle
)
1244 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1246 return sdma_v5_0_hw_init(adev
);
1249 static bool sdma_v5_0_is_idle(void *handle
)
1251 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1254 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1255 u32 tmp
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_STATUS_REG
));
1257 if (!(tmp
& SDMA0_STATUS_REG__IDLE_MASK
))
1264 static int sdma_v5_0_wait_for_idle(void *handle
)
1268 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1270 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1271 sdma0
= RREG32(sdma_v5_0_get_reg_offset(adev
, 0, mmSDMA0_STATUS_REG
));
1272 sdma1
= RREG32(sdma_v5_0_get_reg_offset(adev
, 1, mmSDMA0_STATUS_REG
));
1274 if (sdma0
& sdma1
& SDMA0_STATUS_REG__IDLE_MASK
)
1281 static int sdma_v5_0_soft_reset(void *handle
)
1288 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring
*ring
)
1291 struct amdgpu_device
*adev
= ring
->adev
;
1293 u64 sdma_gfx_preempt
;
1295 amdgpu_sdma_get_index_from_ring(ring
, &index
);
1297 sdma_gfx_preempt
= mmSDMA0_GFX_PREEMPT
;
1299 sdma_gfx_preempt
= mmSDMA1_GFX_PREEMPT
;
1301 /* assert preemption condition */
1302 amdgpu_ring_set_preempt_cond_exec(ring
, false);
1304 /* emit the trailing fence */
1305 ring
->trail_seq
+= 1;
1306 amdgpu_ring_alloc(ring
, 10);
1307 sdma_v5_0_ring_emit_fence(ring
, ring
->trail_fence_gpu_addr
,
1308 ring
->trail_seq
, 0);
1309 amdgpu_ring_commit(ring
);
1311 /* assert IB preemption */
1312 WREG32(sdma_gfx_preempt
, 1);
1314 /* poll the trailing fence */
1315 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1316 if (ring
->trail_seq
==
1317 le32_to_cpu(*(ring
->trail_fence_cpu_addr
)))
1322 if (i
>= adev
->usec_timeout
) {
1324 DRM_ERROR("ring %d failed to be preempted\n", ring
->idx
);
1327 /* deassert IB preemption */
1328 WREG32(sdma_gfx_preempt
, 0);
1330 /* deassert the preemption condition */
1331 amdgpu_ring_set_preempt_cond_exec(ring
, true);
1335 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device
*adev
,
1336 struct amdgpu_irq_src
*source
,
1338 enum amdgpu_interrupt_state state
)
1342 u32 reg_offset
= (type
== AMDGPU_SDMA_IRQ_INSTANCE0
) ?
1343 sdma_v5_0_get_reg_offset(adev
, 0, mmSDMA0_CNTL
) :
1344 sdma_v5_0_get_reg_offset(adev
, 1, mmSDMA0_CNTL
);
1346 sdma_cntl
= RREG32(reg_offset
);
1347 sdma_cntl
= REG_SET_FIELD(sdma_cntl
, SDMA0_CNTL
, TRAP_ENABLE
,
1348 state
== AMDGPU_IRQ_STATE_ENABLE
? 1 : 0);
1349 WREG32(reg_offset
, sdma_cntl
);
1354 static int sdma_v5_0_process_trap_irq(struct amdgpu_device
*adev
,
1355 struct amdgpu_irq_src
*source
,
1356 struct amdgpu_iv_entry
*entry
)
1358 DRM_DEBUG("IH: SDMA trap\n");
1359 switch (entry
->client_id
) {
1360 case SOC15_IH_CLIENTID_SDMA0
:
1361 switch (entry
->ring_id
) {
1363 amdgpu_fence_process(&adev
->sdma
.instance
[0].ring
);
1376 case SOC15_IH_CLIENTID_SDMA1
:
1377 switch (entry
->ring_id
) {
1379 amdgpu_fence_process(&adev
->sdma
.instance
[1].ring
);
1396 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device
*adev
,
1397 struct amdgpu_irq_src
*source
,
1398 struct amdgpu_iv_entry
*entry
)
1403 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device
*adev
,
1409 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1410 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_SDMA_MGCG
)) {
1411 /* Enable sdma clock gating */
1412 def
= data
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_CLK_CTRL
));
1413 data
&= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK
|
1414 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK
|
1415 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK
|
1416 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK
|
1417 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK
|
1418 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK
|
1419 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK
|
1420 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK
);
1422 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_CLK_CTRL
), data
);
1424 /* Disable sdma clock gating */
1425 def
= data
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_CLK_CTRL
));
1426 data
|= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK
|
1427 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK
|
1428 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK
|
1429 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK
|
1430 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK
|
1431 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK
|
1432 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK
|
1433 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK
);
1435 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_CLK_CTRL
), data
);
1440 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device
*adev
,
1446 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1447 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_SDMA_LS
)) {
1448 /* Enable sdma mem light sleep */
1449 def
= data
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_POWER_CNTL
));
1450 data
|= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK
;
1452 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_POWER_CNTL
), data
);
1455 /* Disable sdma mem light sleep */
1456 def
= data
= RREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_POWER_CNTL
));
1457 data
&= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK
;
1459 WREG32(sdma_v5_0_get_reg_offset(adev
, i
, mmSDMA0_POWER_CNTL
), data
);
1465 static int sdma_v5_0_set_clockgating_state(void *handle
,
1466 enum amd_clockgating_state state
)
1468 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1470 if (amdgpu_sriov_vf(adev
))
1473 switch (adev
->asic_type
) {
1475 sdma_v5_0_update_medium_grain_clock_gating(adev
,
1476 state
== AMD_CG_STATE_GATE
? true : false);
1477 sdma_v5_0_update_medium_grain_light_sleep(adev
,
1478 state
== AMD_CG_STATE_GATE
? true : false);
1487 static int sdma_v5_0_set_powergating_state(void *handle
,
1488 enum amd_powergating_state state
)
1493 static void sdma_v5_0_get_clockgating_state(void *handle
, u32
*flags
)
1495 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1498 if (amdgpu_sriov_vf(adev
))
1501 /* AMD_CG_SUPPORT_SDMA_MGCG */
1502 data
= RREG32(sdma_v5_0_get_reg_offset(adev
, 0, mmSDMA0_CLK_CTRL
));
1503 if (!(data
& SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK
))
1504 *flags
|= AMD_CG_SUPPORT_SDMA_MGCG
;
1506 /* AMD_CG_SUPPORT_SDMA_LS */
1507 data
= RREG32(sdma_v5_0_get_reg_offset(adev
, 0, mmSDMA0_POWER_CNTL
));
1508 if (data
& SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK
)
1509 *flags
|= AMD_CG_SUPPORT_SDMA_LS
;
1512 const struct amd_ip_funcs sdma_v5_0_ip_funcs
= {
1513 .name
= "sdma_v5_0",
1514 .early_init
= sdma_v5_0_early_init
,
1516 .sw_init
= sdma_v5_0_sw_init
,
1517 .sw_fini
= sdma_v5_0_sw_fini
,
1518 .hw_init
= sdma_v5_0_hw_init
,
1519 .hw_fini
= sdma_v5_0_hw_fini
,
1520 .suspend
= sdma_v5_0_suspend
,
1521 .resume
= sdma_v5_0_resume
,
1522 .is_idle
= sdma_v5_0_is_idle
,
1523 .wait_for_idle
= sdma_v5_0_wait_for_idle
,
1524 .soft_reset
= sdma_v5_0_soft_reset
,
1525 .set_clockgating_state
= sdma_v5_0_set_clockgating_state
,
1526 .set_powergating_state
= sdma_v5_0_set_powergating_state
,
1527 .get_clockgating_state
= sdma_v5_0_get_clockgating_state
,
1530 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs
= {
1531 .type
= AMDGPU_RING_TYPE_SDMA
,
1533 .nop
= SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
),
1534 .support_64bit_ptrs
= true,
1535 .vmhub
= AMDGPU_GFXHUB
,
1536 .get_rptr
= sdma_v5_0_ring_get_rptr
,
1537 .get_wptr
= sdma_v5_0_ring_get_wptr
,
1538 .set_wptr
= sdma_v5_0_ring_set_wptr
,
1540 5 + /* sdma_v5_0_ring_init_cond_exec */
1541 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1542 3 + /* hdp_invalidate */
1543 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1544 /* sdma_v5_0_ring_emit_vm_flush */
1545 SOC15_FLUSH_GPU_TLB_NUM_WREG
* 3 +
1546 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT
* 6 +
1547 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1548 .emit_ib_size
= 7 + 6, /* sdma_v5_0_ring_emit_ib */
1549 .emit_ib
= sdma_v5_0_ring_emit_ib
,
1550 .emit_fence
= sdma_v5_0_ring_emit_fence
,
1551 .emit_pipeline_sync
= sdma_v5_0_ring_emit_pipeline_sync
,
1552 .emit_vm_flush
= sdma_v5_0_ring_emit_vm_flush
,
1553 .emit_hdp_flush
= sdma_v5_0_ring_emit_hdp_flush
,
1554 .test_ring
= sdma_v5_0_ring_test_ring
,
1555 .test_ib
= sdma_v5_0_ring_test_ib
,
1556 .insert_nop
= sdma_v5_0_ring_insert_nop
,
1557 .pad_ib
= sdma_v5_0_ring_pad_ib
,
1558 .emit_wreg
= sdma_v5_0_ring_emit_wreg
,
1559 .emit_reg_wait
= sdma_v5_0_ring_emit_reg_wait
,
1560 .init_cond_exec
= sdma_v5_0_ring_init_cond_exec
,
1561 .patch_cond_exec
= sdma_v5_0_ring_patch_cond_exec
,
1562 .preempt_ib
= sdma_v5_0_ring_preempt_ib
,
1565 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device
*adev
)
1569 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1570 adev
->sdma
.instance
[i
].ring
.funcs
= &sdma_v5_0_ring_funcs
;
1571 adev
->sdma
.instance
[i
].ring
.me
= i
;
1575 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs
= {
1576 .set
= sdma_v5_0_set_trap_irq_state
,
1577 .process
= sdma_v5_0_process_trap_irq
,
1580 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs
= {
1581 .process
= sdma_v5_0_process_illegal_inst_irq
,
1584 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device
*adev
)
1586 adev
->sdma
.trap_irq
.num_types
= AMDGPU_SDMA_IRQ_LAST
;
1587 adev
->sdma
.trap_irq
.funcs
= &sdma_v5_0_trap_irq_funcs
;
1588 adev
->sdma
.illegal_inst_irq
.funcs
= &sdma_v5_0_illegal_inst_irq_funcs
;
1592 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1594 * @ring: amdgpu_ring structure holding ring information
1595 * @src_offset: src GPU address
1596 * @dst_offset: dst GPU address
1597 * @byte_count: number of bytes to xfer
1599 * Copy GPU buffers using the DMA engine (NAVI10).
1600 * Used by the amdgpu ttm implementation to move pages if
1601 * registered as the asic copy callback.
1603 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib
*ib
,
1604 uint64_t src_offset
,
1605 uint64_t dst_offset
,
1606 uint32_t byte_count
)
1608 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY
) |
1609 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR
);
1610 ib
->ptr
[ib
->length_dw
++] = byte_count
- 1;
1611 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
1612 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src_offset
);
1613 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src_offset
);
1614 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1615 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1619 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1621 * @ring: amdgpu_ring structure holding ring information
1622 * @src_data: value to write to buffer
1623 * @dst_offset: dst GPU address
1624 * @byte_count: number of bytes to xfer
1626 * Fill GPU buffers using the DMA engine (NAVI10).
1628 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib
*ib
,
1630 uint64_t dst_offset
,
1631 uint32_t byte_count
)
1633 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL
);
1634 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1635 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1636 ib
->ptr
[ib
->length_dw
++] = src_data
;
1637 ib
->ptr
[ib
->length_dw
++] = byte_count
- 1;
1640 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs
= {
1641 .copy_max_bytes
= 0x400000,
1643 .emit_copy_buffer
= sdma_v5_0_emit_copy_buffer
,
1645 .fill_max_bytes
= 0x400000,
1647 .emit_fill_buffer
= sdma_v5_0_emit_fill_buffer
,
1650 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device
*adev
)
1652 if (adev
->mman
.buffer_funcs
== NULL
) {
1653 adev
->mman
.buffer_funcs
= &sdma_v5_0_buffer_funcs
;
1654 adev
->mman
.buffer_funcs_ring
= &adev
->sdma
.instance
[0].ring
;
1658 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs
= {
1659 .copy_pte_num_dw
= 7,
1660 .copy_pte
= sdma_v5_0_vm_copy_pte
,
1661 .write_pte
= sdma_v5_0_vm_write_pte
,
1662 .set_pte_pde
= sdma_v5_0_vm_set_pte_pde
,
1665 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device
*adev
)
1667 struct drm_gpu_scheduler
*sched
;
1670 if (adev
->vm_manager
.vm_pte_funcs
== NULL
) {
1671 adev
->vm_manager
.vm_pte_funcs
= &sdma_v5_0_vm_pte_funcs
;
1672 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1673 sched
= &adev
->sdma
.instance
[i
].ring
.sched
;
1674 adev
->vm_manager
.vm_pte_rqs
[i
] =
1675 &sched
->sched_rq
[DRM_SCHED_PRIORITY_KERNEL
];
1677 adev
->vm_manager
.vm_pte_num_rqs
= adev
->sdma
.num_instances
;
1681 const struct amdgpu_ip_block_version sdma_v5_0_ip_block
= {
1682 .type
= AMD_IP_BLOCK_TYPE_SDMA
,
1686 .funcs
= &sdma_v5_0_ip_funcs
,