drivers/gpu/drm/amd/amdgpu/si_dpm.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef __SI_DPM_H__
  24 #define __SI_DPM_H__
  25
  26 #include "amdgpu_atombios.h"
  27 #include "sislands_smc.h"
  28
  29 #define MC_CG_CONFIG                                    0x96f
  30 #define MC_ARB_CG                                       0x9fa
  31 #define         CG_ARB_REQ(x)                           ((x) << 0)
  32 #define         CG_ARB_REQ_MASK                         (0xff << 0)
  33
  34 #define MC_ARB_DRAM_TIMING_1                            0x9fc
  35 #define MC_ARB_DRAM_TIMING_2                            0x9fd
  36 #define MC_ARB_DRAM_TIMING_3                            0x9fe
  37 #define MC_ARB_DRAM_TIMING2_1                           0x9ff
  38 #define MC_ARB_DRAM_TIMING2_2                           0xa00
  39 #define MC_ARB_DRAM_TIMING2_3                           0xa01
  40
  41 #define MAX_NO_OF_MVDD_VALUES 2
  42 #define MAX_NO_VREG_STEPS 32
  43 #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16
  44 #define SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 32
  45 #define SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20
  46 #define RV770_ASI_DFLT                                1000
  47 #define CYPRESS_HASI_DFLT                               400000
  48 #define PCIE_PERF_REQ_PECI_GEN1         2
  49 #define PCIE_PERF_REQ_PECI_GEN2         3
  50 #define PCIE_PERF_REQ_PECI_GEN3         4
  51 #define RV770_DEFAULT_VCLK_FREQ  53300 /* 10 khz */
  52 #define RV770_DEFAULT_DCLK_FREQ  40000 /* 10 khz */
  53
  54 #define SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE 16
  55
  56 #define RV770_SMC_TABLE_ADDRESS 0xB000
  57 #define RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE    3
  58
  59 #define SMC_STROBE_RATIO    0x0F
  60 #define SMC_STROBE_ENABLE   0x10
  61
  62 #define SMC_MC_EDC_RD_FLAG  0x01
  63 #define SMC_MC_EDC_WR_FLAG  0x02
  64 #define SMC_MC_RTT_ENABLE   0x04
  65 #define SMC_MC_STUTTER_EN   0x08
  66
  67 #define RV770_SMC_VOLTAGEMASK_VDDC 0
  68 #define RV770_SMC_VOLTAGEMASK_MVDD 1
  69 #define RV770_SMC_VOLTAGEMASK_VDDCI 2
  70 #define RV770_SMC_VOLTAGEMASK_MAX  4
  71
  72 #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16
  73 #define NISLANDS_SMC_STROBE_RATIO    0x0F
  74 #define NISLANDS_SMC_STROBE_ENABLE   0x10
  75
  76 #define NISLANDS_SMC_MC_EDC_RD_FLAG  0x01
  77 #define NISLANDS_SMC_MC_EDC_WR_FLAG  0x02
  78 #define NISLANDS_SMC_MC_RTT_ENABLE   0x04
  79 #define NISLANDS_SMC_MC_STUTTER_EN   0x08
  80
  81 #define MAX_NO_VREG_STEPS 32
  82
  83 #define NISLANDS_SMC_VOLTAGEMASK_VDDC  0
  84 #define NISLANDS_SMC_VOLTAGEMASK_MVDD  1
  85 #define NISLANDS_SMC_VOLTAGEMASK_VDDCI 2
  86 #define NISLANDS_SMC_VOLTAGEMASK_MAX   4
  87
  88 #define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT               0
  89 #define SISLANDS_MCREGISTERTABLE_ACPI_SLOT                  1
  90 #define SISLANDS_MCREGISTERTABLE_ULV_SLOT                   2
  91 #define SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT     3
  92
  93 #define SISLANDS_LEAKAGE_INDEX0     0xff01
  94 #define SISLANDS_MAX_LEAKAGE_COUNT  4
  95
  96 #define SISLANDS_MAX_HARDWARE_POWERLEVELS 5
  97 #define SISLANDS_INITIAL_STATE_ARB_INDEX    0
  98 #define SISLANDS_ACPI_STATE_ARB_INDEX       1
  99 #define SISLANDS_ULV_STATE_ARB_INDEX        2
 100 #define SISLANDS_DRIVER_STATE_ARB_INDEX     3
 101
 102 #define SISLANDS_DPM2_MAX_PULSE_SKIP        256
 103
 104 #define SISLANDS_DPM2_NEAR_TDP_DEC          10
 105 #define SISLANDS_DPM2_ABOVE_SAFE_INC        5
 106 #define SISLANDS_DPM2_BELOW_SAFE_INC        20
 107
 108 #define SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT            80
 109
 110 #define SISLANDS_DPM2_MAXPS_PERCENT_H                   99
 111 #define SISLANDS_DPM2_MAXPS_PERCENT_M                   99
 112
 113 #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER                 0x3FFF
 114 #define SISLANDS_DPM2_SQ_RAMP_MIN_POWER                 0x12
 115 #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA           0x15
 116 #define SISLANDS_DPM2_SQ_RAMP_STI_SIZE                  0x1E
 117 #define SISLANDS_DPM2_SQ_RAMP_LTI_RATIO                 0xF
 118
 119 #define SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN         10
 120
 121 #define SISLANDS_VRC_DFLT                               0xC000B3
 122 #define SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT             1687
 123 #define SISLANDS_CGULVPARAMETER_DFLT                    0x00040035
 124 #define SISLANDS_CGULVCONTROL_DFLT                      0x1f007550
 125
 126 #define SI_ASI_DFLT                                10000
 127 #define SI_BSP_DFLT                                0x41EB
 128 #define SI_BSU_DFLT                                0x2
 129 #define SI_AH_DFLT                                 5
 130 #define SI_RLP_DFLT                                25
 131 #define SI_RMP_DFLT                                65
 132 #define SI_LHP_DFLT                                40
 133 #define SI_LMP_DFLT                                15
 134 #define SI_TD_DFLT                                 0
 135 #define SI_UTC_DFLT_00                             0x24
 136 #define SI_UTC_DFLT_01                             0x22
 137 #define SI_UTC_DFLT_02                             0x22
 138 #define SI_UTC_DFLT_03                             0x22
 139 #define SI_UTC_DFLT_04                             0x22
 140 #define SI_UTC_DFLT_05                             0x22
 141 #define SI_UTC_DFLT_06                             0x22
 142 #define SI_UTC_DFLT_07                             0x22
 143 #define SI_UTC_DFLT_08                             0x22
 144 #define SI_UTC_DFLT_09                             0x22
 145 #define SI_UTC_DFLT_10                             0x22
 146 #define SI_UTC_DFLT_11                             0x22
 147 #define SI_UTC_DFLT_12                             0x22
 148 #define SI_UTC_DFLT_13                             0x22
 149 #define SI_UTC_DFLT_14                             0x22
 150 #define SI_DTC_DFLT_00                             0x24
 151 #define SI_DTC_DFLT_01                             0x22
 152 #define SI_DTC_DFLT_02                             0x22
 153 #define SI_DTC_DFLT_03                             0x22
 154 #define SI_DTC_DFLT_04                             0x22
 155 #define SI_DTC_DFLT_05                             0x22
 156 #define SI_DTC_DFLT_06                             0x22
 157 #define SI_DTC_DFLT_07                             0x22
 158 #define SI_DTC_DFLT_08                             0x22
 159 #define SI_DTC_DFLT_09                             0x22
 160 #define SI_DTC_DFLT_10                             0x22
 161 #define SI_DTC_DFLT_11                             0x22
 162 #define SI_DTC_DFLT_12                             0x22
 163 #define SI_DTC_DFLT_13                             0x22
 164 #define SI_DTC_DFLT_14                             0x22
 165 #define SI_VRC_DFLT                                0x0000C003
 166 #define SI_VOLTAGERESPONSETIME_DFLT                1000
 167 #define SI_BACKBIASRESPONSETIME_DFLT               1000
 168 #define SI_VRU_DFLT                                0x3
 169 #define SI_SPLLSTEPTIME_DFLT                       0x1000
 170 #define SI_SPLLSTEPUNIT_DFLT                       0x3
 171 #define SI_TPU_DFLT                                0
 172 #define SI_TPC_DFLT                                0x200
 173 #define SI_SSTU_DFLT                               0
 174 #define SI_SST_DFLT                                0x00C8
 175 #define SI_GICST_DFLT                              0x200
 176 #define SI_FCT_DFLT                                0x0400
 177 #define SI_FCTU_DFLT                               0
 178 #define SI_CTXCGTT3DRPHC_DFLT                      0x20
 179 #define SI_CTXCGTT3DRSDC_DFLT                      0x40
 180 #define SI_VDDC3DOORPHC_DFLT                       0x100
 181 #define SI_VDDC3DOORSDC_DFLT                       0x7
 182 #define SI_VDDC3DOORSU_DFLT                        0
 183 #define SI_MPLLLOCKTIME_DFLT                       100
 184 #define SI_MPLLRESETTIME_DFLT                      150
 185 #define SI_VCOSTEPPCT_DFLT                          20
 186 #define SI_ENDINGVCOSTEPPCT_DFLT                    5
 187 #define SI_REFERENCEDIVIDER_DFLT                    4
 188
 189 #define SI_PM_NUMBER_OF_TC 15
 190 #define SI_PM_NUMBER_OF_SCLKS 20
 191 #define SI_PM_NUMBER_OF_MCLKS 4
 192 #define SI_PM_NUMBER_OF_VOLTAGE_LEVELS 4
 193 #define SI_PM_NUMBER_OF_ACTIVITY_LEVELS 3
 194
 195 /* XXX are these ok? */
 196 #define SI_TEMP_RANGE_MIN (90 * 1000)
 197 #define SI_TEMP_RANGE_MAX (120 * 1000)
 198
 199 #define FDO_PWM_MODE_STATIC  1
 200 #define FDO_PWM_MODE_STATIC_RPM 5
 201
 202 enum ni_dc_cac_level
 203 {
 204         NISLANDS_DCCAC_LEVEL_0 = 0,
 205         NISLANDS_DCCAC_LEVEL_1,
 206         NISLANDS_DCCAC_LEVEL_2,
 207         NISLANDS_DCCAC_LEVEL_3,
 208         NISLANDS_DCCAC_LEVEL_4,
 209         NISLANDS_DCCAC_LEVEL_5,
 210         NISLANDS_DCCAC_LEVEL_6,
 211         NISLANDS_DCCAC_LEVEL_7,
 212         NISLANDS_DCCAC_MAX_LEVELS
 213 };
 214
 215 enum si_cac_config_reg_type
 216 {
 217         SISLANDS_CACCONFIG_MMR = 0,
 218         SISLANDS_CACCONFIG_CGIND,
 219         SISLANDS_CACCONFIG_MAX
 220 };
 221
 222 enum si_power_level {
 223         SI_POWER_LEVEL_LOW = 0,
 224         SI_POWER_LEVEL_MEDIUM = 1,
 225         SI_POWER_LEVEL_HIGH = 2,
 226         SI_POWER_LEVEL_CTXSW = 3,
 227 };
 228
 229 enum si_td {
 230         SI_TD_AUTO,
 231         SI_TD_UP,
 232         SI_TD_DOWN,
 233 };
 234
 235 enum si_display_watermark {
 236         SI_DISPLAY_WATERMARK_LOW = 0,
 237         SI_DISPLAY_WATERMARK_HIGH = 1,
 238 };
 239
 240 enum si_display_gap
 241 {
 242     SI_PM_DISPLAY_GAP_VBLANK_OR_WM = 0,
 243     SI_PM_DISPLAY_GAP_VBLANK       = 1,
 244     SI_PM_DISPLAY_GAP_WATERMARK    = 2,
 245     SI_PM_DISPLAY_GAP_IGNORE       = 3,
 246 };
 247
 248 extern const struct amd_ip_funcs si_dpm_ip_funcs;
 249 extern const struct amd_pm_funcs si_dpm_funcs;
 250
 251 struct ni_leakage_coeffients
 252 {
 253         u32 at;
 254         u32 bt;
 255         u32 av;
 256         u32 bv;
 257         s32 t_slope;
 258         s32 t_intercept;
 259         u32 t_ref;
 260 };
 261
 262 struct SMC_Evergreen_MCRegisterAddress
 263 {
 264     uint16_t s0;
 265     uint16_t s1;
 266 };
 267
 268 typedef struct SMC_Evergreen_MCRegisterAddress SMC_Evergreen_MCRegisterAddress;
 269
 270 struct evergreen_mc_reg_entry {
 271         u32 mclk_max;
 272         u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];
 273 };
 274
 275 struct evergreen_mc_reg_table {
 276         u8 last;
 277         u8 num_entries;
 278         u16 valid_flag;
 279         struct evergreen_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
 280         SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];
 281 };
 282
 283 struct SMC_Evergreen_MCRegisterSet
 284 {
 285     uint32_t value[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];
 286 };
 287
 288 typedef struct SMC_Evergreen_MCRegisterSet SMC_Evergreen_MCRegisterSet;
 289
 290 struct SMC_Evergreen_MCRegisters
 291 {
 292     uint8_t                             last;
 293     uint8_t                             reserved[3];
 294     SMC_Evergreen_MCRegisterAddress     address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];
 295     SMC_Evergreen_MCRegisterSet         data[5];
 296 };
 297
 298 typedef struct SMC_Evergreen_MCRegisters SMC_Evergreen_MCRegisters;
 299
 300 struct SMC_NIslands_MCRegisterSet
 301 {
 302     uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
 303 };
 304
 305 typedef struct SMC_NIslands_MCRegisterSet SMC_NIslands_MCRegisterSet;
 306
 307 struct ni_mc_reg_entry {
 308         u32 mclk_max;
 309         u32 mc_data[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
 310 };
 311
 312 struct SMC_NIslands_MCRegisterAddress
 313 {
 314     uint16_t s0;
 315     uint16_t s1;
 316 };
 317
 318 typedef struct SMC_NIslands_MCRegisterAddress SMC_NIslands_MCRegisterAddress;
 319
 320 struct SMC_NIslands_MCRegisters
 321 {
 322     uint8_t                             last;
 323     uint8_t                             reserved[3];
 324     SMC_NIslands_MCRegisterAddress      address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
 325     SMC_NIslands_MCRegisterSet          data[SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT];
 326 };
 327
 328 typedef struct SMC_NIslands_MCRegisters SMC_NIslands_MCRegisters;
 329
 330 struct evergreen_ulv_param {
 331         bool supported;
 332         struct rv7xx_pl *pl;
 333 };
 334
 335 struct evergreen_arb_registers {
 336         u32 mc_arb_dram_timing;
 337         u32 mc_arb_dram_timing2;
 338         u32 mc_arb_rfsh_rate;
 339         u32 mc_arb_burst_time;
 340 };
 341
 342 struct at {
 343         u32 rlp;
 344         u32 rmp;
 345         u32 lhp;
 346         u32 lmp;
 347 };
 348
 349 struct ni_clock_registers {
 350         u32 cg_spll_func_cntl;
 351         u32 cg_spll_func_cntl_2;
 352         u32 cg_spll_func_cntl_3;
 353         u32 cg_spll_func_cntl_4;
 354         u32 cg_spll_spread_spectrum;
 355         u32 cg_spll_spread_spectrum_2;
 356         u32 mclk_pwrmgt_cntl;
 357         u32 dll_cntl;
 358         u32 mpll_ad_func_cntl;
 359         u32 mpll_ad_func_cntl_2;
 360         u32 mpll_dq_func_cntl;
 361         u32 mpll_dq_func_cntl_2;
 362         u32 mpll_ss1;
 363         u32 mpll_ss2;
 364 };
 365
 366 struct RV770_SMC_SCLK_VALUE
 367 {
 368     uint32_t        vCG_SPLL_FUNC_CNTL;
 369     uint32_t        vCG_SPLL_FUNC_CNTL_2;
 370     uint32_t        vCG_SPLL_FUNC_CNTL_3;
 371     uint32_t        vCG_SPLL_SPREAD_SPECTRUM;
 372     uint32_t        vCG_SPLL_SPREAD_SPECTRUM_2;
 373     uint32_t        sclk_value;
 374 };
 375
 376 typedef struct RV770_SMC_SCLK_VALUE RV770_SMC_SCLK_VALUE;
 377
 378 struct RV770_SMC_MCLK_VALUE
 379 {
 380     uint32_t        vMPLL_AD_FUNC_CNTL;
 381     uint32_t        vMPLL_AD_FUNC_CNTL_2;
 382     uint32_t        vMPLL_DQ_FUNC_CNTL;
 383     uint32_t        vMPLL_DQ_FUNC_CNTL_2;
 384     uint32_t        vMCLK_PWRMGT_CNTL;
 385     uint32_t        vDLL_CNTL;
 386     uint32_t        vMPLL_SS;
 387     uint32_t        vMPLL_SS2;
 388     uint32_t        mclk_value;
 389 };
 390
 391 typedef struct RV770_SMC_MCLK_VALUE RV770_SMC_MCLK_VALUE;
 392
 393
 394 struct RV730_SMC_MCLK_VALUE
 395 {
 396     uint32_t        vMCLK_PWRMGT_CNTL;
 397     uint32_t        vDLL_CNTL;
 398     uint32_t        vMPLL_FUNC_CNTL;
 399     uint32_t        vMPLL_FUNC_CNTL2;
 400     uint32_t        vMPLL_FUNC_CNTL3;
 401     uint32_t        vMPLL_SS;
 402     uint32_t        vMPLL_SS2;
 403     uint32_t        mclk_value;
 404 };
 405
 406 typedef struct RV730_SMC_MCLK_VALUE RV730_SMC_MCLK_VALUE;
 407
 408 struct RV770_SMC_VOLTAGE_VALUE
 409 {
 410     uint16_t             value;
 411     uint8_t              index;
 412     uint8_t              padding;
 413 };
 414
 415 typedef struct RV770_SMC_VOLTAGE_VALUE RV770_SMC_VOLTAGE_VALUE;
 416
 417 union RV7XX_SMC_MCLK_VALUE
 418 {
 419     RV770_SMC_MCLK_VALUE    mclk770;
 420     RV730_SMC_MCLK_VALUE    mclk730;
 421 };
 422
 423 typedef union RV7XX_SMC_MCLK_VALUE RV7XX_SMC_MCLK_VALUE, *LPRV7XX_SMC_MCLK_VALUE;
 424
 425 struct RV770_SMC_HW_PERFORMANCE_LEVEL
 426 {
 427     uint8_t                 arbValue;
 428     union{
 429         uint8_t             seqValue;
 430         uint8_t             ACIndex;
 431     };
 432     uint8_t                 displayWatermark;
 433     uint8_t                 gen2PCIE;
 434     uint8_t                 gen2XSP;
 435     uint8_t                 backbias;
 436     uint8_t                 strobeMode;
 437     uint8_t                 mcFlags;
 438     uint32_t                aT;
 439     uint32_t                bSP;
 440     RV770_SMC_SCLK_VALUE    sclk;
 441     RV7XX_SMC_MCLK_VALUE    mclk;
 442     RV770_SMC_VOLTAGE_VALUE vddc;
 443     RV770_SMC_VOLTAGE_VALUE mvdd;
 444     RV770_SMC_VOLTAGE_VALUE vddci;
 445     uint8_t                 reserved1;
 446     uint8_t                 reserved2;
 447     uint8_t                 stateFlags;
 448     uint8_t                 padding;
 449 };
 450
 451 typedef struct RV770_SMC_HW_PERFORMANCE_LEVEL RV770_SMC_HW_PERFORMANCE_LEVEL;
 452
 453 struct RV770_SMC_SWSTATE
 454 {
 455     uint8_t           flags;
 456     uint8_t           padding1;
 457     uint8_t           padding2;
 458     uint8_t           padding3;
 459     RV770_SMC_HW_PERFORMANCE_LEVEL levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
 460 };
 461
 462 typedef struct RV770_SMC_SWSTATE RV770_SMC_SWSTATE;
 463
 464 struct RV770_SMC_VOLTAGEMASKTABLE
 465 {
 466     uint8_t  highMask[RV770_SMC_VOLTAGEMASK_MAX];
 467     uint32_t lowMask[RV770_SMC_VOLTAGEMASK_MAX];
 468 };
 469
 470 typedef struct RV770_SMC_VOLTAGEMASKTABLE RV770_SMC_VOLTAGEMASKTABLE;
 471
 472 struct RV770_SMC_STATETABLE
 473 {
 474     uint8_t             thermalProtectType;
 475     uint8_t             systemFlags;
 476     uint8_t             maxVDDCIndexInPPTable;
 477     uint8_t             extraFlags;
 478     uint8_t             highSMIO[MAX_NO_VREG_STEPS];
 479     uint32_t            lowSMIO[MAX_NO_VREG_STEPS];
 480     RV770_SMC_VOLTAGEMASKTABLE voltageMaskTable;
 481     RV770_SMC_SWSTATE   initialState;
 482     RV770_SMC_SWSTATE   ACPIState;
 483     RV770_SMC_SWSTATE   driverState;
 484     RV770_SMC_SWSTATE   ULVState;
 485 };
 486
 487 typedef struct RV770_SMC_STATETABLE RV770_SMC_STATETABLE;
 488
 489 struct vddc_table_entry {
 490         u16 vddc;
 491         u8 vddc_index;
 492         u8 high_smio;
 493         u32 low_smio;
 494 };
 495
 496 struct rv770_clock_registers {
 497         u32 cg_spll_func_cntl;
 498         u32 cg_spll_func_cntl_2;
 499         u32 cg_spll_func_cntl_3;
 500         u32 cg_spll_spread_spectrum;
 501         u32 cg_spll_spread_spectrum_2;
 502         u32 mpll_ad_func_cntl;
 503         u32 mpll_ad_func_cntl_2;
 504         u32 mpll_dq_func_cntl;
 505         u32 mpll_dq_func_cntl_2;
 506         u32 mclk_pwrmgt_cntl;
 507         u32 dll_cntl;
 508         u32 mpll_ss1;
 509         u32 mpll_ss2;
 510 };
 511
 512 struct rv730_clock_registers {
 513         u32 cg_spll_func_cntl;
 514         u32 cg_spll_func_cntl_2;
 515         u32 cg_spll_func_cntl_3;
 516         u32 cg_spll_spread_spectrum;
 517         u32 cg_spll_spread_spectrum_2;
 518         u32 mclk_pwrmgt_cntl;
 519         u32 dll_cntl;
 520         u32 mpll_func_cntl;
 521         u32 mpll_func_cntl2;
 522         u32 mpll_func_cntl3;
 523         u32 mpll_ss;
 524         u32 mpll_ss2;
 525 };
 526
 527 union r7xx_clock_registers {
 528         struct rv770_clock_registers rv770;
 529         struct rv730_clock_registers rv730;
 530 };
 531
 532 struct rv7xx_power_info {
 533         /* flags */
 534         bool mem_gddr5;
 535         bool pcie_gen2;
 536         bool dynamic_pcie_gen2;
 537         bool acpi_pcie_gen2;
 538         bool boot_in_gen2;
 539         bool voltage_control; /* vddc */
 540         bool mvdd_control;
 541         bool sclk_ss;
 542         bool mclk_ss;
 543         bool dynamic_ss;
 544         bool gfx_clock_gating;
 545         bool mg_clock_gating;
 546         bool mgcgtssm;
 547         bool power_gating;
 548         bool thermal_protection;
 549         bool display_gap;
 550         bool dcodt;
 551         bool ulps;
 552         /* registers */
 553         union r7xx_clock_registers clk_regs;
 554         u32 s0_vid_lower_smio_cntl;
 555         /* voltage */
 556         u32 vddc_mask_low;
 557         u32 mvdd_mask_low;
 558         u32 mvdd_split_frequency;
 559         u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES];
 560         u16 max_vddc;
 561         u16 max_vddc_in_table;
 562         u16 min_vddc_in_table;
 563         struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS];
 564         u8 valid_vddc_entries;
 565         /* dc odt */
 566         u32 mclk_odt_threshold;
 567         u8 odt_value_0[2];
 568         u8 odt_value_1[2];
 569         /* stored values */
 570         u32 boot_sclk;
 571         u16 acpi_vddc;
 572         u32 ref_div;
 573         u32 active_auto_throttle_sources;
 574         u32 mclk_stutter_mode_threshold;
 575         u32 mclk_strobe_mode_threshold;
 576         u32 mclk_edc_enable_threshold;
 577         u32 bsp;
 578         u32 bsu;
 579         u32 pbsp;
 580         u32 pbsu;
 581         u32 dsp;
 582         u32 psp;
 583         u32 asi;
 584         u32 pasi;
 585         u32 vrc;
 586         u32 restricted_levels;
 587         u32 rlp;
 588         u32 rmp;
 589         u32 lhp;
 590         u32 lmp;
 591         /* smc offsets */
 592         u16 state_table_start;
 593         u16 soft_regs_start;
 594         u16 sram_end;
 595         /* scratch structs */
 596         RV770_SMC_STATETABLE smc_statetable;
 597 };
 598
 599 struct rv7xx_pl {
 600         u32 sclk;
 601         u32 mclk;
 602         u16 vddc;
 603         u16 vddci; /* eg+ only */
 604         u32 flags;
 605         enum amdgpu_pcie_gen pcie_gen; /* si+ only */
 606 };
 607
 608 struct rv7xx_ps {
 609         struct rv7xx_pl high;
 610         struct rv7xx_pl medium;
 611         struct rv7xx_pl low;
 612         bool dc_compatible;
 613 };
 614
 615 struct si_ps {
 616         u16 performance_level_count;
 617         bool dc_compatible;
 618         struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
 619 };
 620
 621 struct ni_mc_reg_table {
 622         u8 last;
 623         u8 num_entries;
 624         u16 valid_flag;
 625         struct ni_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
 626         SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
 627 };
 628
 629 struct ni_cac_data
 630 {
 631         struct ni_leakage_coeffients leakage_coefficients;
 632         u32 i_leakage;
 633         s32 leakage_minimum_temperature;
 634         u32 pwr_const;
 635         u32 dc_cac_value;
 636         u32 bif_cac_value;
 637         u32 lkge_pwr;
 638         u8 mc_wr_weight;
 639         u8 mc_rd_weight;
 640         u8 allow_ovrflw;
 641         u8 num_win_tdp;
 642         u8 l2num_win_tdp;
 643         u8 lts_truncate_n;
 644 };
 645
 646 struct evergreen_power_info {
 647         /* must be first! */
 648         struct rv7xx_power_info rv7xx;
 649         /* flags */
 650         bool vddci_control;
 651         bool dynamic_ac_timing;
 652         bool abm;
 653         bool mcls;
 654         bool light_sleep;
 655         bool memory_transition;
 656         bool pcie_performance_request;
 657         bool pcie_performance_request_registered;
 658         bool sclk_deep_sleep;
 659         bool dll_default_on;
 660         bool ls_clock_gating;
 661         bool smu_uvd_hs;
 662         bool uvd_enabled;
 663         /* stored values */
 664         u16 acpi_vddci;
 665         u8 mvdd_high_index;
 666         u8 mvdd_low_index;
 667         u32 mclk_edc_wr_enable_threshold;
 668         struct evergreen_mc_reg_table mc_reg_table;
 669         struct atom_voltage_table vddc_voltage_table;
 670         struct atom_voltage_table vddci_voltage_table;
 671         struct evergreen_arb_registers bootup_arb_registers;
 672         struct evergreen_ulv_param ulv;
 673         struct at ats[2];
 674         /* smc offsets */
 675         u16 mc_reg_table_start;
 676         struct amdgpu_ps current_rps;
 677         struct rv7xx_ps current_ps;
 678         struct amdgpu_ps requested_rps;
 679         struct rv7xx_ps requested_ps;
 680 };
 681
 682 struct PP_NIslands_Dpm2PerfLevel
 683 {
 684     uint8_t     MaxPS;
 685     uint8_t     TgtAct;
 686     uint8_t     MaxPS_StepInc;
 687     uint8_t     MaxPS_StepDec;
 688     uint8_t     PSST;
 689     uint8_t     NearTDPDec;
 690     uint8_t     AboveSafeInc;
 691     uint8_t     BelowSafeInc;
 692     uint8_t     PSDeltaLimit;
 693     uint8_t     PSDeltaWin;
 694     uint8_t     Reserved[6];
 695 };
 696
 697 typedef struct PP_NIslands_Dpm2PerfLevel PP_NIslands_Dpm2PerfLevel;
 698
 699 struct PP_NIslands_DPM2Parameters
 700 {
 701     uint32_t    TDPLimit;
 702     uint32_t    NearTDPLimit;
 703     uint32_t    SafePowerLimit;
 704     uint32_t    PowerBoostLimit;
 705 };
 706 typedef struct PP_NIslands_DPM2Parameters PP_NIslands_DPM2Parameters;
 707
 708 struct NISLANDS_SMC_SCLK_VALUE
 709 {
 710     uint32_t        vCG_SPLL_FUNC_CNTL;
 711     uint32_t        vCG_SPLL_FUNC_CNTL_2;
 712     uint32_t        vCG_SPLL_FUNC_CNTL_3;
 713     uint32_t        vCG_SPLL_FUNC_CNTL_4;
 714     uint32_t        vCG_SPLL_SPREAD_SPECTRUM;
 715     uint32_t        vCG_SPLL_SPREAD_SPECTRUM_2;
 716     uint32_t        sclk_value;
 717 };
 718
 719 typedef struct NISLANDS_SMC_SCLK_VALUE NISLANDS_SMC_SCLK_VALUE;
 720
 721 struct NISLANDS_SMC_MCLK_VALUE
 722 {
 723     uint32_t        vMPLL_FUNC_CNTL;
 724     uint32_t        vMPLL_FUNC_CNTL_1;
 725     uint32_t        vMPLL_FUNC_CNTL_2;
 726     uint32_t        vMPLL_AD_FUNC_CNTL;
 727     uint32_t        vMPLL_AD_FUNC_CNTL_2;
 728     uint32_t        vMPLL_DQ_FUNC_CNTL;
 729     uint32_t        vMPLL_DQ_FUNC_CNTL_2;
 730     uint32_t        vMCLK_PWRMGT_CNTL;
 731     uint32_t        vDLL_CNTL;
 732     uint32_t        vMPLL_SS;
 733     uint32_t        vMPLL_SS2;
 734     uint32_t        mclk_value;
 735 };
 736
 737 typedef struct NISLANDS_SMC_MCLK_VALUE NISLANDS_SMC_MCLK_VALUE;
 738
 739 struct NISLANDS_SMC_VOLTAGE_VALUE
 740 {
 741     uint16_t             value;
 742     uint8_t              index;
 743     uint8_t              padding;
 744 };
 745
 746 typedef struct NISLANDS_SMC_VOLTAGE_VALUE NISLANDS_SMC_VOLTAGE_VALUE;
 747
 748 struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL
 749 {
 750     uint8_t                     arbValue;
 751     uint8_t                     ACIndex;
 752     uint8_t                     displayWatermark;
 753     uint8_t                     gen2PCIE;
 754     uint8_t                     reserved1;
 755     uint8_t                     reserved2;
 756     uint8_t                     strobeMode;
 757     uint8_t                     mcFlags;
 758     uint32_t                    aT;
 759     uint32_t                    bSP;
 760     NISLANDS_SMC_SCLK_VALUE     sclk;
 761     NISLANDS_SMC_MCLK_VALUE     mclk;
 762     NISLANDS_SMC_VOLTAGE_VALUE  vddc;
 763     NISLANDS_SMC_VOLTAGE_VALUE  mvdd;
 764     NISLANDS_SMC_VOLTAGE_VALUE  vddci;
 765     NISLANDS_SMC_VOLTAGE_VALUE  std_vddc;
 766     uint32_t                    powergate_en;
 767     uint8_t                     hUp;
 768     uint8_t                     hDown;
 769     uint8_t                     stateFlags;
 770     uint8_t                     arbRefreshState;
 771     uint32_t                    SQPowerThrottle;
 772     uint32_t                    SQPowerThrottle_2;
 773     uint32_t                    reserved[2];
 774     PP_NIslands_Dpm2PerfLevel   dpm2;
 775 };
 776
 777 typedef struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL NISLANDS_SMC_HW_PERFORMANCE_LEVEL;
 778
 779 struct NISLANDS_SMC_SWSTATE
 780 {
 781     uint8_t                             flags;
 782     uint8_t                             levelCount;
 783     uint8_t                             padding2;
 784     uint8_t                             padding3;
 785     NISLANDS_SMC_HW_PERFORMANCE_LEVEL   levels[1];
 786 };
 787
 788 typedef struct NISLANDS_SMC_SWSTATE NISLANDS_SMC_SWSTATE;
 789
 790 struct NISLANDS_SMC_VOLTAGEMASKTABLE
 791 {
 792     uint8_t  highMask[NISLANDS_SMC_VOLTAGEMASK_MAX];
 793     uint32_t lowMask[NISLANDS_SMC_VOLTAGEMASK_MAX];
 794 };
 795
 796 typedef struct NISLANDS_SMC_VOLTAGEMASKTABLE NISLANDS_SMC_VOLTAGEMASKTABLE;
 797
 798 #define NISLANDS_MAX_NO_VREG_STEPS 32
 799
 800 struct NISLANDS_SMC_STATETABLE
 801 {
 802     uint8_t                             thermalProtectType;
 803     uint8_t                             systemFlags;
 804     uint8_t                             maxVDDCIndexInPPTable;
 805     uint8_t                             extraFlags;
 806     uint8_t                             highSMIO[NISLANDS_MAX_NO_VREG_STEPS];
 807     uint32_t                            lowSMIO[NISLANDS_MAX_NO_VREG_STEPS];
 808     NISLANDS_SMC_VOLTAGEMASKTABLE       voltageMaskTable;
 809     PP_NIslands_DPM2Parameters          dpm2Params;
 810     NISLANDS_SMC_SWSTATE                initialState;
 811     NISLANDS_SMC_SWSTATE                ACPIState;
 812     NISLANDS_SMC_SWSTATE                ULVState;
 813     NISLANDS_SMC_SWSTATE                driverState;
 814     NISLANDS_SMC_HW_PERFORMANCE_LEVEL   dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1];
 815 };
 816
 817 typedef struct NISLANDS_SMC_STATETABLE NISLANDS_SMC_STATETABLE;
 818
 819 struct ni_power_info {
 820         /* must be first! */
 821         struct evergreen_power_info eg;
 822         struct ni_clock_registers clock_registers;
 823         struct ni_mc_reg_table mc_reg_table;
 824         u32 mclk_rtt_mode_threshold;
 825         /* flags */
 826         bool use_power_boost_limit;
 827         bool support_cac_long_term_average;
 828         bool cac_enabled;
 829         bool cac_configuration_required;
 830         bool driver_calculate_cac_leakage;
 831         bool pc_enabled;
 832         bool enable_power_containment;
 833         bool enable_cac;
 834         bool enable_sq_ramping;
 835         /* smc offsets */
 836         u16 arb_table_start;
 837         u16 fan_table_start;
 838         u16 cac_table_start;
 839         u16 spll_table_start;
 840         /* CAC stuff */
 841         struct ni_cac_data cac_data;
 842         u32 dc_cac_table[NISLANDS_DCCAC_MAX_LEVELS];
 843         const struct ni_cac_weights *cac_weights;
 844         u8 lta_window_size;
 845         u8 lts_truncate;
 846         struct si_ps current_ps;
 847         struct si_ps requested_ps;
 848         /* scratch structs */
 849         SMC_NIslands_MCRegisters smc_mc_reg_table;
 850         NISLANDS_SMC_STATETABLE smc_statetable;
 851 };
 852
 853 struct si_cac_config_reg
 854 {
 855         u32 offset;
 856         u32 mask;
 857         u32 shift;
 858         u32 value;
 859         enum si_cac_config_reg_type type;
 860 };
 861
 862 struct si_powertune_data
 863 {
 864         u32 cac_window;
 865         u32 l2_lta_window_size_default;
 866         u8 lts_truncate_default;
 867         u8 shift_n_default;
 868         u8 operating_temp;
 869         struct ni_leakage_coeffients leakage_coefficients;
 870         u32 fixed_kt;
 871         u32 lkge_lut_v0_percent;
 872         u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];
 873         bool enable_powertune_by_default;
 874 };
 875
 876 struct si_dyn_powertune_data
 877 {
 878         u32 cac_leakage;
 879         s32 leakage_minimum_temperature;
 880         u32 wintime;
 881         u32 l2_lta_window_size;
 882         u8 lts_truncate;
 883         u8 shift_n;
 884         u8 dc_pwr_value;
 885         bool disable_uvd_powertune;
 886 };
 887
 888 struct si_dte_data
 889 {
 890         u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
 891         u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
 892         u32 k;
 893         u32 t0;
 894         u32 max_t;
 895         u8 window_size;
 896         u8 temp_select;
 897         u8 dte_mode;
 898         u8 tdep_count;
 899         u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
 900         u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
 901         u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
 902         u32 t_threshold;
 903         bool enable_dte_by_default;
 904 };
 905
 906 struct si_clock_registers {
 907         u32 cg_spll_func_cntl;
 908         u32 cg_spll_func_cntl_2;
 909         u32 cg_spll_func_cntl_3;
 910         u32 cg_spll_func_cntl_4;
 911         u32 cg_spll_spread_spectrum;
 912         u32 cg_spll_spread_spectrum_2;
 913         u32 dll_cntl;
 914         u32 mclk_pwrmgt_cntl;
 915         u32 mpll_ad_func_cntl;
 916         u32 mpll_dq_func_cntl;
 917         u32 mpll_func_cntl;
 918         u32 mpll_func_cntl_1;
 919         u32 mpll_func_cntl_2;
 920         u32 mpll_ss1;
 921         u32 mpll_ss2;
 922 };
 923
 924 struct si_mc_reg_entry {
 925         u32 mclk_max;
 926         u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
 927 };
 928
 929 struct si_mc_reg_table {
 930         u8 last;
 931         u8 num_entries;
 932         u16 valid_flag;
 933         struct si_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
 934         SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
 935 };
 936
 937 struct si_leakage_voltage_entry
 938 {
 939         u16 voltage;
 940         u16 leakage_index;
 941 };
 942
 943 struct si_leakage_voltage
 944 {
 945         u16 count;
 946         struct si_leakage_voltage_entry entries[SISLANDS_MAX_LEAKAGE_COUNT];
 947 };
 948
 949
 950 struct si_ulv_param {
 951         bool supported;
 952         u32 cg_ulv_control;
 953         u32 cg_ulv_parameter;
 954         u32 volt_change_delay;
 955         struct rv7xx_pl pl;
 956         bool one_pcie_lane_in_ulv;
 957 };
 958
 959 struct si_power_info {
 960         /* must be first! */
 961         struct ni_power_info ni;
 962         struct si_clock_registers clock_registers;
 963         struct si_mc_reg_table mc_reg_table;
 964         struct atom_voltage_table mvdd_voltage_table;
 965         struct atom_voltage_table vddc_phase_shed_table;
 966         struct si_leakage_voltage leakage_voltage;
 967         u16 mvdd_bootup_value;
 968         struct si_ulv_param ulv;
 969         u32 max_cu;
 970         /* pcie gen */
 971         enum amdgpu_pcie_gen force_pcie_gen;
 972         enum amdgpu_pcie_gen boot_pcie_gen;
 973         enum amdgpu_pcie_gen acpi_pcie_gen;
 974         u32 sys_pcie_mask;
 975         /* flags */
 976         bool enable_dte;
 977         bool enable_ppm;
 978         bool vddc_phase_shed_control;
 979         bool pspp_notify_required;
 980         bool sclk_deep_sleep_above_low;
 981         bool voltage_control_svi2;
 982         bool vddci_control_svi2;
 983         /* smc offsets */
 984         u32 sram_end;
 985         u32 state_table_start;
 986         u32 soft_regs_start;
 987         u32 mc_reg_table_start;
 988         u32 arb_table_start;
 989         u32 cac_table_start;
 990         u32 dte_table_start;
 991         u32 spll_table_start;
 992         u32 papm_cfg_table_start;
 993         u32 fan_table_start;
 994         /* CAC stuff */
 995         const struct si_cac_config_reg *cac_weights;
 996         const struct si_cac_config_reg *lcac_config;
 997         const struct si_cac_config_reg *cac_override;
 998         const struct si_powertune_data *powertune_data;
 999         struct si_dyn_powertune_data dyn_powertune_data;
1000         /* DTE stuff */
1001         struct si_dte_data dte_data;
1002         /* scratch structs */
1003         SMC_SIslands_MCRegisters smc_mc_reg_table;
1004         SISLANDS_SMC_STATETABLE smc_statetable;
1005         PP_SIslands_PAPMParameters papm_parm;
1006         /* SVI2 */
1007         u8 svd_gpio_id;
1008         u8 svc_gpio_id;
1009         /* fan control */
1010         bool fan_ctrl_is_in_default_mode;
1011         u32 t_min;
1012         u32 fan_ctrl_default_mode;
1013         bool fan_is_controlled_by_smc;
1014 };
1015
1016 #endif