drivers/gpu/drm/amd/amdgpu/si_ih.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_ih.h"
  26 #include "sid.h"
  27 #include "si_ih.h"
  28
  29 static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev);
  30
  31 static void si_ih_enable_interrupts(struct amdgpu_device *adev)
  32 {
  33         u32 ih_cntl = RREG32(IH_CNTL);
  34         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
  35
  36         ih_cntl |= ENABLE_INTR;
  37         ih_rb_cntl |= IH_RB_ENABLE;
  38         WREG32(IH_CNTL, ih_cntl);
  39         WREG32(IH_RB_CNTL, ih_rb_cntl);
  40         adev->irq.ih.enabled = true;
  41 }
  42
  43 static void si_ih_disable_interrupts(struct amdgpu_device *adev)
  44 {
  45         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
  46         u32 ih_cntl = RREG32(IH_CNTL);
  47
  48         ih_rb_cntl &= ~IH_RB_ENABLE;
  49         ih_cntl &= ~ENABLE_INTR;
  50         WREG32(IH_RB_CNTL, ih_rb_cntl);
  51         WREG32(IH_CNTL, ih_cntl);
  52         WREG32(IH_RB_RPTR, 0);
  53         WREG32(IH_RB_WPTR, 0);
  54         adev->irq.ih.enabled = false;
  55         adev->irq.ih.rptr = 0;
  56 }
  57
  58 static int si_ih_irq_init(struct amdgpu_device *adev)
  59 {
  60         int rb_bufsz;
  61         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
  62         u64 wptr_off;
  63
  64         si_ih_disable_interrupts(adev);
  65         WREG32(INTERRUPT_CNTL2, adev->irq.ih.gpu_addr >> 8);
  66         interrupt_cntl = RREG32(INTERRUPT_CNTL);
  67         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
  68         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
  69         WREG32(INTERRUPT_CNTL, interrupt_cntl);
  70
  71         WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
  72         rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
  73
  74         ih_rb_cntl = IH_WPTR_OVERFLOW_ENABLE |
  75                      IH_WPTR_OVERFLOW_CLEAR |
  76                      (rb_bufsz << 1) |
  77                      IH_WPTR_WRITEBACK_ENABLE;
  78
  79         wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
  80         WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
  81         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
  82         WREG32(IH_RB_CNTL, ih_rb_cntl);
  83         WREG32(IH_RB_RPTR, 0);
  84         WREG32(IH_RB_WPTR, 0);
  85
  86         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
  87         if (adev->irq.msi_enabled)
  88                 ih_cntl |= RPTR_REARM;
  89         WREG32(IH_CNTL, ih_cntl);
  90
  91         pci_set_master(adev->pdev);
  92         si_ih_enable_interrupts(adev);
  93
  94         return 0;
  95 }
  96
  97 static void si_ih_irq_disable(struct amdgpu_device *adev)
  98 {
  99         si_ih_disable_interrupts(adev);
 100         mdelay(1);
 101 }
 102
 103 static u32 si_ih_get_wptr(struct amdgpu_device *adev)
 104 {
 105         u32 wptr, tmp;
 106
 107         wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
 108
 109         if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
 110                 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
 111                 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
 112                         wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
 113                 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
 114                 tmp = RREG32(IH_RB_CNTL);
 115                 tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
 116                 WREG32(IH_RB_CNTL, tmp);
 117         }
 118         return (wptr & adev->irq.ih.ptr_mask);
 119 }
 120
 121 static void si_ih_decode_iv(struct amdgpu_device *adev,
 122                              struct amdgpu_iv_entry *entry)
 123 {
 124         u32 ring_index = adev->irq.ih.rptr >> 2;
 125         uint32_t dw[4];
 126
 127         dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
 128         dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
 129         dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
 130         dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
 131
 132         entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
 133         entry->src_id = dw[0] & 0xff;
 134         entry->src_data[0] = dw[1] & 0xfffffff;
 135         entry->ring_id = dw[2] & 0xff;
 136         entry->vm_id = (dw[2] >> 8) & 0xff;
 137
 138         adev->irq.ih.rptr += 16;
 139 }
 140
 141 static void si_ih_set_rptr(struct amdgpu_device *adev)
 142 {
 143         WREG32(IH_RB_RPTR, adev->irq.ih.rptr);
 144 }
 145
 146 static int si_ih_early_init(void *handle)
 147 {
 148         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 149
 150         si_ih_set_interrupt_funcs(adev);
 151
 152         return 0;
 153 }
 154
 155 static int si_ih_sw_init(void *handle)
 156 {
 157         int r;
 158         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 159
 160         r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
 161         if (r)
 162                 return r;
 163
 164         return amdgpu_irq_init(adev);
 165 }
 166
 167 static int si_ih_sw_fini(void *handle)
 168 {
 169         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 170
 171         amdgpu_irq_fini(adev);
 172         amdgpu_ih_ring_fini(adev);
 173
 174         return 0;
 175 }
 176
 177 static int si_ih_hw_init(void *handle)
 178 {
 179         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 180
 181         return si_ih_irq_init(adev);
 182 }
 183
 184 static int si_ih_hw_fini(void *handle)
 185 {
 186         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 187
 188         si_ih_irq_disable(adev);
 189
 190         return 0;
 191 }
 192
 193 static int si_ih_suspend(void *handle)
 194 {
 195         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 196
 197         return si_ih_hw_fini(adev);
 198 }
 199
 200 static int si_ih_resume(void *handle)
 201 {
 202         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 203
 204         return si_ih_hw_init(adev);
 205 }
 206
 207 static bool si_ih_is_idle(void *handle)
 208 {
 209         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 210         u32 tmp = RREG32(SRBM_STATUS);
 211
 212         if (tmp & SRBM_STATUS__IH_BUSY_MASK)
 213                 return false;
 214
 215         return true;
 216 }
 217
 218 static int si_ih_wait_for_idle(void *handle)
 219 {
 220         unsigned i;
 221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 222
 223         for (i = 0; i < adev->usec_timeout; i++) {
 224                 if (si_ih_is_idle(handle))
 225                         return 0;
 226                 udelay(1);
 227         }
 228         return -ETIMEDOUT;
 229 }
 230
 231 static int si_ih_soft_reset(void *handle)
 232 {
 233         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 234
 235         u32 srbm_soft_reset = 0;
 236         u32 tmp = RREG32(SRBM_STATUS);
 237
 238         if (tmp & SRBM_STATUS__IH_BUSY_MASK)
 239                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
 240
 241         if (srbm_soft_reset) {
 242                 tmp = RREG32(SRBM_SOFT_RESET);
 243                 tmp |= srbm_soft_reset;
 244                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 245                 WREG32(SRBM_SOFT_RESET, tmp);
 246                 tmp = RREG32(SRBM_SOFT_RESET);
 247
 248                 udelay(50);
 249
 250                 tmp &= ~srbm_soft_reset;
 251                 WREG32(SRBM_SOFT_RESET, tmp);
 252                 tmp = RREG32(SRBM_SOFT_RESET);
 253
 254                 udelay(50);
 255         }
 256
 257         return 0;
 258 }
 259
 260 static int si_ih_set_clockgating_state(void *handle,
 261                                           enum amd_clockgating_state state)
 262 {
 263         return 0;
 264 }
 265
 266 static int si_ih_set_powergating_state(void *handle,
 267                                           enum amd_powergating_state state)
 268 {
 269         return 0;
 270 }
 271
 272 static const struct amd_ip_funcs si_ih_ip_funcs = {
 273         .name = "si_ih",
 274         .early_init = si_ih_early_init,
 275         .late_init = NULL,
 276         .sw_init = si_ih_sw_init,
 277         .sw_fini = si_ih_sw_fini,
 278         .hw_init = si_ih_hw_init,
 279         .hw_fini = si_ih_hw_fini,
 280         .suspend = si_ih_suspend,
 281         .resume = si_ih_resume,
 282         .is_idle = si_ih_is_idle,
 283         .wait_for_idle = si_ih_wait_for_idle,
 284         .soft_reset = si_ih_soft_reset,
 285         .set_clockgating_state = si_ih_set_clockgating_state,
 286         .set_powergating_state = si_ih_set_powergating_state,
 287 };
 288
 289 static const struct amdgpu_ih_funcs si_ih_funcs = {
 290         .get_wptr = si_ih_get_wptr,
 291         .decode_iv = si_ih_decode_iv,
 292         .set_rptr = si_ih_set_rptr
 293 };
 294
 295 static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev)
 296 {
 297         if (adev->irq.ih_funcs == NULL)
 298                 adev->irq.ih_funcs = &si_ih_funcs;
 299 }
 300
 301 const struct amdgpu_ip_block_version si_ih_ip_block =
 302 {
 303         .type = AMD_IP_BLOCK_TYPE_IH,
 304         .major = 1,
 305         .minor = 0,
 306         .rev = 0,
 307         .funcs = &si_ih_ip_funcs,
 308 };