2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
28 #include "amdgpu_atombios.h"
29 #include "amdgpu_ih.h"
30 #include "amdgpu_uvd.h"
31 #include "amdgpu_vce.h"
32 #include "amdgpu_ucode.h"
33 #include "amdgpu_psp.h"
37 #include "vega10/soc15ip.h"
38 #include "vega10/UVD/uvd_7_0_offset.h"
39 #include "vega10/GC/gc_9_0_offset.h"
40 #include "vega10/GC/gc_9_0_sh_mask.h"
41 #include "vega10/SDMA0/sdma0_4_0_offset.h"
42 #include "vega10/SDMA1/sdma1_4_0_offset.h"
43 #include "vega10/HDP/hdp_4_0_offset.h"
44 #include "vega10/HDP/hdp_4_0_sh_mask.h"
45 #include "vega10/MP/mp_9_0_offset.h"
46 #include "vega10/MP/mp_9_0_sh_mask.h"
47 #include "vega10/SMUIO/smuio_9_0_offset.h"
48 #include "vega10/SMUIO/smuio_9_0_sh_mask.h"
51 #include "soc15_common.h"
54 #include "gfxhub_v1_0.h"
55 #include "mmhub_v1_0.h"
56 #include "vega10_ih.h"
57 #include "sdma_v4_0.h"
61 #include "amdgpu_powerplay.h"
62 #include "dce_virtual.h"
65 #define mmFabricConfigAccessControl 0x0410
66 #define mmFabricConfigAccessControl_BASE_IDX 0
67 #define mmFabricConfigAccessControl_DEFAULT 0x00000000
68 //FabricConfigAccessControl
69 #define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT 0x0
70 #define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT 0x1
71 #define FabricConfigAccessControl__CfgRegInstID__SHIFT 0x10
72 #define FabricConfigAccessControl__CfgRegInstAccEn_MASK 0x00000001L
73 #define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK 0x00000002L
74 #define FabricConfigAccessControl__CfgRegInstID_MASK 0x00FF0000L
77 #define mmDF_PIE_AON0_DfGlobalClkGater 0x00fc
78 #define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX 0
79 //DF_PIE_AON0_DfGlobalClkGater
80 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT 0x0
81 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK 0x0000000FL
85 DF_MGCG_ENABLE_00_CYCLE_DELAY
=1,
86 DF_MGCG_ENABLE_01_CYCLE_DELAY
=2,
87 DF_MGCG_ENABLE_15_CYCLE_DELAY
=13,
88 DF_MGCG_ENABLE_31_CYCLE_DELAY
=14,
89 DF_MGCG_ENABLE_63_CYCLE_DELAY
=15
92 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
93 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
94 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
95 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
98 * Indirect registers accessor
100 static u32
soc15_pcie_rreg(struct amdgpu_device
*adev
, u32 reg
)
102 unsigned long flags
, address
, data
;
104 const struct nbio_pcie_index_data
*nbio_pcie_id
;
106 if (adev
->flags
& AMD_IS_APU
)
107 nbio_pcie_id
= &nbio_v7_0_pcie_index_data
;
109 nbio_pcie_id
= &nbio_v6_1_pcie_index_data
;
111 address
= nbio_pcie_id
->index_offset
;
112 data
= nbio_pcie_id
->data_offset
;
114 spin_lock_irqsave(&adev
->pcie_idx_lock
, flags
);
115 WREG32(address
, reg
);
116 (void)RREG32(address
);
118 spin_unlock_irqrestore(&adev
->pcie_idx_lock
, flags
);
122 static void soc15_pcie_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
124 unsigned long flags
, address
, data
;
125 const struct nbio_pcie_index_data
*nbio_pcie_id
;
127 if (adev
->flags
& AMD_IS_APU
)
128 nbio_pcie_id
= &nbio_v7_0_pcie_index_data
;
130 nbio_pcie_id
= &nbio_v6_1_pcie_index_data
;
132 address
= nbio_pcie_id
->index_offset
;
133 data
= nbio_pcie_id
->data_offset
;
135 spin_lock_irqsave(&adev
->pcie_idx_lock
, flags
);
136 WREG32(address
, reg
);
137 (void)RREG32(address
);
140 spin_unlock_irqrestore(&adev
->pcie_idx_lock
, flags
);
143 static u32
soc15_uvd_ctx_rreg(struct amdgpu_device
*adev
, u32 reg
)
145 unsigned long flags
, address
, data
;
148 address
= SOC15_REG_OFFSET(UVD
, 0, mmUVD_CTX_INDEX
);
149 data
= SOC15_REG_OFFSET(UVD
, 0, mmUVD_CTX_DATA
);
151 spin_lock_irqsave(&adev
->uvd_ctx_idx_lock
, flags
);
152 WREG32(address
, ((reg
) & 0x1ff));
154 spin_unlock_irqrestore(&adev
->uvd_ctx_idx_lock
, flags
);
158 static void soc15_uvd_ctx_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
160 unsigned long flags
, address
, data
;
162 address
= SOC15_REG_OFFSET(UVD
, 0, mmUVD_CTX_INDEX
);
163 data
= SOC15_REG_OFFSET(UVD
, 0, mmUVD_CTX_DATA
);
165 spin_lock_irqsave(&adev
->uvd_ctx_idx_lock
, flags
);
166 WREG32(address
, ((reg
) & 0x1ff));
168 spin_unlock_irqrestore(&adev
->uvd_ctx_idx_lock
, flags
);
171 static u32
soc15_didt_rreg(struct amdgpu_device
*adev
, u32 reg
)
173 unsigned long flags
, address
, data
;
176 address
= SOC15_REG_OFFSET(GC
, 0, mmDIDT_IND_INDEX
);
177 data
= SOC15_REG_OFFSET(GC
, 0, mmDIDT_IND_DATA
);
179 spin_lock_irqsave(&adev
->didt_idx_lock
, flags
);
180 WREG32(address
, (reg
));
182 spin_unlock_irqrestore(&adev
->didt_idx_lock
, flags
);
186 static void soc15_didt_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
188 unsigned long flags
, address
, data
;
190 address
= SOC15_REG_OFFSET(GC
, 0, mmDIDT_IND_INDEX
);
191 data
= SOC15_REG_OFFSET(GC
, 0, mmDIDT_IND_DATA
);
193 spin_lock_irqsave(&adev
->didt_idx_lock
, flags
);
194 WREG32(address
, (reg
));
196 spin_unlock_irqrestore(&adev
->didt_idx_lock
, flags
);
199 static u32
soc15_gc_cac_rreg(struct amdgpu_device
*adev
, u32 reg
)
204 spin_lock_irqsave(&adev
->gc_cac_idx_lock
, flags
);
205 WREG32_SOC15(GC
, 0, mmGC_CAC_IND_INDEX
, (reg
));
206 r
= RREG32_SOC15(GC
, 0, mmGC_CAC_IND_DATA
);
207 spin_unlock_irqrestore(&adev
->gc_cac_idx_lock
, flags
);
211 static void soc15_gc_cac_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
215 spin_lock_irqsave(&adev
->gc_cac_idx_lock
, flags
);
216 WREG32_SOC15(GC
, 0, mmGC_CAC_IND_INDEX
, (reg
));
217 WREG32_SOC15(GC
, 0, mmGC_CAC_IND_DATA
, (v
));
218 spin_unlock_irqrestore(&adev
->gc_cac_idx_lock
, flags
);
221 static u32
soc15_se_cac_rreg(struct amdgpu_device
*adev
, u32 reg
)
226 spin_lock_irqsave(&adev
->se_cac_idx_lock
, flags
);
227 WREG32_SOC15(GC
, 0, mmSE_CAC_IND_INDEX
, (reg
));
228 r
= RREG32_SOC15(GC
, 0, mmSE_CAC_IND_DATA
);
229 spin_unlock_irqrestore(&adev
->se_cac_idx_lock
, flags
);
233 static void soc15_se_cac_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
237 spin_lock_irqsave(&adev
->se_cac_idx_lock
, flags
);
238 WREG32_SOC15(GC
, 0, mmSE_CAC_IND_INDEX
, (reg
));
239 WREG32_SOC15(GC
, 0, mmSE_CAC_IND_DATA
, (v
));
240 spin_unlock_irqrestore(&adev
->se_cac_idx_lock
, flags
);
243 static u32
soc15_get_config_memsize(struct amdgpu_device
*adev
)
245 if (adev
->flags
& AMD_IS_APU
)
246 return nbio_v7_0_get_memsize(adev
);
248 return nbio_v6_1_get_memsize(adev
);
251 static const u32 vega10_golden_init
[] =
255 static const u32 raven_golden_init
[] =
259 static void soc15_init_golden_registers(struct amdgpu_device
*adev
)
261 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
262 mutex_lock(&adev
->grbm_idx_mutex
);
264 switch (adev
->asic_type
) {
266 amdgpu_program_register_sequence(adev
,
268 (const u32
)ARRAY_SIZE(vega10_golden_init
));
271 amdgpu_program_register_sequence(adev
,
273 (const u32
)ARRAY_SIZE(raven_golden_init
));
278 mutex_unlock(&adev
->grbm_idx_mutex
);
280 static u32
soc15_get_xclk(struct amdgpu_device
*adev
)
282 if (adev
->asic_type
== CHIP_VEGA10
)
283 return adev
->clock
.spll
.reference_freq
/4;
285 return adev
->clock
.spll
.reference_freq
;
289 void soc15_grbm_select(struct amdgpu_device
*adev
,
290 u32 me
, u32 pipe
, u32 queue
, u32 vmid
)
292 u32 grbm_gfx_cntl
= 0;
293 grbm_gfx_cntl
= REG_SET_FIELD(grbm_gfx_cntl
, GRBM_GFX_CNTL
, PIPEID
, pipe
);
294 grbm_gfx_cntl
= REG_SET_FIELD(grbm_gfx_cntl
, GRBM_GFX_CNTL
, MEID
, me
);
295 grbm_gfx_cntl
= REG_SET_FIELD(grbm_gfx_cntl
, GRBM_GFX_CNTL
, VMID
, vmid
);
296 grbm_gfx_cntl
= REG_SET_FIELD(grbm_gfx_cntl
, GRBM_GFX_CNTL
, QUEUEID
, queue
);
298 WREG32(SOC15_REG_OFFSET(GC
, 0, mmGRBM_GFX_CNTL
), grbm_gfx_cntl
);
301 static void soc15_vga_set_state(struct amdgpu_device
*adev
, bool state
)
306 static bool soc15_read_disabled_bios(struct amdgpu_device
*adev
)
312 static bool soc15_read_bios_from_rom(struct amdgpu_device
*adev
,
313 u8
*bios
, u32 length_bytes
)
320 if (length_bytes
== 0)
322 /* APU vbios image is part of sbios image */
323 if (adev
->flags
& AMD_IS_APU
)
326 dw_ptr
= (u32
*)bios
;
327 length_dw
= ALIGN(length_bytes
, 4) / 4;
329 /* set rom index to 0 */
330 WREG32(SOC15_REG_OFFSET(SMUIO
, 0, mmROM_INDEX
), 0);
331 /* read out the rom data */
332 for (i
= 0; i
< length_dw
; i
++)
333 dw_ptr
[i
] = RREG32(SOC15_REG_OFFSET(SMUIO
, 0, mmROM_DATA
));
338 static struct amdgpu_allowed_register_entry soc15_allowed_read_registers
[] = {
339 { SOC15_REG_OFFSET(GC
, 0, mmGRBM_STATUS
)},
340 { SOC15_REG_OFFSET(GC
, 0, mmGRBM_STATUS2
)},
341 { SOC15_REG_OFFSET(GC
, 0, mmGRBM_STATUS_SE0
)},
342 { SOC15_REG_OFFSET(GC
, 0, mmGRBM_STATUS_SE1
)},
343 { SOC15_REG_OFFSET(GC
, 0, mmGRBM_STATUS_SE2
)},
344 { SOC15_REG_OFFSET(GC
, 0, mmGRBM_STATUS_SE3
)},
345 { SOC15_REG_OFFSET(SDMA0
, 0, mmSDMA0_STATUS_REG
)},
346 { SOC15_REG_OFFSET(SDMA1
, 0, mmSDMA1_STATUS_REG
)},
347 { SOC15_REG_OFFSET(GC
, 0, mmCP_STAT
)},
348 { SOC15_REG_OFFSET(GC
, 0, mmCP_STALLED_STAT1
)},
349 { SOC15_REG_OFFSET(GC
, 0, mmCP_STALLED_STAT2
)},
350 { SOC15_REG_OFFSET(GC
, 0, mmCP_STALLED_STAT3
)},
351 { SOC15_REG_OFFSET(GC
, 0, mmCP_CPF_BUSY_STAT
)},
352 { SOC15_REG_OFFSET(GC
, 0, mmCP_CPF_STALLED_STAT1
)},
353 { SOC15_REG_OFFSET(GC
, 0, mmCP_CPF_STATUS
)},
354 { SOC15_REG_OFFSET(GC
, 0, mmCP_CPC_STALLED_STAT1
)},
355 { SOC15_REG_OFFSET(GC
, 0, mmCP_CPC_STATUS
)},
356 { SOC15_REG_OFFSET(GC
, 0, mmGB_ADDR_CONFIG
)},
359 static uint32_t soc15_read_indexed_register(struct amdgpu_device
*adev
, u32 se_num
,
360 u32 sh_num
, u32 reg_offset
)
364 mutex_lock(&adev
->grbm_idx_mutex
);
365 if (se_num
!= 0xffffffff || sh_num
!= 0xffffffff)
366 amdgpu_gfx_select_se_sh(adev
, se_num
, sh_num
, 0xffffffff);
368 val
= RREG32(reg_offset
);
370 if (se_num
!= 0xffffffff || sh_num
!= 0xffffffff)
371 amdgpu_gfx_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
372 mutex_unlock(&adev
->grbm_idx_mutex
);
376 static uint32_t soc15_get_register_value(struct amdgpu_device
*adev
,
377 bool indexed
, u32 se_num
,
378 u32 sh_num
, u32 reg_offset
)
381 return soc15_read_indexed_register(adev
, se_num
, sh_num
, reg_offset
);
383 switch (reg_offset
) {
384 case SOC15_REG_OFFSET(GC
, 0, mmGB_ADDR_CONFIG
):
385 return adev
->gfx
.config
.gb_addr_config
;
387 return RREG32(reg_offset
);
392 static int soc15_read_register(struct amdgpu_device
*adev
, u32 se_num
,
393 u32 sh_num
, u32 reg_offset
, u32
*value
)
398 for (i
= 0; i
< ARRAY_SIZE(soc15_allowed_read_registers
); i
++) {
399 if (reg_offset
!= soc15_allowed_read_registers
[i
].reg_offset
)
402 *value
= soc15_get_register_value(adev
,
403 soc15_allowed_read_registers
[i
].grbm_indexed
,
404 se_num
, sh_num
, reg_offset
);
410 static int soc15_asic_reset(struct amdgpu_device
*adev
)
414 amdgpu_atombios_scratch_regs_engine_hung(adev
, true);
416 dev_info(adev
->dev
, "GPU reset\n");
419 pci_clear_master(adev
->pdev
);
421 pci_save_state(adev
->pdev
);
423 for (i
= 0; i
< AMDGPU_MAX_IP_NUM
; i
++) {
424 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_PSP
){
425 adev
->ip_blocks
[i
].version
->funcs
->soft_reset((void *)adev
);
430 pci_restore_state(adev
->pdev
);
432 /* wait for asic to come out of reset */
433 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
434 u32 memsize
= (adev
->flags
& AMD_IS_APU
) ?
435 nbio_v7_0_get_memsize(adev
) :
436 nbio_v6_1_get_memsize(adev
);
437 if (memsize
!= 0xffffffff)
442 amdgpu_atombios_scratch_regs_engine_hung(adev
, false);
447 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
448 u32 cntl_reg, u32 status_reg)
453 static int soc15_set_uvd_clocks(struct amdgpu_device
*adev
, u32 vclk
, u32 dclk
)
457 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
461 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
466 static int soc15_set_vce_clocks(struct amdgpu_device
*adev
, u32 evclk
, u32 ecclk
)
473 static void soc15_pcie_gen3_enable(struct amdgpu_device
*adev
)
475 if (pci_is_root_bus(adev
->pdev
->bus
))
478 if (amdgpu_pcie_gen2
== 0)
481 if (adev
->flags
& AMD_IS_APU
)
484 if (!(adev
->pm
.pcie_gen_mask
& (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2
|
485 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3
)))
491 static void soc15_program_aspm(struct amdgpu_device
*adev
)
494 if (amdgpu_aspm
== 0)
500 static void soc15_enable_doorbell_aperture(struct amdgpu_device
*adev
,
503 if (adev
->flags
& AMD_IS_APU
) {
504 nbio_v7_0_enable_doorbell_aperture(adev
, enable
);
506 nbio_v6_1_enable_doorbell_aperture(adev
, enable
);
507 nbio_v6_1_enable_doorbell_selfring_aperture(adev
, enable
);
511 static const struct amdgpu_ip_block_version vega10_common_ip_block
=
513 .type
= AMD_IP_BLOCK_TYPE_COMMON
,
517 .funcs
= &soc15_common_ip_funcs
,
520 int soc15_set_ip_blocks(struct amdgpu_device
*adev
)
522 nbio_v6_1_detect_hw_virt(adev
);
524 if (amdgpu_sriov_vf(adev
))
525 adev
->virt
.ops
= &xgpu_ai_virt_ops
;
527 switch (adev
->asic_type
) {
529 amdgpu_ip_block_add(adev
, &vega10_common_ip_block
);
530 amdgpu_ip_block_add(adev
, &gmc_v9_0_ip_block
);
531 amdgpu_ip_block_add(adev
, &vega10_ih_ip_block
);
532 if (amdgpu_fw_load_type
== 2 || amdgpu_fw_load_type
== -1)
533 amdgpu_ip_block_add(adev
, &psp_v3_1_ip_block
);
534 if (!amdgpu_sriov_vf(adev
))
535 amdgpu_ip_block_add(adev
, &amdgpu_pp_ip_block
);
536 if (adev
->enable_virtual_display
|| amdgpu_sriov_vf(adev
))
537 amdgpu_ip_block_add(adev
, &dce_virtual_ip_block
);
538 amdgpu_ip_block_add(adev
, &gfx_v9_0_ip_block
);
539 amdgpu_ip_block_add(adev
, &sdma_v4_0_ip_block
);
540 amdgpu_ip_block_add(adev
, &uvd_v7_0_ip_block
);
541 amdgpu_ip_block_add(adev
, &vce_v4_0_ip_block
);
544 amdgpu_ip_block_add(adev
, &vega10_common_ip_block
);
545 amdgpu_ip_block_add(adev
, &gmc_v9_0_ip_block
);
546 amdgpu_ip_block_add(adev
, &vega10_ih_ip_block
);
547 amdgpu_ip_block_add(adev
, &psp_v10_0_ip_block
);
548 amdgpu_ip_block_add(adev
, &amdgpu_pp_ip_block
);
549 if (adev
->enable_virtual_display
|| amdgpu_sriov_vf(adev
))
550 amdgpu_ip_block_add(adev
, &dce_virtual_ip_block
);
551 amdgpu_ip_block_add(adev
, &gfx_v9_0_ip_block
);
552 amdgpu_ip_block_add(adev
, &sdma_v4_0_ip_block
);
553 amdgpu_ip_block_add(adev
, &vcn_v1_0_ip_block
);
562 static uint32_t soc15_get_rev_id(struct amdgpu_device
*adev
)
564 if (adev
->flags
& AMD_IS_APU
)
565 return nbio_v7_0_get_rev_id(adev
);
567 return nbio_v6_1_get_rev_id(adev
);
570 static const struct amdgpu_asic_funcs soc15_asic_funcs
=
572 .read_disabled_bios
= &soc15_read_disabled_bios
,
573 .read_bios_from_rom
= &soc15_read_bios_from_rom
,
574 .read_register
= &soc15_read_register
,
575 .reset
= &soc15_asic_reset
,
576 .set_vga_state
= &soc15_vga_set_state
,
577 .get_xclk
= &soc15_get_xclk
,
578 .set_uvd_clocks
= &soc15_set_uvd_clocks
,
579 .set_vce_clocks
= &soc15_set_vce_clocks
,
580 .get_config_memsize
= &soc15_get_config_memsize
,
583 static int soc15_common_early_init(void *handle
)
585 bool psp_enabled
= false;
586 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
588 adev
->smc_rreg
= NULL
;
589 adev
->smc_wreg
= NULL
;
590 adev
->pcie_rreg
= &soc15_pcie_rreg
;
591 adev
->pcie_wreg
= &soc15_pcie_wreg
;
592 adev
->uvd_ctx_rreg
= &soc15_uvd_ctx_rreg
;
593 adev
->uvd_ctx_wreg
= &soc15_uvd_ctx_wreg
;
594 adev
->didt_rreg
= &soc15_didt_rreg
;
595 adev
->didt_wreg
= &soc15_didt_wreg
;
596 adev
->gc_cac_rreg
= &soc15_gc_cac_rreg
;
597 adev
->gc_cac_wreg
= &soc15_gc_cac_wreg
;
598 adev
->se_cac_rreg
= &soc15_se_cac_rreg
;
599 adev
->se_cac_wreg
= &soc15_se_cac_wreg
;
601 adev
->asic_funcs
= &soc15_asic_funcs
;
603 if (amdgpu_get_ip_block(adev
, AMD_IP_BLOCK_TYPE_PSP
) &&
604 (amdgpu_ip_block_mask
& (1 << AMD_IP_BLOCK_TYPE_PSP
)))
607 adev
->rev_id
= soc15_get_rev_id(adev
);
608 adev
->external_rev_id
= 0xFF;
609 switch (adev
->asic_type
) {
611 adev
->cg_flags
= AMD_CG_SUPPORT_GFX_MGCG
|
612 AMD_CG_SUPPORT_GFX_MGLS
|
613 AMD_CG_SUPPORT_GFX_RLC_LS
|
614 AMD_CG_SUPPORT_GFX_CP_LS
|
615 AMD_CG_SUPPORT_GFX_3D_CGCG
|
616 AMD_CG_SUPPORT_GFX_3D_CGLS
|
617 AMD_CG_SUPPORT_GFX_CGCG
|
618 AMD_CG_SUPPORT_GFX_CGLS
|
619 AMD_CG_SUPPORT_BIF_MGCG
|
620 AMD_CG_SUPPORT_BIF_LS
|
621 AMD_CG_SUPPORT_HDP_LS
|
622 AMD_CG_SUPPORT_DRM_MGCG
|
623 AMD_CG_SUPPORT_DRM_LS
|
624 AMD_CG_SUPPORT_ROM_MGCG
|
625 AMD_CG_SUPPORT_DF_MGCG
|
626 AMD_CG_SUPPORT_SDMA_MGCG
|
627 AMD_CG_SUPPORT_SDMA_LS
|
628 AMD_CG_SUPPORT_MC_MGCG
|
629 AMD_CG_SUPPORT_MC_LS
;
631 adev
->external_rev_id
= 0x1;
634 adev
->cg_flags
= AMD_CG_SUPPORT_GFX_MGCG
|
635 AMD_CG_SUPPORT_GFX_MGLS
|
636 AMD_CG_SUPPORT_GFX_RLC_LS
|
637 AMD_CG_SUPPORT_GFX_CP_LS
|
638 AMD_CG_SUPPORT_GFX_3D_CGCG
|
639 AMD_CG_SUPPORT_GFX_3D_CGLS
|
640 AMD_CG_SUPPORT_GFX_CGCG
|
641 AMD_CG_SUPPORT_GFX_CGLS
|
642 AMD_CG_SUPPORT_BIF_MGCG
|
643 AMD_CG_SUPPORT_BIF_LS
|
644 AMD_CG_SUPPORT_HDP_MGCG
|
645 AMD_CG_SUPPORT_HDP_LS
|
646 AMD_CG_SUPPORT_DRM_MGCG
|
647 AMD_CG_SUPPORT_DRM_LS
|
648 AMD_CG_SUPPORT_ROM_MGCG
|
649 AMD_CG_SUPPORT_MC_MGCG
|
650 AMD_CG_SUPPORT_MC_LS
|
651 AMD_CG_SUPPORT_SDMA_MGCG
|
652 AMD_CG_SUPPORT_SDMA_LS
;
653 adev
->pg_flags
= AMD_PG_SUPPORT_SDMA
|
654 AMD_PG_SUPPORT_MMHUB
;
655 adev
->external_rev_id
= 0x1;
658 /* FIXME: not supported yet */
662 if (amdgpu_sriov_vf(adev
)) {
663 amdgpu_virt_init_setting(adev
);
664 xgpu_ai_mailbox_set_irq_funcs(adev
);
667 adev
->firmware
.load_type
= amdgpu_ucode_get_load_type(adev
, amdgpu_fw_load_type
);
669 amdgpu_get_pcie_info(adev
);
674 static int soc15_common_late_init(void *handle
)
676 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
678 if (amdgpu_sriov_vf(adev
))
679 xgpu_ai_mailbox_get_irq(adev
);
684 static int soc15_common_sw_init(void *handle
)
686 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
688 if (amdgpu_sriov_vf(adev
))
689 xgpu_ai_mailbox_add_irq_id(adev
);
694 static int soc15_common_sw_fini(void *handle
)
699 static int soc15_common_hw_init(void *handle
)
701 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
703 /* move the golden regs per IP block */
704 soc15_init_golden_registers(adev
);
705 /* enable pcie gen2/3 link */
706 soc15_pcie_gen3_enable(adev
);
708 soc15_program_aspm(adev
);
709 /* setup nbio registers */
710 if (!(adev
->flags
& AMD_IS_APU
))
711 nbio_v6_1_init_registers(adev
);
712 /* enable the doorbell aperture */
713 soc15_enable_doorbell_aperture(adev
, true);
718 static int soc15_common_hw_fini(void *handle
)
720 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
722 /* disable the doorbell aperture */
723 soc15_enable_doorbell_aperture(adev
, false);
724 if (amdgpu_sriov_vf(adev
))
725 xgpu_ai_mailbox_put_irq(adev
);
730 static int soc15_common_suspend(void *handle
)
732 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
734 return soc15_common_hw_fini(adev
);
737 static int soc15_common_resume(void *handle
)
739 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
741 return soc15_common_hw_init(adev
);
744 static bool soc15_common_is_idle(void *handle
)
749 static int soc15_common_wait_for_idle(void *handle
)
754 static int soc15_common_soft_reset(void *handle
)
759 static void soc15_update_hdp_light_sleep(struct amdgpu_device
*adev
, bool enable
)
763 def
= data
= RREG32(SOC15_REG_OFFSET(HDP
, 0, mmHDP_MEM_POWER_LS
));
765 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_HDP_LS
))
766 data
|= HDP_MEM_POWER_LS__LS_ENABLE_MASK
;
768 data
&= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK
;
771 WREG32(SOC15_REG_OFFSET(HDP
, 0, mmHDP_MEM_POWER_LS
), data
);
774 static void soc15_update_drm_clock_gating(struct amdgpu_device
*adev
, bool enable
)
778 def
= data
= RREG32(SOC15_REG_OFFSET(MP0
, 0, mmMP0_MISC_CGTT_CTRL0
));
780 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_DRM_MGCG
))
781 data
&= ~(0x01000000 |
790 data
|= (0x01000000 |
800 WREG32(SOC15_REG_OFFSET(MP0
, 0, mmMP0_MISC_CGTT_CTRL0
), data
);
803 static void soc15_update_drm_light_sleep(struct amdgpu_device
*adev
, bool enable
)
807 def
= data
= RREG32(SOC15_REG_OFFSET(MP0
, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL
));
809 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_DRM_LS
))
815 WREG32(SOC15_REG_OFFSET(MP0
, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL
), data
);
818 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device
*adev
,
823 def
= data
= RREG32(SOC15_REG_OFFSET(SMUIO
, 0, mmCGTT_ROM_CLK_CTRL0
));
825 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_ROM_MGCG
))
826 data
&= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK
|
827 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK
);
829 data
|= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK
|
830 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK
;
833 WREG32(SOC15_REG_OFFSET(SMUIO
, 0, mmCGTT_ROM_CLK_CTRL0
), data
);
836 static void soc15_update_df_medium_grain_clock_gating(struct amdgpu_device
*adev
,
841 /* Put DF on broadcast mode */
842 data
= RREG32(SOC15_REG_OFFSET(DF
, 0, mmFabricConfigAccessControl
));
843 data
&= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK
;
844 WREG32(SOC15_REG_OFFSET(DF
, 0, mmFabricConfigAccessControl
), data
);
846 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_DF_MGCG
)) {
847 data
= RREG32(SOC15_REG_OFFSET(DF
, 0, mmDF_PIE_AON0_DfGlobalClkGater
));
848 data
&= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK
;
849 data
|= DF_MGCG_ENABLE_15_CYCLE_DELAY
;
850 WREG32(SOC15_REG_OFFSET(DF
, 0, mmDF_PIE_AON0_DfGlobalClkGater
), data
);
852 data
= RREG32(SOC15_REG_OFFSET(DF
, 0, mmDF_PIE_AON0_DfGlobalClkGater
));
853 data
&= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK
;
854 data
|= DF_MGCG_DISABLE
;
855 WREG32(SOC15_REG_OFFSET(DF
, 0, mmDF_PIE_AON0_DfGlobalClkGater
), data
);
858 WREG32(SOC15_REG_OFFSET(DF
, 0, mmFabricConfigAccessControl
),
859 mmFabricConfigAccessControl_DEFAULT
);
862 static int soc15_common_set_clockgating_state(void *handle
,
863 enum amd_clockgating_state state
)
865 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
867 if (amdgpu_sriov_vf(adev
))
870 switch (adev
->asic_type
) {
872 nbio_v6_1_update_medium_grain_clock_gating(adev
,
873 state
== AMD_CG_STATE_GATE
? true : false);
874 nbio_v6_1_update_medium_grain_light_sleep(adev
,
875 state
== AMD_CG_STATE_GATE
? true : false);
876 soc15_update_hdp_light_sleep(adev
,
877 state
== AMD_CG_STATE_GATE
? true : false);
878 soc15_update_drm_clock_gating(adev
,
879 state
== AMD_CG_STATE_GATE
? true : false);
880 soc15_update_drm_light_sleep(adev
,
881 state
== AMD_CG_STATE_GATE
? true : false);
882 soc15_update_rom_medium_grain_clock_gating(adev
,
883 state
== AMD_CG_STATE_GATE
? true : false);
884 soc15_update_df_medium_grain_clock_gating(adev
,
885 state
== AMD_CG_STATE_GATE
? true : false);
888 nbio_v7_0_update_medium_grain_clock_gating(adev
,
889 state
== AMD_CG_STATE_GATE
? true : false);
890 nbio_v6_1_update_medium_grain_light_sleep(adev
,
891 state
== AMD_CG_STATE_GATE
? true : false);
892 soc15_update_hdp_light_sleep(adev
,
893 state
== AMD_CG_STATE_GATE
? true : false);
894 soc15_update_drm_clock_gating(adev
,
895 state
== AMD_CG_STATE_GATE
? true : false);
896 soc15_update_drm_light_sleep(adev
,
897 state
== AMD_CG_STATE_GATE
? true : false);
898 soc15_update_rom_medium_grain_clock_gating(adev
,
899 state
== AMD_CG_STATE_GATE
? true : false);
907 static void soc15_common_get_clockgating_state(void *handle
, u32
*flags
)
909 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
912 if (amdgpu_sriov_vf(adev
))
915 nbio_v6_1_get_clockgating_state(adev
, flags
);
917 /* AMD_CG_SUPPORT_HDP_LS */
918 data
= RREG32(SOC15_REG_OFFSET(HDP
, 0, mmHDP_MEM_POWER_LS
));
919 if (data
& HDP_MEM_POWER_LS__LS_ENABLE_MASK
)
920 *flags
|= AMD_CG_SUPPORT_HDP_LS
;
922 /* AMD_CG_SUPPORT_DRM_MGCG */
923 data
= RREG32(SOC15_REG_OFFSET(MP0
, 0, mmMP0_MISC_CGTT_CTRL0
));
924 if (!(data
& 0x01000000))
925 *flags
|= AMD_CG_SUPPORT_DRM_MGCG
;
927 /* AMD_CG_SUPPORT_DRM_LS */
928 data
= RREG32(SOC15_REG_OFFSET(MP0
, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL
));
930 *flags
|= AMD_CG_SUPPORT_DRM_LS
;
932 /* AMD_CG_SUPPORT_ROM_MGCG */
933 data
= RREG32(SOC15_REG_OFFSET(SMUIO
, 0, mmCGTT_ROM_CLK_CTRL0
));
934 if (!(data
& CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK
))
935 *flags
|= AMD_CG_SUPPORT_ROM_MGCG
;
937 /* AMD_CG_SUPPORT_DF_MGCG */
938 data
= RREG32(SOC15_REG_OFFSET(DF
, 0, mmDF_PIE_AON0_DfGlobalClkGater
));
939 if (data
& DF_MGCG_ENABLE_15_CYCLE_DELAY
)
940 *flags
|= AMD_CG_SUPPORT_DF_MGCG
;
943 static int soc15_common_set_powergating_state(void *handle
,
944 enum amd_powergating_state state
)
950 const struct amd_ip_funcs soc15_common_ip_funcs
= {
951 .name
= "soc15_common",
952 .early_init
= soc15_common_early_init
,
953 .late_init
= soc15_common_late_init
,
954 .sw_init
= soc15_common_sw_init
,
955 .sw_fini
= soc15_common_sw_fini
,
956 .hw_init
= soc15_common_hw_init
,
957 .hw_fini
= soc15_common_hw_fini
,
958 .suspend
= soc15_common_suspend
,
959 .resume
= soc15_common_resume
,
960 .is_idle
= soc15_common_is_idle
,
961 .wait_for_idle
= soc15_common_wait_for_idle
,
962 .soft_reset
= soc15_common_soft_reset
,
963 .set_clockgating_state
= soc15_common_set_clockgating_state
,
964 .set_powergating_state
= soc15_common_set_powergating_state
,
965 .get_clockgating_state
= soc15_common_get_clockgating_state
,