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Merge tag 'dmaengine-4.21-rc1' of git://git.infradead.org/users/vkoul/slave-dma
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / amd / amdgpu / soc15.c
1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <drm/drmP.h>
27 #include "amdgpu.h"
28 #include "amdgpu_atombios.h"
29 #include "amdgpu_ih.h"
30 #include "amdgpu_uvd.h"
31 #include "amdgpu_vce.h"
32 #include "amdgpu_ucode.h"
33 #include "amdgpu_psp.h"
34 #include "atom.h"
35 #include "amd_pcie.h"
36
37 #include "uvd/uvd_7_0_offset.h"
38 #include "gc/gc_9_0_offset.h"
39 #include "gc/gc_9_0_sh_mask.h"
40 #include "sdma0/sdma0_4_0_offset.h"
41 #include "sdma1/sdma1_4_0_offset.h"
42 #include "hdp/hdp_4_0_offset.h"
43 #include "hdp/hdp_4_0_sh_mask.h"
44 #include "smuio/smuio_9_0_offset.h"
45 #include "smuio/smuio_9_0_sh_mask.h"
46
47 #include "soc15.h"
48 #include "soc15_common.h"
49 #include "gfx_v9_0.h"
50 #include "gmc_v9_0.h"
51 #include "gfxhub_v1_0.h"
52 #include "mmhub_v1_0.h"
53 #include "df_v1_7.h"
54 #include "df_v3_6.h"
55 #include "vega10_ih.h"
56 #include "sdma_v4_0.h"
57 #include "uvd_v7_0.h"
58 #include "vce_v4_0.h"
59 #include "vcn_v1_0.h"
60 #include "dce_virtual.h"
61 #include "mxgpu_ai.h"
62
63 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
64 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
65 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
66 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
67
68 /* for Vega20 register name change */
69 #define mmHDP_MEM_POWER_CTRL 0x00d4
70 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
71 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
72 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
73 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
74 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
75 /*
76 * Indirect registers accessor
77 */
78 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
79 {
80 unsigned long flags, address, data;
81 u32 r;
82 address = adev->nbio_funcs->get_pcie_index_offset(adev);
83 data = adev->nbio_funcs->get_pcie_data_offset(adev);
84
85 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
86 WREG32(address, reg);
87 (void)RREG32(address);
88 r = RREG32(data);
89 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
90 return r;
91 }
92
93 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
94 {
95 unsigned long flags, address, data;
96
97 address = adev->nbio_funcs->get_pcie_index_offset(adev);
98 data = adev->nbio_funcs->get_pcie_data_offset(adev);
99
100 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
101 WREG32(address, reg);
102 (void)RREG32(address);
103 WREG32(data, v);
104 (void)RREG32(data);
105 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
106 }
107
108 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
109 {
110 unsigned long flags, address, data;
111 u32 r;
112
113 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
114 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
115
116 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
117 WREG32(address, ((reg) & 0x1ff));
118 r = RREG32(data);
119 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
120 return r;
121 }
122
123 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
124 {
125 unsigned long flags, address, data;
126
127 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
128 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
129
130 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
131 WREG32(address, ((reg) & 0x1ff));
132 WREG32(data, (v));
133 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
134 }
135
136 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
137 {
138 unsigned long flags, address, data;
139 u32 r;
140
141 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
142 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
143
144 spin_lock_irqsave(&adev->didt_idx_lock, flags);
145 WREG32(address, (reg));
146 r = RREG32(data);
147 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
148 return r;
149 }
150
151 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
152 {
153 unsigned long flags, address, data;
154
155 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
156 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
157
158 spin_lock_irqsave(&adev->didt_idx_lock, flags);
159 WREG32(address, (reg));
160 WREG32(data, (v));
161 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
162 }
163
164 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
165 {
166 unsigned long flags;
167 u32 r;
168
169 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
170 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
171 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
172 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
173 return r;
174 }
175
176 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
177 {
178 unsigned long flags;
179
180 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
181 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
182 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
183 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
184 }
185
186 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
187 {
188 unsigned long flags;
189 u32 r;
190
191 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
192 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
193 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
194 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
195 return r;
196 }
197
198 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
199 {
200 unsigned long flags;
201
202 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
203 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
204 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
205 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
206 }
207
208 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
209 {
210 return adev->nbio_funcs->get_memsize(adev);
211 }
212
213 static u32 soc15_get_xclk(struct amdgpu_device *adev)
214 {
215 return adev->clock.spll.reference_freq;
216 }
217
218
219 void soc15_grbm_select(struct amdgpu_device *adev,
220 u32 me, u32 pipe, u32 queue, u32 vmid)
221 {
222 u32 grbm_gfx_cntl = 0;
223 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
224 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
225 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
226 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
227
228 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
229 }
230
231 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
232 {
233 /* todo */
234 }
235
236 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
237 {
238 /* todo */
239 return false;
240 }
241
242 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
243 u8 *bios, u32 length_bytes)
244 {
245 u32 *dw_ptr;
246 u32 i, length_dw;
247
248 if (bios == NULL)
249 return false;
250 if (length_bytes == 0)
251 return false;
252 /* APU vbios image is part of sbios image */
253 if (adev->flags & AMD_IS_APU)
254 return false;
255
256 dw_ptr = (u32 *)bios;
257 length_dw = ALIGN(length_bytes, 4) / 4;
258
259 /* set rom index to 0 */
260 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
261 /* read out the rom data */
262 for (i = 0; i < length_dw; i++)
263 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
264
265 return true;
266 }
267
268 struct soc15_allowed_register_entry {
269 uint32_t hwip;
270 uint32_t inst;
271 uint32_t seg;
272 uint32_t reg_offset;
273 bool grbm_indexed;
274 };
275
276
277 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
278 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
279 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
280 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
281 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
282 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
283 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
284 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
285 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
286 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
287 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
288 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
289 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
290 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
291 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
292 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
293 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
294 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
295 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
296 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
297 };
298
299 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
300 u32 sh_num, u32 reg_offset)
301 {
302 uint32_t val;
303
304 mutex_lock(&adev->grbm_idx_mutex);
305 if (se_num != 0xffffffff || sh_num != 0xffffffff)
306 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
307
308 val = RREG32(reg_offset);
309
310 if (se_num != 0xffffffff || sh_num != 0xffffffff)
311 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
312 mutex_unlock(&adev->grbm_idx_mutex);
313 return val;
314 }
315
316 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
317 bool indexed, u32 se_num,
318 u32 sh_num, u32 reg_offset)
319 {
320 if (indexed) {
321 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
322 } else {
323 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
324 return adev->gfx.config.gb_addr_config;
325 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
326 return adev->gfx.config.db_debug2;
327 return RREG32(reg_offset);
328 }
329 }
330
331 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
332 u32 sh_num, u32 reg_offset, u32 *value)
333 {
334 uint32_t i;
335 struct soc15_allowed_register_entry *en;
336
337 *value = 0;
338 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
339 en = &soc15_allowed_read_registers[i];
340 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
341 + en->reg_offset))
342 continue;
343
344 *value = soc15_get_register_value(adev,
345 soc15_allowed_read_registers[i].grbm_indexed,
346 se_num, sh_num, reg_offset);
347 return 0;
348 }
349 return -EINVAL;
350 }
351
352
353 /**
354 * soc15_program_register_sequence - program an array of registers.
355 *
356 * @adev: amdgpu_device pointer
357 * @regs: pointer to the register array
358 * @array_size: size of the register array
359 *
360 * Programs an array or registers with and and or masks.
361 * This is a helper for setting golden registers.
362 */
363
364 void soc15_program_register_sequence(struct amdgpu_device *adev,
365 const struct soc15_reg_golden *regs,
366 const u32 array_size)
367 {
368 const struct soc15_reg_golden *entry;
369 u32 tmp, reg;
370 int i;
371
372 for (i = 0; i < array_size; ++i) {
373 entry = &regs[i];
374 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
375
376 if (entry->and_mask == 0xffffffff) {
377 tmp = entry->or_mask;
378 } else {
379 tmp = RREG32(reg);
380 tmp &= ~(entry->and_mask);
381 tmp |= entry->or_mask;
382 }
383 WREG32(reg, tmp);
384 }
385
386 }
387
388
389 static int soc15_asic_reset(struct amdgpu_device *adev)
390 {
391 u32 i;
392
393 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
394
395 dev_info(adev->dev, "GPU reset\n");
396
397 /* disable BM */
398 pci_clear_master(adev->pdev);
399
400 pci_save_state(adev->pdev);
401
402 psp_gpu_reset(adev);
403
404 pci_restore_state(adev->pdev);
405
406 /* wait for asic to come out of reset */
407 for (i = 0; i < adev->usec_timeout; i++) {
408 u32 memsize = adev->nbio_funcs->get_memsize(adev);
409
410 if (memsize != 0xffffffff)
411 break;
412 udelay(1);
413 }
414
415 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
416
417 return 0;
418 }
419
420 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
421 u32 cntl_reg, u32 status_reg)
422 {
423 return 0;
424 }*/
425
426 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
427 {
428 /*int r;
429
430 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
431 if (r)
432 return r;
433
434 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
435 */
436 return 0;
437 }
438
439 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
440 {
441 /* todo */
442
443 return 0;
444 }
445
446 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
447 {
448 if (pci_is_root_bus(adev->pdev->bus))
449 return;
450
451 if (amdgpu_pcie_gen2 == 0)
452 return;
453
454 if (adev->flags & AMD_IS_APU)
455 return;
456
457 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
458 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
459 return;
460
461 /* todo */
462 }
463
464 static void soc15_program_aspm(struct amdgpu_device *adev)
465 {
466
467 if (amdgpu_aspm == 0)
468 return;
469
470 /* todo */
471 }
472
473 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
474 bool enable)
475 {
476 adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
477 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
478 }
479
480 static const struct amdgpu_ip_block_version vega10_common_ip_block =
481 {
482 .type = AMD_IP_BLOCK_TYPE_COMMON,
483 .major = 2,
484 .minor = 0,
485 .rev = 0,
486 .funcs = &soc15_common_ip_funcs,
487 };
488
489 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
490 {
491 return adev->nbio_funcs->get_rev_id(adev);
492 }
493
494 int soc15_set_ip_blocks(struct amdgpu_device *adev)
495 {
496 /* Set IP register base before any HW register access */
497 switch (adev->asic_type) {
498 case CHIP_VEGA10:
499 case CHIP_VEGA12:
500 case CHIP_RAVEN:
501 vega10_reg_base_init(adev);
502 break;
503 case CHIP_VEGA20:
504 vega20_reg_base_init(adev);
505 break;
506 default:
507 return -EINVAL;
508 }
509
510 if (adev->asic_type == CHIP_VEGA20)
511 adev->gmc.xgmi.supported = true;
512
513 if (adev->flags & AMD_IS_APU)
514 adev->nbio_funcs = &nbio_v7_0_funcs;
515 else if (adev->asic_type == CHIP_VEGA20)
516 adev->nbio_funcs = &nbio_v7_4_funcs;
517 else
518 adev->nbio_funcs = &nbio_v6_1_funcs;
519
520 if (adev->asic_type == CHIP_VEGA20)
521 adev->df_funcs = &df_v3_6_funcs;
522 else
523 adev->df_funcs = &df_v1_7_funcs;
524
525 adev->rev_id = soc15_get_rev_id(adev);
526 adev->nbio_funcs->detect_hw_virt(adev);
527
528 if (amdgpu_sriov_vf(adev))
529 adev->virt.ops = &xgpu_ai_virt_ops;
530
531 switch (adev->asic_type) {
532 case CHIP_VEGA10:
533 case CHIP_VEGA12:
534 case CHIP_VEGA20:
535 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
536 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
537 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
538 if (adev->asic_type == CHIP_VEGA20)
539 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
540 else
541 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
542 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
543 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
544 if (!amdgpu_sriov_vf(adev))
545 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
546 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
547 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
548 #if defined(CONFIG_DRM_AMD_DC)
549 else if (amdgpu_device_has_dc_support(adev))
550 amdgpu_device_ip_block_add(adev, &dm_ip_block);
551 #else
552 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
553 #endif
554 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
555 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
556 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
557 }
558 break;
559 case CHIP_RAVEN:
560 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
561 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
562 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
563 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
564 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
565 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
566 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
567 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
568 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
569 #if defined(CONFIG_DRM_AMD_DC)
570 else if (amdgpu_device_has_dc_support(adev))
571 amdgpu_device_ip_block_add(adev, &dm_ip_block);
572 #else
573 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
574 #endif
575 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
576 break;
577 default:
578 return -EINVAL;
579 }
580
581 return 0;
582 }
583
584 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
585 {
586 adev->nbio_funcs->hdp_flush(adev, ring);
587 }
588
589 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
590 struct amdgpu_ring *ring)
591 {
592 if (!ring || !ring->funcs->emit_wreg)
593 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
594 else
595 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
596 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
597 }
598
599 static bool soc15_need_full_reset(struct amdgpu_device *adev)
600 {
601 /* change this when we implement soft reset */
602 return true;
603 }
604
605 static const struct amdgpu_asic_funcs soc15_asic_funcs =
606 {
607 .read_disabled_bios = &soc15_read_disabled_bios,
608 .read_bios_from_rom = &soc15_read_bios_from_rom,
609 .read_register = &soc15_read_register,
610 .reset = &soc15_asic_reset,
611 .set_vga_state = &soc15_vga_set_state,
612 .get_xclk = &soc15_get_xclk,
613 .set_uvd_clocks = &soc15_set_uvd_clocks,
614 .set_vce_clocks = &soc15_set_vce_clocks,
615 .get_config_memsize = &soc15_get_config_memsize,
616 .flush_hdp = &soc15_flush_hdp,
617 .invalidate_hdp = &soc15_invalidate_hdp,
618 .need_full_reset = &soc15_need_full_reset,
619 .init_doorbell_index = &vega10_doorbell_index_init,
620 };
621
622 static const struct amdgpu_asic_funcs vega20_asic_funcs =
623 {
624 .read_disabled_bios = &soc15_read_disabled_bios,
625 .read_bios_from_rom = &soc15_read_bios_from_rom,
626 .read_register = &soc15_read_register,
627 .reset = &soc15_asic_reset,
628 .set_vga_state = &soc15_vga_set_state,
629 .get_xclk = &soc15_get_xclk,
630 .set_uvd_clocks = &soc15_set_uvd_clocks,
631 .set_vce_clocks = &soc15_set_vce_clocks,
632 .get_config_memsize = &soc15_get_config_memsize,
633 .flush_hdp = &soc15_flush_hdp,
634 .invalidate_hdp = &soc15_invalidate_hdp,
635 .need_full_reset = &soc15_need_full_reset,
636 .init_doorbell_index = &vega20_doorbell_index_init,
637 };
638
639 static int soc15_common_early_init(void *handle)
640 {
641 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
642
643 adev->smc_rreg = NULL;
644 adev->smc_wreg = NULL;
645 adev->pcie_rreg = &soc15_pcie_rreg;
646 adev->pcie_wreg = &soc15_pcie_wreg;
647 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
648 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
649 adev->didt_rreg = &soc15_didt_rreg;
650 adev->didt_wreg = &soc15_didt_wreg;
651 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
652 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
653 adev->se_cac_rreg = &soc15_se_cac_rreg;
654 adev->se_cac_wreg = &soc15_se_cac_wreg;
655
656
657 adev->external_rev_id = 0xFF;
658 switch (adev->asic_type) {
659 case CHIP_VEGA10:
660 adev->asic_funcs = &soc15_asic_funcs;
661 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
662 AMD_CG_SUPPORT_GFX_MGLS |
663 AMD_CG_SUPPORT_GFX_RLC_LS |
664 AMD_CG_SUPPORT_GFX_CP_LS |
665 AMD_CG_SUPPORT_GFX_3D_CGCG |
666 AMD_CG_SUPPORT_GFX_3D_CGLS |
667 AMD_CG_SUPPORT_GFX_CGCG |
668 AMD_CG_SUPPORT_GFX_CGLS |
669 AMD_CG_SUPPORT_BIF_MGCG |
670 AMD_CG_SUPPORT_BIF_LS |
671 AMD_CG_SUPPORT_HDP_LS |
672 AMD_CG_SUPPORT_DRM_MGCG |
673 AMD_CG_SUPPORT_DRM_LS |
674 AMD_CG_SUPPORT_ROM_MGCG |
675 AMD_CG_SUPPORT_DF_MGCG |
676 AMD_CG_SUPPORT_SDMA_MGCG |
677 AMD_CG_SUPPORT_SDMA_LS |
678 AMD_CG_SUPPORT_MC_MGCG |
679 AMD_CG_SUPPORT_MC_LS;
680 adev->pg_flags = 0;
681 adev->external_rev_id = 0x1;
682 break;
683 case CHIP_VEGA12:
684 adev->asic_funcs = &soc15_asic_funcs;
685 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
686 AMD_CG_SUPPORT_GFX_MGLS |
687 AMD_CG_SUPPORT_GFX_CGCG |
688 AMD_CG_SUPPORT_GFX_CGLS |
689 AMD_CG_SUPPORT_GFX_3D_CGCG |
690 AMD_CG_SUPPORT_GFX_3D_CGLS |
691 AMD_CG_SUPPORT_GFX_CP_LS |
692 AMD_CG_SUPPORT_MC_LS |
693 AMD_CG_SUPPORT_MC_MGCG |
694 AMD_CG_SUPPORT_SDMA_MGCG |
695 AMD_CG_SUPPORT_SDMA_LS |
696 AMD_CG_SUPPORT_BIF_MGCG |
697 AMD_CG_SUPPORT_BIF_LS |
698 AMD_CG_SUPPORT_HDP_MGCG |
699 AMD_CG_SUPPORT_HDP_LS |
700 AMD_CG_SUPPORT_ROM_MGCG |
701 AMD_CG_SUPPORT_VCE_MGCG |
702 AMD_CG_SUPPORT_UVD_MGCG;
703 adev->pg_flags = 0;
704 adev->external_rev_id = adev->rev_id + 0x14;
705 break;
706 case CHIP_VEGA20:
707 adev->asic_funcs = &vega20_asic_funcs;
708 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
709 AMD_CG_SUPPORT_GFX_MGLS |
710 AMD_CG_SUPPORT_GFX_CGCG |
711 AMD_CG_SUPPORT_GFX_CGLS |
712 AMD_CG_SUPPORT_GFX_3D_CGCG |
713 AMD_CG_SUPPORT_GFX_3D_CGLS |
714 AMD_CG_SUPPORT_GFX_CP_LS |
715 AMD_CG_SUPPORT_MC_LS |
716 AMD_CG_SUPPORT_MC_MGCG |
717 AMD_CG_SUPPORT_SDMA_MGCG |
718 AMD_CG_SUPPORT_SDMA_LS |
719 AMD_CG_SUPPORT_BIF_MGCG |
720 AMD_CG_SUPPORT_BIF_LS |
721 AMD_CG_SUPPORT_HDP_MGCG |
722 AMD_CG_SUPPORT_HDP_LS |
723 AMD_CG_SUPPORT_ROM_MGCG |
724 AMD_CG_SUPPORT_VCE_MGCG |
725 AMD_CG_SUPPORT_UVD_MGCG;
726 adev->pg_flags = 0;
727 adev->external_rev_id = adev->rev_id + 0x28;
728 break;
729 case CHIP_RAVEN:
730 adev->asic_funcs = &soc15_asic_funcs;
731 if (adev->rev_id >= 0x8)
732 adev->external_rev_id = adev->rev_id + 0x81;
733 else if (adev->pdev->device == 0x15d8)
734 adev->external_rev_id = adev->rev_id + 0x41;
735 else
736 adev->external_rev_id = 0x1;
737
738 if (adev->rev_id >= 0x8) {
739 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
740 AMD_CG_SUPPORT_GFX_MGLS |
741 AMD_CG_SUPPORT_GFX_CP_LS |
742 AMD_CG_SUPPORT_GFX_3D_CGCG |
743 AMD_CG_SUPPORT_GFX_3D_CGLS |
744 AMD_CG_SUPPORT_GFX_CGCG |
745 AMD_CG_SUPPORT_GFX_CGLS |
746 AMD_CG_SUPPORT_BIF_LS |
747 AMD_CG_SUPPORT_HDP_LS |
748 AMD_CG_SUPPORT_ROM_MGCG |
749 AMD_CG_SUPPORT_MC_MGCG |
750 AMD_CG_SUPPORT_MC_LS |
751 AMD_CG_SUPPORT_SDMA_MGCG |
752 AMD_CG_SUPPORT_SDMA_LS |
753 AMD_CG_SUPPORT_VCN_MGCG;
754
755 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
756 } else if (adev->pdev->device == 0x15d8) {
757 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS |
758 AMD_CG_SUPPORT_GFX_CP_LS |
759 AMD_CG_SUPPORT_GFX_3D_CGCG |
760 AMD_CG_SUPPORT_GFX_3D_CGLS |
761 AMD_CG_SUPPORT_GFX_CGCG |
762 AMD_CG_SUPPORT_GFX_CGLS |
763 AMD_CG_SUPPORT_BIF_LS |
764 AMD_CG_SUPPORT_HDP_LS |
765 AMD_CG_SUPPORT_ROM_MGCG |
766 AMD_CG_SUPPORT_MC_MGCG |
767 AMD_CG_SUPPORT_MC_LS |
768 AMD_CG_SUPPORT_SDMA_MGCG |
769 AMD_CG_SUPPORT_SDMA_LS;
770
771 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
772 AMD_PG_SUPPORT_MMHUB |
773 AMD_PG_SUPPORT_VCN |
774 AMD_PG_SUPPORT_VCN_DPG;
775 } else {
776 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
777 AMD_CG_SUPPORT_GFX_MGLS |
778 AMD_CG_SUPPORT_GFX_RLC_LS |
779 AMD_CG_SUPPORT_GFX_CP_LS |
780 AMD_CG_SUPPORT_GFX_3D_CGCG |
781 AMD_CG_SUPPORT_GFX_3D_CGLS |
782 AMD_CG_SUPPORT_GFX_CGCG |
783 AMD_CG_SUPPORT_GFX_CGLS |
784 AMD_CG_SUPPORT_BIF_MGCG |
785 AMD_CG_SUPPORT_BIF_LS |
786 AMD_CG_SUPPORT_HDP_MGCG |
787 AMD_CG_SUPPORT_HDP_LS |
788 AMD_CG_SUPPORT_DRM_MGCG |
789 AMD_CG_SUPPORT_DRM_LS |
790 AMD_CG_SUPPORT_ROM_MGCG |
791 AMD_CG_SUPPORT_MC_MGCG |
792 AMD_CG_SUPPORT_MC_LS |
793 AMD_CG_SUPPORT_SDMA_MGCG |
794 AMD_CG_SUPPORT_SDMA_LS |
795 AMD_CG_SUPPORT_VCN_MGCG;
796
797 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
798 }
799
800 if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
801 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
802 AMD_PG_SUPPORT_CP |
803 AMD_PG_SUPPORT_RLC_SMU_HS;
804 break;
805 default:
806 /* FIXME: not supported yet */
807 return -EINVAL;
808 }
809
810 if (amdgpu_sriov_vf(adev)) {
811 amdgpu_virt_init_setting(adev);
812 xgpu_ai_mailbox_set_irq_funcs(adev);
813 }
814
815 return 0;
816 }
817
818 static int soc15_common_late_init(void *handle)
819 {
820 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
821
822 if (amdgpu_sriov_vf(adev))
823 xgpu_ai_mailbox_get_irq(adev);
824
825 return 0;
826 }
827
828 static int soc15_common_sw_init(void *handle)
829 {
830 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
831
832 if (amdgpu_sriov_vf(adev))
833 xgpu_ai_mailbox_add_irq_id(adev);
834
835 return 0;
836 }
837
838 static int soc15_common_sw_fini(void *handle)
839 {
840 return 0;
841 }
842
843 static int soc15_common_hw_init(void *handle)
844 {
845 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
846
847 /* enable pcie gen2/3 link */
848 soc15_pcie_gen3_enable(adev);
849 /* enable aspm */
850 soc15_program_aspm(adev);
851 /* setup nbio registers */
852 adev->nbio_funcs->init_registers(adev);
853 /* enable the doorbell aperture */
854 soc15_enable_doorbell_aperture(adev, true);
855
856 return 0;
857 }
858
859 static int soc15_common_hw_fini(void *handle)
860 {
861 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
862
863 /* disable the doorbell aperture */
864 soc15_enable_doorbell_aperture(adev, false);
865 if (amdgpu_sriov_vf(adev))
866 xgpu_ai_mailbox_put_irq(adev);
867
868 return 0;
869 }
870
871 static int soc15_common_suspend(void *handle)
872 {
873 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
874
875 return soc15_common_hw_fini(adev);
876 }
877
878 static int soc15_common_resume(void *handle)
879 {
880 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
881
882 return soc15_common_hw_init(adev);
883 }
884
885 static bool soc15_common_is_idle(void *handle)
886 {
887 return true;
888 }
889
890 static int soc15_common_wait_for_idle(void *handle)
891 {
892 return 0;
893 }
894
895 static int soc15_common_soft_reset(void *handle)
896 {
897 return 0;
898 }
899
900 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
901 {
902 uint32_t def, data;
903
904 if (adev->asic_type == CHIP_VEGA20) {
905 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
906
907 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
908 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
909 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
910 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
911 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
912 else
913 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
914 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
915 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
916 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
917
918 if (def != data)
919 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
920 } else {
921 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
922
923 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
924 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
925 else
926 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
927
928 if (def != data)
929 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
930 }
931 }
932
933 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
934 {
935 uint32_t def, data;
936
937 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
938
939 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
940 data &= ~(0x01000000 |
941 0x02000000 |
942 0x04000000 |
943 0x08000000 |
944 0x10000000 |
945 0x20000000 |
946 0x40000000 |
947 0x80000000);
948 else
949 data |= (0x01000000 |
950 0x02000000 |
951 0x04000000 |
952 0x08000000 |
953 0x10000000 |
954 0x20000000 |
955 0x40000000 |
956 0x80000000);
957
958 if (def != data)
959 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
960 }
961
962 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
963 {
964 uint32_t def, data;
965
966 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
967
968 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
969 data |= 1;
970 else
971 data &= ~1;
972
973 if (def != data)
974 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
975 }
976
977 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
978 bool enable)
979 {
980 uint32_t def, data;
981
982 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
983
984 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
985 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
986 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
987 else
988 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
989 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
990
991 if (def != data)
992 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
993 }
994
995 static int soc15_common_set_clockgating_state(void *handle,
996 enum amd_clockgating_state state)
997 {
998 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
999
1000 if (amdgpu_sriov_vf(adev))
1001 return 0;
1002
1003 switch (adev->asic_type) {
1004 case CHIP_VEGA10:
1005 case CHIP_VEGA12:
1006 case CHIP_VEGA20:
1007 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
1008 state == AMD_CG_STATE_GATE ? true : false);
1009 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
1010 state == AMD_CG_STATE_GATE ? true : false);
1011 soc15_update_hdp_light_sleep(adev,
1012 state == AMD_CG_STATE_GATE ? true : false);
1013 soc15_update_drm_clock_gating(adev,
1014 state == AMD_CG_STATE_GATE ? true : false);
1015 soc15_update_drm_light_sleep(adev,
1016 state == AMD_CG_STATE_GATE ? true : false);
1017 soc15_update_rom_medium_grain_clock_gating(adev,
1018 state == AMD_CG_STATE_GATE ? true : false);
1019 adev->df_funcs->update_medium_grain_clock_gating(adev,
1020 state == AMD_CG_STATE_GATE ? true : false);
1021 break;
1022 case CHIP_RAVEN:
1023 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
1024 state == AMD_CG_STATE_GATE ? true : false);
1025 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
1026 state == AMD_CG_STATE_GATE ? true : false);
1027 soc15_update_hdp_light_sleep(adev,
1028 state == AMD_CG_STATE_GATE ? true : false);
1029 soc15_update_drm_clock_gating(adev,
1030 state == AMD_CG_STATE_GATE ? true : false);
1031 soc15_update_drm_light_sleep(adev,
1032 state == AMD_CG_STATE_GATE ? true : false);
1033 soc15_update_rom_medium_grain_clock_gating(adev,
1034 state == AMD_CG_STATE_GATE ? true : false);
1035 break;
1036 default:
1037 break;
1038 }
1039 return 0;
1040 }
1041
1042 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1043 {
1044 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1045 int data;
1046
1047 if (amdgpu_sriov_vf(adev))
1048 *flags = 0;
1049
1050 adev->nbio_funcs->get_clockgating_state(adev, flags);
1051
1052 /* AMD_CG_SUPPORT_HDP_LS */
1053 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1054 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1055 *flags |= AMD_CG_SUPPORT_HDP_LS;
1056
1057 /* AMD_CG_SUPPORT_DRM_MGCG */
1058 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1059 if (!(data & 0x01000000))
1060 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1061
1062 /* AMD_CG_SUPPORT_DRM_LS */
1063 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1064 if (data & 0x1)
1065 *flags |= AMD_CG_SUPPORT_DRM_LS;
1066
1067 /* AMD_CG_SUPPORT_ROM_MGCG */
1068 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1069 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1070 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1071
1072 adev->df_funcs->get_clockgating_state(adev, flags);
1073 }
1074
1075 static int soc15_common_set_powergating_state(void *handle,
1076 enum amd_powergating_state state)
1077 {
1078 /* todo */
1079 return 0;
1080 }
1081
1082 const struct amd_ip_funcs soc15_common_ip_funcs = {
1083 .name = "soc15_common",
1084 .early_init = soc15_common_early_init,
1085 .late_init = soc15_common_late_init,
1086 .sw_init = soc15_common_sw_init,
1087 .sw_fini = soc15_common_sw_fini,
1088 .hw_init = soc15_common_hw_init,
1089 .hw_fini = soc15_common_hw_fini,
1090 .suspend = soc15_common_suspend,
1091 .resume = soc15_common_resume,
1092 .is_idle = soc15_common_is_idle,
1093 .wait_for_idle = soc15_common_wait_for_idle,
1094 .soft_reset = soc15_common_soft_reset,
1095 .set_clockgating_state = soc15_common_set_clockgating_state,
1096 .set_powergating_state = soc15_common_set_powergating_state,
1097 .get_clockgating_state= soc15_common_get_clockgating_state,
1098 };
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