2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
28 #include "amdgpu_atombios.h"
29 #include "amdgpu_ih.h"
30 #include "amdgpu_uvd.h"
31 #include "amdgpu_vce.h"
32 #include "amdgpu_ucode.h"
33 #include "amdgpu_psp.h"
37 #include "uvd/uvd_7_0_offset.h"
38 #include "gc/gc_9_0_offset.h"
39 #include "gc/gc_9_0_sh_mask.h"
40 #include "sdma0/sdma0_4_0_offset.h"
41 #include "sdma1/sdma1_4_0_offset.h"
42 #include "hdp/hdp_4_0_offset.h"
43 #include "hdp/hdp_4_0_sh_mask.h"
44 #include "smuio/smuio_9_0_offset.h"
45 #include "smuio/smuio_9_0_sh_mask.h"
48 #include "soc15_common.h"
51 #include "gfxhub_v1_0.h"
52 #include "mmhub_v1_0.h"
55 #include "vega10_ih.h"
56 #include "sdma_v4_0.h"
60 #include "dce_virtual.h"
63 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
64 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
65 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
66 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
68 /* for Vega20 register name change */
69 #define mmHDP_MEM_POWER_CTRL 0x00d4
70 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
71 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
72 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
73 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
74 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
76 * Indirect registers accessor
78 static u32
soc15_pcie_rreg(struct amdgpu_device
*adev
, u32 reg
)
80 unsigned long flags
, address
, data
;
82 address
= adev
->nbio_funcs
->get_pcie_index_offset(adev
);
83 data
= adev
->nbio_funcs
->get_pcie_data_offset(adev
);
85 spin_lock_irqsave(&adev
->pcie_idx_lock
, flags
);
87 (void)RREG32(address
);
89 spin_unlock_irqrestore(&adev
->pcie_idx_lock
, flags
);
93 static void soc15_pcie_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
95 unsigned long flags
, address
, data
;
97 address
= adev
->nbio_funcs
->get_pcie_index_offset(adev
);
98 data
= adev
->nbio_funcs
->get_pcie_data_offset(adev
);
100 spin_lock_irqsave(&adev
->pcie_idx_lock
, flags
);
101 WREG32(address
, reg
);
102 (void)RREG32(address
);
105 spin_unlock_irqrestore(&adev
->pcie_idx_lock
, flags
);
108 static u32
soc15_uvd_ctx_rreg(struct amdgpu_device
*adev
, u32 reg
)
110 unsigned long flags
, address
, data
;
113 address
= SOC15_REG_OFFSET(UVD
, 0, mmUVD_CTX_INDEX
);
114 data
= SOC15_REG_OFFSET(UVD
, 0, mmUVD_CTX_DATA
);
116 spin_lock_irqsave(&adev
->uvd_ctx_idx_lock
, flags
);
117 WREG32(address
, ((reg
) & 0x1ff));
119 spin_unlock_irqrestore(&adev
->uvd_ctx_idx_lock
, flags
);
123 static void soc15_uvd_ctx_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
125 unsigned long flags
, address
, data
;
127 address
= SOC15_REG_OFFSET(UVD
, 0, mmUVD_CTX_INDEX
);
128 data
= SOC15_REG_OFFSET(UVD
, 0, mmUVD_CTX_DATA
);
130 spin_lock_irqsave(&adev
->uvd_ctx_idx_lock
, flags
);
131 WREG32(address
, ((reg
) & 0x1ff));
133 spin_unlock_irqrestore(&adev
->uvd_ctx_idx_lock
, flags
);
136 static u32
soc15_didt_rreg(struct amdgpu_device
*adev
, u32 reg
)
138 unsigned long flags
, address
, data
;
141 address
= SOC15_REG_OFFSET(GC
, 0, mmDIDT_IND_INDEX
);
142 data
= SOC15_REG_OFFSET(GC
, 0, mmDIDT_IND_DATA
);
144 spin_lock_irqsave(&adev
->didt_idx_lock
, flags
);
145 WREG32(address
, (reg
));
147 spin_unlock_irqrestore(&adev
->didt_idx_lock
, flags
);
151 static void soc15_didt_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
153 unsigned long flags
, address
, data
;
155 address
= SOC15_REG_OFFSET(GC
, 0, mmDIDT_IND_INDEX
);
156 data
= SOC15_REG_OFFSET(GC
, 0, mmDIDT_IND_DATA
);
158 spin_lock_irqsave(&adev
->didt_idx_lock
, flags
);
159 WREG32(address
, (reg
));
161 spin_unlock_irqrestore(&adev
->didt_idx_lock
, flags
);
164 static u32
soc15_gc_cac_rreg(struct amdgpu_device
*adev
, u32 reg
)
169 spin_lock_irqsave(&adev
->gc_cac_idx_lock
, flags
);
170 WREG32_SOC15(GC
, 0, mmGC_CAC_IND_INDEX
, (reg
));
171 r
= RREG32_SOC15(GC
, 0, mmGC_CAC_IND_DATA
);
172 spin_unlock_irqrestore(&adev
->gc_cac_idx_lock
, flags
);
176 static void soc15_gc_cac_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
180 spin_lock_irqsave(&adev
->gc_cac_idx_lock
, flags
);
181 WREG32_SOC15(GC
, 0, mmGC_CAC_IND_INDEX
, (reg
));
182 WREG32_SOC15(GC
, 0, mmGC_CAC_IND_DATA
, (v
));
183 spin_unlock_irqrestore(&adev
->gc_cac_idx_lock
, flags
);
186 static u32
soc15_se_cac_rreg(struct amdgpu_device
*adev
, u32 reg
)
191 spin_lock_irqsave(&adev
->se_cac_idx_lock
, flags
);
192 WREG32_SOC15(GC
, 0, mmSE_CAC_IND_INDEX
, (reg
));
193 r
= RREG32_SOC15(GC
, 0, mmSE_CAC_IND_DATA
);
194 spin_unlock_irqrestore(&adev
->se_cac_idx_lock
, flags
);
198 static void soc15_se_cac_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
202 spin_lock_irqsave(&adev
->se_cac_idx_lock
, flags
);
203 WREG32_SOC15(GC
, 0, mmSE_CAC_IND_INDEX
, (reg
));
204 WREG32_SOC15(GC
, 0, mmSE_CAC_IND_DATA
, (v
));
205 spin_unlock_irqrestore(&adev
->se_cac_idx_lock
, flags
);
208 static u32
soc15_get_config_memsize(struct amdgpu_device
*adev
)
210 return adev
->nbio_funcs
->get_memsize(adev
);
213 static u32
soc15_get_xclk(struct amdgpu_device
*adev
)
215 return adev
->clock
.spll
.reference_freq
;
219 void soc15_grbm_select(struct amdgpu_device
*adev
,
220 u32 me
, u32 pipe
, u32 queue
, u32 vmid
)
222 u32 grbm_gfx_cntl
= 0;
223 grbm_gfx_cntl
= REG_SET_FIELD(grbm_gfx_cntl
, GRBM_GFX_CNTL
, PIPEID
, pipe
);
224 grbm_gfx_cntl
= REG_SET_FIELD(grbm_gfx_cntl
, GRBM_GFX_CNTL
, MEID
, me
);
225 grbm_gfx_cntl
= REG_SET_FIELD(grbm_gfx_cntl
, GRBM_GFX_CNTL
, VMID
, vmid
);
226 grbm_gfx_cntl
= REG_SET_FIELD(grbm_gfx_cntl
, GRBM_GFX_CNTL
, QUEUEID
, queue
);
228 WREG32(SOC15_REG_OFFSET(GC
, 0, mmGRBM_GFX_CNTL
), grbm_gfx_cntl
);
231 static void soc15_vga_set_state(struct amdgpu_device
*adev
, bool state
)
236 static bool soc15_read_disabled_bios(struct amdgpu_device
*adev
)
242 static bool soc15_read_bios_from_rom(struct amdgpu_device
*adev
,
243 u8
*bios
, u32 length_bytes
)
250 if (length_bytes
== 0)
252 /* APU vbios image is part of sbios image */
253 if (adev
->flags
& AMD_IS_APU
)
256 dw_ptr
= (u32
*)bios
;
257 length_dw
= ALIGN(length_bytes
, 4) / 4;
259 /* set rom index to 0 */
260 WREG32(SOC15_REG_OFFSET(SMUIO
, 0, mmROM_INDEX
), 0);
261 /* read out the rom data */
262 for (i
= 0; i
< length_dw
; i
++)
263 dw_ptr
[i
] = RREG32(SOC15_REG_OFFSET(SMUIO
, 0, mmROM_DATA
));
268 struct soc15_allowed_register_entry
{
277 static struct soc15_allowed_register_entry soc15_allowed_read_registers
[] = {
278 { SOC15_REG_ENTRY(GC
, 0, mmGRBM_STATUS
)},
279 { SOC15_REG_ENTRY(GC
, 0, mmGRBM_STATUS2
)},
280 { SOC15_REG_ENTRY(GC
, 0, mmGRBM_STATUS_SE0
)},
281 { SOC15_REG_ENTRY(GC
, 0, mmGRBM_STATUS_SE1
)},
282 { SOC15_REG_ENTRY(GC
, 0, mmGRBM_STATUS_SE2
)},
283 { SOC15_REG_ENTRY(GC
, 0, mmGRBM_STATUS_SE3
)},
284 { SOC15_REG_ENTRY(SDMA0
, 0, mmSDMA0_STATUS_REG
)},
285 { SOC15_REG_ENTRY(SDMA1
, 0, mmSDMA1_STATUS_REG
)},
286 { SOC15_REG_ENTRY(GC
, 0, mmCP_STAT
)},
287 { SOC15_REG_ENTRY(GC
, 0, mmCP_STALLED_STAT1
)},
288 { SOC15_REG_ENTRY(GC
, 0, mmCP_STALLED_STAT2
)},
289 { SOC15_REG_ENTRY(GC
, 0, mmCP_STALLED_STAT3
)},
290 { SOC15_REG_ENTRY(GC
, 0, mmCP_CPF_BUSY_STAT
)},
291 { SOC15_REG_ENTRY(GC
, 0, mmCP_CPF_STALLED_STAT1
)},
292 { SOC15_REG_ENTRY(GC
, 0, mmCP_CPF_STATUS
)},
293 { SOC15_REG_ENTRY(GC
, 0, mmCP_CPC_STALLED_STAT1
)},
294 { SOC15_REG_ENTRY(GC
, 0, mmCP_CPC_STATUS
)},
295 { SOC15_REG_ENTRY(GC
, 0, mmGB_ADDR_CONFIG
)},
296 { SOC15_REG_ENTRY(GC
, 0, mmDB_DEBUG2
)},
299 static uint32_t soc15_read_indexed_register(struct amdgpu_device
*adev
, u32 se_num
,
300 u32 sh_num
, u32 reg_offset
)
304 mutex_lock(&adev
->grbm_idx_mutex
);
305 if (se_num
!= 0xffffffff || sh_num
!= 0xffffffff)
306 amdgpu_gfx_select_se_sh(adev
, se_num
, sh_num
, 0xffffffff);
308 val
= RREG32(reg_offset
);
310 if (se_num
!= 0xffffffff || sh_num
!= 0xffffffff)
311 amdgpu_gfx_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
312 mutex_unlock(&adev
->grbm_idx_mutex
);
316 static uint32_t soc15_get_register_value(struct amdgpu_device
*adev
,
317 bool indexed
, u32 se_num
,
318 u32 sh_num
, u32 reg_offset
)
321 return soc15_read_indexed_register(adev
, se_num
, sh_num
, reg_offset
);
323 if (reg_offset
== SOC15_REG_OFFSET(GC
, 0, mmGB_ADDR_CONFIG
))
324 return adev
->gfx
.config
.gb_addr_config
;
325 else if (reg_offset
== SOC15_REG_OFFSET(GC
, 0, mmDB_DEBUG2
))
326 return adev
->gfx
.config
.db_debug2
;
327 return RREG32(reg_offset
);
331 static int soc15_read_register(struct amdgpu_device
*adev
, u32 se_num
,
332 u32 sh_num
, u32 reg_offset
, u32
*value
)
335 struct soc15_allowed_register_entry
*en
;
338 for (i
= 0; i
< ARRAY_SIZE(soc15_allowed_read_registers
); i
++) {
339 en
= &soc15_allowed_read_registers
[i
];
340 if (reg_offset
!= (adev
->reg_offset
[en
->hwip
][en
->inst
][en
->seg
]
344 *value
= soc15_get_register_value(adev
,
345 soc15_allowed_read_registers
[i
].grbm_indexed
,
346 se_num
, sh_num
, reg_offset
);
354 * soc15_program_register_sequence - program an array of registers.
356 * @adev: amdgpu_device pointer
357 * @regs: pointer to the register array
358 * @array_size: size of the register array
360 * Programs an array or registers with and and or masks.
361 * This is a helper for setting golden registers.
364 void soc15_program_register_sequence(struct amdgpu_device
*adev
,
365 const struct soc15_reg_golden
*regs
,
366 const u32 array_size
)
368 const struct soc15_reg_golden
*entry
;
372 for (i
= 0; i
< array_size
; ++i
) {
374 reg
= adev
->reg_offset
[entry
->hwip
][entry
->instance
][entry
->segment
] + entry
->reg
;
376 if (entry
->and_mask
== 0xffffffff) {
377 tmp
= entry
->or_mask
;
380 tmp
&= ~(entry
->and_mask
);
381 tmp
|= entry
->or_mask
;
389 static int soc15_asic_reset(struct amdgpu_device
*adev
)
393 amdgpu_atombios_scratch_regs_engine_hung(adev
, true);
395 dev_info(adev
->dev
, "GPU reset\n");
398 pci_clear_master(adev
->pdev
);
400 pci_save_state(adev
->pdev
);
404 pci_restore_state(adev
->pdev
);
406 /* wait for asic to come out of reset */
407 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
408 u32 memsize
= adev
->nbio_funcs
->get_memsize(adev
);
410 if (memsize
!= 0xffffffff)
415 amdgpu_atombios_scratch_regs_engine_hung(adev
, false);
420 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
421 u32 cntl_reg, u32 status_reg)
426 static int soc15_set_uvd_clocks(struct amdgpu_device
*adev
, u32 vclk
, u32 dclk
)
430 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
434 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
439 static int soc15_set_vce_clocks(struct amdgpu_device
*adev
, u32 evclk
, u32 ecclk
)
446 static void soc15_pcie_gen3_enable(struct amdgpu_device
*adev
)
448 if (pci_is_root_bus(adev
->pdev
->bus
))
451 if (amdgpu_pcie_gen2
== 0)
454 if (adev
->flags
& AMD_IS_APU
)
457 if (!(adev
->pm
.pcie_gen_mask
& (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2
|
458 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3
)))
464 static void soc15_program_aspm(struct amdgpu_device
*adev
)
467 if (amdgpu_aspm
== 0)
473 static void soc15_enable_doorbell_aperture(struct amdgpu_device
*adev
,
476 adev
->nbio_funcs
->enable_doorbell_aperture(adev
, enable
);
477 adev
->nbio_funcs
->enable_doorbell_selfring_aperture(adev
, enable
);
480 static const struct amdgpu_ip_block_version vega10_common_ip_block
=
482 .type
= AMD_IP_BLOCK_TYPE_COMMON
,
486 .funcs
= &soc15_common_ip_funcs
,
489 static uint32_t soc15_get_rev_id(struct amdgpu_device
*adev
)
491 return adev
->nbio_funcs
->get_rev_id(adev
);
494 int soc15_set_ip_blocks(struct amdgpu_device
*adev
)
496 /* Set IP register base before any HW register access */
497 switch (adev
->asic_type
) {
501 vega10_reg_base_init(adev
);
504 vega20_reg_base_init(adev
);
510 if (adev
->asic_type
== CHIP_VEGA20
)
511 adev
->gmc
.xgmi
.supported
= true;
513 if (adev
->flags
& AMD_IS_APU
)
514 adev
->nbio_funcs
= &nbio_v7_0_funcs
;
515 else if (adev
->asic_type
== CHIP_VEGA20
)
516 adev
->nbio_funcs
= &nbio_v7_4_funcs
;
518 adev
->nbio_funcs
= &nbio_v6_1_funcs
;
520 if (adev
->asic_type
== CHIP_VEGA20
)
521 adev
->df_funcs
= &df_v3_6_funcs
;
523 adev
->df_funcs
= &df_v1_7_funcs
;
525 adev
->rev_id
= soc15_get_rev_id(adev
);
526 adev
->nbio_funcs
->detect_hw_virt(adev
);
528 if (amdgpu_sriov_vf(adev
))
529 adev
->virt
.ops
= &xgpu_ai_virt_ops
;
531 switch (adev
->asic_type
) {
535 amdgpu_device_ip_block_add(adev
, &vega10_common_ip_block
);
536 amdgpu_device_ip_block_add(adev
, &gmc_v9_0_ip_block
);
537 amdgpu_device_ip_block_add(adev
, &vega10_ih_ip_block
);
538 if (adev
->asic_type
== CHIP_VEGA20
)
539 amdgpu_device_ip_block_add(adev
, &psp_v11_0_ip_block
);
541 amdgpu_device_ip_block_add(adev
, &psp_v3_1_ip_block
);
542 amdgpu_device_ip_block_add(adev
, &gfx_v9_0_ip_block
);
543 amdgpu_device_ip_block_add(adev
, &sdma_v4_0_ip_block
);
544 if (!amdgpu_sriov_vf(adev
))
545 amdgpu_device_ip_block_add(adev
, &pp_smu_ip_block
);
546 if (adev
->enable_virtual_display
|| amdgpu_sriov_vf(adev
))
547 amdgpu_device_ip_block_add(adev
, &dce_virtual_ip_block
);
548 #if defined(CONFIG_DRM_AMD_DC)
549 else if (amdgpu_device_has_dc_support(adev
))
550 amdgpu_device_ip_block_add(adev
, &dm_ip_block
);
552 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
554 if (!(adev
->asic_type
== CHIP_VEGA20
&& amdgpu_sriov_vf(adev
))) {
555 amdgpu_device_ip_block_add(adev
, &uvd_v7_0_ip_block
);
556 amdgpu_device_ip_block_add(adev
, &vce_v4_0_ip_block
);
560 amdgpu_device_ip_block_add(adev
, &vega10_common_ip_block
);
561 amdgpu_device_ip_block_add(adev
, &gmc_v9_0_ip_block
);
562 amdgpu_device_ip_block_add(adev
, &vega10_ih_ip_block
);
563 amdgpu_device_ip_block_add(adev
, &psp_v10_0_ip_block
);
564 amdgpu_device_ip_block_add(adev
, &gfx_v9_0_ip_block
);
565 amdgpu_device_ip_block_add(adev
, &sdma_v4_0_ip_block
);
566 amdgpu_device_ip_block_add(adev
, &pp_smu_ip_block
);
567 if (adev
->enable_virtual_display
|| amdgpu_sriov_vf(adev
))
568 amdgpu_device_ip_block_add(adev
, &dce_virtual_ip_block
);
569 #if defined(CONFIG_DRM_AMD_DC)
570 else if (amdgpu_device_has_dc_support(adev
))
571 amdgpu_device_ip_block_add(adev
, &dm_ip_block
);
573 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
575 amdgpu_device_ip_block_add(adev
, &vcn_v1_0_ip_block
);
584 static void soc15_flush_hdp(struct amdgpu_device
*adev
, struct amdgpu_ring
*ring
)
586 adev
->nbio_funcs
->hdp_flush(adev
, ring
);
589 static void soc15_invalidate_hdp(struct amdgpu_device
*adev
,
590 struct amdgpu_ring
*ring
)
592 if (!ring
|| !ring
->funcs
->emit_wreg
)
593 WREG32_SOC15_NO_KIQ(NBIO
, 0, mmHDP_READ_CACHE_INVALIDATE
, 1);
595 amdgpu_ring_emit_wreg(ring
, SOC15_REG_OFFSET(
596 HDP
, 0, mmHDP_READ_CACHE_INVALIDATE
), 1);
599 static bool soc15_need_full_reset(struct amdgpu_device
*adev
)
601 /* change this when we implement soft reset */
605 static const struct amdgpu_asic_funcs soc15_asic_funcs
=
607 .read_disabled_bios
= &soc15_read_disabled_bios
,
608 .read_bios_from_rom
= &soc15_read_bios_from_rom
,
609 .read_register
= &soc15_read_register
,
610 .reset
= &soc15_asic_reset
,
611 .set_vga_state
= &soc15_vga_set_state
,
612 .get_xclk
= &soc15_get_xclk
,
613 .set_uvd_clocks
= &soc15_set_uvd_clocks
,
614 .set_vce_clocks
= &soc15_set_vce_clocks
,
615 .get_config_memsize
= &soc15_get_config_memsize
,
616 .flush_hdp
= &soc15_flush_hdp
,
617 .invalidate_hdp
= &soc15_invalidate_hdp
,
618 .need_full_reset
= &soc15_need_full_reset
,
619 .init_doorbell_index
= &vega10_doorbell_index_init
,
622 static const struct amdgpu_asic_funcs vega20_asic_funcs
=
624 .read_disabled_bios
= &soc15_read_disabled_bios
,
625 .read_bios_from_rom
= &soc15_read_bios_from_rom
,
626 .read_register
= &soc15_read_register
,
627 .reset
= &soc15_asic_reset
,
628 .set_vga_state
= &soc15_vga_set_state
,
629 .get_xclk
= &soc15_get_xclk
,
630 .set_uvd_clocks
= &soc15_set_uvd_clocks
,
631 .set_vce_clocks
= &soc15_set_vce_clocks
,
632 .get_config_memsize
= &soc15_get_config_memsize
,
633 .flush_hdp
= &soc15_flush_hdp
,
634 .invalidate_hdp
= &soc15_invalidate_hdp
,
635 .need_full_reset
= &soc15_need_full_reset
,
636 .init_doorbell_index
= &vega20_doorbell_index_init
,
639 static int soc15_common_early_init(void *handle
)
641 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
643 adev
->smc_rreg
= NULL
;
644 adev
->smc_wreg
= NULL
;
645 adev
->pcie_rreg
= &soc15_pcie_rreg
;
646 adev
->pcie_wreg
= &soc15_pcie_wreg
;
647 adev
->uvd_ctx_rreg
= &soc15_uvd_ctx_rreg
;
648 adev
->uvd_ctx_wreg
= &soc15_uvd_ctx_wreg
;
649 adev
->didt_rreg
= &soc15_didt_rreg
;
650 adev
->didt_wreg
= &soc15_didt_wreg
;
651 adev
->gc_cac_rreg
= &soc15_gc_cac_rreg
;
652 adev
->gc_cac_wreg
= &soc15_gc_cac_wreg
;
653 adev
->se_cac_rreg
= &soc15_se_cac_rreg
;
654 adev
->se_cac_wreg
= &soc15_se_cac_wreg
;
657 adev
->external_rev_id
= 0xFF;
658 switch (adev
->asic_type
) {
660 adev
->asic_funcs
= &soc15_asic_funcs
;
661 adev
->cg_flags
= AMD_CG_SUPPORT_GFX_MGCG
|
662 AMD_CG_SUPPORT_GFX_MGLS
|
663 AMD_CG_SUPPORT_GFX_RLC_LS
|
664 AMD_CG_SUPPORT_GFX_CP_LS
|
665 AMD_CG_SUPPORT_GFX_3D_CGCG
|
666 AMD_CG_SUPPORT_GFX_3D_CGLS
|
667 AMD_CG_SUPPORT_GFX_CGCG
|
668 AMD_CG_SUPPORT_GFX_CGLS
|
669 AMD_CG_SUPPORT_BIF_MGCG
|
670 AMD_CG_SUPPORT_BIF_LS
|
671 AMD_CG_SUPPORT_HDP_LS
|
672 AMD_CG_SUPPORT_DRM_MGCG
|
673 AMD_CG_SUPPORT_DRM_LS
|
674 AMD_CG_SUPPORT_ROM_MGCG
|
675 AMD_CG_SUPPORT_DF_MGCG
|
676 AMD_CG_SUPPORT_SDMA_MGCG
|
677 AMD_CG_SUPPORT_SDMA_LS
|
678 AMD_CG_SUPPORT_MC_MGCG
|
679 AMD_CG_SUPPORT_MC_LS
;
681 adev
->external_rev_id
= 0x1;
684 adev
->asic_funcs
= &soc15_asic_funcs
;
685 adev
->cg_flags
= AMD_CG_SUPPORT_GFX_MGCG
|
686 AMD_CG_SUPPORT_GFX_MGLS
|
687 AMD_CG_SUPPORT_GFX_CGCG
|
688 AMD_CG_SUPPORT_GFX_CGLS
|
689 AMD_CG_SUPPORT_GFX_3D_CGCG
|
690 AMD_CG_SUPPORT_GFX_3D_CGLS
|
691 AMD_CG_SUPPORT_GFX_CP_LS
|
692 AMD_CG_SUPPORT_MC_LS
|
693 AMD_CG_SUPPORT_MC_MGCG
|
694 AMD_CG_SUPPORT_SDMA_MGCG
|
695 AMD_CG_SUPPORT_SDMA_LS
|
696 AMD_CG_SUPPORT_BIF_MGCG
|
697 AMD_CG_SUPPORT_BIF_LS
|
698 AMD_CG_SUPPORT_HDP_MGCG
|
699 AMD_CG_SUPPORT_HDP_LS
|
700 AMD_CG_SUPPORT_ROM_MGCG
|
701 AMD_CG_SUPPORT_VCE_MGCG
|
702 AMD_CG_SUPPORT_UVD_MGCG
;
704 adev
->external_rev_id
= adev
->rev_id
+ 0x14;
707 adev
->asic_funcs
= &vega20_asic_funcs
;
708 adev
->cg_flags
= AMD_CG_SUPPORT_GFX_MGCG
|
709 AMD_CG_SUPPORT_GFX_MGLS
|
710 AMD_CG_SUPPORT_GFX_CGCG
|
711 AMD_CG_SUPPORT_GFX_CGLS
|
712 AMD_CG_SUPPORT_GFX_3D_CGCG
|
713 AMD_CG_SUPPORT_GFX_3D_CGLS
|
714 AMD_CG_SUPPORT_GFX_CP_LS
|
715 AMD_CG_SUPPORT_MC_LS
|
716 AMD_CG_SUPPORT_MC_MGCG
|
717 AMD_CG_SUPPORT_SDMA_MGCG
|
718 AMD_CG_SUPPORT_SDMA_LS
|
719 AMD_CG_SUPPORT_BIF_MGCG
|
720 AMD_CG_SUPPORT_BIF_LS
|
721 AMD_CG_SUPPORT_HDP_MGCG
|
722 AMD_CG_SUPPORT_HDP_LS
|
723 AMD_CG_SUPPORT_ROM_MGCG
|
724 AMD_CG_SUPPORT_VCE_MGCG
|
725 AMD_CG_SUPPORT_UVD_MGCG
;
727 adev
->external_rev_id
= adev
->rev_id
+ 0x28;
730 adev
->asic_funcs
= &soc15_asic_funcs
;
731 if (adev
->rev_id
>= 0x8)
732 adev
->external_rev_id
= adev
->rev_id
+ 0x79;
733 else if (adev
->pdev
->device
== 0x15d8)
734 adev
->external_rev_id
= adev
->rev_id
+ 0x41;
735 else if (adev
->rev_id
== 1)
736 adev
->external_rev_id
= adev
->rev_id
+ 0x20;
738 adev
->external_rev_id
= adev
->rev_id
+ 0x01;
740 if (adev
->rev_id
>= 0x8) {
741 adev
->cg_flags
= AMD_CG_SUPPORT_GFX_MGCG
|
742 AMD_CG_SUPPORT_GFX_MGLS
|
743 AMD_CG_SUPPORT_GFX_CP_LS
|
744 AMD_CG_SUPPORT_GFX_3D_CGCG
|
745 AMD_CG_SUPPORT_GFX_3D_CGLS
|
746 AMD_CG_SUPPORT_GFX_CGCG
|
747 AMD_CG_SUPPORT_GFX_CGLS
|
748 AMD_CG_SUPPORT_BIF_LS
|
749 AMD_CG_SUPPORT_HDP_LS
|
750 AMD_CG_SUPPORT_ROM_MGCG
|
751 AMD_CG_SUPPORT_MC_MGCG
|
752 AMD_CG_SUPPORT_MC_LS
|
753 AMD_CG_SUPPORT_SDMA_MGCG
|
754 AMD_CG_SUPPORT_SDMA_LS
|
755 AMD_CG_SUPPORT_VCN_MGCG
;
757 adev
->pg_flags
= AMD_PG_SUPPORT_SDMA
| AMD_PG_SUPPORT_VCN
;
758 } else if (adev
->pdev
->device
== 0x15d8) {
759 adev
->cg_flags
= AMD_CG_SUPPORT_GFX_MGLS
|
760 AMD_CG_SUPPORT_GFX_CP_LS
|
761 AMD_CG_SUPPORT_GFX_3D_CGCG
|
762 AMD_CG_SUPPORT_GFX_3D_CGLS
|
763 AMD_CG_SUPPORT_GFX_CGCG
|
764 AMD_CG_SUPPORT_GFX_CGLS
|
765 AMD_CG_SUPPORT_BIF_LS
|
766 AMD_CG_SUPPORT_HDP_LS
|
767 AMD_CG_SUPPORT_ROM_MGCG
|
768 AMD_CG_SUPPORT_MC_MGCG
|
769 AMD_CG_SUPPORT_MC_LS
|
770 AMD_CG_SUPPORT_SDMA_MGCG
|
771 AMD_CG_SUPPORT_SDMA_LS
;
773 adev
->pg_flags
= AMD_PG_SUPPORT_SDMA
|
774 AMD_PG_SUPPORT_MMHUB
|
776 AMD_PG_SUPPORT_VCN_DPG
;
778 adev
->cg_flags
= AMD_CG_SUPPORT_GFX_MGCG
|
779 AMD_CG_SUPPORT_GFX_MGLS
|
780 AMD_CG_SUPPORT_GFX_RLC_LS
|
781 AMD_CG_SUPPORT_GFX_CP_LS
|
782 AMD_CG_SUPPORT_GFX_3D_CGCG
|
783 AMD_CG_SUPPORT_GFX_3D_CGLS
|
784 AMD_CG_SUPPORT_GFX_CGCG
|
785 AMD_CG_SUPPORT_GFX_CGLS
|
786 AMD_CG_SUPPORT_BIF_MGCG
|
787 AMD_CG_SUPPORT_BIF_LS
|
788 AMD_CG_SUPPORT_HDP_MGCG
|
789 AMD_CG_SUPPORT_HDP_LS
|
790 AMD_CG_SUPPORT_DRM_MGCG
|
791 AMD_CG_SUPPORT_DRM_LS
|
792 AMD_CG_SUPPORT_ROM_MGCG
|
793 AMD_CG_SUPPORT_MC_MGCG
|
794 AMD_CG_SUPPORT_MC_LS
|
795 AMD_CG_SUPPORT_SDMA_MGCG
|
796 AMD_CG_SUPPORT_SDMA_LS
|
797 AMD_CG_SUPPORT_VCN_MGCG
;
799 adev
->pg_flags
= AMD_PG_SUPPORT_SDMA
| AMD_PG_SUPPORT_VCN
;
802 if (adev
->powerplay
.pp_feature
& PP_GFXOFF_MASK
)
803 adev
->pg_flags
|= AMD_PG_SUPPORT_GFX_PG
|
805 AMD_PG_SUPPORT_RLC_SMU_HS
;
808 /* FIXME: not supported yet */
812 if (amdgpu_sriov_vf(adev
)) {
813 amdgpu_virt_init_setting(adev
);
814 xgpu_ai_mailbox_set_irq_funcs(adev
);
820 static int soc15_common_late_init(void *handle
)
822 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
824 if (amdgpu_sriov_vf(adev
))
825 xgpu_ai_mailbox_get_irq(adev
);
830 static int soc15_common_sw_init(void *handle
)
832 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
834 if (amdgpu_sriov_vf(adev
))
835 xgpu_ai_mailbox_add_irq_id(adev
);
840 static int soc15_common_sw_fini(void *handle
)
845 static int soc15_common_hw_init(void *handle
)
847 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
849 /* enable pcie gen2/3 link */
850 soc15_pcie_gen3_enable(adev
);
852 soc15_program_aspm(adev
);
853 /* setup nbio registers */
854 adev
->nbio_funcs
->init_registers(adev
);
855 /* enable the doorbell aperture */
856 soc15_enable_doorbell_aperture(adev
, true);
861 static int soc15_common_hw_fini(void *handle
)
863 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
865 /* disable the doorbell aperture */
866 soc15_enable_doorbell_aperture(adev
, false);
867 if (amdgpu_sriov_vf(adev
))
868 xgpu_ai_mailbox_put_irq(adev
);
873 static int soc15_common_suspend(void *handle
)
875 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
877 return soc15_common_hw_fini(adev
);
880 static int soc15_common_resume(void *handle
)
882 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
884 return soc15_common_hw_init(adev
);
887 static bool soc15_common_is_idle(void *handle
)
892 static int soc15_common_wait_for_idle(void *handle
)
897 static int soc15_common_soft_reset(void *handle
)
902 static void soc15_update_hdp_light_sleep(struct amdgpu_device
*adev
, bool enable
)
906 if (adev
->asic_type
== CHIP_VEGA20
) {
907 def
= data
= RREG32(SOC15_REG_OFFSET(HDP
, 0, mmHDP_MEM_POWER_CTRL
));
909 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_HDP_LS
))
910 data
|= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK
|
911 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK
|
912 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK
|
913 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK
;
915 data
&= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK
|
916 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK
|
917 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK
|
918 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK
);
921 WREG32(SOC15_REG_OFFSET(HDP
, 0, mmHDP_MEM_POWER_CTRL
), data
);
923 def
= data
= RREG32(SOC15_REG_OFFSET(HDP
, 0, mmHDP_MEM_POWER_LS
));
925 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_HDP_LS
))
926 data
|= HDP_MEM_POWER_LS__LS_ENABLE_MASK
;
928 data
&= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK
;
931 WREG32(SOC15_REG_OFFSET(HDP
, 0, mmHDP_MEM_POWER_LS
), data
);
935 static void soc15_update_drm_clock_gating(struct amdgpu_device
*adev
, bool enable
)
939 def
= data
= RREG32(SOC15_REG_OFFSET(MP0
, 0, mmMP0_MISC_CGTT_CTRL0
));
941 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_DRM_MGCG
))
942 data
&= ~(0x01000000 |
951 data
|= (0x01000000 |
961 WREG32(SOC15_REG_OFFSET(MP0
, 0, mmMP0_MISC_CGTT_CTRL0
), data
);
964 static void soc15_update_drm_light_sleep(struct amdgpu_device
*adev
, bool enable
)
968 def
= data
= RREG32(SOC15_REG_OFFSET(MP0
, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL
));
970 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_DRM_LS
))
976 WREG32(SOC15_REG_OFFSET(MP0
, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL
), data
);
979 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device
*adev
,
984 def
= data
= RREG32(SOC15_REG_OFFSET(SMUIO
, 0, mmCGTT_ROM_CLK_CTRL0
));
986 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_ROM_MGCG
))
987 data
&= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK
|
988 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK
);
990 data
|= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK
|
991 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK
;
994 WREG32(SOC15_REG_OFFSET(SMUIO
, 0, mmCGTT_ROM_CLK_CTRL0
), data
);
997 static int soc15_common_set_clockgating_state(void *handle
,
998 enum amd_clockgating_state state
)
1000 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1002 if (amdgpu_sriov_vf(adev
))
1005 switch (adev
->asic_type
) {
1009 adev
->nbio_funcs
->update_medium_grain_clock_gating(adev
,
1010 state
== AMD_CG_STATE_GATE
? true : false);
1011 adev
->nbio_funcs
->update_medium_grain_light_sleep(adev
,
1012 state
== AMD_CG_STATE_GATE
? true : false);
1013 soc15_update_hdp_light_sleep(adev
,
1014 state
== AMD_CG_STATE_GATE
? true : false);
1015 soc15_update_drm_clock_gating(adev
,
1016 state
== AMD_CG_STATE_GATE
? true : false);
1017 soc15_update_drm_light_sleep(adev
,
1018 state
== AMD_CG_STATE_GATE
? true : false);
1019 soc15_update_rom_medium_grain_clock_gating(adev
,
1020 state
== AMD_CG_STATE_GATE
? true : false);
1021 adev
->df_funcs
->update_medium_grain_clock_gating(adev
,
1022 state
== AMD_CG_STATE_GATE
? true : false);
1025 adev
->nbio_funcs
->update_medium_grain_clock_gating(adev
,
1026 state
== AMD_CG_STATE_GATE
? true : false);
1027 adev
->nbio_funcs
->update_medium_grain_light_sleep(adev
,
1028 state
== AMD_CG_STATE_GATE
? true : false);
1029 soc15_update_hdp_light_sleep(adev
,
1030 state
== AMD_CG_STATE_GATE
? true : false);
1031 soc15_update_drm_clock_gating(adev
,
1032 state
== AMD_CG_STATE_GATE
? true : false);
1033 soc15_update_drm_light_sleep(adev
,
1034 state
== AMD_CG_STATE_GATE
? true : false);
1035 soc15_update_rom_medium_grain_clock_gating(adev
,
1036 state
== AMD_CG_STATE_GATE
? true : false);
1044 static void soc15_common_get_clockgating_state(void *handle
, u32
*flags
)
1046 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1049 if (amdgpu_sriov_vf(adev
))
1052 adev
->nbio_funcs
->get_clockgating_state(adev
, flags
);
1054 /* AMD_CG_SUPPORT_HDP_LS */
1055 data
= RREG32(SOC15_REG_OFFSET(HDP
, 0, mmHDP_MEM_POWER_LS
));
1056 if (data
& HDP_MEM_POWER_LS__LS_ENABLE_MASK
)
1057 *flags
|= AMD_CG_SUPPORT_HDP_LS
;
1059 /* AMD_CG_SUPPORT_DRM_MGCG */
1060 data
= RREG32(SOC15_REG_OFFSET(MP0
, 0, mmMP0_MISC_CGTT_CTRL0
));
1061 if (!(data
& 0x01000000))
1062 *flags
|= AMD_CG_SUPPORT_DRM_MGCG
;
1064 /* AMD_CG_SUPPORT_DRM_LS */
1065 data
= RREG32(SOC15_REG_OFFSET(MP0
, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL
));
1067 *flags
|= AMD_CG_SUPPORT_DRM_LS
;
1069 /* AMD_CG_SUPPORT_ROM_MGCG */
1070 data
= RREG32(SOC15_REG_OFFSET(SMUIO
, 0, mmCGTT_ROM_CLK_CTRL0
));
1071 if (!(data
& CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK
))
1072 *flags
|= AMD_CG_SUPPORT_ROM_MGCG
;
1074 adev
->df_funcs
->get_clockgating_state(adev
, flags
);
1077 static int soc15_common_set_powergating_state(void *handle
,
1078 enum amd_powergating_state state
)
1084 const struct amd_ip_funcs soc15_common_ip_funcs
= {
1085 .name
= "soc15_common",
1086 .early_init
= soc15_common_early_init
,
1087 .late_init
= soc15_common_late_init
,
1088 .sw_init
= soc15_common_sw_init
,
1089 .sw_fini
= soc15_common_sw_fini
,
1090 .hw_init
= soc15_common_hw_init
,
1091 .hw_fini
= soc15_common_hw_fini
,
1092 .suspend
= soc15_common_suspend
,
1093 .resume
= soc15_common_resume
,
1094 .is_idle
= soc15_common_is_idle
,
1095 .wait_for_idle
= soc15_common_wait_for_idle
,
1096 .soft_reset
= soc15_common_soft_reset
,
1097 .set_clockgating_state
= soc15_common_set_clockgating_state
,
1098 .set_powergating_state
= soc15_common_set_powergating_state
,
1099 .get_clockgating_state
= soc15_common_get_clockgating_state
,