2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Christian König <christian.koenig@amd.com>
25 #include <linux/firmware.h>
28 #include "amdgpu_uvd.h"
31 #include "uvd/uvd_4_2_d.h"
32 #include "uvd/uvd_4_2_sh_mask.h"
34 #include "oss/oss_2_0_d.h"
35 #include "oss/oss_2_0_sh_mask.h"
37 #include "bif/bif_4_1_d.h"
39 #include "smu/smu_7_0_1_d.h"
40 #include "smu/smu_7_0_1_sh_mask.h"
42 static void uvd_v4_2_mc_resume(struct amdgpu_device
*adev
);
43 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device
*adev
);
44 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device
*adev
);
45 static int uvd_v4_2_start(struct amdgpu_device
*adev
);
46 static void uvd_v4_2_stop(struct amdgpu_device
*adev
);
47 static int uvd_v4_2_set_clockgating_state(void *handle
,
48 enum amd_clockgating_state state
);
49 static void uvd_v4_2_set_dcm(struct amdgpu_device
*adev
,
52 * uvd_v4_2_ring_get_rptr - get read pointer
54 * @ring: amdgpu_ring pointer
56 * Returns the current hardware read pointer
58 static uint64_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring
*ring
)
60 struct amdgpu_device
*adev
= ring
->adev
;
62 return RREG32(mmUVD_RBC_RB_RPTR
);
66 * uvd_v4_2_ring_get_wptr - get write pointer
68 * @ring: amdgpu_ring pointer
70 * Returns the current hardware write pointer
72 static uint64_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring
*ring
)
74 struct amdgpu_device
*adev
= ring
->adev
;
76 return RREG32(mmUVD_RBC_RB_WPTR
);
80 * uvd_v4_2_ring_set_wptr - set write pointer
82 * @ring: amdgpu_ring pointer
84 * Commits the write pointer to the hardware
86 static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring
*ring
)
88 struct amdgpu_device
*adev
= ring
->adev
;
90 WREG32(mmUVD_RBC_RB_WPTR
, lower_32_bits(ring
->wptr
));
93 static int uvd_v4_2_early_init(void *handle
)
95 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
97 uvd_v4_2_set_ring_funcs(adev
);
98 uvd_v4_2_set_irq_funcs(adev
);
103 static int uvd_v4_2_sw_init(void *handle
)
105 struct amdgpu_ring
*ring
;
106 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
110 r
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_LEGACY
, 124, &adev
->uvd
.irq
);
114 r
= amdgpu_uvd_sw_init(adev
);
118 r
= amdgpu_uvd_resume(adev
);
122 ring
= &adev
->uvd
.ring
;
123 sprintf(ring
->name
, "uvd");
124 r
= amdgpu_ring_init(adev
, ring
, 512, &adev
->uvd
.irq
, 0);
129 static int uvd_v4_2_sw_fini(void *handle
)
132 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
134 r
= amdgpu_uvd_suspend(adev
);
138 return amdgpu_uvd_sw_fini(adev
);
141 static void uvd_v4_2_enable_mgcg(struct amdgpu_device
*adev
,
144 * uvd_v4_2_hw_init - start and test UVD block
146 * @adev: amdgpu_device pointer
148 * Initialize the hardware, boot up the VCPU and do some testing
150 static int uvd_v4_2_hw_init(void *handle
)
152 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
153 struct amdgpu_ring
*ring
= &adev
->uvd
.ring
;
157 uvd_v4_2_enable_mgcg(adev
, true);
158 amdgpu_asic_set_uvd_clocks(adev
, 10000, 10000);
161 r
= amdgpu_ring_test_ring(ring
);
167 r
= amdgpu_ring_alloc(ring
, 10);
169 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r
);
173 tmp
= PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
, 0);
174 amdgpu_ring_write(ring
, tmp
);
175 amdgpu_ring_write(ring
, 0xFFFFF);
177 tmp
= PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
, 0);
178 amdgpu_ring_write(ring
, tmp
);
179 amdgpu_ring_write(ring
, 0xFFFFF);
181 tmp
= PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
, 0);
182 amdgpu_ring_write(ring
, tmp
);
183 amdgpu_ring_write(ring
, 0xFFFFF);
185 /* Clear timeout status bits */
186 amdgpu_ring_write(ring
, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS
, 0));
187 amdgpu_ring_write(ring
, 0x8);
189 amdgpu_ring_write(ring
, PACKET0(mmUVD_SEMA_CNTL
, 0));
190 amdgpu_ring_write(ring
, 3);
192 amdgpu_ring_commit(ring
);
196 DRM_INFO("UVD initialized successfully.\n");
202 * uvd_v4_2_hw_fini - stop the hardware block
204 * @adev: amdgpu_device pointer
206 * Stop the UVD block, mark ring as not ready any more
208 static int uvd_v4_2_hw_fini(void *handle
)
210 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
211 struct amdgpu_ring
*ring
= &adev
->uvd
.ring
;
213 if (RREG32(mmUVD_STATUS
) != 0)
221 static int uvd_v4_2_suspend(void *handle
)
224 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
226 r
= uvd_v4_2_hw_fini(adev
);
230 return amdgpu_uvd_suspend(adev
);
233 static int uvd_v4_2_resume(void *handle
)
236 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
238 r
= amdgpu_uvd_resume(adev
);
242 return uvd_v4_2_hw_init(adev
);
246 * uvd_v4_2_start - start UVD block
248 * @adev: amdgpu_device pointer
250 * Setup and start the UVD block
252 static int uvd_v4_2_start(struct amdgpu_device
*adev
)
254 struct amdgpu_ring
*ring
= &adev
->uvd
.ring
;
258 /* disable byte swapping */
259 u32 lmi_swap_cntl
= 0;
260 u32 mp_swap_cntl
= 0;
263 WREG32_P(mmUVD_STATUS
, 1<<2, ~(1<<2));
265 uvd_v4_2_set_dcm(adev
, true);
266 WREG32(mmUVD_CGC_GATE
, 0);
268 /* take UVD block out of reset */
269 WREG32_P(mmSRBM_SOFT_RESET
, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK
);
272 /* enable VCPU clock */
273 WREG32(mmUVD_VCPU_CNTL
, 1 << 9);
275 /* disable interupt */
276 WREG32_P(mmUVD_MASTINT_EN
, 0, ~(1 << 1));
279 /* swap (8 in 32) RB and IB */
283 WREG32(mmUVD_LMI_SWAP_CNTL
, lmi_swap_cntl
);
284 WREG32(mmUVD_MP_SWAP_CNTL
, mp_swap_cntl
);
285 /* initialize UVD memory controller */
286 WREG32(mmUVD_LMI_CTRL
, 0x203108);
288 tmp
= RREG32(mmUVD_MPC_CNTL
);
289 WREG32(mmUVD_MPC_CNTL
, tmp
| 0x10);
291 WREG32(mmUVD_MPC_SET_MUXA0
, 0x40c2040);
292 WREG32(mmUVD_MPC_SET_MUXA1
, 0x0);
293 WREG32(mmUVD_MPC_SET_MUXB0
, 0x40c2040);
294 WREG32(mmUVD_MPC_SET_MUXB1
, 0x0);
295 WREG32(mmUVD_MPC_SET_ALU
, 0);
296 WREG32(mmUVD_MPC_SET_MUX
, 0x88);
298 uvd_v4_2_mc_resume(adev
);
300 tmp
= RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL
);
301 WREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL
, tmp
& (~0x10));
304 WREG32_P(mmUVD_LMI_CTRL2
, 0, ~(1 << 8));
306 WREG32_P(mmUVD_SOFT_RESET
, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
);
308 WREG32_P(mmUVD_SOFT_RESET
, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
);
310 WREG32_P(mmUVD_SOFT_RESET
, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
);
314 for (i
= 0; i
< 10; ++i
) {
316 for (j
= 0; j
< 100; ++j
) {
317 status
= RREG32(mmUVD_STATUS
);
326 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
327 WREG32_P(mmUVD_SOFT_RESET
, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
,
328 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
);
330 WREG32_P(mmUVD_SOFT_RESET
, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
);
336 DRM_ERROR("UVD not responding, giving up!!!\n");
340 /* enable interupt */
341 WREG32_P(mmUVD_MASTINT_EN
, 3<<1, ~(3 << 1));
343 WREG32_P(mmUVD_STATUS
, 0, ~(1<<2));
345 /* force RBC into idle state */
346 WREG32(mmUVD_RBC_RB_CNTL
, 0x11010101);
348 /* Set the write pointer delay */
349 WREG32(mmUVD_RBC_RB_WPTR_CNTL
, 0);
351 /* programm the 4GB memory segment for rptr and ring buffer */
352 WREG32(mmUVD_LMI_EXT40_ADDR
, upper_32_bits(ring
->gpu_addr
) |
353 (0x7 << 16) | (0x1 << 31));
355 /* Initialize the ring buffer's read and write pointers */
356 WREG32(mmUVD_RBC_RB_RPTR
, 0x0);
358 ring
->wptr
= RREG32(mmUVD_RBC_RB_RPTR
);
359 WREG32(mmUVD_RBC_RB_WPTR
, lower_32_bits(ring
->wptr
));
361 /* set the ring address */
362 WREG32(mmUVD_RBC_RB_BASE
, ring
->gpu_addr
);
364 /* Set ring buffer size */
365 rb_bufsz
= order_base_2(ring
->ring_size
);
366 rb_bufsz
= (0x1 << 8) | rb_bufsz
;
367 WREG32_P(mmUVD_RBC_RB_CNTL
, rb_bufsz
, ~0x11f1f);
373 * uvd_v4_2_stop - stop UVD block
375 * @adev: amdgpu_device pointer
379 static void uvd_v4_2_stop(struct amdgpu_device
*adev
)
384 WREG32(mmUVD_RBC_RB_CNTL
, 0x11010101);
386 for (i
= 0; i
< 10; ++i
) {
387 for (j
= 0; j
< 100; ++j
) {
388 status
= RREG32(mmUVD_STATUS
);
397 for (i
= 0; i
< 10; ++i
) {
398 for (j
= 0; j
< 100; ++j
) {
399 status
= RREG32(mmUVD_LMI_STATUS
);
408 /* Stall UMC and register bus before resetting VCPU */
409 WREG32_P(mmUVD_LMI_CTRL2
, 1 << 8, ~(1 << 8));
411 for (i
= 0; i
< 10; ++i
) {
412 for (j
= 0; j
< 100; ++j
) {
413 status
= RREG32(mmUVD_LMI_STATUS
);
422 WREG32_P(0x3D49, 0, ~(1 << 2));
424 WREG32_P(mmUVD_VCPU_CNTL
, 0, ~(1 << 9));
426 /* put LMI, VCPU, RBC etc... into reset */
427 WREG32(mmUVD_SOFT_RESET
, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
|
428 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
|
429 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
);
431 WREG32(mmUVD_STATUS
, 0);
433 uvd_v4_2_set_dcm(adev
, false);
437 * uvd_v4_2_ring_emit_fence - emit an fence & trap command
439 * @ring: amdgpu_ring pointer
440 * @fence: fence to emit
442 * Write a fence and a trap command to the ring.
444 static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
, u64 seq
,
447 WARN_ON(flags
& AMDGPU_FENCE_FLAG_64BIT
);
449 amdgpu_ring_write(ring
, PACKET0(mmUVD_CONTEXT_ID
, 0));
450 amdgpu_ring_write(ring
, seq
);
451 amdgpu_ring_write(ring
, PACKET0(mmUVD_GPCOM_VCPU_DATA0
, 0));
452 amdgpu_ring_write(ring
, addr
& 0xffffffff);
453 amdgpu_ring_write(ring
, PACKET0(mmUVD_GPCOM_VCPU_DATA1
, 0));
454 amdgpu_ring_write(ring
, upper_32_bits(addr
) & 0xff);
455 amdgpu_ring_write(ring
, PACKET0(mmUVD_GPCOM_VCPU_CMD
, 0));
456 amdgpu_ring_write(ring
, 0);
458 amdgpu_ring_write(ring
, PACKET0(mmUVD_GPCOM_VCPU_DATA0
, 0));
459 amdgpu_ring_write(ring
, 0);
460 amdgpu_ring_write(ring
, PACKET0(mmUVD_GPCOM_VCPU_DATA1
, 0));
461 amdgpu_ring_write(ring
, 0);
462 amdgpu_ring_write(ring
, PACKET0(mmUVD_GPCOM_VCPU_CMD
, 0));
463 amdgpu_ring_write(ring
, 2);
467 * uvd_v4_2_ring_emit_hdp_flush - emit an hdp flush
469 * @ring: amdgpu_ring pointer
471 * Emits an hdp flush.
473 static void uvd_v4_2_ring_emit_hdp_flush(struct amdgpu_ring
*ring
)
475 amdgpu_ring_write(ring
, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL
, 0));
476 amdgpu_ring_write(ring
, 0);
480 * uvd_v4_2_ring_hdp_invalidate - emit an hdp invalidate
482 * @ring: amdgpu_ring pointer
484 * Emits an hdp invalidate.
486 static void uvd_v4_2_ring_emit_hdp_invalidate(struct amdgpu_ring
*ring
)
488 amdgpu_ring_write(ring
, PACKET0(mmHDP_DEBUG0
, 0));
489 amdgpu_ring_write(ring
, 1);
493 * uvd_v4_2_ring_test_ring - register write test
495 * @ring: amdgpu_ring pointer
497 * Test if we can successfully write to the context register
499 static int uvd_v4_2_ring_test_ring(struct amdgpu_ring
*ring
)
501 struct amdgpu_device
*adev
= ring
->adev
;
506 WREG32(mmUVD_CONTEXT_ID
, 0xCAFEDEAD);
507 r
= amdgpu_ring_alloc(ring
, 3);
509 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
513 amdgpu_ring_write(ring
, PACKET0(mmUVD_CONTEXT_ID
, 0));
514 amdgpu_ring_write(ring
, 0xDEADBEEF);
515 amdgpu_ring_commit(ring
);
516 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
517 tmp
= RREG32(mmUVD_CONTEXT_ID
);
518 if (tmp
== 0xDEADBEEF)
523 if (i
< adev
->usec_timeout
) {
524 DRM_INFO("ring test on %d succeeded in %d usecs\n",
527 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
535 * uvd_v4_2_ring_emit_ib - execute indirect buffer
537 * @ring: amdgpu_ring pointer
538 * @ib: indirect buffer to execute
540 * Write ring commands to execute the indirect buffer
542 static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring
*ring
,
543 struct amdgpu_ib
*ib
,
544 unsigned vm_id
, bool ctx_switch
)
546 amdgpu_ring_write(ring
, PACKET0(mmUVD_RBC_IB_BASE
, 0));
547 amdgpu_ring_write(ring
, ib
->gpu_addr
);
548 amdgpu_ring_write(ring
, PACKET0(mmUVD_RBC_IB_SIZE
, 0));
549 amdgpu_ring_write(ring
, ib
->length_dw
);
553 * uvd_v4_2_mc_resume - memory controller programming
555 * @adev: amdgpu_device pointer
557 * Let the UVD memory controller know it's offsets
559 static void uvd_v4_2_mc_resume(struct amdgpu_device
*adev
)
564 /* programm the VCPU memory controller bits 0-27 */
565 addr
= (adev
->uvd
.gpu_addr
+ AMDGPU_UVD_FIRMWARE_OFFSET
) >> 3;
566 size
= AMDGPU_GPU_PAGE_ALIGN(adev
->uvd
.fw
->size
+ 4) >> 3;
567 WREG32(mmUVD_VCPU_CACHE_OFFSET0
, addr
);
568 WREG32(mmUVD_VCPU_CACHE_SIZE0
, size
);
571 size
= AMDGPU_UVD_HEAP_SIZE
>> 3;
572 WREG32(mmUVD_VCPU_CACHE_OFFSET1
, addr
);
573 WREG32(mmUVD_VCPU_CACHE_SIZE1
, size
);
576 size
= (AMDGPU_UVD_STACK_SIZE
+
577 (AMDGPU_UVD_SESSION_SIZE
* adev
->uvd
.max_handles
)) >> 3;
578 WREG32(mmUVD_VCPU_CACHE_OFFSET2
, addr
);
579 WREG32(mmUVD_VCPU_CACHE_SIZE2
, size
);
582 addr
= (adev
->uvd
.gpu_addr
>> 28) & 0xF;
583 WREG32(mmUVD_LMI_ADDR_EXT
, (addr
<< 12) | (addr
<< 0));
586 addr
= (adev
->uvd
.gpu_addr
>> 32) & 0xFF;
587 WREG32(mmUVD_LMI_EXT40_ADDR
, addr
| (0x9 << 16) | (0x1 << 31));
589 WREG32(mmUVD_UDEC_ADDR_CONFIG
, adev
->gfx
.config
.gb_addr_config
);
590 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG
, adev
->gfx
.config
.gb_addr_config
);
591 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG
, adev
->gfx
.config
.gb_addr_config
);
594 static void uvd_v4_2_enable_mgcg(struct amdgpu_device
*adev
,
599 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_UVD_MGCG
)) {
600 data
= RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL
);
602 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL
, data
);
604 orig
= data
= RREG32(mmUVD_CGC_CTRL
);
605 data
|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
;
607 WREG32(mmUVD_CGC_CTRL
, data
);
609 data
= RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL
);
611 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL
, data
);
613 orig
= data
= RREG32(mmUVD_CGC_CTRL
);
614 data
&= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
;
616 WREG32(mmUVD_CGC_CTRL
, data
);
620 static void uvd_v4_2_set_dcm(struct amdgpu_device
*adev
,
625 WREG32_FIELD(UVD_CGC_GATE
, REGS
, 0);
627 tmp
= RREG32(mmUVD_CGC_CTRL
);
628 tmp
&= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK
| UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK
);
629 tmp
|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
|
630 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
) |
631 (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT
);
635 tmp2
= UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK
|
636 UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK
|
637 (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT
);
643 WREG32(mmUVD_CGC_CTRL
, tmp
);
644 WREG32_UVD_CTX(ixUVD_CGC_CTRL2
, tmp2
);
647 static bool uvd_v4_2_is_idle(void *handle
)
649 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
651 return !(RREG32(mmSRBM_STATUS
) & SRBM_STATUS__UVD_BUSY_MASK
);
654 static int uvd_v4_2_wait_for_idle(void *handle
)
657 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
659 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
660 if (!(RREG32(mmSRBM_STATUS
) & SRBM_STATUS__UVD_BUSY_MASK
))
666 static int uvd_v4_2_soft_reset(void *handle
)
668 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
672 WREG32_P(mmSRBM_SOFT_RESET
, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK
,
673 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK
);
676 return uvd_v4_2_start(adev
);
679 static int uvd_v4_2_set_interrupt_state(struct amdgpu_device
*adev
,
680 struct amdgpu_irq_src
*source
,
682 enum amdgpu_interrupt_state state
)
688 static int uvd_v4_2_process_interrupt(struct amdgpu_device
*adev
,
689 struct amdgpu_irq_src
*source
,
690 struct amdgpu_iv_entry
*entry
)
692 DRM_DEBUG("IH: UVD TRAP\n");
693 amdgpu_fence_process(&adev
->uvd
.ring
);
697 static int uvd_v4_2_set_clockgating_state(void *handle
,
698 enum amd_clockgating_state state
)
703 static int uvd_v4_2_set_powergating_state(void *handle
,
704 enum amd_powergating_state state
)
706 /* This doesn't actually powergate the UVD block.
707 * That's done in the dpm code via the SMC. This
708 * just re-inits the block as necessary. The actual
709 * gating still happens in the dpm code. We should
710 * revisit this when there is a cleaner line between
711 * the smc and the hw blocks
713 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
715 if (state
== AMD_PG_STATE_GATE
) {
717 if (adev
->pg_flags
& AMD_PG_SUPPORT_UVD
&& amdgpu_dpm
== 0) {
718 if (!(RREG32_SMC(ixCURRENT_PG_STATUS
) &
719 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK
)) {
720 WREG32(mmUVD_PGFSM_CONFIG
, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK
|
721 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK
|
722 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK
));
728 if (adev
->pg_flags
& AMD_PG_SUPPORT_UVD
&& amdgpu_dpm
== 0) {
729 if (RREG32_SMC(ixCURRENT_PG_STATUS
) &
730 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK
) {
731 WREG32(mmUVD_PGFSM_CONFIG
, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK
|
732 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK
|
733 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK
));
737 return uvd_v4_2_start(adev
);
741 static const struct amd_ip_funcs uvd_v4_2_ip_funcs
= {
743 .early_init
= uvd_v4_2_early_init
,
745 .sw_init
= uvd_v4_2_sw_init
,
746 .sw_fini
= uvd_v4_2_sw_fini
,
747 .hw_init
= uvd_v4_2_hw_init
,
748 .hw_fini
= uvd_v4_2_hw_fini
,
749 .suspend
= uvd_v4_2_suspend
,
750 .resume
= uvd_v4_2_resume
,
751 .is_idle
= uvd_v4_2_is_idle
,
752 .wait_for_idle
= uvd_v4_2_wait_for_idle
,
753 .soft_reset
= uvd_v4_2_soft_reset
,
754 .set_clockgating_state
= uvd_v4_2_set_clockgating_state
,
755 .set_powergating_state
= uvd_v4_2_set_powergating_state
,
758 static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs
= {
759 .type
= AMDGPU_RING_TYPE_UVD
,
761 .nop
= PACKET0(mmUVD_NO_OP
, 0),
762 .support_64bit_ptrs
= false,
763 .get_rptr
= uvd_v4_2_ring_get_rptr
,
764 .get_wptr
= uvd_v4_2_ring_get_wptr
,
765 .set_wptr
= uvd_v4_2_ring_set_wptr
,
766 .parse_cs
= amdgpu_uvd_ring_parse_cs
,
768 2 + /* uvd_v4_2_ring_emit_hdp_flush */
769 2 + /* uvd_v4_2_ring_emit_hdp_invalidate */
770 14, /* uvd_v4_2_ring_emit_fence x1 no user fence */
771 .emit_ib_size
= 4, /* uvd_v4_2_ring_emit_ib */
772 .emit_ib
= uvd_v4_2_ring_emit_ib
,
773 .emit_fence
= uvd_v4_2_ring_emit_fence
,
774 .emit_hdp_flush
= uvd_v4_2_ring_emit_hdp_flush
,
775 .emit_hdp_invalidate
= uvd_v4_2_ring_emit_hdp_invalidate
,
776 .test_ring
= uvd_v4_2_ring_test_ring
,
777 .test_ib
= amdgpu_uvd_ring_test_ib
,
778 .insert_nop
= amdgpu_ring_insert_nop
,
779 .pad_ib
= amdgpu_ring_generic_pad_ib
,
780 .begin_use
= amdgpu_uvd_ring_begin_use
,
781 .end_use
= amdgpu_uvd_ring_end_use
,
784 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device
*adev
)
786 adev
->uvd
.ring
.funcs
= &uvd_v4_2_ring_funcs
;
789 static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs
= {
790 .set
= uvd_v4_2_set_interrupt_state
,
791 .process
= uvd_v4_2_process_interrupt
,
794 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device
*adev
)
796 adev
->uvd
.irq
.num_types
= 1;
797 adev
->uvd
.irq
.funcs
= &uvd_v4_2_irq_funcs
;
800 const struct amdgpu_ip_block_version uvd_v4_2_ip_block
=
802 .type
= AMD_IP_BLOCK_TYPE_UVD
,
806 .funcs
= &uvd_v4_2_ip_funcs
,