2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Christian König <christian.koenig@amd.com>
25 #include <linux/firmware.h>
28 #include "amdgpu_uvd.h"
30 #include "uvd/uvd_5_0_d.h"
31 #include "uvd/uvd_5_0_sh_mask.h"
32 #include "oss/oss_2_0_d.h"
33 #include "oss/oss_2_0_sh_mask.h"
35 static void uvd_v5_0_set_ring_funcs(struct amdgpu_device
*adev
);
36 static void uvd_v5_0_set_irq_funcs(struct amdgpu_device
*adev
);
37 static int uvd_v5_0_start(struct amdgpu_device
*adev
);
38 static void uvd_v5_0_stop(struct amdgpu_device
*adev
);
41 * uvd_v5_0_ring_get_rptr - get read pointer
43 * @ring: amdgpu_ring pointer
45 * Returns the current hardware read pointer
47 static uint32_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring
*ring
)
49 struct amdgpu_device
*adev
= ring
->adev
;
51 return RREG32(mmUVD_RBC_RB_RPTR
);
55 * uvd_v5_0_ring_get_wptr - get write pointer
57 * @ring: amdgpu_ring pointer
59 * Returns the current hardware write pointer
61 static uint32_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring
*ring
)
63 struct amdgpu_device
*adev
= ring
->adev
;
65 return RREG32(mmUVD_RBC_RB_WPTR
);
69 * uvd_v5_0_ring_set_wptr - set write pointer
71 * @ring: amdgpu_ring pointer
73 * Commits the write pointer to the hardware
75 static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring
*ring
)
77 struct amdgpu_device
*adev
= ring
->adev
;
79 WREG32(mmUVD_RBC_RB_WPTR
, ring
->wptr
);
82 static int uvd_v5_0_early_init(void *handle
)
84 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
86 uvd_v5_0_set_ring_funcs(adev
);
87 uvd_v5_0_set_irq_funcs(adev
);
92 static int uvd_v5_0_sw_init(void *handle
)
94 struct amdgpu_ring
*ring
;
95 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
99 r
= amdgpu_irq_add_id(adev
, 124, &adev
->uvd
.irq
);
103 r
= amdgpu_uvd_sw_init(adev
);
107 r
= amdgpu_uvd_resume(adev
);
111 ring
= &adev
->uvd
.ring
;
112 sprintf(ring
->name
, "uvd");
113 r
= amdgpu_ring_init(adev
, ring
, 4096, CP_PACKET2
, 0xf,
114 &adev
->uvd
.irq
, 0, AMDGPU_RING_TYPE_UVD
);
119 static int uvd_v5_0_sw_fini(void *handle
)
122 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
124 r
= amdgpu_uvd_suspend(adev
);
128 r
= amdgpu_uvd_sw_fini(adev
);
136 * uvd_v5_0_hw_init - start and test UVD block
138 * @adev: amdgpu_device pointer
140 * Initialize the hardware, boot up the VCPU and do some testing
142 static int uvd_v5_0_hw_init(void *handle
)
144 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
145 struct amdgpu_ring
*ring
= &adev
->uvd
.ring
;
149 /* raise clocks while booting up the VCPU */
150 amdgpu_asic_set_uvd_clocks(adev
, 53300, 40000);
152 r
= uvd_v5_0_start(adev
);
157 r
= amdgpu_ring_test_ring(ring
);
163 r
= amdgpu_ring_alloc(ring
, 10);
165 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r
);
169 tmp
= PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
, 0);
170 amdgpu_ring_write(ring
, tmp
);
171 amdgpu_ring_write(ring
, 0xFFFFF);
173 tmp
= PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
, 0);
174 amdgpu_ring_write(ring
, tmp
);
175 amdgpu_ring_write(ring
, 0xFFFFF);
177 tmp
= PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
, 0);
178 amdgpu_ring_write(ring
, tmp
);
179 amdgpu_ring_write(ring
, 0xFFFFF);
181 /* Clear timeout status bits */
182 amdgpu_ring_write(ring
, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS
, 0));
183 amdgpu_ring_write(ring
, 0x8);
185 amdgpu_ring_write(ring
, PACKET0(mmUVD_SEMA_CNTL
, 0));
186 amdgpu_ring_write(ring
, 3);
188 amdgpu_ring_commit(ring
);
191 /* lower clocks again */
192 amdgpu_asic_set_uvd_clocks(adev
, 0, 0);
195 DRM_INFO("UVD initialized successfully.\n");
201 * uvd_v5_0_hw_fini - stop the hardware block
203 * @adev: amdgpu_device pointer
205 * Stop the UVD block, mark ring as not ready any more
207 static int uvd_v5_0_hw_fini(void *handle
)
209 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
210 struct amdgpu_ring
*ring
= &adev
->uvd
.ring
;
218 static int uvd_v5_0_suspend(void *handle
)
221 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
223 r
= uvd_v5_0_hw_fini(adev
);
227 r
= amdgpu_uvd_suspend(adev
);
234 static int uvd_v5_0_resume(void *handle
)
237 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
239 r
= amdgpu_uvd_resume(adev
);
243 r
= uvd_v5_0_hw_init(adev
);
251 * uvd_v5_0_mc_resume - memory controller programming
253 * @adev: amdgpu_device pointer
255 * Let the UVD memory controller know it's offsets
257 static void uvd_v5_0_mc_resume(struct amdgpu_device
*adev
)
262 /* programm memory controller bits 0-27 */
263 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
,
264 lower_32_bits(adev
->uvd
.gpu_addr
));
265 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
,
266 upper_32_bits(adev
->uvd
.gpu_addr
));
268 offset
= AMDGPU_UVD_FIRMWARE_OFFSET
;
269 size
= AMDGPU_GPU_PAGE_ALIGN(adev
->uvd
.fw
->size
+ 4);
270 WREG32(mmUVD_VCPU_CACHE_OFFSET0
, offset
>> 3);
271 WREG32(mmUVD_VCPU_CACHE_SIZE0
, size
);
274 size
= AMDGPU_UVD_STACK_SIZE
;
275 WREG32(mmUVD_VCPU_CACHE_OFFSET1
, offset
>> 3);
276 WREG32(mmUVD_VCPU_CACHE_SIZE1
, size
);
279 size
= AMDGPU_UVD_HEAP_SIZE
;
280 WREG32(mmUVD_VCPU_CACHE_OFFSET2
, offset
>> 3);
281 WREG32(mmUVD_VCPU_CACHE_SIZE2
, size
);
283 WREG32(mmUVD_UDEC_ADDR_CONFIG
, adev
->gfx
.config
.gb_addr_config
);
284 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG
, adev
->gfx
.config
.gb_addr_config
);
285 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG
, adev
->gfx
.config
.gb_addr_config
);
289 * uvd_v5_0_start - start UVD block
291 * @adev: amdgpu_device pointer
293 * Setup and start the UVD block
295 static int uvd_v5_0_start(struct amdgpu_device
*adev
)
297 struct amdgpu_ring
*ring
= &adev
->uvd
.ring
;
298 uint32_t rb_bufsz
, tmp
;
299 uint32_t lmi_swap_cntl
;
300 uint32_t mp_swap_cntl
;
304 WREG32_P(mmUVD_POWER_STATUS
, 0, ~(1 << 2));
306 /* disable byte swapping */
310 uvd_v5_0_mc_resume(adev
);
312 /* disable clock gating */
313 WREG32(mmUVD_CGC_GATE
, 0);
315 /* disable interupt */
316 WREG32_P(mmUVD_MASTINT_EN
, 0, ~(1 << 1));
318 /* stall UMC and register bus before resetting VCPU */
319 WREG32_P(mmUVD_LMI_CTRL2
, 1 << 8, ~(1 << 8));
322 /* put LMI, VCPU, RBC etc... into reset */
323 WREG32(mmUVD_SOFT_RESET
, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
|
324 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
| UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK
|
325 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK
| UVD_SOFT_RESET__CSM_SOFT_RESET_MASK
|
326 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK
| UVD_SOFT_RESET__TAP_SOFT_RESET_MASK
|
327 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
);
330 /* take UVD block out of reset */
331 WREG32_P(mmSRBM_SOFT_RESET
, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK
);
334 /* initialize UVD memory controller */
335 WREG32(mmUVD_LMI_CTRL
, 0x40 | (1 << 8) | (1 << 13) |
336 (1 << 21) | (1 << 9) | (1 << 20));
339 /* swap (8 in 32) RB and IB */
343 WREG32(mmUVD_LMI_SWAP_CNTL
, lmi_swap_cntl
);
344 WREG32(mmUVD_MP_SWAP_CNTL
, mp_swap_cntl
);
346 WREG32(mmUVD_MPC_SET_MUXA0
, 0x40c2040);
347 WREG32(mmUVD_MPC_SET_MUXA1
, 0x0);
348 WREG32(mmUVD_MPC_SET_MUXB0
, 0x40c2040);
349 WREG32(mmUVD_MPC_SET_MUXB1
, 0x0);
350 WREG32(mmUVD_MPC_SET_ALU
, 0);
351 WREG32(mmUVD_MPC_SET_MUX
, 0x88);
353 /* take all subblocks out of reset, except VCPU */
354 WREG32(mmUVD_SOFT_RESET
, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
);
357 /* enable VCPU clock */
358 WREG32(mmUVD_VCPU_CNTL
, 1 << 9);
361 WREG32_P(mmUVD_LMI_CTRL2
, 0, ~(1 << 8));
363 /* boot up the VCPU */
364 WREG32(mmUVD_SOFT_RESET
, 0);
367 for (i
= 0; i
< 10; ++i
) {
369 for (j
= 0; j
< 100; ++j
) {
370 status
= RREG32(mmUVD_STATUS
);
379 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
380 WREG32_P(mmUVD_SOFT_RESET
, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
,
381 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
);
383 WREG32_P(mmUVD_SOFT_RESET
, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
);
389 DRM_ERROR("UVD not responding, giving up!!!\n");
392 /* enable master interrupt */
393 WREG32_P(mmUVD_MASTINT_EN
, 3 << 1, ~(3 << 1));
395 /* clear the bit 4 of UVD_STATUS */
396 WREG32_P(mmUVD_STATUS
, 0, ~(2 << 1));
398 rb_bufsz
= order_base_2(ring
->ring_size
);
400 tmp
= REG_SET_FIELD(tmp
, UVD_RBC_RB_CNTL
, RB_BUFSZ
, rb_bufsz
);
401 tmp
= REG_SET_FIELD(tmp
, UVD_RBC_RB_CNTL
, RB_BLKSZ
, 1);
402 tmp
= REG_SET_FIELD(tmp
, UVD_RBC_RB_CNTL
, RB_NO_FETCH
, 1);
403 tmp
= REG_SET_FIELD(tmp
, UVD_RBC_RB_CNTL
, RB_WPTR_POLL_EN
, 0);
404 tmp
= REG_SET_FIELD(tmp
, UVD_RBC_RB_CNTL
, RB_NO_UPDATE
, 1);
405 tmp
= REG_SET_FIELD(tmp
, UVD_RBC_RB_CNTL
, RB_RPTR_WR_EN
, 1);
406 /* force RBC into idle state */
407 WREG32(mmUVD_RBC_RB_CNTL
, tmp
);
409 /* set the write pointer delay */
410 WREG32(mmUVD_RBC_RB_WPTR_CNTL
, 0);
412 /* set the wb address */
413 WREG32(mmUVD_RBC_RB_RPTR_ADDR
, (upper_32_bits(ring
->gpu_addr
) >> 2));
415 /* programm the RB_BASE for ring buffer */
416 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
,
417 lower_32_bits(ring
->gpu_addr
));
418 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
,
419 upper_32_bits(ring
->gpu_addr
));
421 /* Initialize the ring buffer's read and write pointers */
422 WREG32(mmUVD_RBC_RB_RPTR
, 0);
424 ring
->wptr
= RREG32(mmUVD_RBC_RB_RPTR
);
425 WREG32(mmUVD_RBC_RB_WPTR
, ring
->wptr
);
427 WREG32_P(mmUVD_RBC_RB_CNTL
, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK
);
433 * uvd_v5_0_stop - stop UVD block
435 * @adev: amdgpu_device pointer
439 static void uvd_v5_0_stop(struct amdgpu_device
*adev
)
441 /* force RBC into idle state */
442 WREG32(mmUVD_RBC_RB_CNTL
, 0x11010101);
444 /* Stall UMC and register bus before resetting VCPU */
445 WREG32_P(mmUVD_LMI_CTRL2
, 1 << 8, ~(1 << 8));
448 /* put VCPU into reset */
449 WREG32(mmUVD_SOFT_RESET
, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
);
452 /* disable VCPU clock */
453 WREG32(mmUVD_VCPU_CNTL
, 0x0);
455 /* Unstall UMC and register bus */
456 WREG32_P(mmUVD_LMI_CTRL2
, 0, ~(1 << 8));
460 * uvd_v5_0_ring_emit_fence - emit an fence & trap command
462 * @ring: amdgpu_ring pointer
463 * @fence: fence to emit
465 * Write a fence and a trap command to the ring.
467 static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
, u64 seq
,
470 WARN_ON(flags
& AMDGPU_FENCE_FLAG_64BIT
);
472 amdgpu_ring_write(ring
, PACKET0(mmUVD_CONTEXT_ID
, 0));
473 amdgpu_ring_write(ring
, seq
);
474 amdgpu_ring_write(ring
, PACKET0(mmUVD_GPCOM_VCPU_DATA0
, 0));
475 amdgpu_ring_write(ring
, addr
& 0xffffffff);
476 amdgpu_ring_write(ring
, PACKET0(mmUVD_GPCOM_VCPU_DATA1
, 0));
477 amdgpu_ring_write(ring
, upper_32_bits(addr
) & 0xff);
478 amdgpu_ring_write(ring
, PACKET0(mmUVD_GPCOM_VCPU_CMD
, 0));
479 amdgpu_ring_write(ring
, 0);
481 amdgpu_ring_write(ring
, PACKET0(mmUVD_GPCOM_VCPU_DATA0
, 0));
482 amdgpu_ring_write(ring
, 0);
483 amdgpu_ring_write(ring
, PACKET0(mmUVD_GPCOM_VCPU_DATA1
, 0));
484 amdgpu_ring_write(ring
, 0);
485 amdgpu_ring_write(ring
, PACKET0(mmUVD_GPCOM_VCPU_CMD
, 0));
486 amdgpu_ring_write(ring
, 2);
490 * uvd_v5_0_ring_test_ring - register write test
492 * @ring: amdgpu_ring pointer
494 * Test if we can successfully write to the context register
496 static int uvd_v5_0_ring_test_ring(struct amdgpu_ring
*ring
)
498 struct amdgpu_device
*adev
= ring
->adev
;
503 WREG32(mmUVD_CONTEXT_ID
, 0xCAFEDEAD);
504 r
= amdgpu_ring_alloc(ring
, 3);
506 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
510 amdgpu_ring_write(ring
, PACKET0(mmUVD_CONTEXT_ID
, 0));
511 amdgpu_ring_write(ring
, 0xDEADBEEF);
512 amdgpu_ring_commit(ring
);
513 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
514 tmp
= RREG32(mmUVD_CONTEXT_ID
);
515 if (tmp
== 0xDEADBEEF)
520 if (i
< adev
->usec_timeout
) {
521 DRM_INFO("ring test on %d succeeded in %d usecs\n",
524 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
532 * uvd_v5_0_ring_emit_ib - execute indirect buffer
534 * @ring: amdgpu_ring pointer
535 * @ib: indirect buffer to execute
537 * Write ring commands to execute the indirect buffer
539 static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring
*ring
,
540 struct amdgpu_ib
*ib
)
542 amdgpu_ring_write(ring
, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW
, 0));
543 amdgpu_ring_write(ring
, lower_32_bits(ib
->gpu_addr
));
544 amdgpu_ring_write(ring
, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH
, 0));
545 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
));
546 amdgpu_ring_write(ring
, PACKET0(mmUVD_RBC_IB_SIZE
, 0));
547 amdgpu_ring_write(ring
, ib
->length_dw
);
551 * uvd_v5_0_ring_test_ib - test ib execution
553 * @ring: amdgpu_ring pointer
555 * Test if we can successfully execute an IB
557 static int uvd_v5_0_ring_test_ib(struct amdgpu_ring
*ring
)
559 struct amdgpu_device
*adev
= ring
->adev
;
560 struct fence
*fence
= NULL
;
563 r
= amdgpu_asic_set_uvd_clocks(adev
, 53300, 40000);
565 DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r
);
569 r
= amdgpu_uvd_get_create_msg(ring
, 1, NULL
);
571 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r
);
575 r
= amdgpu_uvd_get_destroy_msg(ring
, 1, true, &fence
);
577 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r
);
581 r
= fence_wait(fence
, false);
583 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r
);
586 DRM_INFO("ib test on ring %d succeeded\n", ring
->idx
);
589 amdgpu_asic_set_uvd_clocks(adev
, 0, 0);
593 static bool uvd_v5_0_is_idle(void *handle
)
595 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
597 return !(RREG32(mmSRBM_STATUS
) & SRBM_STATUS__UVD_BUSY_MASK
);
600 static int uvd_v5_0_wait_for_idle(void *handle
)
603 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
605 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
606 if (!(RREG32(mmSRBM_STATUS
) & SRBM_STATUS__UVD_BUSY_MASK
))
612 static int uvd_v5_0_soft_reset(void *handle
)
614 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
618 WREG32_P(mmSRBM_SOFT_RESET
, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK
,
619 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK
);
622 return uvd_v5_0_start(adev
);
625 static void uvd_v5_0_print_status(void *handle
)
627 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
628 dev_info(adev
->dev
, "UVD 5.0 registers\n");
629 dev_info(adev
->dev
, " UVD_SEMA_ADDR_LOW=0x%08X\n",
630 RREG32(mmUVD_SEMA_ADDR_LOW
));
631 dev_info(adev
->dev
, " UVD_SEMA_ADDR_HIGH=0x%08X\n",
632 RREG32(mmUVD_SEMA_ADDR_HIGH
));
633 dev_info(adev
->dev
, " UVD_SEMA_CMD=0x%08X\n",
634 RREG32(mmUVD_SEMA_CMD
));
635 dev_info(adev
->dev
, " UVD_GPCOM_VCPU_CMD=0x%08X\n",
636 RREG32(mmUVD_GPCOM_VCPU_CMD
));
637 dev_info(adev
->dev
, " UVD_GPCOM_VCPU_DATA0=0x%08X\n",
638 RREG32(mmUVD_GPCOM_VCPU_DATA0
));
639 dev_info(adev
->dev
, " UVD_GPCOM_VCPU_DATA1=0x%08X\n",
640 RREG32(mmUVD_GPCOM_VCPU_DATA1
));
641 dev_info(adev
->dev
, " UVD_ENGINE_CNTL=0x%08X\n",
642 RREG32(mmUVD_ENGINE_CNTL
));
643 dev_info(adev
->dev
, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
644 RREG32(mmUVD_UDEC_ADDR_CONFIG
));
645 dev_info(adev
->dev
, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
646 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG
));
647 dev_info(adev
->dev
, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
648 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG
));
649 dev_info(adev
->dev
, " UVD_SEMA_CNTL=0x%08X\n",
650 RREG32(mmUVD_SEMA_CNTL
));
651 dev_info(adev
->dev
, " UVD_LMI_EXT40_ADDR=0x%08X\n",
652 RREG32(mmUVD_LMI_EXT40_ADDR
));
653 dev_info(adev
->dev
, " UVD_CTX_INDEX=0x%08X\n",
654 RREG32(mmUVD_CTX_INDEX
));
655 dev_info(adev
->dev
, " UVD_CTX_DATA=0x%08X\n",
656 RREG32(mmUVD_CTX_DATA
));
657 dev_info(adev
->dev
, " UVD_CGC_GATE=0x%08X\n",
658 RREG32(mmUVD_CGC_GATE
));
659 dev_info(adev
->dev
, " UVD_CGC_CTRL=0x%08X\n",
660 RREG32(mmUVD_CGC_CTRL
));
661 dev_info(adev
->dev
, " UVD_LMI_CTRL2=0x%08X\n",
662 RREG32(mmUVD_LMI_CTRL2
));
663 dev_info(adev
->dev
, " UVD_MASTINT_EN=0x%08X\n",
664 RREG32(mmUVD_MASTINT_EN
));
665 dev_info(adev
->dev
, " UVD_LMI_ADDR_EXT=0x%08X\n",
666 RREG32(mmUVD_LMI_ADDR_EXT
));
667 dev_info(adev
->dev
, " UVD_LMI_CTRL=0x%08X\n",
668 RREG32(mmUVD_LMI_CTRL
));
669 dev_info(adev
->dev
, " UVD_LMI_SWAP_CNTL=0x%08X\n",
670 RREG32(mmUVD_LMI_SWAP_CNTL
));
671 dev_info(adev
->dev
, " UVD_MP_SWAP_CNTL=0x%08X\n",
672 RREG32(mmUVD_MP_SWAP_CNTL
));
673 dev_info(adev
->dev
, " UVD_MPC_SET_MUXA0=0x%08X\n",
674 RREG32(mmUVD_MPC_SET_MUXA0
));
675 dev_info(adev
->dev
, " UVD_MPC_SET_MUXA1=0x%08X\n",
676 RREG32(mmUVD_MPC_SET_MUXA1
));
677 dev_info(adev
->dev
, " UVD_MPC_SET_MUXB0=0x%08X\n",
678 RREG32(mmUVD_MPC_SET_MUXB0
));
679 dev_info(adev
->dev
, " UVD_MPC_SET_MUXB1=0x%08X\n",
680 RREG32(mmUVD_MPC_SET_MUXB1
));
681 dev_info(adev
->dev
, " UVD_MPC_SET_MUX=0x%08X\n",
682 RREG32(mmUVD_MPC_SET_MUX
));
683 dev_info(adev
->dev
, " UVD_MPC_SET_ALU=0x%08X\n",
684 RREG32(mmUVD_MPC_SET_ALU
));
685 dev_info(adev
->dev
, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
686 RREG32(mmUVD_VCPU_CACHE_OFFSET0
));
687 dev_info(adev
->dev
, " UVD_VCPU_CACHE_SIZE0=0x%08X\n",
688 RREG32(mmUVD_VCPU_CACHE_SIZE0
));
689 dev_info(adev
->dev
, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
690 RREG32(mmUVD_VCPU_CACHE_OFFSET1
));
691 dev_info(adev
->dev
, " UVD_VCPU_CACHE_SIZE1=0x%08X\n",
692 RREG32(mmUVD_VCPU_CACHE_SIZE1
));
693 dev_info(adev
->dev
, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
694 RREG32(mmUVD_VCPU_CACHE_OFFSET2
));
695 dev_info(adev
->dev
, " UVD_VCPU_CACHE_SIZE2=0x%08X\n",
696 RREG32(mmUVD_VCPU_CACHE_SIZE2
));
697 dev_info(adev
->dev
, " UVD_VCPU_CNTL=0x%08X\n",
698 RREG32(mmUVD_VCPU_CNTL
));
699 dev_info(adev
->dev
, " UVD_SOFT_RESET=0x%08X\n",
700 RREG32(mmUVD_SOFT_RESET
));
701 dev_info(adev
->dev
, " UVD_LMI_RBC_IB_64BIT_BAR_LOW=0x%08X\n",
702 RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW
));
703 dev_info(adev
->dev
, " UVD_LMI_RBC_IB_64BIT_BAR_HIGH=0x%08X\n",
704 RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH
));
705 dev_info(adev
->dev
, " UVD_RBC_IB_SIZE=0x%08X\n",
706 RREG32(mmUVD_RBC_IB_SIZE
));
707 dev_info(adev
->dev
, " UVD_LMI_RBC_RB_64BIT_BAR_LOW=0x%08X\n",
708 RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
));
709 dev_info(adev
->dev
, " UVD_LMI_RBC_RB_64BIT_BAR_HIGH=0x%08X\n",
710 RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
));
711 dev_info(adev
->dev
, " UVD_RBC_RB_RPTR=0x%08X\n",
712 RREG32(mmUVD_RBC_RB_RPTR
));
713 dev_info(adev
->dev
, " UVD_RBC_RB_WPTR=0x%08X\n",
714 RREG32(mmUVD_RBC_RB_WPTR
));
715 dev_info(adev
->dev
, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
716 RREG32(mmUVD_RBC_RB_WPTR_CNTL
));
717 dev_info(adev
->dev
, " UVD_RBC_RB_CNTL=0x%08X\n",
718 RREG32(mmUVD_RBC_RB_CNTL
));
719 dev_info(adev
->dev
, " UVD_STATUS=0x%08X\n",
720 RREG32(mmUVD_STATUS
));
721 dev_info(adev
->dev
, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
722 RREG32(mmUVD_SEMA_TIMEOUT_STATUS
));
723 dev_info(adev
->dev
, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
724 RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
));
725 dev_info(adev
->dev
, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
726 RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
));
727 dev_info(adev
->dev
, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
728 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
));
729 dev_info(adev
->dev
, " UVD_CONTEXT_ID=0x%08X\n",
730 RREG32(mmUVD_CONTEXT_ID
));
731 dev_info(adev
->dev
, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
732 RREG32(mmUVD_UDEC_ADDR_CONFIG
));
733 dev_info(adev
->dev
, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
734 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG
));
735 dev_info(adev
->dev
, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
736 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG
));
739 static int uvd_v5_0_set_interrupt_state(struct amdgpu_device
*adev
,
740 struct amdgpu_irq_src
*source
,
742 enum amdgpu_interrupt_state state
)
748 static int uvd_v5_0_process_interrupt(struct amdgpu_device
*adev
,
749 struct amdgpu_irq_src
*source
,
750 struct amdgpu_iv_entry
*entry
)
752 DRM_DEBUG("IH: UVD TRAP\n");
753 amdgpu_fence_process(&adev
->uvd
.ring
);
757 static int uvd_v5_0_set_clockgating_state(void *handle
,
758 enum amd_clockgating_state state
)
760 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
762 if (!(adev
->cg_flags
& AMD_CG_SUPPORT_UVD_MGCG
))
768 static int uvd_v5_0_set_powergating_state(void *handle
,
769 enum amd_powergating_state state
)
771 /* This doesn't actually powergate the UVD block.
772 * That's done in the dpm code via the SMC. This
773 * just re-inits the block as necessary. The actual
774 * gating still happens in the dpm code. We should
775 * revisit this when there is a cleaner line between
776 * the smc and the hw blocks
778 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
780 if (!(adev
->pg_flags
& AMD_PG_SUPPORT_UVD
))
783 if (state
== AMD_PG_STATE_GATE
) {
787 return uvd_v5_0_start(adev
);
791 const struct amd_ip_funcs uvd_v5_0_ip_funcs
= {
792 .early_init
= uvd_v5_0_early_init
,
794 .sw_init
= uvd_v5_0_sw_init
,
795 .sw_fini
= uvd_v5_0_sw_fini
,
796 .hw_init
= uvd_v5_0_hw_init
,
797 .hw_fini
= uvd_v5_0_hw_fini
,
798 .suspend
= uvd_v5_0_suspend
,
799 .resume
= uvd_v5_0_resume
,
800 .is_idle
= uvd_v5_0_is_idle
,
801 .wait_for_idle
= uvd_v5_0_wait_for_idle
,
802 .soft_reset
= uvd_v5_0_soft_reset
,
803 .print_status
= uvd_v5_0_print_status
,
804 .set_clockgating_state
= uvd_v5_0_set_clockgating_state
,
805 .set_powergating_state
= uvd_v5_0_set_powergating_state
,
808 static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs
= {
809 .get_rptr
= uvd_v5_0_ring_get_rptr
,
810 .get_wptr
= uvd_v5_0_ring_get_wptr
,
811 .set_wptr
= uvd_v5_0_ring_set_wptr
,
812 .parse_cs
= amdgpu_uvd_ring_parse_cs
,
813 .emit_ib
= uvd_v5_0_ring_emit_ib
,
814 .emit_fence
= uvd_v5_0_ring_emit_fence
,
815 .test_ring
= uvd_v5_0_ring_test_ring
,
816 .test_ib
= uvd_v5_0_ring_test_ib
,
817 .insert_nop
= amdgpu_ring_insert_nop
,
818 .pad_ib
= amdgpu_ring_generic_pad_ib
,
821 static void uvd_v5_0_set_ring_funcs(struct amdgpu_device
*adev
)
823 adev
->uvd
.ring
.funcs
= &uvd_v5_0_ring_funcs
;
826 static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs
= {
827 .set
= uvd_v5_0_set_interrupt_state
,
828 .process
= uvd_v5_0_process_interrupt
,
831 static void uvd_v5_0_set_irq_funcs(struct amdgpu_device
*adev
)
833 adev
->uvd
.irq
.num_types
= 1;
834 adev
->uvd
.irq
.funcs
= &uvd_v5_0_irq_funcs
;