2 * Copyright 2014 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
25 * Authors: Christian König <christian.koenig@amd.com>
28 #include <linux/firmware.h>
31 #include "amdgpu_vce.h"
33 #include "vce/vce_3_0_d.h"
34 #include "vce/vce_3_0_sh_mask.h"
35 #include "oss/oss_3_0_d.h"
36 #include "oss/oss_3_0_sh_mask.h"
37 #include "gca/gfx_8_0_d.h"
38 #include "smu/smu_7_1_2_d.h"
39 #include "smu/smu_7_1_2_sh_mask.h"
41 #define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04
42 #define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10
44 #define VCE_V3_0_FW_SIZE (384 * 1024)
45 #define VCE_V3_0_STACK_SIZE (64 * 1024)
46 #define VCE_V3_0_DATA_SIZE ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 1024))
48 static void vce_v3_0_mc_resume(struct amdgpu_device
*adev
, int idx
);
49 static void vce_v3_0_set_ring_funcs(struct amdgpu_device
*adev
);
50 static void vce_v3_0_set_irq_funcs(struct amdgpu_device
*adev
);
53 * vce_v3_0_ring_get_rptr - get read pointer
55 * @ring: amdgpu_ring pointer
57 * Returns the current hardware read pointer
59 static uint32_t vce_v3_0_ring_get_rptr(struct amdgpu_ring
*ring
)
61 struct amdgpu_device
*adev
= ring
->adev
;
63 if (ring
== &adev
->vce
.ring
[0])
64 return RREG32(mmVCE_RB_RPTR
);
66 return RREG32(mmVCE_RB_RPTR2
);
70 * vce_v3_0_ring_get_wptr - get write pointer
72 * @ring: amdgpu_ring pointer
74 * Returns the current hardware write pointer
76 static uint32_t vce_v3_0_ring_get_wptr(struct amdgpu_ring
*ring
)
78 struct amdgpu_device
*adev
= ring
->adev
;
80 if (ring
== &adev
->vce
.ring
[0])
81 return RREG32(mmVCE_RB_WPTR
);
83 return RREG32(mmVCE_RB_WPTR2
);
87 * vce_v3_0_ring_set_wptr - set write pointer
89 * @ring: amdgpu_ring pointer
91 * Commits the write pointer to the hardware
93 static void vce_v3_0_ring_set_wptr(struct amdgpu_ring
*ring
)
95 struct amdgpu_device
*adev
= ring
->adev
;
97 if (ring
== &adev
->vce
.ring
[0])
98 WREG32(mmVCE_RB_WPTR
, ring
->wptr
);
100 WREG32(mmVCE_RB_WPTR2
, ring
->wptr
);
104 * vce_v3_0_start - start VCE block
106 * @adev: amdgpu_device pointer
108 * Setup and start the VCE block
110 static int vce_v3_0_start(struct amdgpu_device
*adev
)
112 struct amdgpu_ring
*ring
;
115 mutex_lock(&adev
->grbm_idx_mutex
);
116 for (idx
= 0; idx
< 2; ++idx
) {
118 if (adev
->vce
.harvest_config
& (1 << idx
))
122 WREG32_P(mmGRBM_GFX_INDEX
, 0,
123 ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK
);
125 WREG32_P(mmGRBM_GFX_INDEX
,
126 GRBM_GFX_INDEX__VCE_INSTANCE_MASK
,
127 ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK
);
129 vce_v3_0_mc_resume(adev
, idx
);
132 WREG32_P(mmVCE_STATUS
, 1, ~1);
134 WREG32_P(mmVCE_VCPU_CNTL
, VCE_VCPU_CNTL__CLK_EN_MASK
,
135 ~VCE_VCPU_CNTL__CLK_EN_MASK
);
137 WREG32_P(mmVCE_SOFT_RESET
,
138 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
,
139 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
);
143 WREG32_P(mmVCE_SOFT_RESET
, 0,
144 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
);
146 for (i
= 0; i
< 10; ++i
) {
148 for (j
= 0; j
< 100; ++j
) {
149 status
= RREG32(mmVCE_STATUS
);
158 DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
159 WREG32_P(mmVCE_SOFT_RESET
,
160 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
,
161 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
);
163 WREG32_P(mmVCE_SOFT_RESET
, 0,
164 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
);
169 /* clear BUSY flag */
170 WREG32_P(mmVCE_STATUS
, 0, ~1);
173 DRM_ERROR("VCE not responding, giving up!!!\n");
174 mutex_unlock(&adev
->grbm_idx_mutex
);
179 WREG32_P(mmGRBM_GFX_INDEX
, 0, ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK
);
180 mutex_unlock(&adev
->grbm_idx_mutex
);
182 ring
= &adev
->vce
.ring
[0];
183 WREG32(mmVCE_RB_RPTR
, ring
->wptr
);
184 WREG32(mmVCE_RB_WPTR
, ring
->wptr
);
185 WREG32(mmVCE_RB_BASE_LO
, ring
->gpu_addr
);
186 WREG32(mmVCE_RB_BASE_HI
, upper_32_bits(ring
->gpu_addr
));
187 WREG32(mmVCE_RB_SIZE
, ring
->ring_size
/ 4);
189 ring
= &adev
->vce
.ring
[1];
190 WREG32(mmVCE_RB_RPTR2
, ring
->wptr
);
191 WREG32(mmVCE_RB_WPTR2
, ring
->wptr
);
192 WREG32(mmVCE_RB_BASE_LO2
, ring
->gpu_addr
);
193 WREG32(mmVCE_RB_BASE_HI2
, upper_32_bits(ring
->gpu_addr
));
194 WREG32(mmVCE_RB_SIZE2
, ring
->ring_size
/ 4);
199 #define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074
200 #define VCE_HARVEST_FUSE_MACRO__SHIFT 27
201 #define VCE_HARVEST_FUSE_MACRO__MASK 0x18000000
203 static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device
*adev
)
208 /* Fiji is single pipe */
209 if (adev
->asic_type
== CHIP_FIJI
) {
210 ret
= AMDGPU_VCE_HARVEST_VCE1
;
214 /* Tonga and CZ are dual or single pipe */
215 if (adev
->flags
& AMD_IS_APU
)
216 tmp
= (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS
) &
217 VCE_HARVEST_FUSE_MACRO__MASK
) >>
218 VCE_HARVEST_FUSE_MACRO__SHIFT
;
220 tmp
= (RREG32_SMC(ixCC_HARVEST_FUSES
) &
221 CC_HARVEST_FUSES__VCE_DISABLE_MASK
) >>
222 CC_HARVEST_FUSES__VCE_DISABLE__SHIFT
;
226 ret
= AMDGPU_VCE_HARVEST_VCE0
;
229 ret
= AMDGPU_VCE_HARVEST_VCE1
;
232 ret
= AMDGPU_VCE_HARVEST_VCE0
| AMDGPU_VCE_HARVEST_VCE1
;
241 static int vce_v3_0_early_init(void *handle
)
243 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
245 adev
->vce
.harvest_config
= vce_v3_0_get_harvest_config(adev
);
247 if ((adev
->vce
.harvest_config
&
248 (AMDGPU_VCE_HARVEST_VCE0
| AMDGPU_VCE_HARVEST_VCE1
)) ==
249 (AMDGPU_VCE_HARVEST_VCE0
| AMDGPU_VCE_HARVEST_VCE1
))
252 vce_v3_0_set_ring_funcs(adev
);
253 vce_v3_0_set_irq_funcs(adev
);
258 static int vce_v3_0_sw_init(void *handle
)
260 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
261 struct amdgpu_ring
*ring
;
265 r
= amdgpu_irq_add_id(adev
, 167, &adev
->vce
.irq
);
269 r
= amdgpu_vce_sw_init(adev
, VCE_V3_0_FW_SIZE
+
270 (VCE_V3_0_STACK_SIZE
+ VCE_V3_0_DATA_SIZE
) * 2);
274 r
= amdgpu_vce_resume(adev
);
278 ring
= &adev
->vce
.ring
[0];
279 sprintf(ring
->name
, "vce0");
280 r
= amdgpu_ring_init(adev
, ring
, 4096, VCE_CMD_NO_OP
, 0xf,
281 &adev
->vce
.irq
, 0, AMDGPU_RING_TYPE_VCE
);
285 ring
= &adev
->vce
.ring
[1];
286 sprintf(ring
->name
, "vce1");
287 r
= amdgpu_ring_init(adev
, ring
, 4096, VCE_CMD_NO_OP
, 0xf,
288 &adev
->vce
.irq
, 0, AMDGPU_RING_TYPE_VCE
);
295 static int vce_v3_0_sw_fini(void *handle
)
298 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
300 r
= amdgpu_vce_suspend(adev
);
304 r
= amdgpu_vce_sw_fini(adev
);
311 static int vce_v3_0_hw_init(void *handle
)
313 struct amdgpu_ring
*ring
;
315 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
317 r
= vce_v3_0_start(adev
);
321 ring
= &adev
->vce
.ring
[0];
323 r
= amdgpu_ring_test_ring(ring
);
329 ring
= &adev
->vce
.ring
[1];
331 r
= amdgpu_ring_test_ring(ring
);
337 DRM_INFO("VCE initialized successfully.\n");
342 static int vce_v3_0_hw_fini(void *handle
)
347 static int vce_v3_0_suspend(void *handle
)
350 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
352 r
= vce_v3_0_hw_fini(adev
);
356 r
= amdgpu_vce_suspend(adev
);
363 static int vce_v3_0_resume(void *handle
)
366 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
368 r
= amdgpu_vce_resume(adev
);
372 r
= vce_v3_0_hw_init(adev
);
379 static void vce_v3_0_mc_resume(struct amdgpu_device
*adev
, int idx
)
381 uint32_t offset
, size
;
383 WREG32_P(mmVCE_CLOCK_GATING_A
, 0, ~(1 << 16));
384 WREG32_P(mmVCE_UENC_CLOCK_GATING
, 0x1FF000, ~0xFF9FF000);
385 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING
, 0x3F, ~0x3F);
386 WREG32(mmVCE_CLOCK_GATING_B
, 0xf7);
388 WREG32(mmVCE_LMI_CTRL
, 0x00398000);
389 WREG32_P(mmVCE_LMI_CACHE_CTRL
, 0x0, ~0x1);
390 WREG32(mmVCE_LMI_SWAP_CNTL
, 0);
391 WREG32(mmVCE_LMI_SWAP_CNTL1
, 0);
392 WREG32(mmVCE_LMI_VM_CTRL
, 0);
394 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR
, (adev
->vce
.gpu_addr
>> 8));
395 offset
= AMDGPU_VCE_FIRMWARE_OFFSET
;
396 size
= VCE_V3_0_FW_SIZE
;
397 WREG32(mmVCE_VCPU_CACHE_OFFSET0
, offset
& 0x7fffffff);
398 WREG32(mmVCE_VCPU_CACHE_SIZE0
, size
);
402 size
= VCE_V3_0_STACK_SIZE
;
403 WREG32(mmVCE_VCPU_CACHE_OFFSET1
, offset
& 0x7fffffff);
404 WREG32(mmVCE_VCPU_CACHE_SIZE1
, size
);
406 size
= VCE_V3_0_DATA_SIZE
;
407 WREG32(mmVCE_VCPU_CACHE_OFFSET2
, offset
& 0x7fffffff);
408 WREG32(mmVCE_VCPU_CACHE_SIZE2
, size
);
410 offset
+= size
+ VCE_V3_0_STACK_SIZE
+ VCE_V3_0_DATA_SIZE
;
411 size
= VCE_V3_0_STACK_SIZE
;
412 WREG32(mmVCE_VCPU_CACHE_OFFSET1
, offset
& 0xfffffff);
413 WREG32(mmVCE_VCPU_CACHE_SIZE1
, size
);
415 size
= VCE_V3_0_DATA_SIZE
;
416 WREG32(mmVCE_VCPU_CACHE_OFFSET2
, offset
& 0xfffffff);
417 WREG32(mmVCE_VCPU_CACHE_SIZE2
, size
);
420 WREG32_P(mmVCE_LMI_CTRL2
, 0x0, ~0x100);
422 WREG32_P(mmVCE_SYS_INT_EN
, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
,
423 ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
);
426 static bool vce_v3_0_is_idle(void *handle
)
428 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
432 for (idx
= 0; idx
< 2; ++idx
) {
433 if (adev
->vce
.harvest_config
& (1 << idx
))
437 mask
|= SRBM_STATUS2__VCE0_BUSY_MASK
;
439 mask
|= SRBM_STATUS2__VCE1_BUSY_MASK
;
442 return !(RREG32(mmSRBM_STATUS2
) & mask
);
445 static int vce_v3_0_wait_for_idle(void *handle
)
448 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
452 for (idx
= 0; idx
< 2; ++idx
) {
453 if (adev
->vce
.harvest_config
& (1 << idx
))
457 mask
|= SRBM_STATUS2__VCE0_BUSY_MASK
;
459 mask
|= SRBM_STATUS2__VCE1_BUSY_MASK
;
462 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
463 if (!(RREG32(mmSRBM_STATUS2
) & mask
))
469 static int vce_v3_0_soft_reset(void *handle
)
471 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
475 for (idx
= 0; idx
< 2; ++idx
) {
476 if (adev
->vce
.harvest_config
& (1 << idx
))
480 mask
|= SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK
;
482 mask
|= SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK
;
484 WREG32_P(mmSRBM_SOFT_RESET
, mask
,
485 ~(SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK
|
486 SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK
));
489 return vce_v3_0_start(adev
);
492 static void vce_v3_0_print_status(void *handle
)
494 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
496 dev_info(adev
->dev
, "VCE 3.0 registers\n");
497 dev_info(adev
->dev
, " VCE_STATUS=0x%08X\n",
498 RREG32(mmVCE_STATUS
));
499 dev_info(adev
->dev
, " VCE_VCPU_CNTL=0x%08X\n",
500 RREG32(mmVCE_VCPU_CNTL
));
501 dev_info(adev
->dev
, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n",
502 RREG32(mmVCE_VCPU_CACHE_OFFSET0
));
503 dev_info(adev
->dev
, " VCE_VCPU_CACHE_SIZE0=0x%08X\n",
504 RREG32(mmVCE_VCPU_CACHE_SIZE0
));
505 dev_info(adev
->dev
, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n",
506 RREG32(mmVCE_VCPU_CACHE_OFFSET1
));
507 dev_info(adev
->dev
, " VCE_VCPU_CACHE_SIZE1=0x%08X\n",
508 RREG32(mmVCE_VCPU_CACHE_SIZE1
));
509 dev_info(adev
->dev
, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n",
510 RREG32(mmVCE_VCPU_CACHE_OFFSET2
));
511 dev_info(adev
->dev
, " VCE_VCPU_CACHE_SIZE2=0x%08X\n",
512 RREG32(mmVCE_VCPU_CACHE_SIZE2
));
513 dev_info(adev
->dev
, " VCE_SOFT_RESET=0x%08X\n",
514 RREG32(mmVCE_SOFT_RESET
));
515 dev_info(adev
->dev
, " VCE_RB_BASE_LO2=0x%08X\n",
516 RREG32(mmVCE_RB_BASE_LO2
));
517 dev_info(adev
->dev
, " VCE_RB_BASE_HI2=0x%08X\n",
518 RREG32(mmVCE_RB_BASE_HI2
));
519 dev_info(adev
->dev
, " VCE_RB_SIZE2=0x%08X\n",
520 RREG32(mmVCE_RB_SIZE2
));
521 dev_info(adev
->dev
, " VCE_RB_RPTR2=0x%08X\n",
522 RREG32(mmVCE_RB_RPTR2
));
523 dev_info(adev
->dev
, " VCE_RB_WPTR2=0x%08X\n",
524 RREG32(mmVCE_RB_WPTR2
));
525 dev_info(adev
->dev
, " VCE_RB_BASE_LO=0x%08X\n",
526 RREG32(mmVCE_RB_BASE_LO
));
527 dev_info(adev
->dev
, " VCE_RB_BASE_HI=0x%08X\n",
528 RREG32(mmVCE_RB_BASE_HI
));
529 dev_info(adev
->dev
, " VCE_RB_SIZE=0x%08X\n",
530 RREG32(mmVCE_RB_SIZE
));
531 dev_info(adev
->dev
, " VCE_RB_RPTR=0x%08X\n",
532 RREG32(mmVCE_RB_RPTR
));
533 dev_info(adev
->dev
, " VCE_RB_WPTR=0x%08X\n",
534 RREG32(mmVCE_RB_WPTR
));
535 dev_info(adev
->dev
, " VCE_CLOCK_GATING_A=0x%08X\n",
536 RREG32(mmVCE_CLOCK_GATING_A
));
537 dev_info(adev
->dev
, " VCE_CLOCK_GATING_B=0x%08X\n",
538 RREG32(mmVCE_CLOCK_GATING_B
));
539 dev_info(adev
->dev
, " VCE_UENC_CLOCK_GATING=0x%08X\n",
540 RREG32(mmVCE_UENC_CLOCK_GATING
));
541 dev_info(adev
->dev
, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n",
542 RREG32(mmVCE_UENC_REG_CLOCK_GATING
));
543 dev_info(adev
->dev
, " VCE_SYS_INT_EN=0x%08X\n",
544 RREG32(mmVCE_SYS_INT_EN
));
545 dev_info(adev
->dev
, " VCE_LMI_CTRL2=0x%08X\n",
546 RREG32(mmVCE_LMI_CTRL2
));
547 dev_info(adev
->dev
, " VCE_LMI_CTRL=0x%08X\n",
548 RREG32(mmVCE_LMI_CTRL
));
549 dev_info(adev
->dev
, " VCE_LMI_VM_CTRL=0x%08X\n",
550 RREG32(mmVCE_LMI_VM_CTRL
));
551 dev_info(adev
->dev
, " VCE_LMI_SWAP_CNTL=0x%08X\n",
552 RREG32(mmVCE_LMI_SWAP_CNTL
));
553 dev_info(adev
->dev
, " VCE_LMI_SWAP_CNTL1=0x%08X\n",
554 RREG32(mmVCE_LMI_SWAP_CNTL1
));
555 dev_info(adev
->dev
, " VCE_LMI_CACHE_CTRL=0x%08X\n",
556 RREG32(mmVCE_LMI_CACHE_CTRL
));
559 static int vce_v3_0_set_interrupt_state(struct amdgpu_device
*adev
,
560 struct amdgpu_irq_src
*source
,
562 enum amdgpu_interrupt_state state
)
566 if (state
== AMDGPU_IRQ_STATE_ENABLE
)
567 val
|= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
;
569 WREG32_P(mmVCE_SYS_INT_EN
, val
, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
);
573 static int vce_v3_0_process_interrupt(struct amdgpu_device
*adev
,
574 struct amdgpu_irq_src
*source
,
575 struct amdgpu_iv_entry
*entry
)
577 DRM_DEBUG("IH: VCE\n");
578 switch (entry
->src_data
) {
580 amdgpu_fence_process(&adev
->vce
.ring
[0]);
583 amdgpu_fence_process(&adev
->vce
.ring
[1]);
586 DRM_ERROR("Unhandled interrupt: %d %d\n",
587 entry
->src_id
, entry
->src_data
);
594 static int vce_v3_0_set_clockgating_state(void *handle
,
595 enum amd_clockgating_state state
)
600 static int vce_v3_0_set_powergating_state(void *handle
,
601 enum amd_powergating_state state
)
603 /* This doesn't actually powergate the VCE block.
604 * That's done in the dpm code via the SMC. This
605 * just re-inits the block as necessary. The actual
606 * gating still happens in the dpm code. We should
607 * revisit this when there is a cleaner line between
608 * the smc and the hw blocks
610 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
612 if (state
== AMD_PG_STATE_GATE
)
613 /* XXX do we need a vce_v3_0_stop()? */
616 return vce_v3_0_start(adev
);
619 const struct amd_ip_funcs vce_v3_0_ip_funcs
= {
620 .early_init
= vce_v3_0_early_init
,
622 .sw_init
= vce_v3_0_sw_init
,
623 .sw_fini
= vce_v3_0_sw_fini
,
624 .hw_init
= vce_v3_0_hw_init
,
625 .hw_fini
= vce_v3_0_hw_fini
,
626 .suspend
= vce_v3_0_suspend
,
627 .resume
= vce_v3_0_resume
,
628 .is_idle
= vce_v3_0_is_idle
,
629 .wait_for_idle
= vce_v3_0_wait_for_idle
,
630 .soft_reset
= vce_v3_0_soft_reset
,
631 .print_status
= vce_v3_0_print_status
,
632 .set_clockgating_state
= vce_v3_0_set_clockgating_state
,
633 .set_powergating_state
= vce_v3_0_set_powergating_state
,
636 static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs
= {
637 .get_rptr
= vce_v3_0_ring_get_rptr
,
638 .get_wptr
= vce_v3_0_ring_get_wptr
,
639 .set_wptr
= vce_v3_0_ring_set_wptr
,
640 .parse_cs
= amdgpu_vce_ring_parse_cs
,
641 .emit_ib
= amdgpu_vce_ring_emit_ib
,
642 .emit_fence
= amdgpu_vce_ring_emit_fence
,
643 .emit_semaphore
= amdgpu_vce_ring_emit_semaphore
,
644 .test_ring
= amdgpu_vce_ring_test_ring
,
645 .test_ib
= amdgpu_vce_ring_test_ib
,
646 .is_lockup
= amdgpu_ring_test_lockup
,
647 .insert_nop
= amdgpu_ring_insert_nop
,
650 static void vce_v3_0_set_ring_funcs(struct amdgpu_device
*adev
)
652 adev
->vce
.ring
[0].funcs
= &vce_v3_0_ring_funcs
;
653 adev
->vce
.ring
[1].funcs
= &vce_v3_0_ring_funcs
;
656 static const struct amdgpu_irq_src_funcs vce_v3_0_irq_funcs
= {
657 .set
= vce_v3_0_set_interrupt_state
,
658 .process
= vce_v3_0_process_interrupt
,
661 static void vce_v3_0_set_irq_funcs(struct amdgpu_device
*adev
)
663 adev
->vce
.irq
.num_types
= 1;
664 adev
->vce
.irq
.funcs
= &vce_v3_0_irq_funcs
;