2 * Copyright 2014 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
25 * Authors: Christian König <christian.koenig@amd.com>
28 #include <linux/firmware.h>
31 #include "amdgpu_vce.h"
33 #include "vce/vce_3_0_d.h"
34 #include "vce/vce_3_0_sh_mask.h"
35 #include "oss/oss_2_0_d.h"
36 #include "oss/oss_2_0_sh_mask.h"
37 #include "gca/gfx_8_0_d.h"
39 #define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04
40 #define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10
42 #define VCE_V3_0_FW_SIZE (384 * 1024)
43 #define VCE_V3_0_STACK_SIZE (64 * 1024)
44 #define VCE_V3_0_DATA_SIZE ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 1024))
46 static void vce_v3_0_mc_resume(struct amdgpu_device
*adev
, int idx
);
47 static void vce_v3_0_set_ring_funcs(struct amdgpu_device
*adev
);
48 static void vce_v3_0_set_irq_funcs(struct amdgpu_device
*adev
);
51 * vce_v3_0_ring_get_rptr - get read pointer
53 * @ring: amdgpu_ring pointer
55 * Returns the current hardware read pointer
57 static uint32_t vce_v3_0_ring_get_rptr(struct amdgpu_ring
*ring
)
59 struct amdgpu_device
*adev
= ring
->adev
;
61 if (ring
== &adev
->vce
.ring
[0])
62 return RREG32(mmVCE_RB_RPTR
);
64 return RREG32(mmVCE_RB_RPTR2
);
68 * vce_v3_0_ring_get_wptr - get write pointer
70 * @ring: amdgpu_ring pointer
72 * Returns the current hardware write pointer
74 static uint32_t vce_v3_0_ring_get_wptr(struct amdgpu_ring
*ring
)
76 struct amdgpu_device
*adev
= ring
->adev
;
78 if (ring
== &adev
->vce
.ring
[0])
79 return RREG32(mmVCE_RB_WPTR
);
81 return RREG32(mmVCE_RB_WPTR2
);
85 * vce_v3_0_ring_set_wptr - set write pointer
87 * @ring: amdgpu_ring pointer
89 * Commits the write pointer to the hardware
91 static void vce_v3_0_ring_set_wptr(struct amdgpu_ring
*ring
)
93 struct amdgpu_device
*adev
= ring
->adev
;
95 if (ring
== &adev
->vce
.ring
[0])
96 WREG32(mmVCE_RB_WPTR
, ring
->wptr
);
98 WREG32(mmVCE_RB_WPTR2
, ring
->wptr
);
102 * vce_v3_0_start - start VCE block
104 * @adev: amdgpu_device pointer
106 * Setup and start the VCE block
108 static int vce_v3_0_start(struct amdgpu_device
*adev
)
110 struct amdgpu_ring
*ring
;
113 mutex_lock(&adev
->grbm_idx_mutex
);
114 for (idx
= 0; idx
< 2; ++idx
) {
116 WREG32_P(mmGRBM_GFX_INDEX
, 0,
117 ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK
);
119 WREG32_P(mmGRBM_GFX_INDEX
,
120 GRBM_GFX_INDEX__VCE_INSTANCE_MASK
,
121 ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK
);
123 vce_v3_0_mc_resume(adev
, idx
);
126 WREG32_P(mmVCE_STATUS
, 1, ~1);
128 WREG32_P(mmVCE_VCPU_CNTL
, VCE_VCPU_CNTL__CLK_EN_MASK
,
129 ~VCE_VCPU_CNTL__CLK_EN_MASK
);
131 WREG32_P(mmVCE_SOFT_RESET
,
132 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
,
133 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
);
137 WREG32_P(mmVCE_SOFT_RESET
, 0,
138 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
);
140 for (i
= 0; i
< 10; ++i
) {
142 for (j
= 0; j
< 100; ++j
) {
143 status
= RREG32(mmVCE_STATUS
);
152 DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
153 WREG32_P(mmVCE_SOFT_RESET
,
154 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
,
155 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
);
157 WREG32_P(mmVCE_SOFT_RESET
, 0,
158 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
);
163 /* clear BUSY flag */
164 WREG32_P(mmVCE_STATUS
, 0, ~1);
167 DRM_ERROR("VCE not responding, giving up!!!\n");
168 mutex_unlock(&adev
->grbm_idx_mutex
);
173 WREG32_P(mmGRBM_GFX_INDEX
, 0, ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK
);
174 mutex_unlock(&adev
->grbm_idx_mutex
);
176 ring
= &adev
->vce
.ring
[0];
177 WREG32(mmVCE_RB_RPTR
, ring
->wptr
);
178 WREG32(mmVCE_RB_WPTR
, ring
->wptr
);
179 WREG32(mmVCE_RB_BASE_LO
, ring
->gpu_addr
);
180 WREG32(mmVCE_RB_BASE_HI
, upper_32_bits(ring
->gpu_addr
));
181 WREG32(mmVCE_RB_SIZE
, ring
->ring_size
/ 4);
183 ring
= &adev
->vce
.ring
[1];
184 WREG32(mmVCE_RB_RPTR2
, ring
->wptr
);
185 WREG32(mmVCE_RB_WPTR2
, ring
->wptr
);
186 WREG32(mmVCE_RB_BASE_LO2
, ring
->gpu_addr
);
187 WREG32(mmVCE_RB_BASE_HI2
, upper_32_bits(ring
->gpu_addr
));
188 WREG32(mmVCE_RB_SIZE2
, ring
->ring_size
/ 4);
193 static int vce_v3_0_early_init(void *handle
)
195 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
197 vce_v3_0_set_ring_funcs(adev
);
198 vce_v3_0_set_irq_funcs(adev
);
203 static int vce_v3_0_sw_init(void *handle
)
205 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
206 struct amdgpu_ring
*ring
;
210 r
= amdgpu_irq_add_id(adev
, 167, &adev
->vce
.irq
);
214 r
= amdgpu_vce_sw_init(adev
, VCE_V3_0_FW_SIZE
+
215 (VCE_V3_0_STACK_SIZE
+ VCE_V3_0_DATA_SIZE
) * 2);
219 r
= amdgpu_vce_resume(adev
);
223 ring
= &adev
->vce
.ring
[0];
224 sprintf(ring
->name
, "vce0");
225 r
= amdgpu_ring_init(adev
, ring
, 4096, VCE_CMD_NO_OP
, 0xf,
226 &adev
->vce
.irq
, 0, AMDGPU_RING_TYPE_VCE
);
230 ring
= &adev
->vce
.ring
[1];
231 sprintf(ring
->name
, "vce1");
232 r
= amdgpu_ring_init(adev
, ring
, 4096, VCE_CMD_NO_OP
, 0xf,
233 &adev
->vce
.irq
, 0, AMDGPU_RING_TYPE_VCE
);
240 static int vce_v3_0_sw_fini(void *handle
)
243 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
245 r
= amdgpu_vce_suspend(adev
);
249 r
= amdgpu_vce_sw_fini(adev
);
256 static int vce_v3_0_hw_init(void *handle
)
258 struct amdgpu_ring
*ring
;
260 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
262 r
= vce_v3_0_start(adev
);
266 ring
= &adev
->vce
.ring
[0];
268 r
= amdgpu_ring_test_ring(ring
);
274 ring
= &adev
->vce
.ring
[1];
276 r
= amdgpu_ring_test_ring(ring
);
282 DRM_INFO("VCE initialized successfully.\n");
287 static int vce_v3_0_hw_fini(void *handle
)
292 static int vce_v3_0_suspend(void *handle
)
295 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
297 r
= vce_v3_0_hw_fini(adev
);
301 r
= amdgpu_vce_suspend(adev
);
308 static int vce_v3_0_resume(void *handle
)
311 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
313 r
= amdgpu_vce_resume(adev
);
317 r
= vce_v3_0_hw_init(adev
);
324 static void vce_v3_0_mc_resume(struct amdgpu_device
*adev
, int idx
)
326 uint32_t offset
, size
;
328 WREG32_P(mmVCE_CLOCK_GATING_A
, 0, ~(1 << 16));
329 WREG32_P(mmVCE_UENC_CLOCK_GATING
, 0x1FF000, ~0xFF9FF000);
330 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING
, 0x3F, ~0x3F);
331 WREG32(mmVCE_CLOCK_GATING_B
, 0xf7);
333 WREG32(mmVCE_LMI_CTRL
, 0x00398000);
334 WREG32_P(mmVCE_LMI_CACHE_CTRL
, 0x0, ~0x1);
335 WREG32(mmVCE_LMI_SWAP_CNTL
, 0);
336 WREG32(mmVCE_LMI_SWAP_CNTL1
, 0);
337 WREG32(mmVCE_LMI_VM_CTRL
, 0);
339 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR
, (adev
->vce
.gpu_addr
>> 8));
340 offset
= AMDGPU_VCE_FIRMWARE_OFFSET
;
341 size
= VCE_V3_0_FW_SIZE
;
342 WREG32(mmVCE_VCPU_CACHE_OFFSET0
, offset
& 0x7fffffff);
343 WREG32(mmVCE_VCPU_CACHE_SIZE0
, size
);
347 size
= VCE_V3_0_STACK_SIZE
;
348 WREG32(mmVCE_VCPU_CACHE_OFFSET1
, offset
& 0x7fffffff);
349 WREG32(mmVCE_VCPU_CACHE_SIZE1
, size
);
351 size
= VCE_V3_0_DATA_SIZE
;
352 WREG32(mmVCE_VCPU_CACHE_OFFSET2
, offset
& 0x7fffffff);
353 WREG32(mmVCE_VCPU_CACHE_SIZE2
, size
);
355 offset
+= size
+ VCE_V3_0_STACK_SIZE
+ VCE_V3_0_DATA_SIZE
;
356 size
= VCE_V3_0_STACK_SIZE
;
357 WREG32(mmVCE_VCPU_CACHE_OFFSET1
, offset
& 0xfffffff);
358 WREG32(mmVCE_VCPU_CACHE_SIZE1
, size
);
360 size
= VCE_V3_0_DATA_SIZE
;
361 WREG32(mmVCE_VCPU_CACHE_OFFSET2
, offset
& 0xfffffff);
362 WREG32(mmVCE_VCPU_CACHE_SIZE2
, size
);
365 WREG32_P(mmVCE_LMI_CTRL2
, 0x0, ~0x100);
367 WREG32_P(mmVCE_SYS_INT_EN
, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
,
368 ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
);
371 static bool vce_v3_0_is_idle(void *handle
)
373 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
375 return !(RREG32(mmSRBM_STATUS2
) & SRBM_STATUS2__VCE_BUSY_MASK
);
378 static int vce_v3_0_wait_for_idle(void *handle
)
381 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
383 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
384 if (!(RREG32(mmSRBM_STATUS2
) & SRBM_STATUS2__VCE_BUSY_MASK
))
390 static int vce_v3_0_soft_reset(void *handle
)
392 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
394 WREG32_P(mmSRBM_SOFT_RESET
, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK
,
395 ~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK
);
398 return vce_v3_0_start(adev
);
401 static void vce_v3_0_print_status(void *handle
)
403 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
405 dev_info(adev
->dev
, "VCE 3.0 registers\n");
406 dev_info(adev
->dev
, " VCE_STATUS=0x%08X\n",
407 RREG32(mmVCE_STATUS
));
408 dev_info(adev
->dev
, " VCE_VCPU_CNTL=0x%08X\n",
409 RREG32(mmVCE_VCPU_CNTL
));
410 dev_info(adev
->dev
, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n",
411 RREG32(mmVCE_VCPU_CACHE_OFFSET0
));
412 dev_info(adev
->dev
, " VCE_VCPU_CACHE_SIZE0=0x%08X\n",
413 RREG32(mmVCE_VCPU_CACHE_SIZE0
));
414 dev_info(adev
->dev
, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n",
415 RREG32(mmVCE_VCPU_CACHE_OFFSET1
));
416 dev_info(adev
->dev
, " VCE_VCPU_CACHE_SIZE1=0x%08X\n",
417 RREG32(mmVCE_VCPU_CACHE_SIZE1
));
418 dev_info(adev
->dev
, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n",
419 RREG32(mmVCE_VCPU_CACHE_OFFSET2
));
420 dev_info(adev
->dev
, " VCE_VCPU_CACHE_SIZE2=0x%08X\n",
421 RREG32(mmVCE_VCPU_CACHE_SIZE2
));
422 dev_info(adev
->dev
, " VCE_SOFT_RESET=0x%08X\n",
423 RREG32(mmVCE_SOFT_RESET
));
424 dev_info(adev
->dev
, " VCE_RB_BASE_LO2=0x%08X\n",
425 RREG32(mmVCE_RB_BASE_LO2
));
426 dev_info(adev
->dev
, " VCE_RB_BASE_HI2=0x%08X\n",
427 RREG32(mmVCE_RB_BASE_HI2
));
428 dev_info(adev
->dev
, " VCE_RB_SIZE2=0x%08X\n",
429 RREG32(mmVCE_RB_SIZE2
));
430 dev_info(adev
->dev
, " VCE_RB_RPTR2=0x%08X\n",
431 RREG32(mmVCE_RB_RPTR2
));
432 dev_info(adev
->dev
, " VCE_RB_WPTR2=0x%08X\n",
433 RREG32(mmVCE_RB_WPTR2
));
434 dev_info(adev
->dev
, " VCE_RB_BASE_LO=0x%08X\n",
435 RREG32(mmVCE_RB_BASE_LO
));
436 dev_info(adev
->dev
, " VCE_RB_BASE_HI=0x%08X\n",
437 RREG32(mmVCE_RB_BASE_HI
));
438 dev_info(adev
->dev
, " VCE_RB_SIZE=0x%08X\n",
439 RREG32(mmVCE_RB_SIZE
));
440 dev_info(adev
->dev
, " VCE_RB_RPTR=0x%08X\n",
441 RREG32(mmVCE_RB_RPTR
));
442 dev_info(adev
->dev
, " VCE_RB_WPTR=0x%08X\n",
443 RREG32(mmVCE_RB_WPTR
));
444 dev_info(adev
->dev
, " VCE_CLOCK_GATING_A=0x%08X\n",
445 RREG32(mmVCE_CLOCK_GATING_A
));
446 dev_info(adev
->dev
, " VCE_CLOCK_GATING_B=0x%08X\n",
447 RREG32(mmVCE_CLOCK_GATING_B
));
448 dev_info(adev
->dev
, " VCE_UENC_CLOCK_GATING=0x%08X\n",
449 RREG32(mmVCE_UENC_CLOCK_GATING
));
450 dev_info(adev
->dev
, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n",
451 RREG32(mmVCE_UENC_REG_CLOCK_GATING
));
452 dev_info(adev
->dev
, " VCE_SYS_INT_EN=0x%08X\n",
453 RREG32(mmVCE_SYS_INT_EN
));
454 dev_info(adev
->dev
, " VCE_LMI_CTRL2=0x%08X\n",
455 RREG32(mmVCE_LMI_CTRL2
));
456 dev_info(adev
->dev
, " VCE_LMI_CTRL=0x%08X\n",
457 RREG32(mmVCE_LMI_CTRL
));
458 dev_info(adev
->dev
, " VCE_LMI_VM_CTRL=0x%08X\n",
459 RREG32(mmVCE_LMI_VM_CTRL
));
460 dev_info(adev
->dev
, " VCE_LMI_SWAP_CNTL=0x%08X\n",
461 RREG32(mmVCE_LMI_SWAP_CNTL
));
462 dev_info(adev
->dev
, " VCE_LMI_SWAP_CNTL1=0x%08X\n",
463 RREG32(mmVCE_LMI_SWAP_CNTL1
));
464 dev_info(adev
->dev
, " VCE_LMI_CACHE_CTRL=0x%08X\n",
465 RREG32(mmVCE_LMI_CACHE_CTRL
));
468 static int vce_v3_0_set_interrupt_state(struct amdgpu_device
*adev
,
469 struct amdgpu_irq_src
*source
,
471 enum amdgpu_interrupt_state state
)
475 if (state
== AMDGPU_IRQ_STATE_ENABLE
)
476 val
|= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
;
478 WREG32_P(mmVCE_SYS_INT_EN
, val
, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
);
482 static int vce_v3_0_process_interrupt(struct amdgpu_device
*adev
,
483 struct amdgpu_irq_src
*source
,
484 struct amdgpu_iv_entry
*entry
)
486 DRM_DEBUG("IH: VCE\n");
487 switch (entry
->src_data
) {
489 amdgpu_fence_process(&adev
->vce
.ring
[0]);
492 amdgpu_fence_process(&adev
->vce
.ring
[1]);
495 DRM_ERROR("Unhandled interrupt: %d %d\n",
496 entry
->src_id
, entry
->src_data
);
503 static int vce_v3_0_set_clockgating_state(void *handle
,
504 enum amd_clockgating_state state
)
509 static int vce_v3_0_set_powergating_state(void *handle
,
510 enum amd_powergating_state state
)
512 /* This doesn't actually powergate the VCE block.
513 * That's done in the dpm code via the SMC. This
514 * just re-inits the block as necessary. The actual
515 * gating still happens in the dpm code. We should
516 * revisit this when there is a cleaner line between
517 * the smc and the hw blocks
519 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
521 if (state
== AMD_PG_STATE_GATE
)
522 /* XXX do we need a vce_v3_0_stop()? */
525 return vce_v3_0_start(adev
);
528 const struct amd_ip_funcs vce_v3_0_ip_funcs
= {
529 .early_init
= vce_v3_0_early_init
,
531 .sw_init
= vce_v3_0_sw_init
,
532 .sw_fini
= vce_v3_0_sw_fini
,
533 .hw_init
= vce_v3_0_hw_init
,
534 .hw_fini
= vce_v3_0_hw_fini
,
535 .suspend
= vce_v3_0_suspend
,
536 .resume
= vce_v3_0_resume
,
537 .is_idle
= vce_v3_0_is_idle
,
538 .wait_for_idle
= vce_v3_0_wait_for_idle
,
539 .soft_reset
= vce_v3_0_soft_reset
,
540 .print_status
= vce_v3_0_print_status
,
541 .set_clockgating_state
= vce_v3_0_set_clockgating_state
,
542 .set_powergating_state
= vce_v3_0_set_powergating_state
,
545 static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs
= {
546 .get_rptr
= vce_v3_0_ring_get_rptr
,
547 .get_wptr
= vce_v3_0_ring_get_wptr
,
548 .set_wptr
= vce_v3_0_ring_set_wptr
,
549 .parse_cs
= amdgpu_vce_ring_parse_cs
,
550 .emit_ib
= amdgpu_vce_ring_emit_ib
,
551 .emit_fence
= amdgpu_vce_ring_emit_fence
,
552 .emit_semaphore
= amdgpu_vce_ring_emit_semaphore
,
553 .test_ring
= amdgpu_vce_ring_test_ring
,
554 .test_ib
= amdgpu_vce_ring_test_ib
,
555 .is_lockup
= amdgpu_ring_test_lockup
,
558 static void vce_v3_0_set_ring_funcs(struct amdgpu_device
*adev
)
560 adev
->vce
.ring
[0].funcs
= &vce_v3_0_ring_funcs
;
561 adev
->vce
.ring
[1].funcs
= &vce_v3_0_ring_funcs
;
564 static const struct amdgpu_irq_src_funcs vce_v3_0_irq_funcs
= {
565 .set
= vce_v3_0_set_interrupt_state
,
566 .process
= vce_v3_0_process_interrupt
,
569 static void vce_v3_0_set_irq_funcs(struct amdgpu_device
*adev
)
571 adev
->vce
.irq
.num_types
= 1;
572 adev
->vce
.irq
.funcs
= &vce_v3_0_irq_funcs
;