2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
28 #include "amdgpu_atombios.h"
29 #include "amdgpu_ih.h"
30 #include "amdgpu_uvd.h"
31 #include "amdgpu_vce.h"
32 #include "amdgpu_ucode.h"
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
38 #include "oss/oss_3_0_d.h"
39 #include "oss/oss_3_0_sh_mask.h"
41 #include "bif/bif_5_0_d.h"
42 #include "bif/bif_5_0_sh_mask.h"
44 #include "gca/gfx_8_0_d.h"
45 #include "gca/gfx_8_0_sh_mask.h"
47 #include "smu/smu_7_1_1_d.h"
48 #include "smu/smu_7_1_1_sh_mask.h"
50 #include "uvd/uvd_5_0_d.h"
51 #include "uvd/uvd_5_0_sh_mask.h"
53 #include "vce/vce_3_0_d.h"
54 #include "vce/vce_3_0_sh_mask.h"
56 #include "dce/dce_10_0_d.h"
57 #include "dce/dce_10_0_sh_mask.h"
64 #include "sdma_v2_4.h"
65 #include "sdma_v3_0.h"
66 #include "dce_v10_0.h"
67 #include "dce_v11_0.h"
68 #include "iceland_ih.h"
76 * Indirect registers accessor
78 static u32
vi_pcie_rreg(struct amdgpu_device
*adev
, u32 reg
)
83 spin_lock_irqsave(&adev
->pcie_idx_lock
, flags
);
84 WREG32(mmPCIE_INDEX
, reg
);
85 (void)RREG32(mmPCIE_INDEX
);
86 r
= RREG32(mmPCIE_DATA
);
87 spin_unlock_irqrestore(&adev
->pcie_idx_lock
, flags
);
91 static void vi_pcie_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
95 spin_lock_irqsave(&adev
->pcie_idx_lock
, flags
);
96 WREG32(mmPCIE_INDEX
, reg
);
97 (void)RREG32(mmPCIE_INDEX
);
98 WREG32(mmPCIE_DATA
, v
);
99 (void)RREG32(mmPCIE_DATA
);
100 spin_unlock_irqrestore(&adev
->pcie_idx_lock
, flags
);
103 static u32
vi_smc_rreg(struct amdgpu_device
*adev
, u32 reg
)
108 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
109 WREG32(mmSMC_IND_INDEX_0
, (reg
));
110 r
= RREG32(mmSMC_IND_DATA_0
);
111 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
115 static void vi_smc_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
119 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
120 WREG32(mmSMC_IND_INDEX_0
, (reg
));
121 WREG32(mmSMC_IND_DATA_0
, (v
));
122 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
126 #define mmMP0PUB_IND_INDEX 0x180
127 #define mmMP0PUB_IND_DATA 0x181
129 static u32
cz_smc_rreg(struct amdgpu_device
*adev
, u32 reg
)
134 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
135 WREG32(mmMP0PUB_IND_INDEX
, (reg
));
136 r
= RREG32(mmMP0PUB_IND_DATA
);
137 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
141 static void cz_smc_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
145 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
146 WREG32(mmMP0PUB_IND_INDEX
, (reg
));
147 WREG32(mmMP0PUB_IND_DATA
, (v
));
148 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
151 static u32
vi_uvd_ctx_rreg(struct amdgpu_device
*adev
, u32 reg
)
156 spin_lock_irqsave(&adev
->uvd_ctx_idx_lock
, flags
);
157 WREG32(mmUVD_CTX_INDEX
, ((reg
) & 0x1ff));
158 r
= RREG32(mmUVD_CTX_DATA
);
159 spin_unlock_irqrestore(&adev
->uvd_ctx_idx_lock
, flags
);
163 static void vi_uvd_ctx_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
167 spin_lock_irqsave(&adev
->uvd_ctx_idx_lock
, flags
);
168 WREG32(mmUVD_CTX_INDEX
, ((reg
) & 0x1ff));
169 WREG32(mmUVD_CTX_DATA
, (v
));
170 spin_unlock_irqrestore(&adev
->uvd_ctx_idx_lock
, flags
);
173 static u32
vi_didt_rreg(struct amdgpu_device
*adev
, u32 reg
)
178 spin_lock_irqsave(&adev
->didt_idx_lock
, flags
);
179 WREG32(mmDIDT_IND_INDEX
, (reg
));
180 r
= RREG32(mmDIDT_IND_DATA
);
181 spin_unlock_irqrestore(&adev
->didt_idx_lock
, flags
);
185 static void vi_didt_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
189 spin_lock_irqsave(&adev
->didt_idx_lock
, flags
);
190 WREG32(mmDIDT_IND_INDEX
, (reg
));
191 WREG32(mmDIDT_IND_DATA
, (v
));
192 spin_unlock_irqrestore(&adev
->didt_idx_lock
, flags
);
195 static const u32 tonga_mgcg_cgcg_init
[] =
197 mmCGTT_DRM_CLK_CTRL0
, 0xffffffff, 0x00600100,
198 mmPCIE_INDEX
, 0xffffffff, 0x0140001c,
199 mmPCIE_DATA
, 0x000f0000, 0x00000000,
200 mmSMC_IND_INDEX_4
, 0xffffffff, 0xC060000C,
201 mmSMC_IND_DATA_4
, 0xc0000fff, 0x00000100,
202 mmCGTT_DRM_CLK_CTRL0
, 0xff000fff, 0x00000100,
203 mmHDP_XDP_CGTT_BLK_CTRL
, 0xc0000fff, 0x00000104,
206 static const u32 fiji_mgcg_cgcg_init
[] =
208 mmCGTT_DRM_CLK_CTRL0
, 0xffffffff, 0x00600100,
209 mmPCIE_INDEX
, 0xffffffff, 0x0140001c,
210 mmPCIE_DATA
, 0x000f0000, 0x00000000,
211 mmSMC_IND_INDEX_4
, 0xffffffff, 0xC060000C,
212 mmSMC_IND_DATA_4
, 0xc0000fff, 0x00000100,
213 mmCGTT_DRM_CLK_CTRL0
, 0xff000fff, 0x00000100,
214 mmHDP_XDP_CGTT_BLK_CTRL
, 0xc0000fff, 0x00000104,
217 static const u32 iceland_mgcg_cgcg_init
[] =
219 mmPCIE_INDEX
, 0xffffffff, ixPCIE_CNTL2
,
220 mmPCIE_DATA
, 0x000f0000, 0x00000000,
221 mmSMC_IND_INDEX_4
, 0xffffffff, ixCGTT_ROM_CLK_CTRL0
,
222 mmSMC_IND_DATA_4
, 0xc0000fff, 0x00000100,
223 mmHDP_XDP_CGTT_BLK_CTRL
, 0xc0000fff, 0x00000104,
226 static const u32 cz_mgcg_cgcg_init
[] =
228 mmCGTT_DRM_CLK_CTRL0
, 0xffffffff, 0x00600100,
229 mmPCIE_INDEX
, 0xffffffff, 0x0140001c,
230 mmPCIE_DATA
, 0x000f0000, 0x00000000,
231 mmCGTT_DRM_CLK_CTRL0
, 0xff000fff, 0x00000100,
232 mmHDP_XDP_CGTT_BLK_CTRL
, 0xc0000fff, 0x00000104,
235 static void vi_init_golden_registers(struct amdgpu_device
*adev
)
237 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
238 mutex_lock(&adev
->grbm_idx_mutex
);
240 switch (adev
->asic_type
) {
242 amdgpu_program_register_sequence(adev
,
243 iceland_mgcg_cgcg_init
,
244 (const u32
)ARRAY_SIZE(iceland_mgcg_cgcg_init
));
247 amdgpu_program_register_sequence(adev
,
249 (const u32
)ARRAY_SIZE(fiji_mgcg_cgcg_init
));
252 amdgpu_program_register_sequence(adev
,
253 tonga_mgcg_cgcg_init
,
254 (const u32
)ARRAY_SIZE(tonga_mgcg_cgcg_init
));
257 amdgpu_program_register_sequence(adev
,
259 (const u32
)ARRAY_SIZE(cz_mgcg_cgcg_init
));
264 mutex_unlock(&adev
->grbm_idx_mutex
);
268 * vi_get_xclk - get the xclk
270 * @adev: amdgpu_device pointer
272 * Returns the reference clock used by the gfx engine
275 static u32
vi_get_xclk(struct amdgpu_device
*adev
)
277 u32 reference_clock
= adev
->clock
.spll
.reference_freq
;
280 if (adev
->flags
& AMD_IS_APU
)
281 return reference_clock
;
283 tmp
= RREG32_SMC(ixCG_CLKPIN_CNTL_2
);
284 if (REG_GET_FIELD(tmp
, CG_CLKPIN_CNTL_2
, MUX_TCLK_TO_XCLK
))
287 tmp
= RREG32_SMC(ixCG_CLKPIN_CNTL
);
288 if (REG_GET_FIELD(tmp
, CG_CLKPIN_CNTL
, XTALIN_DIVIDE
))
289 return reference_clock
/ 4;
291 return reference_clock
;
295 * vi_srbm_select - select specific register instances
297 * @adev: amdgpu_device pointer
298 * @me: selected ME (micro engine)
303 * Switches the currently active registers instances. Some
304 * registers are instanced per VMID, others are instanced per
305 * me/pipe/queue combination.
307 void vi_srbm_select(struct amdgpu_device
*adev
,
308 u32 me
, u32 pipe
, u32 queue
, u32 vmid
)
310 u32 srbm_gfx_cntl
= 0;
311 srbm_gfx_cntl
= REG_SET_FIELD(srbm_gfx_cntl
, SRBM_GFX_CNTL
, PIPEID
, pipe
);
312 srbm_gfx_cntl
= REG_SET_FIELD(srbm_gfx_cntl
, SRBM_GFX_CNTL
, MEID
, me
);
313 srbm_gfx_cntl
= REG_SET_FIELD(srbm_gfx_cntl
, SRBM_GFX_CNTL
, VMID
, vmid
);
314 srbm_gfx_cntl
= REG_SET_FIELD(srbm_gfx_cntl
, SRBM_GFX_CNTL
, QUEUEID
, queue
);
315 WREG32(mmSRBM_GFX_CNTL
, srbm_gfx_cntl
);
318 static void vi_vga_set_state(struct amdgpu_device
*adev
, bool state
)
323 static bool vi_read_disabled_bios(struct amdgpu_device
*adev
)
326 u32 d1vga_control
= 0;
327 u32 d2vga_control
= 0;
328 u32 vga_render_control
= 0;
332 bus_cntl
= RREG32(mmBUS_CNTL
);
333 if (adev
->mode_info
.num_crtc
) {
334 d1vga_control
= RREG32(mmD1VGA_CONTROL
);
335 d2vga_control
= RREG32(mmD2VGA_CONTROL
);
336 vga_render_control
= RREG32(mmVGA_RENDER_CONTROL
);
338 rom_cntl
= RREG32_SMC(ixROM_CNTL
);
341 WREG32(mmBUS_CNTL
, (bus_cntl
& ~BUS_CNTL__BIOS_ROM_DIS_MASK
));
342 if (adev
->mode_info
.num_crtc
) {
343 /* Disable VGA mode */
344 WREG32(mmD1VGA_CONTROL
,
345 (d1vga_control
& ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK
|
346 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK
)));
347 WREG32(mmD2VGA_CONTROL
,
348 (d2vga_control
& ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK
|
349 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK
)));
350 WREG32(mmVGA_RENDER_CONTROL
,
351 (vga_render_control
& ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK
));
353 WREG32_SMC(ixROM_CNTL
, rom_cntl
| ROM_CNTL__SCK_OVERWRITE_MASK
);
355 r
= amdgpu_read_bios(adev
);
358 WREG32(mmBUS_CNTL
, bus_cntl
);
359 if (adev
->mode_info
.num_crtc
) {
360 WREG32(mmD1VGA_CONTROL
, d1vga_control
);
361 WREG32(mmD2VGA_CONTROL
, d2vga_control
);
362 WREG32(mmVGA_RENDER_CONTROL
, vga_render_control
);
364 WREG32_SMC(ixROM_CNTL
, rom_cntl
);
367 static struct amdgpu_allowed_register_entry tonga_allowed_read_registers
[] = {
368 {mmGB_MACROTILE_MODE7
, true},
371 static struct amdgpu_allowed_register_entry cz_allowed_read_registers
[] = {
372 {mmGB_TILE_MODE7
, true},
373 {mmGB_TILE_MODE12
, true},
374 {mmGB_TILE_MODE17
, true},
375 {mmGB_TILE_MODE23
, true},
376 {mmGB_MACROTILE_MODE7
, true},
379 static struct amdgpu_allowed_register_entry vi_allowed_read_registers
[] = {
380 {mmGRBM_STATUS
, false},
381 {mmGRBM_STATUS2
, false},
382 {mmGRBM_STATUS_SE0
, false},
383 {mmGRBM_STATUS_SE1
, false},
384 {mmGRBM_STATUS_SE2
, false},
385 {mmGRBM_STATUS_SE3
, false},
386 {mmSRBM_STATUS
, false},
387 {mmSRBM_STATUS2
, false},
388 {mmSRBM_STATUS3
, false},
389 {mmSDMA0_STATUS_REG
+ SDMA0_REGISTER_OFFSET
, false},
390 {mmSDMA0_STATUS_REG
+ SDMA1_REGISTER_OFFSET
, false},
392 {mmCP_STALLED_STAT1
, false},
393 {mmCP_STALLED_STAT2
, false},
394 {mmCP_STALLED_STAT3
, false},
395 {mmCP_CPF_BUSY_STAT
, false},
396 {mmCP_CPF_STALLED_STAT1
, false},
397 {mmCP_CPF_STATUS
, false},
398 {mmCP_CPC_BUSY_STAT
, false},
399 {mmCP_CPC_STALLED_STAT1
, false},
400 {mmCP_CPC_STATUS
, false},
401 {mmGB_ADDR_CONFIG
, false},
402 {mmMC_ARB_RAMCFG
, false},
403 {mmGB_TILE_MODE0
, false},
404 {mmGB_TILE_MODE1
, false},
405 {mmGB_TILE_MODE2
, false},
406 {mmGB_TILE_MODE3
, false},
407 {mmGB_TILE_MODE4
, false},
408 {mmGB_TILE_MODE5
, false},
409 {mmGB_TILE_MODE6
, false},
410 {mmGB_TILE_MODE7
, false},
411 {mmGB_TILE_MODE8
, false},
412 {mmGB_TILE_MODE9
, false},
413 {mmGB_TILE_MODE10
, false},
414 {mmGB_TILE_MODE11
, false},
415 {mmGB_TILE_MODE12
, false},
416 {mmGB_TILE_MODE13
, false},
417 {mmGB_TILE_MODE14
, false},
418 {mmGB_TILE_MODE15
, false},
419 {mmGB_TILE_MODE16
, false},
420 {mmGB_TILE_MODE17
, false},
421 {mmGB_TILE_MODE18
, false},
422 {mmGB_TILE_MODE19
, false},
423 {mmGB_TILE_MODE20
, false},
424 {mmGB_TILE_MODE21
, false},
425 {mmGB_TILE_MODE22
, false},
426 {mmGB_TILE_MODE23
, false},
427 {mmGB_TILE_MODE24
, false},
428 {mmGB_TILE_MODE25
, false},
429 {mmGB_TILE_MODE26
, false},
430 {mmGB_TILE_MODE27
, false},
431 {mmGB_TILE_MODE28
, false},
432 {mmGB_TILE_MODE29
, false},
433 {mmGB_TILE_MODE30
, false},
434 {mmGB_TILE_MODE31
, false},
435 {mmGB_MACROTILE_MODE0
, false},
436 {mmGB_MACROTILE_MODE1
, false},
437 {mmGB_MACROTILE_MODE2
, false},
438 {mmGB_MACROTILE_MODE3
, false},
439 {mmGB_MACROTILE_MODE4
, false},
440 {mmGB_MACROTILE_MODE5
, false},
441 {mmGB_MACROTILE_MODE6
, false},
442 {mmGB_MACROTILE_MODE7
, false},
443 {mmGB_MACROTILE_MODE8
, false},
444 {mmGB_MACROTILE_MODE9
, false},
445 {mmGB_MACROTILE_MODE10
, false},
446 {mmGB_MACROTILE_MODE11
, false},
447 {mmGB_MACROTILE_MODE12
, false},
448 {mmGB_MACROTILE_MODE13
, false},
449 {mmGB_MACROTILE_MODE14
, false},
450 {mmGB_MACROTILE_MODE15
, false},
451 {mmCC_RB_BACKEND_DISABLE
, false, true},
452 {mmGC_USER_RB_BACKEND_DISABLE
, false, true},
453 {mmGB_BACKEND_MAP
, false, false},
454 {mmPA_SC_RASTER_CONFIG
, false, true},
455 {mmPA_SC_RASTER_CONFIG_1
, false, true},
458 static uint32_t vi_read_indexed_register(struct amdgpu_device
*adev
, u32 se_num
,
459 u32 sh_num
, u32 reg_offset
)
463 mutex_lock(&adev
->grbm_idx_mutex
);
464 if (se_num
!= 0xffffffff || sh_num
!= 0xffffffff)
465 gfx_v8_0_select_se_sh(adev
, se_num
, sh_num
);
467 val
= RREG32(reg_offset
);
469 if (se_num
!= 0xffffffff || sh_num
!= 0xffffffff)
470 gfx_v8_0_select_se_sh(adev
, 0xffffffff, 0xffffffff);
471 mutex_unlock(&adev
->grbm_idx_mutex
);
475 static int vi_read_register(struct amdgpu_device
*adev
, u32 se_num
,
476 u32 sh_num
, u32 reg_offset
, u32
*value
)
478 struct amdgpu_allowed_register_entry
*asic_register_table
= NULL
;
479 struct amdgpu_allowed_register_entry
*asic_register_entry
;
483 switch (adev
->asic_type
) {
485 asic_register_table
= tonga_allowed_read_registers
;
486 size
= ARRAY_SIZE(tonga_allowed_read_registers
);
491 asic_register_table
= cz_allowed_read_registers
;
492 size
= ARRAY_SIZE(cz_allowed_read_registers
);
498 if (asic_register_table
) {
499 for (i
= 0; i
< size
; i
++) {
500 asic_register_entry
= asic_register_table
+ i
;
501 if (reg_offset
!= asic_register_entry
->reg_offset
)
503 if (!asic_register_entry
->untouched
)
504 *value
= asic_register_entry
->grbm_indexed
?
505 vi_read_indexed_register(adev
, se_num
,
506 sh_num
, reg_offset
) :
512 for (i
= 0; i
< ARRAY_SIZE(vi_allowed_read_registers
); i
++) {
513 if (reg_offset
!= vi_allowed_read_registers
[i
].reg_offset
)
516 if (!vi_allowed_read_registers
[i
].untouched
)
517 *value
= vi_allowed_read_registers
[i
].grbm_indexed
?
518 vi_read_indexed_register(adev
, se_num
,
519 sh_num
, reg_offset
) :
526 static void vi_print_gpu_status_regs(struct amdgpu_device
*adev
)
528 dev_info(adev
->dev
, " GRBM_STATUS=0x%08X\n",
529 RREG32(mmGRBM_STATUS
));
530 dev_info(adev
->dev
, " GRBM_STATUS2=0x%08X\n",
531 RREG32(mmGRBM_STATUS2
));
532 dev_info(adev
->dev
, " GRBM_STATUS_SE0=0x%08X\n",
533 RREG32(mmGRBM_STATUS_SE0
));
534 dev_info(adev
->dev
, " GRBM_STATUS_SE1=0x%08X\n",
535 RREG32(mmGRBM_STATUS_SE1
));
536 dev_info(adev
->dev
, " GRBM_STATUS_SE2=0x%08X\n",
537 RREG32(mmGRBM_STATUS_SE2
));
538 dev_info(adev
->dev
, " GRBM_STATUS_SE3=0x%08X\n",
539 RREG32(mmGRBM_STATUS_SE3
));
540 dev_info(adev
->dev
, " SRBM_STATUS=0x%08X\n",
541 RREG32(mmSRBM_STATUS
));
542 dev_info(adev
->dev
, " SRBM_STATUS2=0x%08X\n",
543 RREG32(mmSRBM_STATUS2
));
544 dev_info(adev
->dev
, " SDMA0_STATUS_REG = 0x%08X\n",
545 RREG32(mmSDMA0_STATUS_REG
+ SDMA0_REGISTER_OFFSET
));
546 dev_info(adev
->dev
, " SDMA1_STATUS_REG = 0x%08X\n",
547 RREG32(mmSDMA0_STATUS_REG
+ SDMA1_REGISTER_OFFSET
));
548 dev_info(adev
->dev
, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT
));
549 dev_info(adev
->dev
, " CP_STALLED_STAT1 = 0x%08x\n",
550 RREG32(mmCP_STALLED_STAT1
));
551 dev_info(adev
->dev
, " CP_STALLED_STAT2 = 0x%08x\n",
552 RREG32(mmCP_STALLED_STAT2
));
553 dev_info(adev
->dev
, " CP_STALLED_STAT3 = 0x%08x\n",
554 RREG32(mmCP_STALLED_STAT3
));
555 dev_info(adev
->dev
, " CP_CPF_BUSY_STAT = 0x%08x\n",
556 RREG32(mmCP_CPF_BUSY_STAT
));
557 dev_info(adev
->dev
, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
558 RREG32(mmCP_CPF_STALLED_STAT1
));
559 dev_info(adev
->dev
, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS
));
560 dev_info(adev
->dev
, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT
));
561 dev_info(adev
->dev
, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
562 RREG32(mmCP_CPC_STALLED_STAT1
));
563 dev_info(adev
->dev
, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS
));
567 * vi_gpu_check_soft_reset - check which blocks are busy
569 * @adev: amdgpu_device pointer
571 * Check which blocks are busy and return the relevant reset
572 * mask to be used by vi_gpu_soft_reset().
573 * Returns a mask of the blocks to be reset.
575 u32
vi_gpu_check_soft_reset(struct amdgpu_device
*adev
)
581 tmp
= RREG32(mmGRBM_STATUS
);
582 if (tmp
& (GRBM_STATUS__PA_BUSY_MASK
| GRBM_STATUS__SC_BUSY_MASK
|
583 GRBM_STATUS__BCI_BUSY_MASK
| GRBM_STATUS__SX_BUSY_MASK
|
584 GRBM_STATUS__TA_BUSY_MASK
| GRBM_STATUS__VGT_BUSY_MASK
|
585 GRBM_STATUS__DB_BUSY_MASK
| GRBM_STATUS__CB_BUSY_MASK
|
586 GRBM_STATUS__GDS_BUSY_MASK
| GRBM_STATUS__SPI_BUSY_MASK
|
587 GRBM_STATUS__IA_BUSY_MASK
| GRBM_STATUS__IA_BUSY_NO_DMA_MASK
))
588 reset_mask
|= AMDGPU_RESET_GFX
;
590 if (tmp
& (GRBM_STATUS__CP_BUSY_MASK
| GRBM_STATUS__CP_COHERENCY_BUSY_MASK
))
591 reset_mask
|= AMDGPU_RESET_CP
;
594 tmp
= RREG32(mmGRBM_STATUS2
);
595 if (tmp
& GRBM_STATUS2__RLC_BUSY_MASK
)
596 reset_mask
|= AMDGPU_RESET_RLC
;
598 if (tmp
& (GRBM_STATUS2__CPF_BUSY_MASK
|
599 GRBM_STATUS2__CPC_BUSY_MASK
|
600 GRBM_STATUS2__CPG_BUSY_MASK
))
601 reset_mask
|= AMDGPU_RESET_CP
;
604 tmp
= RREG32(mmSRBM_STATUS2
);
605 if (tmp
& SRBM_STATUS2__SDMA_BUSY_MASK
)
606 reset_mask
|= AMDGPU_RESET_DMA
;
608 if (tmp
& SRBM_STATUS2__SDMA1_BUSY_MASK
)
609 reset_mask
|= AMDGPU_RESET_DMA1
;
612 tmp
= RREG32(mmSRBM_STATUS
);
614 if (tmp
& SRBM_STATUS__IH_BUSY_MASK
)
615 reset_mask
|= AMDGPU_RESET_IH
;
617 if (tmp
& SRBM_STATUS__SEM_BUSY_MASK
)
618 reset_mask
|= AMDGPU_RESET_SEM
;
620 if (tmp
& SRBM_STATUS__GRBM_RQ_PENDING_MASK
)
621 reset_mask
|= AMDGPU_RESET_GRBM
;
623 if (adev
->asic_type
!= CHIP_TOPAZ
) {
624 if (tmp
& (SRBM_STATUS__UVD_RQ_PENDING_MASK
|
625 SRBM_STATUS__UVD_BUSY_MASK
))
626 reset_mask
|= AMDGPU_RESET_UVD
;
629 if (tmp
& SRBM_STATUS__VMC_BUSY_MASK
)
630 reset_mask
|= AMDGPU_RESET_VMC
;
632 if (tmp
& (SRBM_STATUS__MCB_BUSY_MASK
| SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK
|
633 SRBM_STATUS__MCC_BUSY_MASK
| SRBM_STATUS__MCD_BUSY_MASK
))
634 reset_mask
|= AMDGPU_RESET_MC
;
636 /* SDMA0_STATUS_REG */
637 tmp
= RREG32(mmSDMA0_STATUS_REG
+ SDMA0_REGISTER_OFFSET
);
638 if (!(tmp
& SDMA0_STATUS_REG__IDLE_MASK
))
639 reset_mask
|= AMDGPU_RESET_DMA
;
641 /* SDMA1_STATUS_REG */
642 tmp
= RREG32(mmSDMA0_STATUS_REG
+ SDMA1_REGISTER_OFFSET
);
643 if (!(tmp
& SDMA0_STATUS_REG__IDLE_MASK
))
644 reset_mask
|= AMDGPU_RESET_DMA1
;
647 if (adev
->asic_type
!= CHIP_TOPAZ
) {
648 tmp
= RREG32(mmVCE_STATUS
);
649 if (tmp
& VCE_STATUS__VCPU_REPORT_RB0_BUSY_MASK
)
650 reset_mask
|= AMDGPU_RESET_VCE
;
651 if (tmp
& VCE_STATUS__VCPU_REPORT_RB1_BUSY_MASK
)
652 reset_mask
|= AMDGPU_RESET_VCE1
;
656 if (adev
->asic_type
!= CHIP_TOPAZ
) {
657 if (amdgpu_display_is_display_hung(adev
))
658 reset_mask
|= AMDGPU_RESET_DISPLAY
;
662 /* Skip MC reset as it's mostly likely not hung, just busy */
663 if (reset_mask
& AMDGPU_RESET_MC
) {
664 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask
);
665 reset_mask
&= ~AMDGPU_RESET_MC
;
672 * vi_gpu_soft_reset - soft reset GPU
674 * @adev: amdgpu_device pointer
675 * @reset_mask: mask of which blocks to reset
677 * Soft reset the blocks specified in @reset_mask.
679 static void vi_gpu_soft_reset(struct amdgpu_device
*adev
, u32 reset_mask
)
681 struct amdgpu_mode_mc_save save
;
682 u32 grbm_soft_reset
= 0, srbm_soft_reset
= 0;
688 dev_info(adev
->dev
, "GPU softreset: 0x%08X\n", reset_mask
);
690 vi_print_gpu_status_regs(adev
);
691 dev_info(adev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
692 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR
));
693 dev_info(adev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
694 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS
));
700 //gfx_v8_0_rlc_stop(adev);
702 /* Disable GFX parsing/prefetching */
703 tmp
= RREG32(mmCP_ME_CNTL
);
704 tmp
= REG_SET_FIELD(tmp
, CP_ME_CNTL
, ME_HALT
, 1);
705 tmp
= REG_SET_FIELD(tmp
, CP_ME_CNTL
, PFP_HALT
, 1);
706 tmp
= REG_SET_FIELD(tmp
, CP_ME_CNTL
, CE_HALT
, 1);
707 WREG32(mmCP_ME_CNTL
, tmp
);
709 /* Disable MEC parsing/prefetching */
710 tmp
= RREG32(mmCP_MEC_CNTL
);
711 tmp
= REG_SET_FIELD(tmp
, CP_MEC_CNTL
, MEC_ME1_HALT
, 1);
712 tmp
= REG_SET_FIELD(tmp
, CP_MEC_CNTL
, MEC_ME2_HALT
, 1);
713 WREG32(mmCP_MEC_CNTL
, tmp
);
715 if (reset_mask
& AMDGPU_RESET_DMA
) {
717 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
);
718 tmp
= REG_SET_FIELD(tmp
, SDMA0_F32_CNTL
, HALT
, 1);
719 WREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
, tmp
);
721 if (reset_mask
& AMDGPU_RESET_DMA1
) {
723 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
);
724 tmp
= REG_SET_FIELD(tmp
, SDMA0_F32_CNTL
, HALT
, 1);
725 WREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
, tmp
);
728 gmc_v8_0_mc_stop(adev
, &save
);
729 if (amdgpu_asic_wait_for_mc_idle(adev
)) {
730 dev_warn(adev
->dev
, "Wait for MC idle timedout !\n");
733 if (reset_mask
& (AMDGPU_RESET_GFX
| AMDGPU_RESET_COMPUTE
| AMDGPU_RESET_CP
)) {
735 REG_SET_FIELD(grbm_soft_reset
, GRBM_SOFT_RESET
, SOFT_RESET_CP
, 1);
737 REG_SET_FIELD(grbm_soft_reset
, GRBM_SOFT_RESET
, SOFT_RESET_GFX
, 1);
740 if (reset_mask
& AMDGPU_RESET_CP
) {
742 REG_SET_FIELD(grbm_soft_reset
, GRBM_SOFT_RESET
, SOFT_RESET_CP
, 1);
744 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_GRBM
, 1);
747 if (reset_mask
& AMDGPU_RESET_DMA
)
749 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_SDMA
, 1);
751 if (reset_mask
& AMDGPU_RESET_DMA1
)
753 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_SDMA1
, 1);
755 if (reset_mask
& AMDGPU_RESET_DISPLAY
)
757 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_DC
, 1);
759 if (reset_mask
& AMDGPU_RESET_RLC
)
761 REG_SET_FIELD(grbm_soft_reset
, GRBM_SOFT_RESET
, SOFT_RESET_RLC
, 1);
763 if (reset_mask
& AMDGPU_RESET_SEM
)
765 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_SEM
, 1);
767 if (reset_mask
& AMDGPU_RESET_IH
)
769 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_IH
, 1);
771 if (reset_mask
& AMDGPU_RESET_GRBM
)
773 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_GRBM
, 1);
775 if (reset_mask
& AMDGPU_RESET_VMC
)
777 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_VMC
, 1);
779 if (reset_mask
& AMDGPU_RESET_UVD
)
781 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_UVD
, 1);
783 if (reset_mask
& AMDGPU_RESET_VCE
)
785 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_VCE0
, 1);
787 if (reset_mask
& AMDGPU_RESET_VCE
)
789 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_VCE1
, 1);
791 if (!(adev
->flags
& AMD_IS_APU
)) {
792 if (reset_mask
& AMDGPU_RESET_MC
)
794 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_MC
, 1);
797 if (grbm_soft_reset
) {
798 tmp
= RREG32(mmGRBM_SOFT_RESET
);
799 tmp
|= grbm_soft_reset
;
800 dev_info(adev
->dev
, "GRBM_SOFT_RESET=0x%08X\n", tmp
);
801 WREG32(mmGRBM_SOFT_RESET
, tmp
);
802 tmp
= RREG32(mmGRBM_SOFT_RESET
);
806 tmp
&= ~grbm_soft_reset
;
807 WREG32(mmGRBM_SOFT_RESET
, tmp
);
808 tmp
= RREG32(mmGRBM_SOFT_RESET
);
811 if (srbm_soft_reset
) {
812 tmp
= RREG32(mmSRBM_SOFT_RESET
);
813 tmp
|= srbm_soft_reset
;
814 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
815 WREG32(mmSRBM_SOFT_RESET
, tmp
);
816 tmp
= RREG32(mmSRBM_SOFT_RESET
);
820 tmp
&= ~srbm_soft_reset
;
821 WREG32(mmSRBM_SOFT_RESET
, tmp
);
822 tmp
= RREG32(mmSRBM_SOFT_RESET
);
825 /* Wait a little for things to settle down */
828 gmc_v8_0_mc_resume(adev
, &save
);
831 vi_print_gpu_status_regs(adev
);
834 static void vi_gpu_pci_config_reset(struct amdgpu_device
*adev
)
836 struct amdgpu_mode_mc_save save
;
839 dev_info(adev
->dev
, "GPU pci config reset\n");
845 /* Disable GFX parsing/prefetching */
846 tmp
= RREG32(mmCP_ME_CNTL
);
847 tmp
= REG_SET_FIELD(tmp
, CP_ME_CNTL
, ME_HALT
, 1);
848 tmp
= REG_SET_FIELD(tmp
, CP_ME_CNTL
, PFP_HALT
, 1);
849 tmp
= REG_SET_FIELD(tmp
, CP_ME_CNTL
, CE_HALT
, 1);
850 WREG32(mmCP_ME_CNTL
, tmp
);
852 /* Disable MEC parsing/prefetching */
853 tmp
= RREG32(mmCP_MEC_CNTL
);
854 tmp
= REG_SET_FIELD(tmp
, CP_MEC_CNTL
, MEC_ME1_HALT
, 1);
855 tmp
= REG_SET_FIELD(tmp
, CP_MEC_CNTL
, MEC_ME2_HALT
, 1);
856 WREG32(mmCP_MEC_CNTL
, tmp
);
858 /* Disable GFX parsing/prefetching */
859 WREG32(mmCP_ME_CNTL
, CP_ME_CNTL__ME_HALT_MASK
|
860 CP_ME_CNTL__PFP_HALT_MASK
| CP_ME_CNTL__CE_HALT_MASK
);
862 /* Disable MEC parsing/prefetching */
863 WREG32(mmCP_MEC_CNTL
,
864 CP_MEC_CNTL__MEC_ME1_HALT_MASK
| CP_MEC_CNTL__MEC_ME2_HALT_MASK
);
867 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
);
868 tmp
= REG_SET_FIELD(tmp
, SDMA0_F32_CNTL
, HALT
, 1);
869 WREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
, tmp
);
872 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
);
873 tmp
= REG_SET_FIELD(tmp
, SDMA0_F32_CNTL
, HALT
, 1);
874 WREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
, tmp
);
876 /* XXX other engines? */
878 /* halt the rlc, disable cp internal ints */
880 //gfx_v8_0_rlc_stop(adev);
884 /* disable mem access */
885 gmc_v8_0_mc_stop(adev
, &save
);
886 if (amdgpu_asic_wait_for_mc_idle(adev
)) {
887 dev_warn(adev
->dev
, "Wait for MC idle timed out !\n");
891 pci_clear_master(adev
->pdev
);
893 amdgpu_pci_config_reset(adev
);
897 /* wait for asic to come out of reset */
898 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
899 if (RREG32(mmCONFIG_MEMSIZE
) != 0xffffffff)
906 static void vi_set_bios_scratch_engine_hung(struct amdgpu_device
*adev
, bool hung
)
908 u32 tmp
= RREG32(mmBIOS_SCRATCH_3
);
911 tmp
|= ATOM_S3_ASIC_GUI_ENGINE_HUNG
;
913 tmp
&= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG
;
915 WREG32(mmBIOS_SCRATCH_3
, tmp
);
919 * vi_asic_reset - soft reset GPU
921 * @adev: amdgpu_device pointer
923 * Look up which blocks are hung and attempt
925 * Returns 0 for success.
927 static int vi_asic_reset(struct amdgpu_device
*adev
)
931 reset_mask
= vi_gpu_check_soft_reset(adev
);
934 vi_set_bios_scratch_engine_hung(adev
, true);
937 vi_gpu_soft_reset(adev
, reset_mask
);
939 reset_mask
= vi_gpu_check_soft_reset(adev
);
941 /* try pci config reset */
942 if (reset_mask
&& amdgpu_hard_reset
)
943 vi_gpu_pci_config_reset(adev
);
945 reset_mask
= vi_gpu_check_soft_reset(adev
);
948 vi_set_bios_scratch_engine_hung(adev
, false);
953 static int vi_set_uvd_clock(struct amdgpu_device
*adev
, u32 clock
,
954 u32 cntl_reg
, u32 status_reg
)
957 struct atom_clock_dividers dividers
;
960 r
= amdgpu_atombios_get_clock_dividers(adev
,
961 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK
,
962 clock
, false, ÷rs
);
966 tmp
= RREG32_SMC(cntl_reg
);
967 tmp
&= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK
|
968 CG_DCLK_CNTL__DCLK_DIVIDER_MASK
);
969 tmp
|= dividers
.post_divider
;
970 WREG32_SMC(cntl_reg
, tmp
);
972 for (i
= 0; i
< 100; i
++) {
973 if (RREG32_SMC(status_reg
) & CG_DCLK_STATUS__DCLK_STATUS_MASK
)
983 static int vi_set_uvd_clocks(struct amdgpu_device
*adev
, u32 vclk
, u32 dclk
)
987 r
= vi_set_uvd_clock(adev
, vclk
, ixCG_VCLK_CNTL
, ixCG_VCLK_STATUS
);
991 r
= vi_set_uvd_clock(adev
, dclk
, ixCG_DCLK_CNTL
, ixCG_DCLK_STATUS
);
996 static int vi_set_vce_clocks(struct amdgpu_device
*adev
, u32 evclk
, u32 ecclk
)
1003 static void vi_pcie_gen3_enable(struct amdgpu_device
*adev
)
1008 if (amdgpu_pcie_gen2
== 0)
1011 if (adev
->flags
& AMD_IS_APU
)
1014 ret
= drm_pcie_get_speed_cap_mask(adev
->ddev
, &mask
);
1018 if (!(mask
& (DRM_PCIE_SPEED_50
| DRM_PCIE_SPEED_80
)))
1024 static void vi_program_aspm(struct amdgpu_device
*adev
)
1027 if (amdgpu_aspm
== 0)
1033 static void vi_enable_doorbell_aperture(struct amdgpu_device
*adev
,
1038 /* not necessary on CZ */
1039 if (adev
->flags
& AMD_IS_APU
)
1042 tmp
= RREG32(mmBIF_DOORBELL_APER_EN
);
1044 tmp
= REG_SET_FIELD(tmp
, BIF_DOORBELL_APER_EN
, BIF_DOORBELL_APER_EN
, 1);
1046 tmp
= REG_SET_FIELD(tmp
, BIF_DOORBELL_APER_EN
, BIF_DOORBELL_APER_EN
, 0);
1048 WREG32(mmBIF_DOORBELL_APER_EN
, tmp
);
1051 /* topaz has no DCE, UVD, VCE */
1052 static const struct amdgpu_ip_block_version topaz_ip_blocks
[] =
1054 /* ORDER MATTERS! */
1056 .type
= AMD_IP_BLOCK_TYPE_COMMON
,
1060 .funcs
= &vi_common_ip_funcs
,
1063 .type
= AMD_IP_BLOCK_TYPE_GMC
,
1067 .funcs
= &gmc_v8_0_ip_funcs
,
1070 .type
= AMD_IP_BLOCK_TYPE_IH
,
1074 .funcs
= &iceland_ih_ip_funcs
,
1077 .type
= AMD_IP_BLOCK_TYPE_SMC
,
1081 .funcs
= &iceland_dpm_ip_funcs
,
1084 .type
= AMD_IP_BLOCK_TYPE_GFX
,
1088 .funcs
= &gfx_v8_0_ip_funcs
,
1091 .type
= AMD_IP_BLOCK_TYPE_SDMA
,
1095 .funcs
= &sdma_v2_4_ip_funcs
,
1099 static const struct amdgpu_ip_block_version tonga_ip_blocks
[] =
1101 /* ORDER MATTERS! */
1103 .type
= AMD_IP_BLOCK_TYPE_COMMON
,
1107 .funcs
= &vi_common_ip_funcs
,
1110 .type
= AMD_IP_BLOCK_TYPE_GMC
,
1114 .funcs
= &gmc_v8_0_ip_funcs
,
1117 .type
= AMD_IP_BLOCK_TYPE_IH
,
1121 .funcs
= &tonga_ih_ip_funcs
,
1124 .type
= AMD_IP_BLOCK_TYPE_SMC
,
1128 .funcs
= &tonga_dpm_ip_funcs
,
1131 .type
= AMD_IP_BLOCK_TYPE_DCE
,
1135 .funcs
= &dce_v10_0_ip_funcs
,
1138 .type
= AMD_IP_BLOCK_TYPE_GFX
,
1142 .funcs
= &gfx_v8_0_ip_funcs
,
1145 .type
= AMD_IP_BLOCK_TYPE_SDMA
,
1149 .funcs
= &sdma_v3_0_ip_funcs
,
1152 .type
= AMD_IP_BLOCK_TYPE_UVD
,
1156 .funcs
= &uvd_v5_0_ip_funcs
,
1159 .type
= AMD_IP_BLOCK_TYPE_VCE
,
1163 .funcs
= &vce_v3_0_ip_funcs
,
1167 static const struct amdgpu_ip_block_version fiji_ip_blocks
[] =
1169 /* ORDER MATTERS! */
1171 .type
= AMD_IP_BLOCK_TYPE_COMMON
,
1175 .funcs
= &vi_common_ip_funcs
,
1178 .type
= AMD_IP_BLOCK_TYPE_GMC
,
1182 .funcs
= &gmc_v8_0_ip_funcs
,
1185 .type
= AMD_IP_BLOCK_TYPE_IH
,
1189 .funcs
= &tonga_ih_ip_funcs
,
1192 .type
= AMD_IP_BLOCK_TYPE_SMC
,
1196 .funcs
= &fiji_dpm_ip_funcs
,
1200 static const struct amdgpu_ip_block_version cz_ip_blocks
[] =
1202 /* ORDER MATTERS! */
1204 .type
= AMD_IP_BLOCK_TYPE_COMMON
,
1208 .funcs
= &vi_common_ip_funcs
,
1211 .type
= AMD_IP_BLOCK_TYPE_GMC
,
1215 .funcs
= &gmc_v8_0_ip_funcs
,
1218 .type
= AMD_IP_BLOCK_TYPE_IH
,
1222 .funcs
= &cz_ih_ip_funcs
,
1225 .type
= AMD_IP_BLOCK_TYPE_SMC
,
1229 .funcs
= &cz_dpm_ip_funcs
,
1232 .type
= AMD_IP_BLOCK_TYPE_DCE
,
1236 .funcs
= &dce_v11_0_ip_funcs
,
1239 .type
= AMD_IP_BLOCK_TYPE_GFX
,
1243 .funcs
= &gfx_v8_0_ip_funcs
,
1246 .type
= AMD_IP_BLOCK_TYPE_SDMA
,
1250 .funcs
= &sdma_v3_0_ip_funcs
,
1253 .type
= AMD_IP_BLOCK_TYPE_UVD
,
1257 .funcs
= &uvd_v6_0_ip_funcs
,
1260 .type
= AMD_IP_BLOCK_TYPE_VCE
,
1264 .funcs
= &vce_v3_0_ip_funcs
,
1268 int vi_set_ip_blocks(struct amdgpu_device
*adev
)
1270 switch (adev
->asic_type
) {
1272 adev
->ip_blocks
= topaz_ip_blocks
;
1273 adev
->num_ip_blocks
= ARRAY_SIZE(topaz_ip_blocks
);
1276 adev
->ip_blocks
= fiji_ip_blocks
;
1277 adev
->num_ip_blocks
= ARRAY_SIZE(fiji_ip_blocks
);
1280 adev
->ip_blocks
= tonga_ip_blocks
;
1281 adev
->num_ip_blocks
= ARRAY_SIZE(tonga_ip_blocks
);
1284 adev
->ip_blocks
= cz_ip_blocks
;
1285 adev
->num_ip_blocks
= ARRAY_SIZE(cz_ip_blocks
);
1288 /* FIXME: not supported yet */
1295 static uint32_t vi_get_rev_id(struct amdgpu_device
*adev
)
1297 if (adev
->asic_type
== CHIP_TOPAZ
)
1298 return (RREG32(mmPCIE_EFUSE4
) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK
)
1299 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT
;
1301 return (RREG32(mmCC_DRM_ID_STRAPS
) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK
)
1302 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT
;
1305 static const struct amdgpu_asic_funcs vi_asic_funcs
=
1307 .read_disabled_bios
= &vi_read_disabled_bios
,
1308 .read_register
= &vi_read_register
,
1309 .reset
= &vi_asic_reset
,
1310 .set_vga_state
= &vi_vga_set_state
,
1311 .get_xclk
= &vi_get_xclk
,
1312 .set_uvd_clocks
= &vi_set_uvd_clocks
,
1313 .set_vce_clocks
= &vi_set_vce_clocks
,
1314 .get_cu_info
= &gfx_v8_0_get_cu_info
,
1315 /* these should be moved to their own ip modules */
1316 .get_gpu_clock_counter
= &gfx_v8_0_get_gpu_clock_counter
,
1317 .wait_for_mc_idle
= &gmc_v8_0_mc_wait_for_idle
,
1320 static int vi_common_early_init(void *handle
)
1322 bool smc_enabled
= false;
1323 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1325 if (adev
->flags
& AMD_IS_APU
) {
1326 adev
->smc_rreg
= &cz_smc_rreg
;
1327 adev
->smc_wreg
= &cz_smc_wreg
;
1329 adev
->smc_rreg
= &vi_smc_rreg
;
1330 adev
->smc_wreg
= &vi_smc_wreg
;
1332 adev
->pcie_rreg
= &vi_pcie_rreg
;
1333 adev
->pcie_wreg
= &vi_pcie_wreg
;
1334 adev
->uvd_ctx_rreg
= &vi_uvd_ctx_rreg
;
1335 adev
->uvd_ctx_wreg
= &vi_uvd_ctx_wreg
;
1336 adev
->didt_rreg
= &vi_didt_rreg
;
1337 adev
->didt_wreg
= &vi_didt_wreg
;
1339 adev
->asic_funcs
= &vi_asic_funcs
;
1341 if (amdgpu_get_ip_block(adev
, AMD_IP_BLOCK_TYPE_SMC
) &&
1342 (amdgpu_ip_block_mask
& (1 << AMD_IP_BLOCK_TYPE_SMC
)))
1345 adev
->rev_id
= vi_get_rev_id(adev
);
1346 adev
->external_rev_id
= 0xFF;
1347 switch (adev
->asic_type
) {
1349 adev
->has_uvd
= false;
1352 adev
->external_rev_id
= 0x1;
1353 if (amdgpu_smc_load_fw
&& smc_enabled
)
1354 adev
->firmware
.smu_load
= true;
1358 adev
->has_uvd
= true;
1361 adev
->external_rev_id
= adev
->rev_id
+ 0x14;
1362 if (amdgpu_smc_load_fw
&& smc_enabled
)
1363 adev
->firmware
.smu_load
= true;
1366 adev
->has_uvd
= true;
1368 adev
->pg_flags
= AMDGPU_PG_SUPPORT_UVD
| AMDGPU_PG_SUPPORT_VCE
;
1369 adev
->external_rev_id
= adev
->rev_id
+ 0x1;
1370 if (amdgpu_smc_load_fw
&& smc_enabled
)
1371 adev
->firmware
.smu_load
= true;
1374 /* FIXME: not supported yet */
1381 static int vi_common_sw_init(void *handle
)
1386 static int vi_common_sw_fini(void *handle
)
1391 static int vi_common_hw_init(void *handle
)
1393 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1395 /* move the golden regs per IP block */
1396 vi_init_golden_registers(adev
);
1397 /* enable pcie gen2/3 link */
1398 vi_pcie_gen3_enable(adev
);
1400 vi_program_aspm(adev
);
1401 /* enable the doorbell aperture */
1402 vi_enable_doorbell_aperture(adev
, true);
1407 static int vi_common_hw_fini(void *handle
)
1409 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1411 /* enable the doorbell aperture */
1412 vi_enable_doorbell_aperture(adev
, false);
1417 static int vi_common_suspend(void *handle
)
1419 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1421 return vi_common_hw_fini(adev
);
1424 static int vi_common_resume(void *handle
)
1426 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1428 return vi_common_hw_init(adev
);
1431 static bool vi_common_is_idle(void *handle
)
1436 static int vi_common_wait_for_idle(void *handle
)
1441 static void vi_common_print_status(void *handle
)
1446 static int vi_common_soft_reset(void *handle
)
1451 static int vi_common_set_clockgating_state(void *handle
,
1452 enum amd_clockgating_state state
)
1457 static int vi_common_set_powergating_state(void *handle
,
1458 enum amd_powergating_state state
)
1463 const struct amd_ip_funcs vi_common_ip_funcs
= {
1464 .early_init
= vi_common_early_init
,
1466 .sw_init
= vi_common_sw_init
,
1467 .sw_fini
= vi_common_sw_fini
,
1468 .hw_init
= vi_common_hw_init
,
1469 .hw_fini
= vi_common_hw_fini
,
1470 .suspend
= vi_common_suspend
,
1471 .resume
= vi_common_resume
,
1472 .is_idle
= vi_common_is_idle
,
1473 .wait_for_idle
= vi_common_wait_for_idle
,
1474 .soft_reset
= vi_common_soft_reset
,
1475 .print_status
= vi_common_print_status
,
1476 .set_clockgating_state
= vi_common_set_clockgating_state
,
1477 .set_powergating_state
= vi_common_set_powergating_state
,