2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
28 #include "amdgpu_atombios.h"
29 #include "amdgpu_ih.h"
30 #include "amdgpu_uvd.h"
31 #include "amdgpu_vce.h"
32 #include "amdgpu_ucode.h"
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
38 #include "oss/oss_3_0_d.h"
39 #include "oss/oss_3_0_sh_mask.h"
41 #include "bif/bif_5_0_d.h"
42 #include "bif/bif_5_0_sh_mask.h"
44 #include "gca/gfx_8_0_d.h"
45 #include "gca/gfx_8_0_sh_mask.h"
47 #include "smu/smu_7_1_1_d.h"
48 #include "smu/smu_7_1_1_sh_mask.h"
50 #include "uvd/uvd_5_0_d.h"
51 #include "uvd/uvd_5_0_sh_mask.h"
53 #include "vce/vce_3_0_d.h"
54 #include "vce/vce_3_0_sh_mask.h"
56 #include "dce/dce_10_0_d.h"
57 #include "dce/dce_10_0_sh_mask.h"
64 #include "sdma_v2_4.h"
65 #include "sdma_v3_0.h"
66 #include "dce_v10_0.h"
67 #include "dce_v11_0.h"
68 #include "iceland_ih.h"
76 * Indirect registers accessor
78 static u32
vi_pcie_rreg(struct amdgpu_device
*adev
, u32 reg
)
83 spin_lock_irqsave(&adev
->pcie_idx_lock
, flags
);
84 WREG32(mmPCIE_INDEX
, reg
);
85 (void)RREG32(mmPCIE_INDEX
);
86 r
= RREG32(mmPCIE_DATA
);
87 spin_unlock_irqrestore(&adev
->pcie_idx_lock
, flags
);
91 static void vi_pcie_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
95 spin_lock_irqsave(&adev
->pcie_idx_lock
, flags
);
96 WREG32(mmPCIE_INDEX
, reg
);
97 (void)RREG32(mmPCIE_INDEX
);
98 WREG32(mmPCIE_DATA
, v
);
99 (void)RREG32(mmPCIE_DATA
);
100 spin_unlock_irqrestore(&adev
->pcie_idx_lock
, flags
);
103 static u32
vi_smc_rreg(struct amdgpu_device
*adev
, u32 reg
)
108 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
109 WREG32(mmSMC_IND_INDEX_0
, (reg
));
110 r
= RREG32(mmSMC_IND_DATA_0
);
111 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
115 static void vi_smc_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
119 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
120 WREG32(mmSMC_IND_INDEX_0
, (reg
));
121 WREG32(mmSMC_IND_DATA_0
, (v
));
122 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
125 static u32
vi_uvd_ctx_rreg(struct amdgpu_device
*adev
, u32 reg
)
130 spin_lock_irqsave(&adev
->uvd_ctx_idx_lock
, flags
);
131 WREG32(mmUVD_CTX_INDEX
, ((reg
) & 0x1ff));
132 r
= RREG32(mmUVD_CTX_DATA
);
133 spin_unlock_irqrestore(&adev
->uvd_ctx_idx_lock
, flags
);
137 static void vi_uvd_ctx_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
141 spin_lock_irqsave(&adev
->uvd_ctx_idx_lock
, flags
);
142 WREG32(mmUVD_CTX_INDEX
, ((reg
) & 0x1ff));
143 WREG32(mmUVD_CTX_DATA
, (v
));
144 spin_unlock_irqrestore(&adev
->uvd_ctx_idx_lock
, flags
);
147 static u32
vi_didt_rreg(struct amdgpu_device
*adev
, u32 reg
)
152 spin_lock_irqsave(&adev
->didt_idx_lock
, flags
);
153 WREG32(mmDIDT_IND_INDEX
, (reg
));
154 r
= RREG32(mmDIDT_IND_DATA
);
155 spin_unlock_irqrestore(&adev
->didt_idx_lock
, flags
);
159 static void vi_didt_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
163 spin_lock_irqsave(&adev
->didt_idx_lock
, flags
);
164 WREG32(mmDIDT_IND_INDEX
, (reg
));
165 WREG32(mmDIDT_IND_DATA
, (v
));
166 spin_unlock_irqrestore(&adev
->didt_idx_lock
, flags
);
169 static const u32 tonga_mgcg_cgcg_init
[] =
171 mmCGTT_DRM_CLK_CTRL0
, 0xffffffff, 0x00600100,
172 mmPCIE_INDEX
, 0xffffffff, 0x0140001c,
173 mmPCIE_DATA
, 0x000f0000, 0x00000000,
174 mmSMC_IND_INDEX_4
, 0xffffffff, 0xC060000C,
175 mmSMC_IND_DATA_4
, 0xc0000fff, 0x00000100,
176 mmXDMA_CLOCK_GATING_CNTL
, 0xffffffff, 0x00000100,
177 mmXDMA_MEM_POWER_CNTL
, 0x00000101, 0x00000000,
178 mmCGTT_DRM_CLK_CTRL0
, 0xff000fff, 0x00000100,
179 mmHDP_XDP_CGTT_BLK_CTRL
, 0xc0000fff, 0x00000104,
182 static const u32 iceland_mgcg_cgcg_init
[] =
184 mmPCIE_INDEX
, 0xffffffff, ixPCIE_CNTL2
,
185 mmPCIE_DATA
, 0x000f0000, 0x00000000,
186 mmSMC_IND_INDEX_4
, 0xffffffff, ixCGTT_ROM_CLK_CTRL0
,
187 mmSMC_IND_DATA_4
, 0xc0000fff, 0x00000100,
188 mmHDP_XDP_CGTT_BLK_CTRL
, 0xc0000fff, 0x00000104,
191 static const u32 cz_mgcg_cgcg_init
[] =
193 mmCGTT_DRM_CLK_CTRL0
, 0xffffffff, 0x00600100,
194 mmPCIE_INDEX
, 0xffffffff, 0x0140001c,
195 mmPCIE_DATA
, 0x000f0000, 0x00000000,
196 mmXDMA_CLOCK_GATING_CNTL
, 0xffffffff, 0x00000100,
197 mmXDMA_MEM_POWER_CNTL
, 0x00000101, 0x00000000,
198 mmCGTT_DRM_CLK_CTRL0
, 0xff000fff, 0x00000100,
199 mmHDP_XDP_CGTT_BLK_CTRL
, 0xc0000fff, 0x00000104,
202 static void vi_init_golden_registers(struct amdgpu_device
*adev
)
204 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
205 mutex_lock(&adev
->grbm_idx_mutex
);
207 switch (adev
->asic_type
) {
209 amdgpu_program_register_sequence(adev
,
210 iceland_mgcg_cgcg_init
,
211 (const u32
)ARRAY_SIZE(iceland_mgcg_cgcg_init
));
214 amdgpu_program_register_sequence(adev
,
215 tonga_mgcg_cgcg_init
,
216 (const u32
)ARRAY_SIZE(tonga_mgcg_cgcg_init
));
219 amdgpu_program_register_sequence(adev
,
221 (const u32
)ARRAY_SIZE(cz_mgcg_cgcg_init
));
226 mutex_unlock(&adev
->grbm_idx_mutex
);
230 * vi_get_xclk - get the xclk
232 * @adev: amdgpu_device pointer
234 * Returns the reference clock used by the gfx engine
237 static u32
vi_get_xclk(struct amdgpu_device
*adev
)
239 u32 reference_clock
= adev
->clock
.spll
.reference_freq
;
242 if (adev
->flags
& AMDGPU_IS_APU
)
243 return reference_clock
;
245 tmp
= RREG32_SMC(ixCG_CLKPIN_CNTL_2
);
246 if (REG_GET_FIELD(tmp
, CG_CLKPIN_CNTL_2
, MUX_TCLK_TO_XCLK
))
249 tmp
= RREG32_SMC(ixCG_CLKPIN_CNTL
);
250 if (REG_GET_FIELD(tmp
, CG_CLKPIN_CNTL
, XTALIN_DIVIDE
))
251 return reference_clock
/ 4;
253 return reference_clock
;
257 * vi_srbm_select - select specific register instances
259 * @adev: amdgpu_device pointer
260 * @me: selected ME (micro engine)
265 * Switches the currently active registers instances. Some
266 * registers are instanced per VMID, others are instanced per
267 * me/pipe/queue combination.
269 void vi_srbm_select(struct amdgpu_device
*adev
,
270 u32 me
, u32 pipe
, u32 queue
, u32 vmid
)
272 u32 srbm_gfx_cntl
= 0;
273 srbm_gfx_cntl
= REG_SET_FIELD(srbm_gfx_cntl
, SRBM_GFX_CNTL
, PIPEID
, pipe
);
274 srbm_gfx_cntl
= REG_SET_FIELD(srbm_gfx_cntl
, SRBM_GFX_CNTL
, MEID
, me
);
275 srbm_gfx_cntl
= REG_SET_FIELD(srbm_gfx_cntl
, SRBM_GFX_CNTL
, VMID
, vmid
);
276 srbm_gfx_cntl
= REG_SET_FIELD(srbm_gfx_cntl
, SRBM_GFX_CNTL
, QUEUEID
, queue
);
277 WREG32(mmSRBM_GFX_CNTL
, srbm_gfx_cntl
);
280 static void vi_vga_set_state(struct amdgpu_device
*adev
, bool state
)
285 static bool vi_read_disabled_bios(struct amdgpu_device
*adev
)
288 u32 d1vga_control
= 0;
289 u32 d2vga_control
= 0;
290 u32 vga_render_control
= 0;
294 bus_cntl
= RREG32(mmBUS_CNTL
);
295 if (adev
->mode_info
.num_crtc
) {
296 d1vga_control
= RREG32(mmD1VGA_CONTROL
);
297 d2vga_control
= RREG32(mmD2VGA_CONTROL
);
298 vga_render_control
= RREG32(mmVGA_RENDER_CONTROL
);
300 rom_cntl
= RREG32_SMC(ixROM_CNTL
);
303 WREG32(mmBUS_CNTL
, (bus_cntl
& ~BUS_CNTL__BIOS_ROM_DIS_MASK
));
304 if (adev
->mode_info
.num_crtc
) {
305 /* Disable VGA mode */
306 WREG32(mmD1VGA_CONTROL
,
307 (d1vga_control
& ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK
|
308 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK
)));
309 WREG32(mmD2VGA_CONTROL
,
310 (d2vga_control
& ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK
|
311 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK
)));
312 WREG32(mmVGA_RENDER_CONTROL
,
313 (vga_render_control
& ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK
));
315 WREG32_SMC(ixROM_CNTL
, rom_cntl
| ROM_CNTL__SCK_OVERWRITE_MASK
);
317 r
= amdgpu_read_bios(adev
);
320 WREG32(mmBUS_CNTL
, bus_cntl
);
321 if (adev
->mode_info
.num_crtc
) {
322 WREG32(mmD1VGA_CONTROL
, d1vga_control
);
323 WREG32(mmD2VGA_CONTROL
, d2vga_control
);
324 WREG32(mmVGA_RENDER_CONTROL
, vga_render_control
);
326 WREG32_SMC(ixROM_CNTL
, rom_cntl
);
329 static struct amdgpu_allowed_register_entry tonga_allowed_read_registers
[] = {
330 {mmGB_MACROTILE_MODE7
, true},
333 static struct amdgpu_allowed_register_entry cz_allowed_read_registers
[] = {
334 {mmGB_TILE_MODE7
, true},
335 {mmGB_TILE_MODE12
, true},
336 {mmGB_TILE_MODE17
, true},
337 {mmGB_TILE_MODE23
, true},
338 {mmGB_MACROTILE_MODE7
, true},
341 static struct amdgpu_allowed_register_entry vi_allowed_read_registers
[] = {
342 {mmGRBM_STATUS
, false},
343 {mmGB_ADDR_CONFIG
, false},
344 {mmMC_ARB_RAMCFG
, false},
345 {mmGB_TILE_MODE0
, false},
346 {mmGB_TILE_MODE1
, false},
347 {mmGB_TILE_MODE2
, false},
348 {mmGB_TILE_MODE3
, false},
349 {mmGB_TILE_MODE4
, false},
350 {mmGB_TILE_MODE5
, false},
351 {mmGB_TILE_MODE6
, false},
352 {mmGB_TILE_MODE7
, false},
353 {mmGB_TILE_MODE8
, false},
354 {mmGB_TILE_MODE9
, false},
355 {mmGB_TILE_MODE10
, false},
356 {mmGB_TILE_MODE11
, false},
357 {mmGB_TILE_MODE12
, false},
358 {mmGB_TILE_MODE13
, false},
359 {mmGB_TILE_MODE14
, false},
360 {mmGB_TILE_MODE15
, false},
361 {mmGB_TILE_MODE16
, false},
362 {mmGB_TILE_MODE17
, false},
363 {mmGB_TILE_MODE18
, false},
364 {mmGB_TILE_MODE19
, false},
365 {mmGB_TILE_MODE20
, false},
366 {mmGB_TILE_MODE21
, false},
367 {mmGB_TILE_MODE22
, false},
368 {mmGB_TILE_MODE23
, false},
369 {mmGB_TILE_MODE24
, false},
370 {mmGB_TILE_MODE25
, false},
371 {mmGB_TILE_MODE26
, false},
372 {mmGB_TILE_MODE27
, false},
373 {mmGB_TILE_MODE28
, false},
374 {mmGB_TILE_MODE29
, false},
375 {mmGB_TILE_MODE30
, false},
376 {mmGB_TILE_MODE31
, false},
377 {mmGB_MACROTILE_MODE0
, false},
378 {mmGB_MACROTILE_MODE1
, false},
379 {mmGB_MACROTILE_MODE2
, false},
380 {mmGB_MACROTILE_MODE3
, false},
381 {mmGB_MACROTILE_MODE4
, false},
382 {mmGB_MACROTILE_MODE5
, false},
383 {mmGB_MACROTILE_MODE6
, false},
384 {mmGB_MACROTILE_MODE7
, false},
385 {mmGB_MACROTILE_MODE8
, false},
386 {mmGB_MACROTILE_MODE9
, false},
387 {mmGB_MACROTILE_MODE10
, false},
388 {mmGB_MACROTILE_MODE11
, false},
389 {mmGB_MACROTILE_MODE12
, false},
390 {mmGB_MACROTILE_MODE13
, false},
391 {mmGB_MACROTILE_MODE14
, false},
392 {mmGB_MACROTILE_MODE15
, false},
393 {mmCC_RB_BACKEND_DISABLE
, false, true},
394 {mmGC_USER_RB_BACKEND_DISABLE
, false, true},
395 {mmGB_BACKEND_MAP
, false, false},
396 {mmPA_SC_RASTER_CONFIG
, false, true},
397 {mmPA_SC_RASTER_CONFIG_1
, false, true},
400 static uint32_t vi_read_indexed_register(struct amdgpu_device
*adev
, u32 se_num
,
401 u32 sh_num
, u32 reg_offset
)
405 mutex_lock(&adev
->grbm_idx_mutex
);
406 if (se_num
!= 0xffffffff || sh_num
!= 0xffffffff)
407 gfx_v8_0_select_se_sh(adev
, se_num
, sh_num
);
409 val
= RREG32(reg_offset
);
411 if (se_num
!= 0xffffffff || sh_num
!= 0xffffffff)
412 gfx_v8_0_select_se_sh(adev
, 0xffffffff, 0xffffffff);
413 mutex_unlock(&adev
->grbm_idx_mutex
);
417 static int vi_read_register(struct amdgpu_device
*adev
, u32 se_num
,
418 u32 sh_num
, u32 reg_offset
, u32
*value
)
420 struct amdgpu_allowed_register_entry
*asic_register_table
= NULL
;
421 struct amdgpu_allowed_register_entry
*asic_register_entry
;
425 switch (adev
->asic_type
) {
427 asic_register_table
= tonga_allowed_read_registers
;
428 size
= ARRAY_SIZE(tonga_allowed_read_registers
);
432 asic_register_table
= cz_allowed_read_registers
;
433 size
= ARRAY_SIZE(cz_allowed_read_registers
);
439 if (asic_register_table
) {
440 for (i
= 0; i
< size
; i
++) {
441 asic_register_entry
= asic_register_table
+ i
;
442 if (reg_offset
!= asic_register_entry
->reg_offset
)
444 if (!asic_register_entry
->untouched
)
445 *value
= asic_register_entry
->grbm_indexed
?
446 vi_read_indexed_register(adev
, se_num
,
447 sh_num
, reg_offset
) :
453 for (i
= 0; i
< ARRAY_SIZE(vi_allowed_read_registers
); i
++) {
454 if (reg_offset
!= vi_allowed_read_registers
[i
].reg_offset
)
457 if (!vi_allowed_read_registers
[i
].untouched
)
458 *value
= vi_allowed_read_registers
[i
].grbm_indexed
?
459 vi_read_indexed_register(adev
, se_num
,
460 sh_num
, reg_offset
) :
467 static void vi_print_gpu_status_regs(struct amdgpu_device
*adev
)
469 dev_info(adev
->dev
, " GRBM_STATUS=0x%08X\n",
470 RREG32(mmGRBM_STATUS
));
471 dev_info(adev
->dev
, " GRBM_STATUS2=0x%08X\n",
472 RREG32(mmGRBM_STATUS2
));
473 dev_info(adev
->dev
, " GRBM_STATUS_SE0=0x%08X\n",
474 RREG32(mmGRBM_STATUS_SE0
));
475 dev_info(adev
->dev
, " GRBM_STATUS_SE1=0x%08X\n",
476 RREG32(mmGRBM_STATUS_SE1
));
477 dev_info(adev
->dev
, " GRBM_STATUS_SE2=0x%08X\n",
478 RREG32(mmGRBM_STATUS_SE2
));
479 dev_info(adev
->dev
, " GRBM_STATUS_SE3=0x%08X\n",
480 RREG32(mmGRBM_STATUS_SE3
));
481 dev_info(adev
->dev
, " SRBM_STATUS=0x%08X\n",
482 RREG32(mmSRBM_STATUS
));
483 dev_info(adev
->dev
, " SRBM_STATUS2=0x%08X\n",
484 RREG32(mmSRBM_STATUS2
));
485 dev_info(adev
->dev
, " SDMA0_STATUS_REG = 0x%08X\n",
486 RREG32(mmSDMA0_STATUS_REG
+ SDMA0_REGISTER_OFFSET
));
487 dev_info(adev
->dev
, " SDMA1_STATUS_REG = 0x%08X\n",
488 RREG32(mmSDMA0_STATUS_REG
+ SDMA1_REGISTER_OFFSET
));
489 dev_info(adev
->dev
, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT
));
490 dev_info(adev
->dev
, " CP_STALLED_STAT1 = 0x%08x\n",
491 RREG32(mmCP_STALLED_STAT1
));
492 dev_info(adev
->dev
, " CP_STALLED_STAT2 = 0x%08x\n",
493 RREG32(mmCP_STALLED_STAT2
));
494 dev_info(adev
->dev
, " CP_STALLED_STAT3 = 0x%08x\n",
495 RREG32(mmCP_STALLED_STAT3
));
496 dev_info(adev
->dev
, " CP_CPF_BUSY_STAT = 0x%08x\n",
497 RREG32(mmCP_CPF_BUSY_STAT
));
498 dev_info(adev
->dev
, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
499 RREG32(mmCP_CPF_STALLED_STAT1
));
500 dev_info(adev
->dev
, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS
));
501 dev_info(adev
->dev
, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT
));
502 dev_info(adev
->dev
, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
503 RREG32(mmCP_CPC_STALLED_STAT1
));
504 dev_info(adev
->dev
, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS
));
508 * vi_gpu_check_soft_reset - check which blocks are busy
510 * @adev: amdgpu_device pointer
512 * Check which blocks are busy and return the relevant reset
513 * mask to be used by vi_gpu_soft_reset().
514 * Returns a mask of the blocks to be reset.
516 u32
vi_gpu_check_soft_reset(struct amdgpu_device
*adev
)
522 tmp
= RREG32(mmGRBM_STATUS
);
523 if (tmp
& (GRBM_STATUS__PA_BUSY_MASK
| GRBM_STATUS__SC_BUSY_MASK
|
524 GRBM_STATUS__BCI_BUSY_MASK
| GRBM_STATUS__SX_BUSY_MASK
|
525 GRBM_STATUS__TA_BUSY_MASK
| GRBM_STATUS__VGT_BUSY_MASK
|
526 GRBM_STATUS__DB_BUSY_MASK
| GRBM_STATUS__CB_BUSY_MASK
|
527 GRBM_STATUS__GDS_BUSY_MASK
| GRBM_STATUS__SPI_BUSY_MASK
|
528 GRBM_STATUS__IA_BUSY_MASK
| GRBM_STATUS__IA_BUSY_NO_DMA_MASK
))
529 reset_mask
|= AMDGPU_RESET_GFX
;
531 if (tmp
& (GRBM_STATUS__CP_BUSY_MASK
| GRBM_STATUS__CP_COHERENCY_BUSY_MASK
))
532 reset_mask
|= AMDGPU_RESET_CP
;
535 tmp
= RREG32(mmGRBM_STATUS2
);
536 if (tmp
& GRBM_STATUS2__RLC_BUSY_MASK
)
537 reset_mask
|= AMDGPU_RESET_RLC
;
539 if (tmp
& (GRBM_STATUS2__CPF_BUSY_MASK
|
540 GRBM_STATUS2__CPC_BUSY_MASK
|
541 GRBM_STATUS2__CPG_BUSY_MASK
))
542 reset_mask
|= AMDGPU_RESET_CP
;
545 tmp
= RREG32(mmSRBM_STATUS2
);
546 if (tmp
& SRBM_STATUS2__SDMA_BUSY_MASK
)
547 reset_mask
|= AMDGPU_RESET_DMA
;
549 if (tmp
& SRBM_STATUS2__SDMA1_BUSY_MASK
)
550 reset_mask
|= AMDGPU_RESET_DMA1
;
553 tmp
= RREG32(mmSRBM_STATUS
);
555 if (tmp
& SRBM_STATUS__IH_BUSY_MASK
)
556 reset_mask
|= AMDGPU_RESET_IH
;
558 if (tmp
& SRBM_STATUS__SEM_BUSY_MASK
)
559 reset_mask
|= AMDGPU_RESET_SEM
;
561 if (tmp
& SRBM_STATUS__GRBM_RQ_PENDING_MASK
)
562 reset_mask
|= AMDGPU_RESET_GRBM
;
564 if (adev
->asic_type
!= CHIP_TOPAZ
) {
565 if (tmp
& (SRBM_STATUS__UVD_RQ_PENDING_MASK
|
566 SRBM_STATUS__UVD_BUSY_MASK
))
567 reset_mask
|= AMDGPU_RESET_UVD
;
570 if (tmp
& SRBM_STATUS__VMC_BUSY_MASK
)
571 reset_mask
|= AMDGPU_RESET_VMC
;
573 if (tmp
& (SRBM_STATUS__MCB_BUSY_MASK
| SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK
|
574 SRBM_STATUS__MCC_BUSY_MASK
| SRBM_STATUS__MCD_BUSY_MASK
))
575 reset_mask
|= AMDGPU_RESET_MC
;
577 /* SDMA0_STATUS_REG */
578 tmp
= RREG32(mmSDMA0_STATUS_REG
+ SDMA0_REGISTER_OFFSET
);
579 if (!(tmp
& SDMA0_STATUS_REG__IDLE_MASK
))
580 reset_mask
|= AMDGPU_RESET_DMA
;
582 /* SDMA1_STATUS_REG */
583 tmp
= RREG32(mmSDMA0_STATUS_REG
+ SDMA1_REGISTER_OFFSET
);
584 if (!(tmp
& SDMA0_STATUS_REG__IDLE_MASK
))
585 reset_mask
|= AMDGPU_RESET_DMA1
;
588 if (adev
->asic_type
!= CHIP_TOPAZ
) {
589 tmp
= RREG32(mmVCE_STATUS
);
590 if (tmp
& VCE_STATUS__VCPU_REPORT_RB0_BUSY_MASK
)
591 reset_mask
|= AMDGPU_RESET_VCE
;
592 if (tmp
& VCE_STATUS__VCPU_REPORT_RB1_BUSY_MASK
)
593 reset_mask
|= AMDGPU_RESET_VCE1
;
597 if (adev
->asic_type
!= CHIP_TOPAZ
) {
598 if (amdgpu_display_is_display_hung(adev
))
599 reset_mask
|= AMDGPU_RESET_DISPLAY
;
603 /* Skip MC reset as it's mostly likely not hung, just busy */
604 if (reset_mask
& AMDGPU_RESET_MC
) {
605 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask
);
606 reset_mask
&= ~AMDGPU_RESET_MC
;
613 * vi_gpu_soft_reset - soft reset GPU
615 * @adev: amdgpu_device pointer
616 * @reset_mask: mask of which blocks to reset
618 * Soft reset the blocks specified in @reset_mask.
620 static void vi_gpu_soft_reset(struct amdgpu_device
*adev
, u32 reset_mask
)
622 struct amdgpu_mode_mc_save save
;
623 u32 grbm_soft_reset
= 0, srbm_soft_reset
= 0;
629 dev_info(adev
->dev
, "GPU softreset: 0x%08X\n", reset_mask
);
631 vi_print_gpu_status_regs(adev
);
632 dev_info(adev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
633 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR
));
634 dev_info(adev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
635 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS
));
641 //gfx_v8_0_rlc_stop(adev);
643 /* Disable GFX parsing/prefetching */
644 tmp
= RREG32(mmCP_ME_CNTL
);
645 tmp
= REG_SET_FIELD(tmp
, CP_ME_CNTL
, ME_HALT
, 1);
646 tmp
= REG_SET_FIELD(tmp
, CP_ME_CNTL
, PFP_HALT
, 1);
647 tmp
= REG_SET_FIELD(tmp
, CP_ME_CNTL
, CE_HALT
, 1);
648 WREG32(mmCP_ME_CNTL
, tmp
);
650 /* Disable MEC parsing/prefetching */
651 tmp
= RREG32(mmCP_MEC_CNTL
);
652 tmp
= REG_SET_FIELD(tmp
, CP_MEC_CNTL
, MEC_ME1_HALT
, 1);
653 tmp
= REG_SET_FIELD(tmp
, CP_MEC_CNTL
, MEC_ME2_HALT
, 1);
654 WREG32(mmCP_MEC_CNTL
, tmp
);
656 if (reset_mask
& AMDGPU_RESET_DMA
) {
658 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
);
659 tmp
= REG_SET_FIELD(tmp
, SDMA0_F32_CNTL
, HALT
, 1);
660 WREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
, tmp
);
662 if (reset_mask
& AMDGPU_RESET_DMA1
) {
664 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
);
665 tmp
= REG_SET_FIELD(tmp
, SDMA0_F32_CNTL
, HALT
, 1);
666 WREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
, tmp
);
669 gmc_v8_0_mc_stop(adev
, &save
);
670 if (amdgpu_asic_wait_for_mc_idle(adev
)) {
671 dev_warn(adev
->dev
, "Wait for MC idle timedout !\n");
674 if (reset_mask
& (AMDGPU_RESET_GFX
| AMDGPU_RESET_COMPUTE
| AMDGPU_RESET_CP
)) {
676 REG_SET_FIELD(grbm_soft_reset
, GRBM_SOFT_RESET
, SOFT_RESET_CP
, 1);
678 REG_SET_FIELD(grbm_soft_reset
, GRBM_SOFT_RESET
, SOFT_RESET_GFX
, 1);
681 if (reset_mask
& AMDGPU_RESET_CP
) {
683 REG_SET_FIELD(grbm_soft_reset
, GRBM_SOFT_RESET
, SOFT_RESET_CP
, 1);
685 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_GRBM
, 1);
688 if (reset_mask
& AMDGPU_RESET_DMA
)
690 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_SDMA
, 1);
692 if (reset_mask
& AMDGPU_RESET_DMA1
)
694 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_SDMA1
, 1);
696 if (reset_mask
& AMDGPU_RESET_DISPLAY
)
698 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_DC
, 1);
700 if (reset_mask
& AMDGPU_RESET_RLC
)
702 REG_SET_FIELD(grbm_soft_reset
, GRBM_SOFT_RESET
, SOFT_RESET_RLC
, 1);
704 if (reset_mask
& AMDGPU_RESET_SEM
)
706 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_SEM
, 1);
708 if (reset_mask
& AMDGPU_RESET_IH
)
710 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_IH
, 1);
712 if (reset_mask
& AMDGPU_RESET_GRBM
)
714 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_GRBM
, 1);
716 if (reset_mask
& AMDGPU_RESET_VMC
)
718 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_VMC
, 1);
720 if (reset_mask
& AMDGPU_RESET_UVD
)
722 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_UVD
, 1);
724 if (reset_mask
& AMDGPU_RESET_VCE
)
726 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_VCE0
, 1);
728 if (reset_mask
& AMDGPU_RESET_VCE
)
730 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_VCE1
, 1);
732 if (!(adev
->flags
& AMDGPU_IS_APU
)) {
733 if (reset_mask
& AMDGPU_RESET_MC
)
735 REG_SET_FIELD(srbm_soft_reset
, SRBM_SOFT_RESET
, SOFT_RESET_MC
, 1);
738 if (grbm_soft_reset
) {
739 tmp
= RREG32(mmGRBM_SOFT_RESET
);
740 tmp
|= grbm_soft_reset
;
741 dev_info(adev
->dev
, "GRBM_SOFT_RESET=0x%08X\n", tmp
);
742 WREG32(mmGRBM_SOFT_RESET
, tmp
);
743 tmp
= RREG32(mmGRBM_SOFT_RESET
);
747 tmp
&= ~grbm_soft_reset
;
748 WREG32(mmGRBM_SOFT_RESET
, tmp
);
749 tmp
= RREG32(mmGRBM_SOFT_RESET
);
752 if (srbm_soft_reset
) {
753 tmp
= RREG32(mmSRBM_SOFT_RESET
);
754 tmp
|= srbm_soft_reset
;
755 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
756 WREG32(mmSRBM_SOFT_RESET
, tmp
);
757 tmp
= RREG32(mmSRBM_SOFT_RESET
);
761 tmp
&= ~srbm_soft_reset
;
762 WREG32(mmSRBM_SOFT_RESET
, tmp
);
763 tmp
= RREG32(mmSRBM_SOFT_RESET
);
766 /* Wait a little for things to settle down */
769 gmc_v8_0_mc_resume(adev
, &save
);
772 vi_print_gpu_status_regs(adev
);
775 static void vi_gpu_pci_config_reset(struct amdgpu_device
*adev
)
777 struct amdgpu_mode_mc_save save
;
780 dev_info(adev
->dev
, "GPU pci config reset\n");
786 /* Disable GFX parsing/prefetching */
787 tmp
= RREG32(mmCP_ME_CNTL
);
788 tmp
= REG_SET_FIELD(tmp
, CP_ME_CNTL
, ME_HALT
, 1);
789 tmp
= REG_SET_FIELD(tmp
, CP_ME_CNTL
, PFP_HALT
, 1);
790 tmp
= REG_SET_FIELD(tmp
, CP_ME_CNTL
, CE_HALT
, 1);
791 WREG32(mmCP_ME_CNTL
, tmp
);
793 /* Disable MEC parsing/prefetching */
794 tmp
= RREG32(mmCP_MEC_CNTL
);
795 tmp
= REG_SET_FIELD(tmp
, CP_MEC_CNTL
, MEC_ME1_HALT
, 1);
796 tmp
= REG_SET_FIELD(tmp
, CP_MEC_CNTL
, MEC_ME2_HALT
, 1);
797 WREG32(mmCP_MEC_CNTL
, tmp
);
799 /* Disable GFX parsing/prefetching */
800 WREG32(mmCP_ME_CNTL
, CP_ME_CNTL__ME_HALT_MASK
|
801 CP_ME_CNTL__PFP_HALT_MASK
| CP_ME_CNTL__CE_HALT_MASK
);
803 /* Disable MEC parsing/prefetching */
804 WREG32(mmCP_MEC_CNTL
,
805 CP_MEC_CNTL__MEC_ME1_HALT_MASK
| CP_MEC_CNTL__MEC_ME2_HALT_MASK
);
808 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
);
809 tmp
= REG_SET_FIELD(tmp
, SDMA0_F32_CNTL
, HALT
, 1);
810 WREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
, tmp
);
813 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
);
814 tmp
= REG_SET_FIELD(tmp
, SDMA0_F32_CNTL
, HALT
, 1);
815 WREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
, tmp
);
817 /* XXX other engines? */
819 /* halt the rlc, disable cp internal ints */
821 //gfx_v8_0_rlc_stop(adev);
825 /* disable mem access */
826 gmc_v8_0_mc_stop(adev
, &save
);
827 if (amdgpu_asic_wait_for_mc_idle(adev
)) {
828 dev_warn(adev
->dev
, "Wait for MC idle timed out !\n");
832 pci_clear_master(adev
->pdev
);
834 amdgpu_pci_config_reset(adev
);
838 /* wait for asic to come out of reset */
839 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
840 if (RREG32(mmCONFIG_MEMSIZE
) != 0xffffffff)
847 static void vi_set_bios_scratch_engine_hung(struct amdgpu_device
*adev
, bool hung
)
849 u32 tmp
= RREG32(mmBIOS_SCRATCH_3
);
852 tmp
|= ATOM_S3_ASIC_GUI_ENGINE_HUNG
;
854 tmp
&= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG
;
856 WREG32(mmBIOS_SCRATCH_3
, tmp
);
860 * vi_asic_reset - soft reset GPU
862 * @adev: amdgpu_device pointer
864 * Look up which blocks are hung and attempt
866 * Returns 0 for success.
868 static int vi_asic_reset(struct amdgpu_device
*adev
)
872 reset_mask
= vi_gpu_check_soft_reset(adev
);
875 vi_set_bios_scratch_engine_hung(adev
, true);
878 vi_gpu_soft_reset(adev
, reset_mask
);
880 reset_mask
= vi_gpu_check_soft_reset(adev
);
882 /* try pci config reset */
883 if (reset_mask
&& amdgpu_hard_reset
)
884 vi_gpu_pci_config_reset(adev
);
886 reset_mask
= vi_gpu_check_soft_reset(adev
);
889 vi_set_bios_scratch_engine_hung(adev
, false);
894 static int vi_set_uvd_clock(struct amdgpu_device
*adev
, u32 clock
,
895 u32 cntl_reg
, u32 status_reg
)
898 struct atom_clock_dividers dividers
;
901 r
= amdgpu_atombios_get_clock_dividers(adev
,
902 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK
,
903 clock
, false, ÷rs
);
907 tmp
= RREG32_SMC(cntl_reg
);
908 tmp
&= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK
|
909 CG_DCLK_CNTL__DCLK_DIVIDER_MASK
);
910 tmp
|= dividers
.post_divider
;
911 WREG32_SMC(cntl_reg
, tmp
);
913 for (i
= 0; i
< 100; i
++) {
914 if (RREG32_SMC(status_reg
) & CG_DCLK_STATUS__DCLK_STATUS_MASK
)
924 static int vi_set_uvd_clocks(struct amdgpu_device
*adev
, u32 vclk
, u32 dclk
)
928 r
= vi_set_uvd_clock(adev
, vclk
, ixCG_VCLK_CNTL
, ixCG_VCLK_STATUS
);
932 r
= vi_set_uvd_clock(adev
, dclk
, ixCG_DCLK_CNTL
, ixCG_DCLK_STATUS
);
937 static int vi_set_vce_clocks(struct amdgpu_device
*adev
, u32 evclk
, u32 ecclk
)
944 static void vi_pcie_gen3_enable(struct amdgpu_device
*adev
)
949 if (amdgpu_pcie_gen2
== 0)
952 if (adev
->flags
& AMDGPU_IS_APU
)
955 ret
= drm_pcie_get_speed_cap_mask(adev
->ddev
, &mask
);
959 if (!(mask
& (DRM_PCIE_SPEED_50
| DRM_PCIE_SPEED_80
)))
965 static void vi_program_aspm(struct amdgpu_device
*adev
)
968 if (amdgpu_aspm
== 0)
974 static void vi_enable_doorbell_aperture(struct amdgpu_device
*adev
,
979 /* not necessary on CZ */
980 if (adev
->flags
& AMDGPU_IS_APU
)
983 tmp
= RREG32(mmBIF_DOORBELL_APER_EN
);
985 tmp
= REG_SET_FIELD(tmp
, BIF_DOORBELL_APER_EN
, BIF_DOORBELL_APER_EN
, 1);
987 tmp
= REG_SET_FIELD(tmp
, BIF_DOORBELL_APER_EN
, BIF_DOORBELL_APER_EN
, 0);
989 WREG32(mmBIF_DOORBELL_APER_EN
, tmp
);
992 /* topaz has no DCE, UVD, VCE */
993 static const struct amdgpu_ip_block_version topaz_ip_blocks
[] =
997 .type
= AMDGPU_IP_BLOCK_TYPE_COMMON
,
1001 .funcs
= &vi_common_ip_funcs
,
1004 .type
= AMDGPU_IP_BLOCK_TYPE_GMC
,
1008 .funcs
= &gmc_v8_0_ip_funcs
,
1011 .type
= AMDGPU_IP_BLOCK_TYPE_IH
,
1015 .funcs
= &iceland_ih_ip_funcs
,
1018 .type
= AMDGPU_IP_BLOCK_TYPE_SMC
,
1022 .funcs
= &iceland_dpm_ip_funcs
,
1025 .type
= AMDGPU_IP_BLOCK_TYPE_GFX
,
1029 .funcs
= &gfx_v8_0_ip_funcs
,
1032 .type
= AMDGPU_IP_BLOCK_TYPE_SDMA
,
1036 .funcs
= &sdma_v2_4_ip_funcs
,
1040 static const struct amdgpu_ip_block_version tonga_ip_blocks
[] =
1042 /* ORDER MATTERS! */
1044 .type
= AMDGPU_IP_BLOCK_TYPE_COMMON
,
1048 .funcs
= &vi_common_ip_funcs
,
1051 .type
= AMDGPU_IP_BLOCK_TYPE_GMC
,
1055 .funcs
= &gmc_v8_0_ip_funcs
,
1058 .type
= AMDGPU_IP_BLOCK_TYPE_IH
,
1062 .funcs
= &tonga_ih_ip_funcs
,
1065 .type
= AMDGPU_IP_BLOCK_TYPE_SMC
,
1069 .funcs
= &tonga_dpm_ip_funcs
,
1072 .type
= AMDGPU_IP_BLOCK_TYPE_DCE
,
1076 .funcs
= &dce_v10_0_ip_funcs
,
1079 .type
= AMDGPU_IP_BLOCK_TYPE_GFX
,
1083 .funcs
= &gfx_v8_0_ip_funcs
,
1086 .type
= AMDGPU_IP_BLOCK_TYPE_SDMA
,
1090 .funcs
= &sdma_v3_0_ip_funcs
,
1093 .type
= AMDGPU_IP_BLOCK_TYPE_UVD
,
1097 .funcs
= &uvd_v5_0_ip_funcs
,
1100 .type
= AMDGPU_IP_BLOCK_TYPE_VCE
,
1104 .funcs
= &vce_v3_0_ip_funcs
,
1108 static const struct amdgpu_ip_block_version cz_ip_blocks
[] =
1110 /* ORDER MATTERS! */
1112 .type
= AMDGPU_IP_BLOCK_TYPE_COMMON
,
1116 .funcs
= &vi_common_ip_funcs
,
1119 .type
= AMDGPU_IP_BLOCK_TYPE_GMC
,
1123 .funcs
= &gmc_v8_0_ip_funcs
,
1126 .type
= AMDGPU_IP_BLOCK_TYPE_IH
,
1130 .funcs
= &cz_ih_ip_funcs
,
1133 .type
= AMDGPU_IP_BLOCK_TYPE_SMC
,
1137 .funcs
= &cz_dpm_ip_funcs
,
1140 .type
= AMDGPU_IP_BLOCK_TYPE_DCE
,
1144 .funcs
= &dce_v11_0_ip_funcs
,
1147 .type
= AMDGPU_IP_BLOCK_TYPE_GFX
,
1151 .funcs
= &gfx_v8_0_ip_funcs
,
1154 .type
= AMDGPU_IP_BLOCK_TYPE_SDMA
,
1158 .funcs
= &sdma_v3_0_ip_funcs
,
1161 .type
= AMDGPU_IP_BLOCK_TYPE_UVD
,
1165 .funcs
= &uvd_v6_0_ip_funcs
,
1168 .type
= AMDGPU_IP_BLOCK_TYPE_VCE
,
1172 .funcs
= &vce_v3_0_ip_funcs
,
1176 int vi_set_ip_blocks(struct amdgpu_device
*adev
)
1178 switch (adev
->asic_type
) {
1180 adev
->ip_blocks
= topaz_ip_blocks
;
1181 adev
->num_ip_blocks
= ARRAY_SIZE(topaz_ip_blocks
);
1184 adev
->ip_blocks
= tonga_ip_blocks
;
1185 adev
->num_ip_blocks
= ARRAY_SIZE(tonga_ip_blocks
);
1188 adev
->ip_blocks
= cz_ip_blocks
;
1189 adev
->num_ip_blocks
= ARRAY_SIZE(cz_ip_blocks
);
1192 /* FIXME: not supported yet */
1196 adev
->ip_block_enabled
= kcalloc(adev
->num_ip_blocks
, sizeof(bool), GFP_KERNEL
);
1197 if (adev
->ip_block_enabled
== NULL
)
1203 static uint32_t vi_get_rev_id(struct amdgpu_device
*adev
)
1205 if (adev
->asic_type
== CHIP_TOPAZ
)
1206 return (RREG32(mmPCIE_EFUSE4
) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK
)
1207 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT
;
1209 return (RREG32(mmCC_DRM_ID_STRAPS
) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK
)
1210 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT
;
1213 static const struct amdgpu_asic_funcs vi_asic_funcs
=
1215 .read_disabled_bios
= &vi_read_disabled_bios
,
1216 .read_register
= &vi_read_register
,
1217 .reset
= &vi_asic_reset
,
1218 .set_vga_state
= &vi_vga_set_state
,
1219 .get_xclk
= &vi_get_xclk
,
1220 .set_uvd_clocks
= &vi_set_uvd_clocks
,
1221 .set_vce_clocks
= &vi_set_vce_clocks
,
1222 .get_cu_info
= &gfx_v8_0_get_cu_info
,
1223 /* these should be moved to their own ip modules */
1224 .get_gpu_clock_counter
= &gfx_v8_0_get_gpu_clock_counter
,
1225 .wait_for_mc_idle
= &gmc_v8_0_mc_wait_for_idle
,
1228 static int vi_common_early_init(struct amdgpu_device
*adev
)
1230 bool smc_enabled
= false;
1232 adev
->smc_rreg
= &vi_smc_rreg
;
1233 adev
->smc_wreg
= &vi_smc_wreg
;
1234 adev
->pcie_rreg
= &vi_pcie_rreg
;
1235 adev
->pcie_wreg
= &vi_pcie_wreg
;
1236 adev
->uvd_ctx_rreg
= &vi_uvd_ctx_rreg
;
1237 adev
->uvd_ctx_wreg
= &vi_uvd_ctx_wreg
;
1238 adev
->didt_rreg
= &vi_didt_rreg
;
1239 adev
->didt_wreg
= &vi_didt_wreg
;
1241 adev
->asic_funcs
= &vi_asic_funcs
;
1243 if (amdgpu_get_ip_block(adev
, AMDGPU_IP_BLOCK_TYPE_SMC
) &&
1244 (amdgpu_ip_block_mask
& (1 << AMDGPU_IP_BLOCK_TYPE_SMC
)))
1247 adev
->rev_id
= vi_get_rev_id(adev
);
1248 adev
->external_rev_id
= 0xFF;
1249 switch (adev
->asic_type
) {
1251 adev
->has_uvd
= false;
1254 adev
->external_rev_id
= 0x1;
1255 if (amdgpu_smc_load_fw
&& smc_enabled
)
1256 adev
->firmware
.smu_load
= true;
1259 adev
->has_uvd
= true;
1262 adev
->external_rev_id
= adev
->rev_id
+ 0x14;
1263 if (amdgpu_smc_load_fw
&& smc_enabled
)
1264 adev
->firmware
.smu_load
= true;
1267 adev
->has_uvd
= true;
1269 adev
->pg_flags
= AMDGPU_PG_SUPPORT_UVD
;
1270 adev
->external_rev_id
= adev
->rev_id
+ 0x1;
1271 if (amdgpu_smc_load_fw
&& smc_enabled
)
1272 adev
->firmware
.smu_load
= true;
1275 /* FIXME: not supported yet */
1282 static int vi_common_sw_init(struct amdgpu_device
*adev
)
1287 static int vi_common_sw_fini(struct amdgpu_device
*adev
)
1292 static int vi_common_hw_init(struct amdgpu_device
*adev
)
1294 /* move the golden regs per IP block */
1295 vi_init_golden_registers(adev
);
1296 /* enable pcie gen2/3 link */
1297 vi_pcie_gen3_enable(adev
);
1299 vi_program_aspm(adev
);
1300 /* enable the doorbell aperture */
1301 vi_enable_doorbell_aperture(adev
, true);
1306 static int vi_common_hw_fini(struct amdgpu_device
*adev
)
1308 /* enable the doorbell aperture */
1309 vi_enable_doorbell_aperture(adev
, false);
1314 static int vi_common_suspend(struct amdgpu_device
*adev
)
1316 return vi_common_hw_fini(adev
);
1319 static int vi_common_resume(struct amdgpu_device
*adev
)
1321 return vi_common_hw_init(adev
);
1324 static bool vi_common_is_idle(struct amdgpu_device
*adev
)
1329 static int vi_common_wait_for_idle(struct amdgpu_device
*adev
)
1334 static void vi_common_print_status(struct amdgpu_device
*adev
)
1339 static int vi_common_soft_reset(struct amdgpu_device
*adev
)
1341 /* XXX hard reset?? */
1345 static int vi_common_set_clockgating_state(struct amdgpu_device
*adev
,
1346 enum amdgpu_clockgating_state state
)
1351 static int vi_common_set_powergating_state(struct amdgpu_device
*adev
,
1352 enum amdgpu_powergating_state state
)
1357 const struct amdgpu_ip_funcs vi_common_ip_funcs
= {
1358 .early_init
= vi_common_early_init
,
1360 .sw_init
= vi_common_sw_init
,
1361 .sw_fini
= vi_common_sw_fini
,
1362 .hw_init
= vi_common_hw_init
,
1363 .hw_fini
= vi_common_hw_fini
,
1364 .suspend
= vi_common_suspend
,
1365 .resume
= vi_common_resume
,
1366 .is_idle
= vi_common_is_idle
,
1367 .wait_for_idle
= vi_common_wait_for_idle
,
1368 .soft_reset
= vi_common_soft_reset
,
1369 .print_status
= vi_common_print_status
,
1370 .set_clockgating_state
= vi_common_set_clockgating_state
,
1371 .set_powergating_state
= vi_common_set_powergating_state
,