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git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - drivers/gpu/drm/amd/amdgpu/vid.h
2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */
27 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */
28 #define SDMA_MAX_INSTANCE 2
30 /* crtc instance offsets */
31 #define CRTC0_REGISTER_OFFSET (0x1b9c - 0x1b9c)
32 #define CRTC1_REGISTER_OFFSET (0x1d9c - 0x1b9c)
33 #define CRTC2_REGISTER_OFFSET (0x1f9c - 0x1b9c)
34 #define CRTC3_REGISTER_OFFSET (0x419c - 0x1b9c)
35 #define CRTC4_REGISTER_OFFSET (0x439c - 0x1b9c)
36 #define CRTC5_REGISTER_OFFSET (0x459c - 0x1b9c)
37 #define CRTC6_REGISTER_OFFSET (0x479c - 0x1b9c)
39 /* dig instance offsets */
40 #define DIG0_REGISTER_OFFSET (0x4a00 - 0x4a00)
41 #define DIG1_REGISTER_OFFSET (0x4b00 - 0x4a00)
42 #define DIG2_REGISTER_OFFSET (0x4c00 - 0x4a00)
43 #define DIG3_REGISTER_OFFSET (0x4d00 - 0x4a00)
44 #define DIG4_REGISTER_OFFSET (0x4e00 - 0x4a00)
45 #define DIG5_REGISTER_OFFSET (0x4f00 - 0x4a00)
46 #define DIG6_REGISTER_OFFSET (0x5400 - 0x4a00)
47 #define DIG7_REGISTER_OFFSET (0x5600 - 0x4a00)
48 #define DIG8_REGISTER_OFFSET (0x5700 - 0x4a00)
50 /* audio endpt instance offsets */
51 #define AUD0_REGISTER_OFFSET (0x17a8 - 0x17a8)
52 #define AUD1_REGISTER_OFFSET (0x17ac - 0x17a8)
53 #define AUD2_REGISTER_OFFSET (0x17b0 - 0x17a8)
54 #define AUD3_REGISTER_OFFSET (0x17b4 - 0x17a8)
55 #define AUD4_REGISTER_OFFSET (0x17b8 - 0x17a8)
56 #define AUD5_REGISTER_OFFSET (0x17bc - 0x17a8)
57 #define AUD6_REGISTER_OFFSET (0x17c0 - 0x17a8)
58 #define AUD7_REGISTER_OFFSET (0x17c4 - 0x17a8)
60 /* hpd instance offsets */
61 #define HPD0_REGISTER_OFFSET (0x1898 - 0x1898)
62 #define HPD1_REGISTER_OFFSET (0x18a0 - 0x1898)
63 #define HPD2_REGISTER_OFFSET (0x18a8 - 0x1898)
64 #define HPD3_REGISTER_OFFSET (0x18b0 - 0x1898)
65 #define HPD4_REGISTER_OFFSET (0x18b8 - 0x1898)
66 #define HPD5_REGISTER_OFFSET (0x18c0 - 0x1898)
68 #define AMDGPU_NUM_OF_VMIDS 8
70 #define PIPEID(x) ((x) << 0)
71 #define MEID(x) ((x) << 2)
72 #define VMID(x) ((x) << 4)
73 #define QUEUEID(x) ((x) << 8)
75 #define MC_SEQ_MISC0__MT__MASK 0xf0000000
76 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000
77 #define MC_SEQ_MISC0__MT__DDR2 0x20000000
78 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000
79 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000
80 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000
81 #define MC_SEQ_MISC0__MT__HBM 0x60000000
82 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000
87 #define PACKET_TYPE0 0
88 #define PACKET_TYPE1 1
89 #define PACKET_TYPE2 2
90 #define PACKET_TYPE3 3
92 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
93 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
94 #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
95 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
96 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
99 #define CP_PACKET2 0x80000000
100 #define PACKET2_PAD_SHIFT 0
101 #define PACKET2_PAD_MASK (0x3fffffff << 0)
103 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
105 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
106 (((op) & 0xFF) << 8) | \
107 ((n) & 0x3FFF) << 16)
109 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
112 #define PACKET3_NOP 0x10
113 #define PACKET3_SET_BASE 0x11
114 #define PACKET3_BASE_INDEX(x) ((x) << 0)
115 #define CE_PARTITION_BASE 3
116 #define PACKET3_CLEAR_STATE 0x12
117 #define PACKET3_INDEX_BUFFER_SIZE 0x13
118 #define PACKET3_DISPATCH_DIRECT 0x15
119 #define PACKET3_DISPATCH_INDIRECT 0x16
120 #define PACKET3_ATOMIC_GDS 0x1D
121 #define PACKET3_ATOMIC_MEM 0x1E
122 #define PACKET3_OCCLUSION_QUERY 0x1F
123 #define PACKET3_SET_PREDICATION 0x20
124 #define PACKET3_REG_RMW 0x21
125 #define PACKET3_COND_EXEC 0x22
126 #define PACKET3_PRED_EXEC 0x23
127 #define PACKET3_DRAW_INDIRECT 0x24
128 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
129 #define PACKET3_INDEX_BASE 0x26
130 #define PACKET3_DRAW_INDEX_2 0x27
131 #define PACKET3_CONTEXT_CONTROL 0x28
132 #define PACKET3_INDEX_TYPE 0x2A
133 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
134 #define PACKET3_DRAW_INDEX_AUTO 0x2D
135 #define PACKET3_NUM_INSTANCES 0x2F
136 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
137 #define PACKET3_INDIRECT_BUFFER_CONST 0x33
138 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
139 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
140 #define PACKET3_DRAW_PREAMBLE 0x36
141 #define PACKET3_WRITE_DATA 0x37
142 #define WRITE_DATA_DST_SEL(x) ((x) << 8)
144 * 1 - memory (sync - via GRBM)
148 * 5 - memory (async - direct)
150 #define WR_ONE_ADDR (1 << 16)
151 #define WR_CONFIRM (1 << 20)
152 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
156 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
161 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
162 #define PACKET3_MEM_SEMAPHORE 0x39
163 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
164 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
165 # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
166 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
167 # define PACKET3_SEM_SEL_WAIT (0x7 << 29)
168 #define PACKET3_WAIT_REG_MEM 0x3C
169 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
178 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
182 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
186 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
190 #define PACKET3_INDIRECT_BUFFER 0x3F
191 #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)
192 #define INDIRECT_BUFFER_VALID (1 << 23)
193 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
198 #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21)
199 #define PACKET3_COPY_DATA 0x40
200 #define PACKET3_PFP_SYNC_ME 0x42
201 #define PACKET3_SURFACE_SYNC 0x43
202 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
203 # define PACKET3_DEST_BASE_1_ENA (1 << 1)
204 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
205 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
206 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
207 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
208 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
209 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
210 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
211 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
212 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
213 # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)
214 # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */
215 # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */
216 # define PACKET3_DEST_BASE_2_ENA (1 << 19)
217 # define PACKET3_DEST_BASE_3_ENA (1 << 21)
218 # define PACKET3_TCL1_ACTION_ENA (1 << 22)
219 # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */
220 # define PACKET3_CB_ACTION_ENA (1 << 25)
221 # define PACKET3_DB_ACTION_ENA (1 << 26)
222 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
223 # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
224 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
225 #define PACKET3_COND_WRITE 0x45
226 #define PACKET3_EVENT_WRITE 0x46
227 #define EVENT_TYPE(x) ((x) << 0)
228 #define EVENT_INDEX(x) ((x) << 8)
229 /* 0 - any non-TS event
230 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
231 * 2 - SAMPLE_PIPELINESTAT
232 * 3 - SAMPLE_STREAMOUTSTAT*
233 * 4 - *S_PARTIAL_FLUSH
237 #define PACKET3_EVENT_WRITE_EOP 0x47
238 #define EOP_TCL1_VOL_ACTION_EN (1 << 12)
239 #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
240 #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
241 #define EOP_TCL1_ACTION_EN (1 << 16)
242 #define EOP_TC_ACTION_EN (1 << 17) /* L2 */
243 #define EOP_TCL2_VOLATILE (1 << 24)
244 #define EOP_CACHE_POLICY(x) ((x) << 25)
249 #define DATA_SEL(x) ((x) << 29)
251 * 1 - send low 32bit data
252 * 2 - send 64bit data
253 * 3 - send 64bit GPU counter value
254 * 4 - send 64bit sys counter value
256 #define INT_SEL(x) ((x) << 24)
258 * 1 - interrupt only (DATA_SEL = 0)
259 * 2 - interrupt when data write is confirmed
261 #define DST_SEL(x) ((x) << 16)
265 #define PACKET3_EVENT_WRITE_EOS 0x48
266 #define PACKET3_RELEASE_MEM 0x49
267 #define PACKET3_PREAMBLE_CNTL 0x4A
268 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
269 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
270 #define PACKET3_DMA_DATA 0x50
273 * 3. SRC_ADDR_LO or DATA [31:0]
274 * 4. SRC_ADDR_HI [31:0]
275 * 5. DST_ADDR_LO [31:0]
276 * 6. DST_ADDR_HI [7:0]
277 * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
280 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
284 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
289 # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)
290 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)
291 /* 0 - DST_ADDR using DAS
293 * 3 - DST_ADDR using L2
295 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
300 # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)
301 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)
302 /* 0 - SRC_ADDR using SAS
305 * 3 - SRC_ADDR using L2
307 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
309 # define PACKET3_DMA_DATA_DIS_WC (1 << 21)
310 # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22)
316 # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24)
322 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26)
326 # define PACKET3_DMA_DATA_CMD_DAS (1 << 27)
330 # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
331 # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
332 # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
333 #define PACKET3_AQUIRE_MEM 0x58
334 #define PACKET3_REWIND 0x59
335 #define PACKET3_LOAD_UCONFIG_REG 0x5E
336 #define PACKET3_LOAD_SH_REG 0x5F
337 #define PACKET3_LOAD_CONFIG_REG 0x60
338 #define PACKET3_LOAD_CONTEXT_REG 0x61
339 #define PACKET3_SET_CONFIG_REG 0x68
340 #define PACKET3_SET_CONFIG_REG_START 0x00002000
341 #define PACKET3_SET_CONFIG_REG_END 0x00002c00
342 #define PACKET3_SET_CONTEXT_REG 0x69
343 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000
344 #define PACKET3_SET_CONTEXT_REG_END 0x0000a400
345 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
346 #define PACKET3_SET_SH_REG 0x76
347 #define PACKET3_SET_SH_REG_START 0x00002c00
348 #define PACKET3_SET_SH_REG_END 0x00003000
349 #define PACKET3_SET_SH_REG_OFFSET 0x77
350 #define PACKET3_SET_QUEUE_REG 0x78
351 #define PACKET3_SET_UCONFIG_REG 0x79
352 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000
353 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400
354 #define PACKET3_SCRATCH_RAM_WRITE 0x7D
355 #define PACKET3_SCRATCH_RAM_READ 0x7E
356 #define PACKET3_LOAD_CONST_RAM 0x80
357 #define PACKET3_WRITE_CONST_RAM 0x81
358 #define PACKET3_DUMP_CONST_RAM 0x83
359 #define PACKET3_INCREMENT_CE_COUNTER 0x84
360 #define PACKET3_INCREMENT_DE_COUNTER 0x85
361 #define PACKET3_WAIT_ON_CE_COUNTER 0x86
362 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
363 #define PACKET3_SWITCH_BUFFER 0x8B
364 #define PACKET3_SET_RESOURCES 0xA0
367 * 3. QUEUE_MASK_LO [31:0]
368 * 4. QUEUE_MASK_HI [31:0]
369 * 5. GWS_MASK_LO [31:0]
370 * 6. GWS_MASK_HI [31:0]
372 * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0]
374 # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0)
375 # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16)
376 # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29)
377 #define PACKET3_MAP_QUEUES 0xA2
381 * 4. MQD_ADDR_LO [31:0]
382 * 5. MQD_ADDR_HI [31:0]
383 * 6. WPTR_ADDR_LO [31:0]
384 * 7. WPTR_ADDR_HI [31:0]
387 # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4)
388 # define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8)
389 # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21)
390 # define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24)
391 # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26)
392 # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29)
394 # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1)
395 # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2)
396 # define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 26)
397 # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 29)
398 # define PACKET3_MAP_QUEUES_ME(x) ((x) << 31)
399 #define PACKET3_UNMAP_QUEUES 0xA3
408 # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0)
409 /* 0 - PREEMPT_QUEUES
411 * 2 - DISABLE_PROCESS_QUEUES
412 * 3 - PREEMPT_QUEUES_NO_UNMAP
414 # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4)
415 # define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26)
416 # define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29)
418 # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0)
420 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2)
422 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2)
424 # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0)
426 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2)
428 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2)
429 #define PACKET3_QUERY_STATUS 0xA4
439 # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0)
440 # define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28)
441 # define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30)
443 # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0)
445 # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2)
446 # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25)
449 #define VCE_CMD_NO_OP 0x00000000
450 #define VCE_CMD_END 0x00000001
451 #define VCE_CMD_IB 0x00000002
452 #define VCE_CMD_FENCE 0x00000003
453 #define VCE_CMD_TRAP 0x00000004
454 #define VCE_CMD_IB_AUTO 0x00000005
455 #define VCE_CMD_SEMAPHORE 0x00000006
457 #define VCE_CMD_IB_VM 0x00000102
458 #define VCE_CMD_WAIT_GE 0x00000106
459 #define VCE_CMD_UPDATE_PTB 0x00000107
460 #define VCE_CMD_FLUSH_TLB 0x00000108
462 /* mmPA_SC_RASTER_CONFIG mask */
463 #define RB_MAP_PKR0(x) ((x) << 0)
464 #define RB_MAP_PKR0_MASK (0x3 << 0)
465 #define RB_MAP_PKR1(x) ((x) << 2)
466 #define RB_MAP_PKR1_MASK (0x3 << 2)
467 #define RB_XSEL2(x) ((x) << 4)
468 #define RB_XSEL2_MASK (0x3 << 4)
469 #define RB_XSEL (1 << 6)
470 #define RB_YSEL (1 << 7)
471 #define PKR_MAP(x) ((x) << 8)
472 #define PKR_MAP_MASK (0x3 << 8)
473 #define PKR_XSEL(x) ((x) << 10)
474 #define PKR_XSEL_MASK (0x3 << 10)
475 #define PKR_YSEL(x) ((x) << 12)
476 #define PKR_YSEL_MASK (0x3 << 12)
477 #define SC_MAP(x) ((x) << 16)
478 #define SC_MAP_MASK (0x3 << 16)
479 #define SC_XSEL(x) ((x) << 18)
480 #define SC_XSEL_MASK (0x3 << 18)
481 #define SC_YSEL(x) ((x) << 20)
482 #define SC_YSEL_MASK (0x3 << 20)
483 #define SE_MAP(x) ((x) << 24)
484 #define SE_MAP_MASK (0x3 << 24)
485 #define SE_XSEL(x) ((x) << 26)
486 #define SE_XSEL_MASK (0x3 << 26)
487 #define SE_YSEL(x) ((x) << 28)
488 #define SE_YSEL_MASK (0x3 << 28)
490 /* mmPA_SC_RASTER_CONFIG_1 mask */
491 #define SE_PAIR_MAP(x) ((x) << 0)
492 #define SE_PAIR_MAP_MASK (0x3 << 0)
493 #define SE_PAIR_XSEL(x) ((x) << 2)
494 #define SE_PAIR_XSEL_MASK (0x3 << 2)
495 #define SE_PAIR_YSEL(x) ((x) << 4)
496 #define SE_PAIR_YSEL_MASK (0x3 << 4)