2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dm_services_types.h"
28 #include "dc/inc/core_types.h"
32 #include "amdgpu_display.h"
34 #include "amdgpu_dm.h"
35 #include "amdgpu_pm.h"
37 #include "amd_shared.h"
38 #include "amdgpu_dm_irq.h"
39 #include "dm_helpers.h"
40 #include "dm_services_types.h"
41 #include "amdgpu_dm_mst_types.h"
43 #include "ivsrcid/ivsrcid_vislands30.h"
45 #include <linux/module.h>
46 #include <linux/moduleparam.h>
47 #include <linux/version.h>
48 #include <linux/types.h>
51 #include <drm/drm_atomic.h>
52 #include <drm/drm_atomic_helper.h>
53 #include <drm/drm_dp_mst_helper.h>
54 #include <drm/drm_fb_helper.h>
55 #include <drm/drm_edid.h>
57 #include "modules/inc/mod_freesync.h"
59 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
60 #include "ivsrcid/irqsrcs_dcn_1_0.h"
62 #include "raven1/DCN/dcn_1_0_offset.h"
63 #include "raven1/DCN/dcn_1_0_sh_mask.h"
64 #include "vega10/soc15ip.h"
66 #include "soc15_common.h"
69 #include "modules/inc/mod_freesync.h"
71 #include "i2caux_interface.h"
73 /* basic init/fini API */
74 static int amdgpu_dm_init(struct amdgpu_device
*adev
);
75 static void amdgpu_dm_fini(struct amdgpu_device
*adev
);
77 /* initializes drm_device display related structures, based on the information
78 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
79 * drm_encoder, drm_mode_config
81 * Returns 0 on success
83 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device
*adev
);
84 /* removes and deallocates the drm structures, created by the above function */
85 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager
*dm
);
88 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector
*aconnector
);
90 static int amdgpu_dm_plane_init(struct amdgpu_display_manager
*dm
,
91 struct amdgpu_plane
*aplane
,
92 unsigned long possible_crtcs
);
93 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager
*dm
,
94 struct drm_plane
*plane
,
96 static int amdgpu_dm_connector_init(struct amdgpu_display_manager
*dm
,
97 struct amdgpu_dm_connector
*amdgpu_dm_connector
,
99 struct amdgpu_encoder
*amdgpu_encoder
);
100 static int amdgpu_dm_encoder_init(struct drm_device
*dev
,
101 struct amdgpu_encoder
*aencoder
,
102 uint32_t link_index
);
104 static int amdgpu_dm_connector_get_modes(struct drm_connector
*connector
);
106 static int amdgpu_dm_atomic_commit(struct drm_device
*dev
,
107 struct drm_atomic_state
*state
,
110 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state
*state
);
112 static int amdgpu_dm_atomic_check(struct drm_device
*dev
,
113 struct drm_atomic_state
*state
);
118 static const enum drm_plane_type dm_plane_type_default
[AMDGPU_MAX_PLANES
] = {
119 DRM_PLANE_TYPE_PRIMARY
,
120 DRM_PLANE_TYPE_PRIMARY
,
121 DRM_PLANE_TYPE_PRIMARY
,
122 DRM_PLANE_TYPE_PRIMARY
,
123 DRM_PLANE_TYPE_PRIMARY
,
124 DRM_PLANE_TYPE_PRIMARY
,
127 static const enum drm_plane_type dm_plane_type_carizzo
[AMDGPU_MAX_PLANES
] = {
128 DRM_PLANE_TYPE_PRIMARY
,
129 DRM_PLANE_TYPE_PRIMARY
,
130 DRM_PLANE_TYPE_PRIMARY
,
131 DRM_PLANE_TYPE_OVERLAY
,/* YUV Capable Underlay */
134 static const enum drm_plane_type dm_plane_type_stoney
[AMDGPU_MAX_PLANES
] = {
135 DRM_PLANE_TYPE_PRIMARY
,
136 DRM_PLANE_TYPE_PRIMARY
,
137 DRM_PLANE_TYPE_OVERLAY
, /* YUV Capable Underlay */
141 * dm_vblank_get_counter
144 * Get counter for number of vertical blanks
147 * struct amdgpu_device *adev - [in] desired amdgpu device
148 * int disp_idx - [in] which CRTC to get the counter from
151 * Counter for vertical blanks
153 static u32
dm_vblank_get_counter(struct amdgpu_device
*adev
, int crtc
)
155 if (crtc
>= adev
->mode_info
.num_crtc
)
158 struct amdgpu_crtc
*acrtc
= adev
->mode_info
.crtcs
[crtc
];
159 struct dm_crtc_state
*acrtc_state
= to_dm_crtc_state(
163 if (acrtc_state
->stream
== NULL
) {
164 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
169 return dc_stream_get_vblank_counter(acrtc_state
->stream
);
173 static int dm_crtc_get_scanoutpos(struct amdgpu_device
*adev
, int crtc
,
174 u32
*vbl
, u32
*position
)
176 uint32_t v_blank_start
, v_blank_end
, h_position
, v_position
;
178 if ((crtc
< 0) || (crtc
>= adev
->mode_info
.num_crtc
))
181 struct amdgpu_crtc
*acrtc
= adev
->mode_info
.crtcs
[crtc
];
182 struct dm_crtc_state
*acrtc_state
= to_dm_crtc_state(
185 if (acrtc_state
->stream
== NULL
) {
186 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
192 * TODO rework base driver to use values directly.
193 * for now parse it back into reg-format
195 dc_stream_get_scanoutpos(acrtc_state
->stream
,
201 *position
= v_position
| (h_position
<< 16);
202 *vbl
= v_blank_start
| (v_blank_end
<< 16);
208 static bool dm_is_idle(void *handle
)
214 static int dm_wait_for_idle(void *handle
)
220 static bool dm_check_soft_reset(void *handle
)
225 static int dm_soft_reset(void *handle
)
231 static struct amdgpu_crtc
*
232 get_crtc_by_otg_inst(struct amdgpu_device
*adev
,
235 struct drm_device
*dev
= adev
->ddev
;
236 struct drm_crtc
*crtc
;
237 struct amdgpu_crtc
*amdgpu_crtc
;
240 * following if is check inherited from both functions where this one is
241 * used now. Need to be checked why it could happen.
243 if (otg_inst
== -1) {
245 return adev
->mode_info
.crtcs
[0];
248 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
249 amdgpu_crtc
= to_amdgpu_crtc(crtc
);
251 if (amdgpu_crtc
->otg_inst
== otg_inst
)
258 static void dm_pflip_high_irq(void *interrupt_params
)
260 struct amdgpu_crtc
*amdgpu_crtc
;
261 struct common_irq_params
*irq_params
= interrupt_params
;
262 struct amdgpu_device
*adev
= irq_params
->adev
;
265 amdgpu_crtc
= get_crtc_by_otg_inst(adev
, irq_params
->irq_src
- IRQ_TYPE_PFLIP
);
267 /* IRQ could occur when in initial stage */
268 /*TODO work and BO cleanup */
269 if (amdgpu_crtc
== NULL
) {
270 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
274 spin_lock_irqsave(&adev
->ddev
->event_lock
, flags
);
276 if (amdgpu_crtc
->pflip_status
!= AMDGPU_FLIP_SUBMITTED
){
277 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
278 amdgpu_crtc
->pflip_status
,
279 AMDGPU_FLIP_SUBMITTED
,
280 amdgpu_crtc
->crtc_id
,
282 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
287 /* wakeup usersapce */
288 if (amdgpu_crtc
->event
) {
289 /* Update to correct count/ts if racing with vblank irq */
290 drm_crtc_accurate_vblank_count(&amdgpu_crtc
->base
);
292 drm_crtc_send_vblank_event(&amdgpu_crtc
->base
, amdgpu_crtc
->event
);
294 /* page flip completed. clean up */
295 amdgpu_crtc
->event
= NULL
;
300 amdgpu_crtc
->pflip_status
= AMDGPU_FLIP_NONE
;
301 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
303 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
304 __func__
, amdgpu_crtc
->crtc_id
, amdgpu_crtc
);
306 drm_crtc_vblank_put(&amdgpu_crtc
->base
);
309 static void dm_crtc_high_irq(void *interrupt_params
)
311 struct common_irq_params
*irq_params
= interrupt_params
;
312 struct amdgpu_device
*adev
= irq_params
->adev
;
313 uint8_t crtc_index
= 0;
314 struct amdgpu_crtc
*acrtc
;
316 acrtc
= get_crtc_by_otg_inst(adev
, irq_params
->irq_src
- IRQ_TYPE_VBLANK
);
319 crtc_index
= acrtc
->crtc_id
;
321 drm_handle_vblank(adev
->ddev
, crtc_index
);
324 static int dm_set_clockgating_state(void *handle
,
325 enum amd_clockgating_state state
)
330 static int dm_set_powergating_state(void *handle
,
331 enum amd_powergating_state state
)
336 /* Prototypes of private functions */
337 static int dm_early_init(void* handle
);
339 static void hotplug_notify_work_func(struct work_struct
*work
)
341 struct amdgpu_display_manager
*dm
= container_of(work
, struct amdgpu_display_manager
, mst_hotplug_work
);
342 struct drm_device
*dev
= dm
->ddev
;
344 drm_kms_helper_hotplug_event(dev
);
348 #include "dal_asic_id.h"
349 /* Allocate memory for FBC compressed data */
350 /* TODO: Dynamic allocation */
351 #define AMDGPU_FBC_SIZE (3840 * 2160 * 4)
353 static void amdgpu_dm_initialize_fbc(struct amdgpu_device
*adev
)
356 struct dm_comressor_info
*compressor
= &adev
->dm
.compressor
;
358 if (!compressor
->bo_ptr
) {
359 r
= amdgpu_bo_create_kernel(adev
, AMDGPU_FBC_SIZE
, PAGE_SIZE
,
360 AMDGPU_GEM_DOMAIN_VRAM
, &compressor
->bo_ptr
,
361 &compressor
->gpu_addr
, &compressor
->cpu_addr
);
364 DRM_ERROR("DM: Failed to initialize fbc\n");
373 * Returns 0 on success
375 static int amdgpu_dm_init(struct amdgpu_device
*adev
)
377 struct dc_init_data init_data
;
378 adev
->dm
.ddev
= adev
->ddev
;
379 adev
->dm
.adev
= adev
;
381 /* Zero all the fields */
382 memset(&init_data
, 0, sizeof(init_data
));
384 /* initialize DAL's lock (for SYNC context use) */
385 spin_lock_init(&adev
->dm
.dal_lock
);
387 /* initialize DAL's mutex */
388 mutex_init(&adev
->dm
.dal_mutex
);
390 if(amdgpu_dm_irq_init(adev
)) {
391 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
395 init_data
.asic_id
.chip_family
= adev
->family
;
397 init_data
.asic_id
.pci_revision_id
= adev
->rev_id
;
398 init_data
.asic_id
.hw_internal_rev
= adev
->external_rev_id
;
400 init_data
.asic_id
.vram_width
= adev
->mc
.vram_width
;
401 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
402 init_data
.asic_id
.atombios_base_address
=
403 adev
->mode_info
.atom_context
->bios
;
405 init_data
.driver
= adev
;
407 adev
->dm
.cgs_device
= amdgpu_cgs_create_device(adev
);
409 if (!adev
->dm
.cgs_device
) {
410 DRM_ERROR("amdgpu: failed to create cgs device.\n");
414 init_data
.cgs_device
= adev
->dm
.cgs_device
;
418 init_data
.dce_environment
= DCE_ENV_PRODUCTION_DRV
;
421 init_data
.log_mask
= DC_DEFAULT_LOG_MASK
;
423 init_data
.log_mask
= DC_MIN_LOG_MASK
;
426 if (adev
->family
== FAMILY_CZ
)
427 amdgpu_dm_initialize_fbc(adev
);
428 init_data
.fbc_gpu_addr
= adev
->dm
.compressor
.gpu_addr
;
430 /* Display Core create. */
431 adev
->dm
.dc
= dc_create(&init_data
);
434 DRM_INFO("Display Core initialized!\n");
436 DRM_INFO("Display Core failed to initialize!\n");
438 INIT_WORK(&adev
->dm
.mst_hotplug_work
, hotplug_notify_work_func
);
440 adev
->dm
.freesync_module
= mod_freesync_create(adev
->dm
.dc
);
441 if (!adev
->dm
.freesync_module
) {
443 "amdgpu: failed to initialize freesync_module.\n");
445 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
446 adev
->dm
.freesync_module
);
448 if (amdgpu_dm_initialize_drm_device(adev
)) {
450 "amdgpu: failed to initialize sw for display support.\n");
454 /* Update the actual used number of crtc */
455 adev
->mode_info
.num_crtc
= adev
->dm
.display_indexes_num
;
457 /* TODO: Add_display_info? */
459 /* TODO use dynamic cursor width */
460 adev
->ddev
->mode_config
.cursor_width
= adev
->dm
.dc
->caps
.max_cursor_size
;
461 adev
->ddev
->mode_config
.cursor_height
= adev
->dm
.dc
->caps
.max_cursor_size
;
463 if (drm_vblank_init(adev
->ddev
, adev
->dm
.display_indexes_num
)) {
465 "amdgpu: failed to initialize sw for display support.\n");
469 DRM_DEBUG_DRIVER("KMS initialized.\n");
473 amdgpu_dm_fini(adev
);
478 static void amdgpu_dm_fini(struct amdgpu_device
*adev
)
480 amdgpu_dm_destroy_drm_device(&adev
->dm
);
482 * TODO: pageflip, vlank interrupt
484 * amdgpu_dm_irq_fini(adev);
487 if (adev
->dm
.cgs_device
) {
488 amdgpu_cgs_destroy_device(adev
->dm
.cgs_device
);
489 adev
->dm
.cgs_device
= NULL
;
491 if (adev
->dm
.freesync_module
) {
492 mod_freesync_destroy(adev
->dm
.freesync_module
);
493 adev
->dm
.freesync_module
= NULL
;
495 /* DC Destroy TODO: Replace destroy DAL */
497 dc_destroy(&adev
->dm
.dc
);
501 static int dm_sw_init(void *handle
)
506 static int dm_sw_fini(void *handle
)
511 static int detect_mst_link_for_all_connectors(struct drm_device
*dev
)
513 struct amdgpu_dm_connector
*aconnector
;
514 struct drm_connector
*connector
;
517 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
519 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
520 aconnector
= to_amdgpu_dm_connector(connector
);
521 if (aconnector
->dc_link
->type
== dc_connection_mst_branch
) {
522 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
523 aconnector
, aconnector
->base
.base
.id
);
525 ret
= drm_dp_mst_topology_mgr_set_mst(&aconnector
->mst_mgr
, true);
527 DRM_ERROR("DM_MST: Failed to start MST\n");
528 ((struct dc_link
*)aconnector
->dc_link
)->type
= dc_connection_single
;
534 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
538 static int dm_late_init(void *handle
)
540 struct drm_device
*dev
= ((struct amdgpu_device
*)handle
)->ddev
;
541 int r
= detect_mst_link_for_all_connectors(dev
);
546 static void s3_handle_mst(struct drm_device
*dev
, bool suspend
)
548 struct amdgpu_dm_connector
*aconnector
;
549 struct drm_connector
*connector
;
551 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
553 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
554 aconnector
= to_amdgpu_dm_connector(connector
);
555 if (aconnector
->dc_link
->type
== dc_connection_mst_branch
&&
556 !aconnector
->mst_port
) {
559 drm_dp_mst_topology_mgr_suspend(&aconnector
->mst_mgr
);
561 drm_dp_mst_topology_mgr_resume(&aconnector
->mst_mgr
);
565 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
568 static int dm_hw_init(void *handle
)
570 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
571 /* Create DAL display manager */
572 amdgpu_dm_init(adev
);
573 amdgpu_dm_hpd_init(adev
);
578 static int dm_hw_fini(void *handle
)
580 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
582 amdgpu_dm_hpd_fini(adev
);
584 amdgpu_dm_irq_fini(adev
);
585 amdgpu_dm_fini(adev
);
589 static int dm_suspend(void *handle
)
591 struct amdgpu_device
*adev
= handle
;
592 struct amdgpu_display_manager
*dm
= &adev
->dm
;
595 s3_handle_mst(adev
->ddev
, true);
597 amdgpu_dm_irq_suspend(adev
);
599 WARN_ON(adev
->dm
.cached_state
);
600 adev
->dm
.cached_state
= drm_atomic_helper_suspend(adev
->ddev
);
604 DC_ACPI_CM_POWER_STATE_D3
610 static struct amdgpu_dm_connector
*
611 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state
*state
,
612 struct drm_crtc
*crtc
)
615 struct drm_connector_state
*new_con_state
;
616 struct drm_connector
*connector
;
617 struct drm_crtc
*crtc_from_state
;
619 for_each_new_connector_in_state(state
, connector
, new_con_state
, i
) {
620 crtc_from_state
= new_con_state
->crtc
;
622 if (crtc_from_state
== crtc
)
623 return to_amdgpu_dm_connector(connector
);
629 static int dm_resume(void *handle
)
631 struct amdgpu_device
*adev
= handle
;
632 struct amdgpu_display_manager
*dm
= &adev
->dm
;
634 /* power on hardware */
637 DC_ACPI_CM_POWER_STATE_D0
643 int amdgpu_dm_display_resume(struct amdgpu_device
*adev
)
645 struct drm_device
*ddev
= adev
->ddev
;
646 struct amdgpu_display_manager
*dm
= &adev
->dm
;
647 struct amdgpu_dm_connector
*aconnector
;
648 struct drm_connector
*connector
;
649 struct drm_crtc
*crtc
;
650 struct drm_crtc_state
*new_crtc_state
;
654 /* program HPD filter */
657 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
658 s3_handle_mst(ddev
, false);
661 * early enable HPD Rx IRQ, should be done before set mode as short
662 * pulse interrupts are used for MST
664 amdgpu_dm_irq_resume_early(adev
);
667 list_for_each_entry(connector
,
668 &ddev
->mode_config
.connector_list
, head
) {
669 aconnector
= to_amdgpu_dm_connector(connector
);
672 * this is the case when traversing through already created
673 * MST connectors, should be skipped
675 if (aconnector
->mst_port
)
678 mutex_lock(&aconnector
->hpd_lock
);
679 dc_link_detect(aconnector
->dc_link
, DETECT_REASON_HPD
);
680 aconnector
->dc_sink
= NULL
;
681 amdgpu_dm_update_connector_after_detect(aconnector
);
682 mutex_unlock(&aconnector
->hpd_lock
);
685 /* Force mode set in atomic comit */
686 for_each_new_crtc_in_state(adev
->dm
.cached_state
, crtc
, new_crtc_state
, i
)
687 new_crtc_state
->active_changed
= true;
689 ret
= drm_atomic_helper_resume(ddev
, adev
->dm
.cached_state
);
691 drm_atomic_state_put(adev
->dm
.cached_state
);
692 adev
->dm
.cached_state
= NULL
;
694 amdgpu_dm_irq_resume_late(adev
);
699 static const struct amd_ip_funcs amdgpu_dm_funcs
= {
701 .early_init
= dm_early_init
,
702 .late_init
= dm_late_init
,
703 .sw_init
= dm_sw_init
,
704 .sw_fini
= dm_sw_fini
,
705 .hw_init
= dm_hw_init
,
706 .hw_fini
= dm_hw_fini
,
707 .suspend
= dm_suspend
,
709 .is_idle
= dm_is_idle
,
710 .wait_for_idle
= dm_wait_for_idle
,
711 .check_soft_reset
= dm_check_soft_reset
,
712 .soft_reset
= dm_soft_reset
,
713 .set_clockgating_state
= dm_set_clockgating_state
,
714 .set_powergating_state
= dm_set_powergating_state
,
717 const struct amdgpu_ip_block_version dm_ip_block
=
719 .type
= AMD_IP_BLOCK_TYPE_DCE
,
723 .funcs
= &amdgpu_dm_funcs
,
727 static struct drm_atomic_state
*
728 dm_atomic_state_alloc(struct drm_device
*dev
)
730 struct dm_atomic_state
*state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
735 if (drm_atomic_state_init(dev
, &state
->base
) < 0)
746 dm_atomic_state_clear(struct drm_atomic_state
*state
)
748 struct dm_atomic_state
*dm_state
= to_dm_atomic_state(state
);
750 if (dm_state
->context
) {
751 dc_release_state(dm_state
->context
);
752 dm_state
->context
= NULL
;
755 drm_atomic_state_default_clear(state
);
759 dm_atomic_state_alloc_free(struct drm_atomic_state
*state
)
761 struct dm_atomic_state
*dm_state
= to_dm_atomic_state(state
);
762 drm_atomic_state_default_release(state
);
766 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs
= {
767 .fb_create
= amdgpu_user_framebuffer_create
,
768 .output_poll_changed
= amdgpu_output_poll_changed
,
769 .atomic_check
= amdgpu_dm_atomic_check
,
770 .atomic_commit
= amdgpu_dm_atomic_commit
,
771 .atomic_state_alloc
= dm_atomic_state_alloc
,
772 .atomic_state_clear
= dm_atomic_state_clear
,
773 .atomic_state_free
= dm_atomic_state_alloc_free
776 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs
= {
777 .atomic_commit_tail
= amdgpu_dm_atomic_commit_tail
781 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector
*aconnector
)
783 struct drm_connector
*connector
= &aconnector
->base
;
784 struct drm_device
*dev
= connector
->dev
;
785 struct dc_sink
*sink
;
787 /* MST handled by drm_mst framework */
788 if (aconnector
->mst_mgr
.mst_state
== true)
792 sink
= aconnector
->dc_link
->local_sink
;
794 /* Edid mgmt connector gets first update only in mode_valid hook and then
795 * the connector sink is set to either fake or physical sink depends on link status.
796 * don't do it here if u are during boot
798 if (aconnector
->base
.force
!= DRM_FORCE_UNSPECIFIED
799 && aconnector
->dc_em_sink
) {
801 /* For S3 resume with headless use eml_sink to fake stream
802 * because on resume connecotr->sink is set ti NULL
804 mutex_lock(&dev
->mode_config
.mutex
);
807 if (aconnector
->dc_sink
) {
808 amdgpu_dm_remove_sink_from_freesync_module(
810 /* retain and release bellow are used for
811 * bump up refcount for sink because the link don't point
812 * to it anymore after disconnect so on next crtc to connector
813 * reshuffle by UMD we will get into unwanted dc_sink release
815 if (aconnector
->dc_sink
!= aconnector
->dc_em_sink
)
816 dc_sink_release(aconnector
->dc_sink
);
818 aconnector
->dc_sink
= sink
;
819 amdgpu_dm_add_sink_to_freesync_module(
820 connector
, aconnector
->edid
);
822 amdgpu_dm_remove_sink_from_freesync_module(connector
);
823 if (!aconnector
->dc_sink
)
824 aconnector
->dc_sink
= aconnector
->dc_em_sink
;
825 else if (aconnector
->dc_sink
!= aconnector
->dc_em_sink
)
826 dc_sink_retain(aconnector
->dc_sink
);
829 mutex_unlock(&dev
->mode_config
.mutex
);
834 * TODO: temporary guard to look for proper fix
835 * if this sink is MST sink, we should not do anything
837 if (sink
&& sink
->sink_signal
== SIGNAL_TYPE_DISPLAY_PORT_MST
)
840 if (aconnector
->dc_sink
== sink
) {
841 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
843 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
844 aconnector
->connector_id
);
848 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
849 aconnector
->connector_id
, aconnector
->dc_sink
, sink
);
851 mutex_lock(&dev
->mode_config
.mutex
);
853 /* 1. Update status of the drm connector
854 * 2. Send an event and let userspace tell us what to do */
856 /* TODO: check if we still need the S3 mode update workaround.
857 * If yes, put it here. */
858 if (aconnector
->dc_sink
)
859 amdgpu_dm_remove_sink_from_freesync_module(
862 aconnector
->dc_sink
= sink
;
863 if (sink
->dc_edid
.length
== 0)
864 aconnector
->edid
= NULL
;
867 (struct edid
*) sink
->dc_edid
.raw_edid
;
870 drm_mode_connector_update_edid_property(connector
,
873 amdgpu_dm_add_sink_to_freesync_module(connector
, aconnector
->edid
);
876 amdgpu_dm_remove_sink_from_freesync_module(connector
);
877 drm_mode_connector_update_edid_property(connector
, NULL
);
878 aconnector
->num_modes
= 0;
879 aconnector
->dc_sink
= NULL
;
882 mutex_unlock(&dev
->mode_config
.mutex
);
885 static void handle_hpd_irq(void *param
)
887 struct amdgpu_dm_connector
*aconnector
= (struct amdgpu_dm_connector
*)param
;
888 struct drm_connector
*connector
= &aconnector
->base
;
889 struct drm_device
*dev
= connector
->dev
;
891 /* In case of failure or MST no need to update connector status or notify the OS
892 * since (for MST case) MST does this in it's own context.
894 mutex_lock(&aconnector
->hpd_lock
);
896 if (aconnector
->fake_enable
)
897 aconnector
->fake_enable
= false;
899 if (dc_link_detect(aconnector
->dc_link
, DETECT_REASON_HPD
)) {
900 amdgpu_dm_update_connector_after_detect(aconnector
);
903 drm_modeset_lock_all(dev
);
904 dm_restore_drm_connector_state(dev
, connector
);
905 drm_modeset_unlock_all(dev
);
907 if (aconnector
->base
.force
== DRM_FORCE_UNSPECIFIED
)
908 drm_kms_helper_hotplug_event(dev
);
910 mutex_unlock(&aconnector
->hpd_lock
);
914 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector
*aconnector
)
916 uint8_t esi
[DP_PSR_ERROR_STATUS
- DP_SINK_COUNT_ESI
] = { 0 };
918 bool new_irq_handled
= false;
920 int dpcd_bytes_to_read
;
922 const int max_process_count
= 30;
923 int process_count
= 0;
925 const struct dc_link_status
*link_status
= dc_link_get_status(aconnector
->dc_link
);
927 if (link_status
->dpcd_caps
->dpcd_rev
.raw
< 0x12) {
928 dpcd_bytes_to_read
= DP_LANE0_1_STATUS
- DP_SINK_COUNT
;
929 /* DPCD 0x200 - 0x201 for downstream IRQ */
930 dpcd_addr
= DP_SINK_COUNT
;
932 dpcd_bytes_to_read
= DP_PSR_ERROR_STATUS
- DP_SINK_COUNT_ESI
;
933 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
934 dpcd_addr
= DP_SINK_COUNT_ESI
;
937 dret
= drm_dp_dpcd_read(
938 &aconnector
->dm_dp_aux
.aux
,
943 while (dret
== dpcd_bytes_to_read
&&
944 process_count
< max_process_count
) {
950 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
951 /* handle HPD short pulse irq */
952 if (aconnector
->mst_mgr
.mst_state
)
954 &aconnector
->mst_mgr
,
958 if (new_irq_handled
) {
959 /* ACK at DPCD to notify down stream */
960 const int ack_dpcd_bytes_to_write
=
961 dpcd_bytes_to_read
- 1;
963 for (retry
= 0; retry
< 3; retry
++) {
966 wret
= drm_dp_dpcd_write(
967 &aconnector
->dm_dp_aux
.aux
,
970 ack_dpcd_bytes_to_write
);
971 if (wret
== ack_dpcd_bytes_to_write
)
975 /* check if there is new irq to be handle */
976 dret
= drm_dp_dpcd_read(
977 &aconnector
->dm_dp_aux
.aux
,
982 new_irq_handled
= false;
987 if (process_count
== max_process_count
)
988 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
991 static void handle_hpd_rx_irq(void *param
)
993 struct amdgpu_dm_connector
*aconnector
= (struct amdgpu_dm_connector
*)param
;
994 struct drm_connector
*connector
= &aconnector
->base
;
995 struct drm_device
*dev
= connector
->dev
;
996 const struct dc_link
*dc_link
= aconnector
->dc_link
;
997 bool is_mst_root_connector
= aconnector
->mst_mgr
.mst_state
;
999 /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1000 * conflict, after implement i2c helper, this mutex should be
1003 if (aconnector
->dc_link
->type
!= dc_connection_mst_branch
)
1004 mutex_lock(&aconnector
->hpd_lock
);
1006 if (dc_link_handle_hpd_rx_irq(aconnector
->dc_link
, NULL
) &&
1007 !is_mst_root_connector
) {
1008 /* Downstream Port status changed. */
1009 if (dc_link_detect(aconnector
->dc_link
, DETECT_REASON_HPDRX
)) {
1010 amdgpu_dm_update_connector_after_detect(aconnector
);
1013 drm_modeset_lock_all(dev
);
1014 dm_restore_drm_connector_state(dev
, connector
);
1015 drm_modeset_unlock_all(dev
);
1017 drm_kms_helper_hotplug_event(dev
);
1020 if ((dc_link
->cur_link_settings
.lane_count
!= LANE_COUNT_UNKNOWN
) ||
1021 (dc_link
->type
== dc_connection_mst_branch
))
1022 dm_handle_hpd_rx_irq(aconnector
);
1024 if (aconnector
->dc_link
->type
!= dc_connection_mst_branch
)
1025 mutex_unlock(&aconnector
->hpd_lock
);
1028 static void register_hpd_handlers(struct amdgpu_device
*adev
)
1030 struct drm_device
*dev
= adev
->ddev
;
1031 struct drm_connector
*connector
;
1032 struct amdgpu_dm_connector
*aconnector
;
1033 const struct dc_link
*dc_link
;
1034 struct dc_interrupt_params int_params
= {0};
1036 int_params
.requested_polarity
= INTERRUPT_POLARITY_DEFAULT
;
1037 int_params
.current_polarity
= INTERRUPT_POLARITY_DEFAULT
;
1039 list_for_each_entry(connector
,
1040 &dev
->mode_config
.connector_list
, head
) {
1042 aconnector
= to_amdgpu_dm_connector(connector
);
1043 dc_link
= aconnector
->dc_link
;
1045 if (DC_IRQ_SOURCE_INVALID
!= dc_link
->irq_source_hpd
) {
1046 int_params
.int_context
= INTERRUPT_LOW_IRQ_CONTEXT
;
1047 int_params
.irq_source
= dc_link
->irq_source_hpd
;
1049 amdgpu_dm_irq_register_interrupt(adev
, &int_params
,
1051 (void *) aconnector
);
1054 if (DC_IRQ_SOURCE_INVALID
!= dc_link
->irq_source_hpd_rx
) {
1056 /* Also register for DP short pulse (hpd_rx). */
1057 int_params
.int_context
= INTERRUPT_LOW_IRQ_CONTEXT
;
1058 int_params
.irq_source
= dc_link
->irq_source_hpd_rx
;
1060 amdgpu_dm_irq_register_interrupt(adev
, &int_params
,
1062 (void *) aconnector
);
1067 /* Register IRQ sources and initialize IRQ callbacks */
1068 static int dce110_register_irq_handlers(struct amdgpu_device
*adev
)
1070 struct dc
*dc
= adev
->dm
.dc
;
1071 struct common_irq_params
*c_irq_params
;
1072 struct dc_interrupt_params int_params
= {0};
1075 unsigned client_id
= AMDGPU_IH_CLIENTID_LEGACY
;
1077 if (adev
->asic_type
== CHIP_VEGA10
||
1078 adev
->asic_type
== CHIP_RAVEN
)
1079 client_id
= AMDGPU_IH_CLIENTID_DCE
;
1081 int_params
.requested_polarity
= INTERRUPT_POLARITY_DEFAULT
;
1082 int_params
.current_polarity
= INTERRUPT_POLARITY_DEFAULT
;
1084 /* Actions of amdgpu_irq_add_id():
1085 * 1. Register a set() function with base driver.
1086 * Base driver will call set() function to enable/disable an
1087 * interrupt in DC hardware.
1088 * 2. Register amdgpu_dm_irq_handler().
1089 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1090 * coming from DC hardware.
1091 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1092 * for acknowledging and handling. */
1094 /* Use VBLANK interrupt */
1095 for (i
= VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0
; i
<= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0
; i
++) {
1096 r
= amdgpu_irq_add_id(adev
, client_id
, i
, &adev
->crtc_irq
);
1098 DRM_ERROR("Failed to add crtc irq id!\n");
1102 int_params
.int_context
= INTERRUPT_HIGH_IRQ_CONTEXT
;
1103 int_params
.irq_source
=
1104 dc_interrupt_to_irq_source(dc
, i
, 0);
1106 c_irq_params
= &adev
->dm
.vblank_params
[int_params
.irq_source
- DC_IRQ_SOURCE_VBLANK1
];
1108 c_irq_params
->adev
= adev
;
1109 c_irq_params
->irq_src
= int_params
.irq_source
;
1111 amdgpu_dm_irq_register_interrupt(adev
, &int_params
,
1112 dm_crtc_high_irq
, c_irq_params
);
1115 /* Use GRPH_PFLIP interrupt */
1116 for (i
= VISLANDS30_IV_SRCID_D1_GRPH_PFLIP
;
1117 i
<= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP
; i
+= 2) {
1118 r
= amdgpu_irq_add_id(adev
, client_id
, i
, &adev
->pageflip_irq
);
1120 DRM_ERROR("Failed to add page flip irq id!\n");
1124 int_params
.int_context
= INTERRUPT_HIGH_IRQ_CONTEXT
;
1125 int_params
.irq_source
=
1126 dc_interrupt_to_irq_source(dc
, i
, 0);
1128 c_irq_params
= &adev
->dm
.pflip_params
[int_params
.irq_source
- DC_IRQ_SOURCE_PFLIP_FIRST
];
1130 c_irq_params
->adev
= adev
;
1131 c_irq_params
->irq_src
= int_params
.irq_source
;
1133 amdgpu_dm_irq_register_interrupt(adev
, &int_params
,
1134 dm_pflip_high_irq
, c_irq_params
);
1139 r
= amdgpu_irq_add_id(adev
, client_id
,
1140 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A
, &adev
->hpd_irq
);
1142 DRM_ERROR("Failed to add hpd irq id!\n");
1146 register_hpd_handlers(adev
);
1151 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1152 /* Register IRQ sources and initialize IRQ callbacks */
1153 static int dcn10_register_irq_handlers(struct amdgpu_device
*adev
)
1155 struct dc
*dc
= adev
->dm
.dc
;
1156 struct common_irq_params
*c_irq_params
;
1157 struct dc_interrupt_params int_params
= {0};
1161 int_params
.requested_polarity
= INTERRUPT_POLARITY_DEFAULT
;
1162 int_params
.current_polarity
= INTERRUPT_POLARITY_DEFAULT
;
1164 /* Actions of amdgpu_irq_add_id():
1165 * 1. Register a set() function with base driver.
1166 * Base driver will call set() function to enable/disable an
1167 * interrupt in DC hardware.
1168 * 2. Register amdgpu_dm_irq_handler().
1169 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1170 * coming from DC hardware.
1171 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1172 * for acknowledging and handling.
1175 /* Use VSTARTUP interrupt */
1176 for (i
= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP
;
1177 i
<= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP
+ adev
->mode_info
.num_crtc
- 1;
1179 r
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_DCE
, i
, &adev
->crtc_irq
);
1182 DRM_ERROR("Failed to add crtc irq id!\n");
1186 int_params
.int_context
= INTERRUPT_HIGH_IRQ_CONTEXT
;
1187 int_params
.irq_source
=
1188 dc_interrupt_to_irq_source(dc
, i
, 0);
1190 c_irq_params
= &adev
->dm
.vblank_params
[int_params
.irq_source
- DC_IRQ_SOURCE_VBLANK1
];
1192 c_irq_params
->adev
= adev
;
1193 c_irq_params
->irq_src
= int_params
.irq_source
;
1195 amdgpu_dm_irq_register_interrupt(adev
, &int_params
,
1196 dm_crtc_high_irq
, c_irq_params
);
1199 /* Use GRPH_PFLIP interrupt */
1200 for (i
= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT
;
1201 i
<= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT
+ adev
->mode_info
.num_crtc
- 1;
1203 r
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_DCE
, i
, &adev
->pageflip_irq
);
1205 DRM_ERROR("Failed to add page flip irq id!\n");
1209 int_params
.int_context
= INTERRUPT_HIGH_IRQ_CONTEXT
;
1210 int_params
.irq_source
=
1211 dc_interrupt_to_irq_source(dc
, i
, 0);
1213 c_irq_params
= &adev
->dm
.pflip_params
[int_params
.irq_source
- DC_IRQ_SOURCE_PFLIP_FIRST
];
1215 c_irq_params
->adev
= adev
;
1216 c_irq_params
->irq_src
= int_params
.irq_source
;
1218 amdgpu_dm_irq_register_interrupt(adev
, &int_params
,
1219 dm_pflip_high_irq
, c_irq_params
);
1224 r
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_DCE
, DCN_1_0__SRCID__DC_HPD1_INT
,
1227 DRM_ERROR("Failed to add hpd irq id!\n");
1231 register_hpd_handlers(adev
);
1237 static int amdgpu_dm_mode_config_init(struct amdgpu_device
*adev
)
1241 adev
->mode_info
.mode_config_initialized
= true;
1243 adev
->ddev
->mode_config
.funcs
= (void *)&amdgpu_dm_mode_funcs
;
1244 adev
->ddev
->mode_config
.helper_private
= &amdgpu_dm_mode_config_helperfuncs
;
1246 adev
->ddev
->mode_config
.max_width
= 16384;
1247 adev
->ddev
->mode_config
.max_height
= 16384;
1249 adev
->ddev
->mode_config
.preferred_depth
= 24;
1250 adev
->ddev
->mode_config
.prefer_shadow
= 1;
1251 /* indicate support of immediate flip */
1252 adev
->ddev
->mode_config
.async_page_flip
= true;
1254 adev
->ddev
->mode_config
.fb_base
= adev
->mc
.aper_base
;
1256 r
= amdgpu_modeset_create_props(adev
);
1263 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1264 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1266 static int amdgpu_dm_backlight_update_status(struct backlight_device
*bd
)
1268 struct amdgpu_display_manager
*dm
= bl_get_data(bd
);
1270 if (dc_link_set_backlight_level(dm
->backlight_link
,
1271 bd
->props
.brightness
, 0, 0))
1277 static int amdgpu_dm_backlight_get_brightness(struct backlight_device
*bd
)
1279 return bd
->props
.brightness
;
1282 static const struct backlight_ops amdgpu_dm_backlight_ops
= {
1283 .get_brightness
= amdgpu_dm_backlight_get_brightness
,
1284 .update_status
= amdgpu_dm_backlight_update_status
,
1288 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager
*dm
)
1291 struct backlight_properties props
= { 0 };
1293 props
.max_brightness
= AMDGPU_MAX_BL_LEVEL
;
1294 props
.type
= BACKLIGHT_RAW
;
1296 snprintf(bl_name
, sizeof(bl_name
), "amdgpu_bl%d",
1297 dm
->adev
->ddev
->primary
->index
);
1299 dm
->backlight_dev
= backlight_device_register(bl_name
,
1300 dm
->adev
->ddev
->dev
,
1302 &amdgpu_dm_backlight_ops
,
1305 if (NULL
== dm
->backlight_dev
)
1306 DRM_ERROR("DM: Backlight registration failed!\n");
1308 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name
);
1313 /* In this architecture, the association
1314 * connector -> encoder -> crtc
1315 * id not really requried. The crtc and connector will hold the
1316 * display_index as an abstraction to use with DAL component
1318 * Returns 0 on success
1320 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device
*adev
)
1322 struct amdgpu_display_manager
*dm
= &adev
->dm
;
1324 struct amdgpu_dm_connector
*aconnector
= NULL
;
1325 struct amdgpu_encoder
*aencoder
= NULL
;
1326 struct amdgpu_mode_info
*mode_info
= &adev
->mode_info
;
1328 unsigned long possible_crtcs
;
1330 link_cnt
= dm
->dc
->caps
.max_links
;
1331 if (amdgpu_dm_mode_config_init(dm
->adev
)) {
1332 DRM_ERROR("DM: Failed to initialize mode config\n");
1336 for (i
= 0; i
< dm
->dc
->caps
.max_planes
; i
++) {
1337 mode_info
->planes
[i
] = kzalloc(sizeof(struct amdgpu_plane
),
1339 if (!mode_info
->planes
[i
]) {
1340 DRM_ERROR("KMS: Failed to allocate plane\n");
1341 goto fail_free_planes
;
1343 mode_info
->planes
[i
]->base
.type
= mode_info
->plane_type
[i
];
1346 * HACK: IGT tests expect that each plane can only have one
1347 * one possible CRTC. For now, set one CRTC for each
1348 * plane that is not an underlay, but still allow multiple
1349 * CRTCs for underlay planes.
1351 possible_crtcs
= 1 << i
;
1352 if (i
>= dm
->dc
->caps
.max_streams
)
1353 possible_crtcs
= 0xff;
1355 if (amdgpu_dm_plane_init(dm
, mode_info
->planes
[i
], possible_crtcs
)) {
1356 DRM_ERROR("KMS: Failed to initialize plane\n");
1357 goto fail_free_planes
;
1361 for (i
= 0; i
< dm
->dc
->caps
.max_streams
; i
++)
1362 if (amdgpu_dm_crtc_init(dm
, &mode_info
->planes
[i
]->base
, i
)) {
1363 DRM_ERROR("KMS: Failed to initialize crtc\n");
1364 goto fail_free_planes
;
1367 dm
->display_indexes_num
= dm
->dc
->caps
.max_streams
;
1369 /* loops over all connectors on the board */
1370 for (i
= 0; i
< link_cnt
; i
++) {
1372 if (i
> AMDGPU_DM_MAX_DISPLAY_INDEX
) {
1374 "KMS: Cannot support more than %d display indexes\n",
1375 AMDGPU_DM_MAX_DISPLAY_INDEX
);
1379 aconnector
= kzalloc(sizeof(*aconnector
), GFP_KERNEL
);
1381 goto fail_free_planes
;
1383 aencoder
= kzalloc(sizeof(*aencoder
), GFP_KERNEL
);
1385 goto fail_free_connector
;
1388 if (amdgpu_dm_encoder_init(dm
->ddev
, aencoder
, i
)) {
1389 DRM_ERROR("KMS: Failed to initialize encoder\n");
1390 goto fail_free_encoder
;
1393 if (amdgpu_dm_connector_init(dm
, aconnector
, i
, aencoder
)) {
1394 DRM_ERROR("KMS: Failed to initialize connector\n");
1395 goto fail_free_encoder
;
1398 if (dc_link_detect(dc_get_link_at_index(dm
->dc
, i
),
1399 DETECT_REASON_BOOT
))
1400 amdgpu_dm_update_connector_after_detect(aconnector
);
1403 /* Software is initialized. Now we can register interrupt handlers. */
1404 switch (adev
->asic_type
) {
1414 case CHIP_POLARIS11
:
1415 case CHIP_POLARIS10
:
1416 case CHIP_POLARIS12
:
1418 if (dce110_register_irq_handlers(dm
->adev
)) {
1419 DRM_ERROR("DM: Failed to initialize IRQ\n");
1420 goto fail_free_encoder
;
1423 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1425 if (dcn10_register_irq_handlers(dm
->adev
)) {
1426 DRM_ERROR("DM: Failed to initialize IRQ\n");
1427 goto fail_free_encoder
;
1430 * Temporary disable until pplib/smu interaction is implemented
1432 dm
->dc
->debug
.disable_stutter
= true;
1436 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev
->asic_type
);
1437 goto fail_free_encoder
;
1440 drm_mode_config_reset(dm
->ddev
);
1445 fail_free_connector
:
1448 for (i
= 0; i
< dm
->dc
->caps
.max_planes
; i
++)
1449 kfree(mode_info
->planes
[i
]);
1453 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager
*dm
)
1455 drm_mode_config_cleanup(dm
->ddev
);
1459 /******************************************************************************
1460 * amdgpu_display_funcs functions
1461 *****************************************************************************/
1464 * dm_bandwidth_update - program display watermarks
1466 * @adev: amdgpu_device pointer
1468 * Calculate and program the display watermarks and line buffer allocation.
1470 static void dm_bandwidth_update(struct amdgpu_device
*adev
)
1472 /* TODO: implement later */
1475 static void dm_set_backlight_level(struct amdgpu_encoder
*amdgpu_encoder
,
1478 /* TODO: translate amdgpu_encoder to display_index and call DAL */
1481 static u8
dm_get_backlight_level(struct amdgpu_encoder
*amdgpu_encoder
)
1483 /* TODO: translate amdgpu_encoder to display_index and call DAL */
1487 static int amdgpu_notify_freesync(struct drm_device
*dev
, void *data
,
1488 struct drm_file
*filp
)
1490 struct mod_freesync_params freesync_params
;
1491 uint8_t num_streams
;
1494 struct amdgpu_device
*adev
= dev
->dev_private
;
1497 /* Get freesync enable flag from DRM */
1499 num_streams
= dc_get_current_stream_count(adev
->dm
.dc
);
1501 for (i
= 0; i
< num_streams
; i
++) {
1502 struct dc_stream_state
*stream
;
1503 stream
= dc_get_stream_at_index(adev
->dm
.dc
, i
);
1505 mod_freesync_update_state(adev
->dm
.freesync_module
,
1506 &stream
, 1, &freesync_params
);
1512 static const struct amdgpu_display_funcs dm_display_funcs
= {
1513 .bandwidth_update
= dm_bandwidth_update
, /* called unconditionally */
1514 .vblank_get_counter
= dm_vblank_get_counter
,/* called unconditionally */
1515 .vblank_wait
= NULL
,
1516 .backlight_set_level
=
1517 dm_set_backlight_level
,/* called unconditionally */
1518 .backlight_get_level
=
1519 dm_get_backlight_level
,/* called unconditionally */
1520 .hpd_sense
= NULL
,/* called unconditionally */
1521 .hpd_set_polarity
= NULL
, /* called unconditionally */
1522 .hpd_get_gpio_reg
= NULL
, /* VBIOS parsing. DAL does it. */
1523 .page_flip_get_scanoutpos
=
1524 dm_crtc_get_scanoutpos
,/* called unconditionally */
1525 .add_encoder
= NULL
, /* VBIOS parsing. DAL does it. */
1526 .add_connector
= NULL
, /* VBIOS parsing. DAL does it. */
1527 .notify_freesync
= amdgpu_notify_freesync
,
1531 #if defined(CONFIG_DEBUG_KERNEL_DC)
1533 static ssize_t
s3_debug_store(struct device
*device
,
1534 struct device_attribute
*attr
,
1540 struct pci_dev
*pdev
= to_pci_dev(device
);
1541 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1542 struct amdgpu_device
*adev
= drm_dev
->dev_private
;
1544 ret
= kstrtoint(buf
, 0, &s3_state
);
1549 amdgpu_dm_display_resume(adev
);
1550 drm_kms_helper_hotplug_event(adev
->ddev
);
1555 return ret
== 0 ? count
: 0;
1558 DEVICE_ATTR_WO(s3_debug
);
1562 static int dm_early_init(void *handle
)
1564 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1566 adev
->ddev
->driver
->driver_features
|= DRIVER_ATOMIC
;
1567 amdgpu_dm_set_irq_funcs(adev
);
1569 switch (adev
->asic_type
) {
1572 adev
->mode_info
.num_crtc
= 6;
1573 adev
->mode_info
.num_hpd
= 6;
1574 adev
->mode_info
.num_dig
= 6;
1575 adev
->mode_info
.plane_type
= dm_plane_type_default
;
1578 adev
->mode_info
.num_crtc
= 4;
1579 adev
->mode_info
.num_hpd
= 6;
1580 adev
->mode_info
.num_dig
= 7;
1581 adev
->mode_info
.plane_type
= dm_plane_type_default
;
1585 adev
->mode_info
.num_crtc
= 2;
1586 adev
->mode_info
.num_hpd
= 6;
1587 adev
->mode_info
.num_dig
= 6;
1588 adev
->mode_info
.plane_type
= dm_plane_type_default
;
1592 adev
->mode_info
.num_crtc
= 6;
1593 adev
->mode_info
.num_hpd
= 6;
1594 adev
->mode_info
.num_dig
= 7;
1595 adev
->mode_info
.plane_type
= dm_plane_type_default
;
1598 adev
->mode_info
.num_crtc
= 3;
1599 adev
->mode_info
.num_hpd
= 6;
1600 adev
->mode_info
.num_dig
= 9;
1601 adev
->mode_info
.plane_type
= dm_plane_type_carizzo
;
1604 adev
->mode_info
.num_crtc
= 2;
1605 adev
->mode_info
.num_hpd
= 6;
1606 adev
->mode_info
.num_dig
= 9;
1607 adev
->mode_info
.plane_type
= dm_plane_type_stoney
;
1609 case CHIP_POLARIS11
:
1610 case CHIP_POLARIS12
:
1611 adev
->mode_info
.num_crtc
= 5;
1612 adev
->mode_info
.num_hpd
= 5;
1613 adev
->mode_info
.num_dig
= 5;
1614 adev
->mode_info
.plane_type
= dm_plane_type_default
;
1616 case CHIP_POLARIS10
:
1617 adev
->mode_info
.num_crtc
= 6;
1618 adev
->mode_info
.num_hpd
= 6;
1619 adev
->mode_info
.num_dig
= 6;
1620 adev
->mode_info
.plane_type
= dm_plane_type_default
;
1623 adev
->mode_info
.num_crtc
= 6;
1624 adev
->mode_info
.num_hpd
= 6;
1625 adev
->mode_info
.num_dig
= 6;
1626 adev
->mode_info
.plane_type
= dm_plane_type_default
;
1628 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1630 adev
->mode_info
.num_crtc
= 4;
1631 adev
->mode_info
.num_hpd
= 4;
1632 adev
->mode_info
.num_dig
= 4;
1633 adev
->mode_info
.plane_type
= dm_plane_type_default
;
1637 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev
->asic_type
);
1641 if (adev
->mode_info
.funcs
== NULL
)
1642 adev
->mode_info
.funcs
= &dm_display_funcs
;
1644 /* Note: Do NOT change adev->audio_endpt_rreg and
1645 * adev->audio_endpt_wreg because they are initialised in
1646 * amdgpu_device_init() */
1647 #if defined(CONFIG_DEBUG_KERNEL_DC)
1650 &dev_attr_s3_debug
);
1656 struct dm_connector_state
{
1657 struct drm_connector_state base
;
1659 enum amdgpu_rmx_type scaling
;
1660 uint8_t underscan_vborder
;
1661 uint8_t underscan_hborder
;
1662 bool underscan_enable
;
1665 #define to_dm_connector_state(x)\
1666 container_of((x), struct dm_connector_state, base)
1668 static bool modeset_required(struct drm_crtc_state
*crtc_state
,
1669 struct dc_stream_state
*new_stream
,
1670 struct dc_stream_state
*old_stream
)
1672 if (!drm_atomic_crtc_needs_modeset(crtc_state
))
1675 if (!crtc_state
->enable
)
1678 return crtc_state
->active
;
1681 static bool modereset_required(struct drm_crtc_state
*crtc_state
)
1683 if (!drm_atomic_crtc_needs_modeset(crtc_state
))
1686 return !crtc_state
->enable
|| !crtc_state
->active
;
1689 static void amdgpu_dm_encoder_destroy(struct drm_encoder
*encoder
)
1691 drm_encoder_cleanup(encoder
);
1695 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs
= {
1696 .destroy
= amdgpu_dm_encoder_destroy
,
1699 static bool fill_rects_from_plane_state(const struct drm_plane_state
*state
,
1700 struct dc_plane_state
*plane_state
)
1702 plane_state
->src_rect
.x
= state
->src_x
>> 16;
1703 plane_state
->src_rect
.y
= state
->src_y
>> 16;
1704 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
1705 plane_state
->src_rect
.width
= state
->src_w
>> 16;
1707 if (plane_state
->src_rect
.width
== 0)
1710 plane_state
->src_rect
.height
= state
->src_h
>> 16;
1711 if (plane_state
->src_rect
.height
== 0)
1714 plane_state
->dst_rect
.x
= state
->crtc_x
;
1715 plane_state
->dst_rect
.y
= state
->crtc_y
;
1717 if (state
->crtc_w
== 0)
1720 plane_state
->dst_rect
.width
= state
->crtc_w
;
1722 if (state
->crtc_h
== 0)
1725 plane_state
->dst_rect
.height
= state
->crtc_h
;
1727 plane_state
->clip_rect
= plane_state
->dst_rect
;
1729 switch (state
->rotation
& DRM_MODE_ROTATE_MASK
) {
1730 case DRM_MODE_ROTATE_0
:
1731 plane_state
->rotation
= ROTATION_ANGLE_0
;
1733 case DRM_MODE_ROTATE_90
:
1734 plane_state
->rotation
= ROTATION_ANGLE_90
;
1736 case DRM_MODE_ROTATE_180
:
1737 plane_state
->rotation
= ROTATION_ANGLE_180
;
1739 case DRM_MODE_ROTATE_270
:
1740 plane_state
->rotation
= ROTATION_ANGLE_270
;
1743 plane_state
->rotation
= ROTATION_ANGLE_0
;
1749 static int get_fb_info(const struct amdgpu_framebuffer
*amdgpu_fb
,
1750 uint64_t *tiling_flags
,
1751 uint64_t *fb_location
)
1753 struct amdgpu_bo
*rbo
= gem_to_amdgpu_bo(amdgpu_fb
->obj
);
1754 int r
= amdgpu_bo_reserve(rbo
, false);
1757 DRM_ERROR("Unable to reserve buffer\n");
1762 *fb_location
= amdgpu_bo_gpu_offset(rbo
);
1765 amdgpu_bo_get_tiling_flags(rbo
, tiling_flags
);
1767 amdgpu_bo_unreserve(rbo
);
1772 static int fill_plane_attributes_from_fb(struct amdgpu_device
*adev
,
1773 struct dc_plane_state
*plane_state
,
1774 const struct amdgpu_framebuffer
*amdgpu_fb
,
1777 uint64_t tiling_flags
;
1778 uint64_t fb_location
= 0;
1779 unsigned int awidth
;
1780 const struct drm_framebuffer
*fb
= &amdgpu_fb
->base
;
1782 struct drm_format_name_buf format_name
;
1787 addReq
== true ? &fb_location
:NULL
);
1792 switch (fb
->format
->format
) {
1794 plane_state
->format
= SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS
;
1796 case DRM_FORMAT_RGB565
:
1797 plane_state
->format
= SURFACE_PIXEL_FORMAT_GRPH_RGB565
;
1799 case DRM_FORMAT_XRGB8888
:
1800 case DRM_FORMAT_ARGB8888
:
1801 plane_state
->format
= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888
;
1803 case DRM_FORMAT_XRGB2101010
:
1804 case DRM_FORMAT_ARGB2101010
:
1805 plane_state
->format
= SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010
;
1807 case DRM_FORMAT_XBGR2101010
:
1808 case DRM_FORMAT_ABGR2101010
:
1809 plane_state
->format
= SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
;
1811 case DRM_FORMAT_NV21
:
1812 plane_state
->format
= SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr
;
1814 case DRM_FORMAT_NV12
:
1815 plane_state
->format
= SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb
;
1818 DRM_ERROR("Unsupported screen format %s\n",
1819 drm_get_format_name(fb
->format
->format
, &format_name
));
1823 if (plane_state
->format
< SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
) {
1824 plane_state
->address
.type
= PLN_ADDR_TYPE_GRAPHICS
;
1825 plane_state
->address
.grph
.addr
.low_part
= lower_32_bits(fb_location
);
1826 plane_state
->address
.grph
.addr
.high_part
= upper_32_bits(fb_location
);
1827 plane_state
->plane_size
.grph
.surface_size
.x
= 0;
1828 plane_state
->plane_size
.grph
.surface_size
.y
= 0;
1829 plane_state
->plane_size
.grph
.surface_size
.width
= fb
->width
;
1830 plane_state
->plane_size
.grph
.surface_size
.height
= fb
->height
;
1831 plane_state
->plane_size
.grph
.surface_pitch
=
1832 fb
->pitches
[0] / fb
->format
->cpp
[0];
1833 /* TODO: unhardcode */
1834 plane_state
->color_space
= COLOR_SPACE_SRGB
;
1837 awidth
= ALIGN(fb
->width
, 64);
1838 plane_state
->address
.type
= PLN_ADDR_TYPE_VIDEO_PROGRESSIVE
;
1839 plane_state
->address
.video_progressive
.luma_addr
.low_part
1840 = lower_32_bits(fb_location
);
1841 plane_state
->address
.video_progressive
.chroma_addr
.low_part
1842 = lower_32_bits(fb_location
) +
1843 (awidth
* fb
->height
);
1844 plane_state
->plane_size
.video
.luma_size
.x
= 0;
1845 plane_state
->plane_size
.video
.luma_size
.y
= 0;
1846 plane_state
->plane_size
.video
.luma_size
.width
= awidth
;
1847 plane_state
->plane_size
.video
.luma_size
.height
= fb
->height
;
1848 /* TODO: unhardcode */
1849 plane_state
->plane_size
.video
.luma_pitch
= awidth
;
1851 plane_state
->plane_size
.video
.chroma_size
.x
= 0;
1852 plane_state
->plane_size
.video
.chroma_size
.y
= 0;
1853 plane_state
->plane_size
.video
.chroma_size
.width
= awidth
;
1854 plane_state
->plane_size
.video
.chroma_size
.height
= fb
->height
;
1855 plane_state
->plane_size
.video
.chroma_pitch
= awidth
/ 2;
1857 /* TODO: unhardcode */
1858 plane_state
->color_space
= COLOR_SPACE_YCBCR709
;
1861 memset(&plane_state
->tiling_info
, 0, sizeof(plane_state
->tiling_info
));
1863 /* Fill GFX8 params */
1864 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == DC_ARRAY_2D_TILED_THIN1
) {
1865 unsigned int bankw
, bankh
, mtaspect
, tile_split
, num_banks
;
1867 bankw
= AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
1868 bankh
= AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
1869 mtaspect
= AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
1870 tile_split
= AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
);
1871 num_banks
= AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
1873 /* XXX fix me for VI */
1874 plane_state
->tiling_info
.gfx8
.num_banks
= num_banks
;
1875 plane_state
->tiling_info
.gfx8
.array_mode
=
1876 DC_ARRAY_2D_TILED_THIN1
;
1877 plane_state
->tiling_info
.gfx8
.tile_split
= tile_split
;
1878 plane_state
->tiling_info
.gfx8
.bank_width
= bankw
;
1879 plane_state
->tiling_info
.gfx8
.bank_height
= bankh
;
1880 plane_state
->tiling_info
.gfx8
.tile_aspect
= mtaspect
;
1881 plane_state
->tiling_info
.gfx8
.tile_mode
=
1882 DC_ADDR_SURF_MICRO_TILING_DISPLAY
;
1883 } else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
)
1884 == DC_ARRAY_1D_TILED_THIN1
) {
1885 plane_state
->tiling_info
.gfx8
.array_mode
= DC_ARRAY_1D_TILED_THIN1
;
1888 plane_state
->tiling_info
.gfx8
.pipe_config
=
1889 AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
1891 if (adev
->asic_type
== CHIP_VEGA10
||
1892 adev
->asic_type
== CHIP_RAVEN
) {
1893 /* Fill GFX9 params */
1894 plane_state
->tiling_info
.gfx9
.num_pipes
=
1895 adev
->gfx
.config
.gb_addr_config_fields
.num_pipes
;
1896 plane_state
->tiling_info
.gfx9
.num_banks
=
1897 adev
->gfx
.config
.gb_addr_config_fields
.num_banks
;
1898 plane_state
->tiling_info
.gfx9
.pipe_interleave
=
1899 adev
->gfx
.config
.gb_addr_config_fields
.pipe_interleave_size
;
1900 plane_state
->tiling_info
.gfx9
.num_shader_engines
=
1901 adev
->gfx
.config
.gb_addr_config_fields
.num_se
;
1902 plane_state
->tiling_info
.gfx9
.max_compressed_frags
=
1903 adev
->gfx
.config
.gb_addr_config_fields
.max_compress_frags
;
1904 plane_state
->tiling_info
.gfx9
.num_rb_per_se
=
1905 adev
->gfx
.config
.gb_addr_config_fields
.num_rb_per_se
;
1906 plane_state
->tiling_info
.gfx9
.swizzle
=
1907 AMDGPU_TILING_GET(tiling_flags
, SWIZZLE_MODE
);
1908 plane_state
->tiling_info
.gfx9
.shaderEnable
= 1;
1911 plane_state
->visible
= true;
1912 plane_state
->scaling_quality
.h_taps_c
= 0;
1913 plane_state
->scaling_quality
.v_taps_c
= 0;
1915 /* is this needed? is plane_state zeroed at allocation? */
1916 plane_state
->scaling_quality
.h_taps
= 0;
1917 plane_state
->scaling_quality
.v_taps
= 0;
1918 plane_state
->stereo_format
= PLANE_STEREO_FORMAT_NONE
;
1924 static void fill_gamma_from_crtc_state(const struct drm_crtc_state
*crtc_state
,
1925 struct dc_plane_state
*plane_state
)
1928 struct dc_gamma
*gamma
;
1929 struct drm_color_lut
*lut
=
1930 (struct drm_color_lut
*) crtc_state
->gamma_lut
->data
;
1932 gamma
= dc_create_gamma();
1934 if (gamma
== NULL
) {
1939 gamma
->type
= GAMMA_RGB_256
;
1940 gamma
->num_entries
= GAMMA_RGB_256_ENTRIES
;
1941 for (i
= 0; i
< GAMMA_RGB_256_ENTRIES
; i
++) {
1942 gamma
->entries
.red
[i
] = dal_fixed31_32_from_int(lut
[i
].red
);
1943 gamma
->entries
.green
[i
] = dal_fixed31_32_from_int(lut
[i
].green
);
1944 gamma
->entries
.blue
[i
] = dal_fixed31_32_from_int(lut
[i
].blue
);
1947 plane_state
->gamma_correction
= gamma
;
1950 static int fill_plane_attributes(struct amdgpu_device
*adev
,
1951 struct dc_plane_state
*dc_plane_state
,
1952 struct drm_plane_state
*plane_state
,
1953 struct drm_crtc_state
*crtc_state
,
1956 const struct amdgpu_framebuffer
*amdgpu_fb
=
1957 to_amdgpu_framebuffer(plane_state
->fb
);
1958 const struct drm_crtc
*crtc
= plane_state
->crtc
;
1959 struct dc_transfer_func
*input_tf
;
1962 if (!fill_rects_from_plane_state(plane_state
, dc_plane_state
))
1965 ret
= fill_plane_attributes_from_fb(
1966 crtc
->dev
->dev_private
,
1974 input_tf
= dc_create_transfer_func();
1976 if (input_tf
== NULL
)
1979 input_tf
->type
= TF_TYPE_PREDEFINED
;
1980 input_tf
->tf
= TRANSFER_FUNCTION_SRGB
;
1982 dc_plane_state
->in_transfer_func
= input_tf
;
1984 /* In case of gamma set, update gamma value */
1985 if (crtc_state
->gamma_lut
)
1986 fill_gamma_from_crtc_state(crtc_state
, dc_plane_state
);
1991 /*****************************************************************************/
1993 static void update_stream_scaling_settings(const struct drm_display_mode
*mode
,
1994 const struct dm_connector_state
*dm_state
,
1995 struct dc_stream_state
*stream
)
1997 enum amdgpu_rmx_type rmx_type
;
1999 struct rect src
= { 0 }; /* viewport in composition space*/
2000 struct rect dst
= { 0 }; /* stream addressable area */
2002 /* no mode. nothing to be done */
2006 /* Full screen scaling by default */
2007 src
.width
= mode
->hdisplay
;
2008 src
.height
= mode
->vdisplay
;
2009 dst
.width
= stream
->timing
.h_addressable
;
2010 dst
.height
= stream
->timing
.v_addressable
;
2012 rmx_type
= dm_state
->scaling
;
2013 if (rmx_type
== RMX_ASPECT
|| rmx_type
== RMX_OFF
) {
2014 if (src
.width
* dst
.height
<
2015 src
.height
* dst
.width
) {
2016 /* height needs less upscaling/more downscaling */
2017 dst
.width
= src
.width
*
2018 dst
.height
/ src
.height
;
2020 /* width needs less upscaling/more downscaling */
2021 dst
.height
= src
.height
*
2022 dst
.width
/ src
.width
;
2024 } else if (rmx_type
== RMX_CENTER
) {
2028 dst
.x
= (stream
->timing
.h_addressable
- dst
.width
) / 2;
2029 dst
.y
= (stream
->timing
.v_addressable
- dst
.height
) / 2;
2031 if (dm_state
->underscan_enable
) {
2032 dst
.x
+= dm_state
->underscan_hborder
/ 2;
2033 dst
.y
+= dm_state
->underscan_vborder
/ 2;
2034 dst
.width
-= dm_state
->underscan_hborder
;
2035 dst
.height
-= dm_state
->underscan_vborder
;
2041 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
2042 dst
.x
, dst
.y
, dst
.width
, dst
.height
);
2046 static enum dc_color_depth
2047 convert_color_depth_from_display_info(const struct drm_connector
*connector
)
2049 uint32_t bpc
= connector
->display_info
.bpc
;
2051 /* Limited color depth to 8bit
2052 * TODO: Still need to handle deep color
2059 /* Temporary Work around, DRM don't parse color depth for
2060 * EDID revision before 1.4
2061 * TODO: Fix edid parsing
2063 return COLOR_DEPTH_888
;
2065 return COLOR_DEPTH_666
;
2067 return COLOR_DEPTH_888
;
2069 return COLOR_DEPTH_101010
;
2071 return COLOR_DEPTH_121212
;
2073 return COLOR_DEPTH_141414
;
2075 return COLOR_DEPTH_161616
;
2077 return COLOR_DEPTH_UNDEFINED
;
2081 static enum dc_aspect_ratio
2082 get_aspect_ratio(const struct drm_display_mode
*mode_in
)
2084 int32_t width
= mode_in
->crtc_hdisplay
* 9;
2085 int32_t height
= mode_in
->crtc_vdisplay
* 16;
2087 if ((width
- height
) < 10 && (width
- height
) > -10)
2088 return ASPECT_RATIO_16_9
;
2090 return ASPECT_RATIO_4_3
;
2093 static enum dc_color_space
2094 get_output_color_space(const struct dc_crtc_timing
*dc_crtc_timing
)
2096 enum dc_color_space color_space
= COLOR_SPACE_SRGB
;
2098 switch (dc_crtc_timing
->pixel_encoding
) {
2099 case PIXEL_ENCODING_YCBCR422
:
2100 case PIXEL_ENCODING_YCBCR444
:
2101 case PIXEL_ENCODING_YCBCR420
:
2104 * 27030khz is the separation point between HDTV and SDTV
2105 * according to HDMI spec, we use YCbCr709 and YCbCr601
2108 if (dc_crtc_timing
->pix_clk_khz
> 27030) {
2109 if (dc_crtc_timing
->flags
.Y_ONLY
)
2111 COLOR_SPACE_YCBCR709_LIMITED
;
2113 color_space
= COLOR_SPACE_YCBCR709
;
2115 if (dc_crtc_timing
->flags
.Y_ONLY
)
2117 COLOR_SPACE_YCBCR601_LIMITED
;
2119 color_space
= COLOR_SPACE_YCBCR601
;
2124 case PIXEL_ENCODING_RGB
:
2125 color_space
= COLOR_SPACE_SRGB
;
2136 /*****************************************************************************/
2139 fill_stream_properties_from_drm_display_mode(struct dc_stream_state
*stream
,
2140 const struct drm_display_mode
*mode_in
,
2141 const struct drm_connector
*connector
)
2143 struct dc_crtc_timing
*timing_out
= &stream
->timing
;
2145 memset(timing_out
, 0, sizeof(struct dc_crtc_timing
));
2147 timing_out
->h_border_left
= 0;
2148 timing_out
->h_border_right
= 0;
2149 timing_out
->v_border_top
= 0;
2150 timing_out
->v_border_bottom
= 0;
2151 /* TODO: un-hardcode */
2153 if ((connector
->display_info
.color_formats
& DRM_COLOR_FORMAT_YCRCB444
)
2154 && stream
->sink
->sink_signal
== SIGNAL_TYPE_HDMI_TYPE_A
)
2155 timing_out
->pixel_encoding
= PIXEL_ENCODING_YCBCR444
;
2157 timing_out
->pixel_encoding
= PIXEL_ENCODING_RGB
;
2159 timing_out
->timing_3d_format
= TIMING_3D_FORMAT_NONE
;
2160 timing_out
->display_color_depth
= convert_color_depth_from_display_info(
2162 timing_out
->scan_type
= SCANNING_TYPE_NODATA
;
2163 timing_out
->hdmi_vic
= 0;
2164 timing_out
->vic
= drm_match_cea_mode(mode_in
);
2166 timing_out
->h_addressable
= mode_in
->crtc_hdisplay
;
2167 timing_out
->h_total
= mode_in
->crtc_htotal
;
2168 timing_out
->h_sync_width
=
2169 mode_in
->crtc_hsync_end
- mode_in
->crtc_hsync_start
;
2170 timing_out
->h_front_porch
=
2171 mode_in
->crtc_hsync_start
- mode_in
->crtc_hdisplay
;
2172 timing_out
->v_total
= mode_in
->crtc_vtotal
;
2173 timing_out
->v_addressable
= mode_in
->crtc_vdisplay
;
2174 timing_out
->v_front_porch
=
2175 mode_in
->crtc_vsync_start
- mode_in
->crtc_vdisplay
;
2176 timing_out
->v_sync_width
=
2177 mode_in
->crtc_vsync_end
- mode_in
->crtc_vsync_start
;
2178 timing_out
->pix_clk_khz
= mode_in
->crtc_clock
;
2179 timing_out
->aspect_ratio
= get_aspect_ratio(mode_in
);
2180 if (mode_in
->flags
& DRM_MODE_FLAG_PHSYNC
)
2181 timing_out
->flags
.HSYNC_POSITIVE_POLARITY
= 1;
2182 if (mode_in
->flags
& DRM_MODE_FLAG_PVSYNC
)
2183 timing_out
->flags
.VSYNC_POSITIVE_POLARITY
= 1;
2185 stream
->output_color_space
= get_output_color_space(timing_out
);
2188 struct dc_transfer_func
*tf
= dc_create_transfer_func();
2190 tf
->type
= TF_TYPE_PREDEFINED
;
2191 tf
->tf
= TRANSFER_FUNCTION_SRGB
;
2192 stream
->out_transfer_func
= tf
;
2196 static void fill_audio_info(struct audio_info
*audio_info
,
2197 const struct drm_connector
*drm_connector
,
2198 const struct dc_sink
*dc_sink
)
2201 int cea_revision
= 0;
2202 const struct dc_edid_caps
*edid_caps
= &dc_sink
->edid_caps
;
2204 audio_info
->manufacture_id
= edid_caps
->manufacturer_id
;
2205 audio_info
->product_id
= edid_caps
->product_id
;
2207 cea_revision
= drm_connector
->display_info
.cea_rev
;
2209 while (i
< AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS
&&
2210 edid_caps
->display_name
[i
]) {
2211 audio_info
->display_name
[i
] = edid_caps
->display_name
[i
];
2215 if (cea_revision
>= 3) {
2216 audio_info
->mode_count
= edid_caps
->audio_mode_count
;
2218 for (i
= 0; i
< audio_info
->mode_count
; ++i
) {
2219 audio_info
->modes
[i
].format_code
=
2220 (enum audio_format_code
)
2221 (edid_caps
->audio_modes
[i
].format_code
);
2222 audio_info
->modes
[i
].channel_count
=
2223 edid_caps
->audio_modes
[i
].channel_count
;
2224 audio_info
->modes
[i
].sample_rates
.all
=
2225 edid_caps
->audio_modes
[i
].sample_rate
;
2226 audio_info
->modes
[i
].sample_size
=
2227 edid_caps
->audio_modes
[i
].sample_size
;
2231 audio_info
->flags
.all
= edid_caps
->speaker_flags
;
2233 /* TODO: We only check for the progressive mode, check for interlace mode too */
2234 if (drm_connector
->latency_present
[0]) {
2235 audio_info
->video_latency
= drm_connector
->video_latency
[0];
2236 audio_info
->audio_latency
= drm_connector
->audio_latency
[0];
2239 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2244 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode
*src_mode
,
2245 struct drm_display_mode
*dst_mode
)
2247 dst_mode
->crtc_hdisplay
= src_mode
->crtc_hdisplay
;
2248 dst_mode
->crtc_vdisplay
= src_mode
->crtc_vdisplay
;
2249 dst_mode
->crtc_clock
= src_mode
->crtc_clock
;
2250 dst_mode
->crtc_hblank_start
= src_mode
->crtc_hblank_start
;
2251 dst_mode
->crtc_hblank_end
= src_mode
->crtc_hblank_end
;
2252 dst_mode
->crtc_hsync_start
= src_mode
->crtc_hsync_start
;
2253 dst_mode
->crtc_hsync_end
= src_mode
->crtc_hsync_end
;
2254 dst_mode
->crtc_htotal
= src_mode
->crtc_htotal
;
2255 dst_mode
->crtc_hskew
= src_mode
->crtc_hskew
;
2256 dst_mode
->crtc_vblank_start
= src_mode
->crtc_vblank_start
;
2257 dst_mode
->crtc_vblank_end
= src_mode
->crtc_vblank_end
;
2258 dst_mode
->crtc_vsync_start
= src_mode
->crtc_vsync_start
;
2259 dst_mode
->crtc_vsync_end
= src_mode
->crtc_vsync_end
;
2260 dst_mode
->crtc_vtotal
= src_mode
->crtc_vtotal
;
2264 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode
*drm_mode
,
2265 const struct drm_display_mode
*native_mode
,
2268 if (scale_enabled
) {
2269 copy_crtc_timing_for_drm_display_mode(native_mode
, drm_mode
);
2270 } else if (native_mode
->clock
== drm_mode
->clock
&&
2271 native_mode
->htotal
== drm_mode
->htotal
&&
2272 native_mode
->vtotal
== drm_mode
->vtotal
) {
2273 copy_crtc_timing_for_drm_display_mode(native_mode
, drm_mode
);
2275 /* no scaling nor amdgpu inserted, no need to patch */
2279 static void create_fake_sink(struct amdgpu_dm_connector
*aconnector
)
2281 struct dc_sink
*sink
= NULL
;
2282 struct dc_sink_init_data sink_init_data
= { 0 };
2284 sink_init_data
.link
= aconnector
->dc_link
;
2285 sink_init_data
.sink_signal
= aconnector
->dc_link
->connector_signal
;
2287 sink
= dc_sink_create(&sink_init_data
);
2289 DRM_ERROR("Failed to create sink!\n");
2291 sink
->sink_signal
= SIGNAL_TYPE_VIRTUAL
;
2292 aconnector
->fake_enable
= true;
2294 aconnector
->dc_sink
= sink
;
2295 aconnector
->dc_link
->local_sink
= sink
;
2298 static struct dc_stream_state
*
2299 create_stream_for_sink(struct amdgpu_dm_connector
*aconnector
,
2300 const struct drm_display_mode
*drm_mode
,
2301 const struct dm_connector_state
*dm_state
)
2303 struct drm_display_mode
*preferred_mode
= NULL
;
2304 const struct drm_connector
*drm_connector
;
2305 struct dc_stream_state
*stream
= NULL
;
2306 struct drm_display_mode mode
= *drm_mode
;
2307 bool native_mode_found
= false;
2309 if (aconnector
== NULL
) {
2310 DRM_ERROR("aconnector is NULL!\n");
2311 goto drm_connector_null
;
2314 if (dm_state
== NULL
) {
2315 DRM_ERROR("dm_state is NULL!\n");
2319 drm_connector
= &aconnector
->base
;
2321 if (!aconnector
->dc_sink
)
2322 create_fake_sink(aconnector
);
2324 stream
= dc_create_stream_for_sink(aconnector
->dc_sink
);
2326 if (stream
== NULL
) {
2327 DRM_ERROR("Failed to create stream for sink!\n");
2328 goto stream_create_fail
;
2331 list_for_each_entry(preferred_mode
, &aconnector
->base
.modes
, head
) {
2332 /* Search for preferred mode */
2333 if (preferred_mode
->type
& DRM_MODE_TYPE_PREFERRED
) {
2334 native_mode_found
= true;
2338 if (!native_mode_found
)
2339 preferred_mode
= list_first_entry_or_null(
2340 &aconnector
->base
.modes
,
2341 struct drm_display_mode
,
2344 if (preferred_mode
== NULL
) {
2345 /* This may not be an error, the use case is when we we have no
2346 * usermode calls to reset and set mode upon hotplug. In this
2347 * case, we call set mode ourselves to restore the previous mode
2348 * and the modelist may not be filled in in time.
2350 DRM_DEBUG_DRIVER("No preferred mode found\n");
2352 decide_crtc_timing_for_drm_display_mode(
2353 &mode
, preferred_mode
,
2354 dm_state
->scaling
!= RMX_OFF
);
2357 fill_stream_properties_from_drm_display_mode(stream
,
2358 &mode
, &aconnector
->base
);
2359 update_stream_scaling_settings(&mode
, dm_state
, stream
);
2362 &stream
->audio_info
,
2364 aconnector
->dc_sink
);
2372 static void amdgpu_dm_crtc_destroy(struct drm_crtc
*crtc
)
2374 drm_crtc_cleanup(crtc
);
2378 static void dm_crtc_destroy_state(struct drm_crtc
*crtc
,
2379 struct drm_crtc_state
*state
)
2381 struct dm_crtc_state
*cur
= to_dm_crtc_state(state
);
2383 /* TODO Destroy dc_stream objects are stream object is flattened */
2385 dc_stream_release(cur
->stream
);
2388 __drm_atomic_helper_crtc_destroy_state(state
);
2394 static void dm_crtc_reset_state(struct drm_crtc
*crtc
)
2396 struct dm_crtc_state
*state
;
2399 dm_crtc_destroy_state(crtc
, crtc
->state
);
2401 state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
2402 if (WARN_ON(!state
))
2405 crtc
->state
= &state
->base
;
2406 crtc
->state
->crtc
= crtc
;
2410 static struct drm_crtc_state
*
2411 dm_crtc_duplicate_state(struct drm_crtc
*crtc
)
2413 struct dm_crtc_state
*state
, *cur
;
2415 cur
= to_dm_crtc_state(crtc
->state
);
2417 if (WARN_ON(!crtc
->state
))
2420 state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
2422 __drm_atomic_helper_crtc_duplicate_state(crtc
, &state
->base
);
2425 state
->stream
= cur
->stream
;
2426 dc_stream_retain(state
->stream
);
2429 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2431 return &state
->base
;
2434 /* Implemented only the options currently availible for the driver */
2435 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs
= {
2436 .reset
= dm_crtc_reset_state
,
2437 .destroy
= amdgpu_dm_crtc_destroy
,
2438 .gamma_set
= drm_atomic_helper_legacy_gamma_set
,
2439 .set_config
= drm_atomic_helper_set_config
,
2440 .page_flip
= drm_atomic_helper_page_flip
,
2441 .atomic_duplicate_state
= dm_crtc_duplicate_state
,
2442 .atomic_destroy_state
= dm_crtc_destroy_state
,
2445 static enum drm_connector_status
2446 amdgpu_dm_connector_detect(struct drm_connector
*connector
, bool force
)
2449 struct amdgpu_dm_connector
*aconnector
= to_amdgpu_dm_connector(connector
);
2452 * 1. This interface is NOT called in context of HPD irq.
2453 * 2. This interface *is called* in context of user-mode ioctl. Which
2454 * makes it a bad place for *any* MST-related activit. */
2456 if (aconnector
->base
.force
== DRM_FORCE_UNSPECIFIED
)
2457 connected
= (aconnector
->dc_sink
!= NULL
);
2459 connected
= (aconnector
->base
.force
== DRM_FORCE_ON
);
2461 return (connected
? connector_status_connected
:
2462 connector_status_disconnected
);
2465 int amdgpu_dm_connector_atomic_set_property(struct drm_connector
*connector
,
2466 struct drm_connector_state
*connector_state
,
2467 struct drm_property
*property
,
2470 struct drm_device
*dev
= connector
->dev
;
2471 struct amdgpu_device
*adev
= dev
->dev_private
;
2472 struct dm_connector_state
*dm_old_state
=
2473 to_dm_connector_state(connector
->state
);
2474 struct dm_connector_state
*dm_new_state
=
2475 to_dm_connector_state(connector_state
);
2479 if (property
== dev
->mode_config
.scaling_mode_property
) {
2480 enum amdgpu_rmx_type rmx_type
;
2483 case DRM_MODE_SCALE_CENTER
:
2484 rmx_type
= RMX_CENTER
;
2486 case DRM_MODE_SCALE_ASPECT
:
2487 rmx_type
= RMX_ASPECT
;
2489 case DRM_MODE_SCALE_FULLSCREEN
:
2490 rmx_type
= RMX_FULL
;
2492 case DRM_MODE_SCALE_NONE
:
2498 if (dm_old_state
->scaling
== rmx_type
)
2501 dm_new_state
->scaling
= rmx_type
;
2503 } else if (property
== adev
->mode_info
.underscan_hborder_property
) {
2504 dm_new_state
->underscan_hborder
= val
;
2506 } else if (property
== adev
->mode_info
.underscan_vborder_property
) {
2507 dm_new_state
->underscan_vborder
= val
;
2509 } else if (property
== adev
->mode_info
.underscan_property
) {
2510 dm_new_state
->underscan_enable
= val
;
2517 int amdgpu_dm_connector_atomic_get_property(struct drm_connector
*connector
,
2518 const struct drm_connector_state
*state
,
2519 struct drm_property
*property
,
2522 struct drm_device
*dev
= connector
->dev
;
2523 struct amdgpu_device
*adev
= dev
->dev_private
;
2524 struct dm_connector_state
*dm_state
=
2525 to_dm_connector_state(state
);
2528 if (property
== dev
->mode_config
.scaling_mode_property
) {
2529 switch (dm_state
->scaling
) {
2531 *val
= DRM_MODE_SCALE_CENTER
;
2534 *val
= DRM_MODE_SCALE_ASPECT
;
2537 *val
= DRM_MODE_SCALE_FULLSCREEN
;
2541 *val
= DRM_MODE_SCALE_NONE
;
2545 } else if (property
== adev
->mode_info
.underscan_hborder_property
) {
2546 *val
= dm_state
->underscan_hborder
;
2548 } else if (property
== adev
->mode_info
.underscan_vborder_property
) {
2549 *val
= dm_state
->underscan_vborder
;
2551 } else if (property
== adev
->mode_info
.underscan_property
) {
2552 *val
= dm_state
->underscan_enable
;
2558 static void amdgpu_dm_connector_destroy(struct drm_connector
*connector
)
2560 struct amdgpu_dm_connector
*aconnector
= to_amdgpu_dm_connector(connector
);
2561 const struct dc_link
*link
= aconnector
->dc_link
;
2562 struct amdgpu_device
*adev
= connector
->dev
->dev_private
;
2563 struct amdgpu_display_manager
*dm
= &adev
->dm
;
2564 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2565 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2567 if (link
->connector_signal
& (SIGNAL_TYPE_EDP
| SIGNAL_TYPE_LVDS
)) {
2568 amdgpu_dm_register_backlight_device(dm
);
2570 if (dm
->backlight_dev
) {
2571 backlight_device_unregister(dm
->backlight_dev
);
2572 dm
->backlight_dev
= NULL
;
2577 drm_connector_unregister(connector
);
2578 drm_connector_cleanup(connector
);
2582 void amdgpu_dm_connector_funcs_reset(struct drm_connector
*connector
)
2584 struct dm_connector_state
*state
=
2585 to_dm_connector_state(connector
->state
);
2589 state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
2592 state
->scaling
= RMX_OFF
;
2593 state
->underscan_enable
= false;
2594 state
->underscan_hborder
= 0;
2595 state
->underscan_vborder
= 0;
2597 connector
->state
= &state
->base
;
2598 connector
->state
->connector
= connector
;
2602 struct drm_connector_state
*
2603 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector
*connector
)
2605 struct dm_connector_state
*state
=
2606 to_dm_connector_state(connector
->state
);
2608 struct dm_connector_state
*new_state
=
2609 kmemdup(state
, sizeof(*state
), GFP_KERNEL
);
2612 __drm_atomic_helper_connector_duplicate_state(connector
,
2614 return &new_state
->base
;
2620 static const struct drm_connector_funcs amdgpu_dm_connector_funcs
= {
2621 .reset
= amdgpu_dm_connector_funcs_reset
,
2622 .detect
= amdgpu_dm_connector_detect
,
2623 .fill_modes
= drm_helper_probe_single_connector_modes
,
2624 .destroy
= amdgpu_dm_connector_destroy
,
2625 .atomic_duplicate_state
= amdgpu_dm_connector_atomic_duplicate_state
,
2626 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
2627 .atomic_set_property
= amdgpu_dm_connector_atomic_set_property
,
2628 .atomic_get_property
= amdgpu_dm_connector_atomic_get_property
2631 static struct drm_encoder
*best_encoder(struct drm_connector
*connector
)
2633 int enc_id
= connector
->encoder_ids
[0];
2634 struct drm_mode_object
*obj
;
2635 struct drm_encoder
*encoder
;
2637 DRM_DEBUG_DRIVER("Finding the best encoder\n");
2639 /* pick the encoder ids */
2641 obj
= drm_mode_object_find(connector
->dev
, NULL
, enc_id
, DRM_MODE_OBJECT_ENCODER
);
2643 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2646 encoder
= obj_to_encoder(obj
);
2649 DRM_ERROR("No encoder id\n");
2653 static int get_modes(struct drm_connector
*connector
)
2655 return amdgpu_dm_connector_get_modes(connector
);
2658 static void create_eml_sink(struct amdgpu_dm_connector
*aconnector
)
2660 struct dc_sink_init_data init_params
= {
2661 .link
= aconnector
->dc_link
,
2662 .sink_signal
= SIGNAL_TYPE_VIRTUAL
2664 struct edid
*edid
= (struct edid
*) aconnector
->base
.edid_blob_ptr
->data
;
2666 if (!aconnector
->base
.edid_blob_ptr
||
2667 !aconnector
->base
.edid_blob_ptr
->data
) {
2668 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2669 aconnector
->base
.name
);
2671 aconnector
->base
.force
= DRM_FORCE_OFF
;
2672 aconnector
->base
.override_edid
= false;
2676 aconnector
->edid
= edid
;
2678 aconnector
->dc_em_sink
= dc_link_add_remote_sink(
2679 aconnector
->dc_link
,
2681 (edid
->extensions
+ 1) * EDID_LENGTH
,
2684 if (aconnector
->base
.force
2686 aconnector
->dc_sink
= aconnector
->dc_link
->local_sink
?
2687 aconnector
->dc_link
->local_sink
:
2688 aconnector
->dc_em_sink
;
2691 static void handle_edid_mgmt(struct amdgpu_dm_connector
*aconnector
)
2693 struct dc_link
*link
= (struct dc_link
*)aconnector
->dc_link
;
2695 /* In case of headless boot with force on for DP managed connector
2696 * Those settings have to be != 0 to get initial modeset
2698 if (link
->connector_signal
== SIGNAL_TYPE_DISPLAY_PORT
) {
2699 link
->verified_link_cap
.lane_count
= LANE_COUNT_FOUR
;
2700 link
->verified_link_cap
.link_rate
= LINK_RATE_HIGH2
;
2704 aconnector
->base
.override_edid
= true;
2705 create_eml_sink(aconnector
);
2708 int amdgpu_dm_connector_mode_valid(struct drm_connector
*connector
,
2709 struct drm_display_mode
*mode
)
2711 int result
= MODE_ERROR
;
2712 struct dc_sink
*dc_sink
;
2713 struct amdgpu_device
*adev
= connector
->dev
->dev_private
;
2714 /* TODO: Unhardcode stream count */
2715 struct dc_stream_state
*stream
;
2716 struct amdgpu_dm_connector
*aconnector
= to_amdgpu_dm_connector(connector
);
2718 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
2719 (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
))
2722 /* Only run this the first time mode_valid is called to initilialize
2725 if (aconnector
->base
.force
!= DRM_FORCE_UNSPECIFIED
&&
2726 !aconnector
->dc_em_sink
)
2727 handle_edid_mgmt(aconnector
);
2729 dc_sink
= to_amdgpu_dm_connector(connector
)->dc_sink
;
2731 if (dc_sink
== NULL
) {
2732 DRM_ERROR("dc_sink is NULL!\n");
2736 stream
= dc_create_stream_for_sink(dc_sink
);
2737 if (stream
== NULL
) {
2738 DRM_ERROR("Failed to create stream for sink!\n");
2742 drm_mode_set_crtcinfo(mode
, 0);
2743 fill_stream_properties_from_drm_display_mode(stream
, mode
, connector
);
2745 stream
->src
.width
= mode
->hdisplay
;
2746 stream
->src
.height
= mode
->vdisplay
;
2747 stream
->dst
= stream
->src
;
2749 if (dc_validate_stream(adev
->dm
.dc
, stream
))
2752 dc_stream_release(stream
);
2755 /* TODO: error handling*/
2759 static const struct drm_connector_helper_funcs
2760 amdgpu_dm_connector_helper_funcs
= {
2762 * If hotplug a second bigger display in FB Con mode, bigger resolution
2763 * modes will be filtered by drm_mode_validate_size(), and those modes
2764 * is missing after user start lightdm. So we need to renew modes list.
2765 * in get_modes call back, not just return the modes count
2767 .get_modes
= get_modes
,
2768 .mode_valid
= amdgpu_dm_connector_mode_valid
,
2769 .best_encoder
= best_encoder
2772 static void dm_crtc_helper_disable(struct drm_crtc
*crtc
)
2776 static int dm_crtc_helper_atomic_check(struct drm_crtc
*crtc
,
2777 struct drm_crtc_state
*state
)
2779 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2780 struct dc
*dc
= adev
->dm
.dc
;
2781 struct dm_crtc_state
*dm_crtc_state
= to_dm_crtc_state(state
);
2784 if (unlikely(!dm_crtc_state
->stream
&&
2785 modeset_required(state
, NULL
, dm_crtc_state
->stream
))) {
2790 /* In some use cases, like reset, no stream is attached */
2791 if (!dm_crtc_state
->stream
)
2794 if (dc_validate_stream(dc
, dm_crtc_state
->stream
))
2800 static bool dm_crtc_helper_mode_fixup(struct drm_crtc
*crtc
,
2801 const struct drm_display_mode
*mode
,
2802 struct drm_display_mode
*adjusted_mode
)
2807 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs
= {
2808 .disable
= dm_crtc_helper_disable
,
2809 .atomic_check
= dm_crtc_helper_atomic_check
,
2810 .mode_fixup
= dm_crtc_helper_mode_fixup
2813 static void dm_encoder_helper_disable(struct drm_encoder
*encoder
)
2818 static int dm_encoder_helper_atomic_check(struct drm_encoder
*encoder
,
2819 struct drm_crtc_state
*crtc_state
,
2820 struct drm_connector_state
*conn_state
)
2825 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs
= {
2826 .disable
= dm_encoder_helper_disable
,
2827 .atomic_check
= dm_encoder_helper_atomic_check
2830 static void dm_drm_plane_reset(struct drm_plane
*plane
)
2832 struct dm_plane_state
*amdgpu_state
= NULL
;
2835 plane
->funcs
->atomic_destroy_state(plane
, plane
->state
);
2837 amdgpu_state
= kzalloc(sizeof(*amdgpu_state
), GFP_KERNEL
);
2840 plane
->state
= &amdgpu_state
->base
;
2841 plane
->state
->plane
= plane
;
2842 plane
->state
->rotation
= DRM_MODE_ROTATE_0
;
2847 static struct drm_plane_state
*
2848 dm_drm_plane_duplicate_state(struct drm_plane
*plane
)
2850 struct dm_plane_state
*dm_plane_state
, *old_dm_plane_state
;
2852 old_dm_plane_state
= to_dm_plane_state(plane
->state
);
2853 dm_plane_state
= kzalloc(sizeof(*dm_plane_state
), GFP_KERNEL
);
2854 if (!dm_plane_state
)
2857 __drm_atomic_helper_plane_duplicate_state(plane
, &dm_plane_state
->base
);
2859 if (old_dm_plane_state
->dc_state
) {
2860 dm_plane_state
->dc_state
= old_dm_plane_state
->dc_state
;
2861 dc_plane_state_retain(dm_plane_state
->dc_state
);
2864 return &dm_plane_state
->base
;
2867 void dm_drm_plane_destroy_state(struct drm_plane
*plane
,
2868 struct drm_plane_state
*state
)
2870 struct dm_plane_state
*dm_plane_state
= to_dm_plane_state(state
);
2872 if (dm_plane_state
->dc_state
)
2873 dc_plane_state_release(dm_plane_state
->dc_state
);
2875 drm_atomic_helper_plane_destroy_state(plane
, state
);
2878 static const struct drm_plane_funcs dm_plane_funcs
= {
2879 .update_plane
= drm_atomic_helper_update_plane
,
2880 .disable_plane
= drm_atomic_helper_disable_plane
,
2881 .destroy
= drm_plane_cleanup
,
2882 .reset
= dm_drm_plane_reset
,
2883 .atomic_duplicate_state
= dm_drm_plane_duplicate_state
,
2884 .atomic_destroy_state
= dm_drm_plane_destroy_state
,
2887 static int dm_plane_helper_prepare_fb(struct drm_plane
*plane
,
2888 struct drm_plane_state
*new_state
)
2890 struct amdgpu_framebuffer
*afb
;
2891 struct drm_gem_object
*obj
;
2892 struct amdgpu_bo
*rbo
;
2894 struct dm_plane_state
*dm_plane_state_new
, *dm_plane_state_old
;
2895 unsigned int awidth
;
2897 dm_plane_state_old
= to_dm_plane_state(plane
->state
);
2898 dm_plane_state_new
= to_dm_plane_state(new_state
);
2900 if (!new_state
->fb
) {
2901 DRM_DEBUG_DRIVER("No FB bound\n");
2905 afb
= to_amdgpu_framebuffer(new_state
->fb
);
2908 rbo
= gem_to_amdgpu_bo(obj
);
2909 r
= amdgpu_bo_reserve(rbo
, false);
2910 if (unlikely(r
!= 0))
2913 r
= amdgpu_bo_pin(rbo
, AMDGPU_GEM_DOMAIN_VRAM
, &afb
->address
);
2916 amdgpu_bo_unreserve(rbo
);
2918 if (unlikely(r
!= 0)) {
2919 DRM_ERROR("Failed to pin framebuffer\n");
2925 if (dm_plane_state_new
->dc_state
&&
2926 dm_plane_state_old
->dc_state
!= dm_plane_state_new
->dc_state
) {
2927 struct dc_plane_state
*plane_state
= dm_plane_state_new
->dc_state
;
2929 if (plane_state
->format
< SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
) {
2930 plane_state
->address
.grph
.addr
.low_part
= lower_32_bits(afb
->address
);
2931 plane_state
->address
.grph
.addr
.high_part
= upper_32_bits(afb
->address
);
2933 awidth
= ALIGN(new_state
->fb
->width
, 64);
2934 plane_state
->address
.video_progressive
.luma_addr
.low_part
2935 = lower_32_bits(afb
->address
);
2936 plane_state
->address
.video_progressive
.chroma_addr
.low_part
2937 = lower_32_bits(afb
->address
) +
2938 (awidth
* new_state
->fb
->height
);
2942 /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
2943 * prepare and cleanup in drm_atomic_helper_prepare_planes
2944 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
2945 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
2946 * code touching fram buffers should be avoided for DC.
2948 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
) {
2949 struct amdgpu_crtc
*acrtc
= to_amdgpu_crtc(new_state
->crtc
);
2951 acrtc
->cursor_bo
= obj
;
2956 static void dm_plane_helper_cleanup_fb(struct drm_plane
*plane
,
2957 struct drm_plane_state
*old_state
)
2959 struct amdgpu_bo
*rbo
;
2960 struct amdgpu_framebuffer
*afb
;
2966 afb
= to_amdgpu_framebuffer(old_state
->fb
);
2967 rbo
= gem_to_amdgpu_bo(afb
->obj
);
2968 r
= amdgpu_bo_reserve(rbo
, false);
2970 DRM_ERROR("failed to reserve rbo before unpin\n");
2974 amdgpu_bo_unpin(rbo
);
2975 amdgpu_bo_unreserve(rbo
);
2976 amdgpu_bo_unref(&rbo
);
2979 static int dm_plane_atomic_check(struct drm_plane
*plane
,
2980 struct drm_plane_state
*state
)
2982 struct amdgpu_device
*adev
= plane
->dev
->dev_private
;
2983 struct dc
*dc
= adev
->dm
.dc
;
2984 struct dm_plane_state
*dm_plane_state
= to_dm_plane_state(state
);
2986 if (!dm_plane_state
->dc_state
)
2989 if (dc_validate_plane(dc
, dm_plane_state
->dc_state
))
2995 static const struct drm_plane_helper_funcs dm_plane_helper_funcs
= {
2996 .prepare_fb
= dm_plane_helper_prepare_fb
,
2997 .cleanup_fb
= dm_plane_helper_cleanup_fb
,
2998 .atomic_check
= dm_plane_atomic_check
,
3002 * TODO: these are currently initialized to rgb formats only.
3003 * For future use cases we should either initialize them dynamically based on
3004 * plane capabilities, or initialize this array to all formats, so internal drm
3005 * check will succeed, and let DC to implement proper check
3007 static const uint32_t rgb_formats
[] = {
3009 DRM_FORMAT_XRGB8888
,
3010 DRM_FORMAT_ARGB8888
,
3011 DRM_FORMAT_RGBA8888
,
3012 DRM_FORMAT_XRGB2101010
,
3013 DRM_FORMAT_XBGR2101010
,
3014 DRM_FORMAT_ARGB2101010
,
3015 DRM_FORMAT_ABGR2101010
,
3018 static const uint32_t yuv_formats
[] = {
3023 static const u32 cursor_formats
[] = {
3027 static int amdgpu_dm_plane_init(struct amdgpu_display_manager
*dm
,
3028 struct amdgpu_plane
*aplane
,
3029 unsigned long possible_crtcs
)
3033 switch (aplane
->base
.type
) {
3034 case DRM_PLANE_TYPE_PRIMARY
:
3035 aplane
->base
.format_default
= true;
3037 res
= drm_universal_plane_init(
3043 ARRAY_SIZE(rgb_formats
),
3044 NULL
, aplane
->base
.type
, NULL
);
3046 case DRM_PLANE_TYPE_OVERLAY
:
3047 res
= drm_universal_plane_init(
3053 ARRAY_SIZE(yuv_formats
),
3054 NULL
, aplane
->base
.type
, NULL
);
3056 case DRM_PLANE_TYPE_CURSOR
:
3057 res
= drm_universal_plane_init(
3063 ARRAY_SIZE(cursor_formats
),
3064 NULL
, aplane
->base
.type
, NULL
);
3068 drm_plane_helper_add(&aplane
->base
, &dm_plane_helper_funcs
);
3073 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager
*dm
,
3074 struct drm_plane
*plane
,
3075 uint32_t crtc_index
)
3077 struct amdgpu_crtc
*acrtc
= NULL
;
3078 struct amdgpu_plane
*cursor_plane
;
3082 cursor_plane
= kzalloc(sizeof(*cursor_plane
), GFP_KERNEL
);
3086 cursor_plane
->base
.type
= DRM_PLANE_TYPE_CURSOR
;
3087 res
= amdgpu_dm_plane_init(dm
, cursor_plane
, 0);
3089 acrtc
= kzalloc(sizeof(struct amdgpu_crtc
), GFP_KERNEL
);
3093 res
= drm_crtc_init_with_planes(
3097 &cursor_plane
->base
,
3098 &amdgpu_dm_crtc_funcs
, NULL
);
3103 drm_crtc_helper_add(&acrtc
->base
, &amdgpu_dm_crtc_helper_funcs
);
3105 acrtc
->max_cursor_width
= dm
->adev
->dm
.dc
->caps
.max_cursor_size
;
3106 acrtc
->max_cursor_height
= dm
->adev
->dm
.dc
->caps
.max_cursor_size
;
3108 acrtc
->crtc_id
= crtc_index
;
3109 acrtc
->base
.enabled
= false;
3111 dm
->adev
->mode_info
.crtcs
[crtc_index
] = acrtc
;
3112 drm_mode_crtc_set_gamma_size(&acrtc
->base
, 256);
3118 kfree(cursor_plane
);
3123 static int to_drm_connector_type(enum signal_type st
)
3126 case SIGNAL_TYPE_HDMI_TYPE_A
:
3127 return DRM_MODE_CONNECTOR_HDMIA
;
3128 case SIGNAL_TYPE_EDP
:
3129 return DRM_MODE_CONNECTOR_eDP
;
3130 case SIGNAL_TYPE_RGB
:
3131 return DRM_MODE_CONNECTOR_VGA
;
3132 case SIGNAL_TYPE_DISPLAY_PORT
:
3133 case SIGNAL_TYPE_DISPLAY_PORT_MST
:
3134 return DRM_MODE_CONNECTOR_DisplayPort
;
3135 case SIGNAL_TYPE_DVI_DUAL_LINK
:
3136 case SIGNAL_TYPE_DVI_SINGLE_LINK
:
3137 return DRM_MODE_CONNECTOR_DVID
;
3138 case SIGNAL_TYPE_VIRTUAL
:
3139 return DRM_MODE_CONNECTOR_VIRTUAL
;
3142 return DRM_MODE_CONNECTOR_Unknown
;
3146 static void amdgpu_dm_get_native_mode(struct drm_connector
*connector
)
3148 const struct drm_connector_helper_funcs
*helper
=
3149 connector
->helper_private
;
3150 struct drm_encoder
*encoder
;
3151 struct amdgpu_encoder
*amdgpu_encoder
;
3153 encoder
= helper
->best_encoder(connector
);
3155 if (encoder
== NULL
)
3158 amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3160 amdgpu_encoder
->native_mode
.clock
= 0;
3162 if (!list_empty(&connector
->probed_modes
)) {
3163 struct drm_display_mode
*preferred_mode
= NULL
;
3165 list_for_each_entry(preferred_mode
,
3166 &connector
->probed_modes
,
3168 if (preferred_mode
->type
& DRM_MODE_TYPE_PREFERRED
)
3169 amdgpu_encoder
->native_mode
= *preferred_mode
;
3177 static struct drm_display_mode
*
3178 amdgpu_dm_create_common_mode(struct drm_encoder
*encoder
,
3180 int hdisplay
, int vdisplay
)
3182 struct drm_device
*dev
= encoder
->dev
;
3183 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3184 struct drm_display_mode
*mode
= NULL
;
3185 struct drm_display_mode
*native_mode
= &amdgpu_encoder
->native_mode
;
3187 mode
= drm_mode_duplicate(dev
, native_mode
);
3192 mode
->hdisplay
= hdisplay
;
3193 mode
->vdisplay
= vdisplay
;
3194 mode
->type
&= ~DRM_MODE_TYPE_PREFERRED
;
3195 strncpy(mode
->name
, name
, DRM_DISPLAY_MODE_LEN
);
3201 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder
*encoder
,
3202 struct drm_connector
*connector
)
3204 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3205 struct drm_display_mode
*mode
= NULL
;
3206 struct drm_display_mode
*native_mode
= &amdgpu_encoder
->native_mode
;
3207 struct amdgpu_dm_connector
*amdgpu_dm_connector
=
3208 to_amdgpu_dm_connector(connector
);
3212 char name
[DRM_DISPLAY_MODE_LEN
];
3215 } common_modes
[] = {
3216 { "640x480", 640, 480},
3217 { "800x600", 800, 600},
3218 { "1024x768", 1024, 768},
3219 { "1280x720", 1280, 720},
3220 { "1280x800", 1280, 800},
3221 {"1280x1024", 1280, 1024},
3222 { "1440x900", 1440, 900},
3223 {"1680x1050", 1680, 1050},
3224 {"1600x1200", 1600, 1200},
3225 {"1920x1080", 1920, 1080},
3226 {"1920x1200", 1920, 1200}
3229 n
= ARRAY_SIZE(common_modes
);
3231 for (i
= 0; i
< n
; i
++) {
3232 struct drm_display_mode
*curmode
= NULL
;
3233 bool mode_existed
= false;
3235 if (common_modes
[i
].w
> native_mode
->hdisplay
||
3236 common_modes
[i
].h
> native_mode
->vdisplay
||
3237 (common_modes
[i
].w
== native_mode
->hdisplay
&&
3238 common_modes
[i
].h
== native_mode
->vdisplay
))
3241 list_for_each_entry(curmode
, &connector
->probed_modes
, head
) {
3242 if (common_modes
[i
].w
== curmode
->hdisplay
&&
3243 common_modes
[i
].h
== curmode
->vdisplay
) {
3244 mode_existed
= true;
3252 mode
= amdgpu_dm_create_common_mode(encoder
,
3253 common_modes
[i
].name
, common_modes
[i
].w
,
3255 drm_mode_probed_add(connector
, mode
);
3256 amdgpu_dm_connector
->num_modes
++;
3260 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector
*connector
,
3263 struct amdgpu_dm_connector
*amdgpu_dm_connector
=
3264 to_amdgpu_dm_connector(connector
);
3267 /* empty probed_modes */
3268 INIT_LIST_HEAD(&connector
->probed_modes
);
3269 amdgpu_dm_connector
->num_modes
=
3270 drm_add_edid_modes(connector
, edid
);
3272 drm_edid_to_eld(connector
, edid
);
3274 amdgpu_dm_get_native_mode(connector
);
3276 amdgpu_dm_connector
->num_modes
= 0;
3279 static int amdgpu_dm_connector_get_modes(struct drm_connector
*connector
)
3281 const struct drm_connector_helper_funcs
*helper
=
3282 connector
->helper_private
;
3283 struct amdgpu_dm_connector
*amdgpu_dm_connector
=
3284 to_amdgpu_dm_connector(connector
);
3285 struct drm_encoder
*encoder
;
3286 struct edid
*edid
= amdgpu_dm_connector
->edid
;
3288 encoder
= helper
->best_encoder(connector
);
3290 amdgpu_dm_connector_ddc_get_modes(connector
, edid
);
3291 amdgpu_dm_connector_add_common_modes(encoder
, connector
);
3292 return amdgpu_dm_connector
->num_modes
;
3295 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager
*dm
,
3296 struct amdgpu_dm_connector
*aconnector
,
3298 struct dc_link
*link
,
3301 struct amdgpu_device
*adev
= dm
->ddev
->dev_private
;
3303 aconnector
->connector_id
= link_index
;
3304 aconnector
->dc_link
= link
;
3305 aconnector
->base
.interlace_allowed
= false;
3306 aconnector
->base
.doublescan_allowed
= false;
3307 aconnector
->base
.stereo_allowed
= false;
3308 aconnector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
3309 aconnector
->hpd
.hpd
= AMDGPU_HPD_NONE
; /* not used */
3311 mutex_init(&aconnector
->hpd_lock
);
3313 /* configure support HPD hot plug connector_>polled default value is 0
3314 * which means HPD hot plug not supported
3316 switch (connector_type
) {
3317 case DRM_MODE_CONNECTOR_HDMIA
:
3318 aconnector
->base
.polled
= DRM_CONNECTOR_POLL_HPD
;
3320 case DRM_MODE_CONNECTOR_DisplayPort
:
3321 aconnector
->base
.polled
= DRM_CONNECTOR_POLL_HPD
;
3323 case DRM_MODE_CONNECTOR_DVID
:
3324 aconnector
->base
.polled
= DRM_CONNECTOR_POLL_HPD
;
3330 drm_object_attach_property(&aconnector
->base
.base
,
3331 dm
->ddev
->mode_config
.scaling_mode_property
,
3332 DRM_MODE_SCALE_NONE
);
3334 drm_object_attach_property(&aconnector
->base
.base
,
3335 adev
->mode_info
.underscan_property
,
3337 drm_object_attach_property(&aconnector
->base
.base
,
3338 adev
->mode_info
.underscan_hborder_property
,
3340 drm_object_attach_property(&aconnector
->base
.base
,
3341 adev
->mode_info
.underscan_vborder_property
,
3346 static int amdgpu_dm_i2c_xfer(struct i2c_adapter
*i2c_adap
,
3347 struct i2c_msg
*msgs
, int num
)
3349 struct amdgpu_i2c_adapter
*i2c
= i2c_get_adapdata(i2c_adap
);
3350 struct ddc_service
*ddc_service
= i2c
->ddc_service
;
3351 struct i2c_command cmd
;
3355 cmd
.payloads
= kcalloc(num
, sizeof(struct i2c_payload
), GFP_KERNEL
);
3360 cmd
.number_of_payloads
= num
;
3361 cmd
.engine
= I2C_COMMAND_ENGINE_DEFAULT
;
3364 for (i
= 0; i
< num
; i
++) {
3365 cmd
.payloads
[i
].write
= !(msgs
[i
].flags
& I2C_M_RD
);
3366 cmd
.payloads
[i
].address
= msgs
[i
].addr
;
3367 cmd
.payloads
[i
].length
= msgs
[i
].len
;
3368 cmd
.payloads
[i
].data
= msgs
[i
].buf
;
3371 if (dal_i2caux_submit_i2c_command(
3372 ddc_service
->ctx
->i2caux
,
3373 ddc_service
->ddc_pin
,
3377 kfree(cmd
.payloads
);
3381 static u32
amdgpu_dm_i2c_func(struct i2c_adapter
*adap
)
3383 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
3386 static const struct i2c_algorithm amdgpu_dm_i2c_algo
= {
3387 .master_xfer
= amdgpu_dm_i2c_xfer
,
3388 .functionality
= amdgpu_dm_i2c_func
,
3391 static struct amdgpu_i2c_adapter
*
3392 create_i2c(struct ddc_service
*ddc_service
,
3396 struct amdgpu_device
*adev
= ddc_service
->ctx
->driver_context
;
3397 struct amdgpu_i2c_adapter
*i2c
;
3399 i2c
= kzalloc(sizeof(struct amdgpu_i2c_adapter
), GFP_KERNEL
);
3400 i2c
->base
.owner
= THIS_MODULE
;
3401 i2c
->base
.class = I2C_CLASS_DDC
;
3402 i2c
->base
.dev
.parent
= &adev
->pdev
->dev
;
3403 i2c
->base
.algo
= &amdgpu_dm_i2c_algo
;
3404 snprintf(i2c
->base
.name
, sizeof(i2c
->base
.name
), "AMDGPU DM i2c hw bus %d", link_index
);
3405 i2c_set_adapdata(&i2c
->base
, i2c
);
3406 i2c
->ddc_service
= ddc_service
;
3411 /* Note: this function assumes that dc_link_detect() was called for the
3412 * dc_link which will be represented by this aconnector.
3414 static int amdgpu_dm_connector_init(struct amdgpu_display_manager
*dm
,
3415 struct amdgpu_dm_connector
*aconnector
,
3416 uint32_t link_index
,
3417 struct amdgpu_encoder
*aencoder
)
3421 struct dc
*dc
= dm
->dc
;
3422 struct dc_link
*link
= dc_get_link_at_index(dc
, link_index
);
3423 struct amdgpu_i2c_adapter
*i2c
;
3424 ((struct dc_link
*)link
)->priv
= aconnector
;
3426 DRM_DEBUG_DRIVER("%s()\n", __func__
);
3428 i2c
= create_i2c(link
->ddc
, link
->link_index
, &res
);
3429 aconnector
->i2c
= i2c
;
3430 res
= i2c_add_adapter(&i2c
->base
);
3433 DRM_ERROR("Failed to register hw i2c %d\n", link
->link_index
);
3437 connector_type
= to_drm_connector_type(link
->connector_signal
);
3439 res
= drm_connector_init(
3442 &amdgpu_dm_connector_funcs
,
3446 DRM_ERROR("connector_init failed\n");
3447 aconnector
->connector_id
= -1;
3451 drm_connector_helper_add(
3453 &amdgpu_dm_connector_helper_funcs
);
3455 amdgpu_dm_connector_init_helper(
3462 drm_mode_connector_attach_encoder(
3463 &aconnector
->base
, &aencoder
->base
);
3465 drm_connector_register(&aconnector
->base
);
3467 if (connector_type
== DRM_MODE_CONNECTOR_DisplayPort
3468 || connector_type
== DRM_MODE_CONNECTOR_eDP
)
3469 amdgpu_dm_initialize_dp_connector(dm
, aconnector
);
3471 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3472 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3474 /* NOTE: this currently will create backlight device even if a panel
3475 * is not connected to the eDP/LVDS connector.
3477 * This is less than ideal but we don't have sink information at this
3478 * stage since detection happens after. We can't do detection earlier
3479 * since MST detection needs connectors to be created first.
3481 if (link
->connector_signal
& (SIGNAL_TYPE_EDP
| SIGNAL_TYPE_LVDS
)) {
3482 /* Event if registration failed, we should continue with
3483 * DM initialization because not having a backlight control
3484 * is better then a black screen.
3486 amdgpu_dm_register_backlight_device(dm
);
3488 if (dm
->backlight_dev
)
3489 dm
->backlight_link
= link
;
3496 aconnector
->i2c
= NULL
;
3501 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device
*adev
)
3503 switch (adev
->mode_info
.num_crtc
) {
3520 static int amdgpu_dm_encoder_init(struct drm_device
*dev
,
3521 struct amdgpu_encoder
*aencoder
,
3522 uint32_t link_index
)
3524 struct amdgpu_device
*adev
= dev
->dev_private
;
3526 int res
= drm_encoder_init(dev
,
3528 &amdgpu_dm_encoder_funcs
,
3529 DRM_MODE_ENCODER_TMDS
,
3532 aencoder
->base
.possible_crtcs
= amdgpu_dm_get_encoder_crtc_mask(adev
);
3535 aencoder
->encoder_id
= link_index
;
3537 aencoder
->encoder_id
= -1;
3539 drm_encoder_helper_add(&aencoder
->base
, &amdgpu_dm_encoder_helper_funcs
);
3544 static void manage_dm_interrupts(struct amdgpu_device
*adev
,
3545 struct amdgpu_crtc
*acrtc
,
3549 * this is not correct translation but will work as soon as VBLANK
3550 * constant is the same as PFLIP
3553 amdgpu_crtc_idx_to_irq_type(
3558 drm_crtc_vblank_on(&acrtc
->base
);
3561 &adev
->pageflip_irq
,
3567 &adev
->pageflip_irq
,
3569 drm_crtc_vblank_off(&acrtc
->base
);
3574 is_scaling_state_different(const struct dm_connector_state
*dm_state
,
3575 const struct dm_connector_state
*old_dm_state
)
3577 if (dm_state
->scaling
!= old_dm_state
->scaling
)
3579 if (!dm_state
->underscan_enable
&& old_dm_state
->underscan_enable
) {
3580 if (old_dm_state
->underscan_hborder
!= 0 && old_dm_state
->underscan_vborder
!= 0)
3582 } else if (dm_state
->underscan_enable
&& !old_dm_state
->underscan_enable
) {
3583 if (dm_state
->underscan_hborder
!= 0 && dm_state
->underscan_vborder
!= 0)
3585 } else if (dm_state
->underscan_hborder
!= old_dm_state
->underscan_hborder
||
3586 dm_state
->underscan_vborder
!= old_dm_state
->underscan_vborder
)
3591 static void remove_stream(struct amdgpu_device
*adev
,
3592 struct amdgpu_crtc
*acrtc
,
3593 struct dc_stream_state
*stream
)
3595 /* this is the update mode case */
3596 if (adev
->dm
.freesync_module
)
3597 mod_freesync_remove_stream(adev
->dm
.freesync_module
, stream
);
3599 acrtc
->otg_inst
= -1;
3600 acrtc
->enabled
= false;
3603 static int get_cursor_position(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
3604 struct dc_cursor_position
*position
)
3606 struct amdgpu_crtc
*amdgpu_crtc
= amdgpu_crtc
= to_amdgpu_crtc(crtc
);
3608 int xorigin
= 0, yorigin
= 0;
3610 if (!crtc
|| !plane
->state
->fb
) {
3611 position
->enable
= false;
3617 if ((plane
->state
->crtc_w
> amdgpu_crtc
->max_cursor_width
) ||
3618 (plane
->state
->crtc_h
> amdgpu_crtc
->max_cursor_height
)) {
3619 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3621 plane
->state
->crtc_w
,
3622 plane
->state
->crtc_h
);
3626 x
= plane
->state
->crtc_x
;
3627 y
= plane
->state
->crtc_y
;
3628 /* avivo cursor are offset into the total surface */
3629 x
+= crtc
->primary
->state
->src_x
>> 16;
3630 y
+= crtc
->primary
->state
->src_y
>> 16;
3632 xorigin
= min(-x
, amdgpu_crtc
->max_cursor_width
- 1);
3636 yorigin
= min(-y
, amdgpu_crtc
->max_cursor_height
- 1);
3639 position
->enable
= true;
3642 position
->x_hotspot
= xorigin
;
3643 position
->y_hotspot
= yorigin
;
3648 static void handle_cursor_update(struct drm_plane
*plane
,
3649 struct drm_plane_state
*old_plane_state
)
3651 struct amdgpu_framebuffer
*afb
= to_amdgpu_framebuffer(plane
->state
->fb
);
3652 struct drm_crtc
*crtc
= afb
? plane
->state
->crtc
: old_plane_state
->crtc
;
3653 struct dm_crtc_state
*crtc_state
= crtc
? to_dm_crtc_state(crtc
->state
) : NULL
;
3654 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
3655 uint64_t address
= afb
? afb
->address
: 0;
3656 struct dc_cursor_position position
;
3657 struct dc_cursor_attributes attributes
;
3660 if (!plane
->state
->fb
&& !old_plane_state
->fb
)
3663 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
3665 amdgpu_crtc
->crtc_id
,
3666 plane
->state
->crtc_w
,
3667 plane
->state
->crtc_h
);
3669 ret
= get_cursor_position(plane
, crtc
, &position
);
3673 if (!position
.enable
) {
3674 /* turn off cursor */
3675 if (crtc_state
&& crtc_state
->stream
)
3676 dc_stream_set_cursor_position(crtc_state
->stream
,
3681 amdgpu_crtc
->cursor_width
= plane
->state
->crtc_w
;
3682 amdgpu_crtc
->cursor_height
= plane
->state
->crtc_h
;
3684 attributes
.address
.high_part
= upper_32_bits(address
);
3685 attributes
.address
.low_part
= lower_32_bits(address
);
3686 attributes
.width
= plane
->state
->crtc_w
;
3687 attributes
.height
= plane
->state
->crtc_h
;
3688 attributes
.color_format
= CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA
;
3689 attributes
.rotation_angle
= 0;
3690 attributes
.attribute_flags
.value
= 0;
3692 attributes
.pitch
= attributes
.width
;
3694 if (!dc_stream_set_cursor_attributes(crtc_state
->stream
,
3696 DRM_ERROR("DC failed to set cursor attributes\n");
3698 if (crtc_state
->stream
)
3699 if (!dc_stream_set_cursor_position(crtc_state
->stream
,
3701 DRM_ERROR("DC failed to set cursor position\n");
3704 static void prepare_flip_isr(struct amdgpu_crtc
*acrtc
)
3707 assert_spin_locked(&acrtc
->base
.dev
->event_lock
);
3708 WARN_ON(acrtc
->event
);
3710 acrtc
->event
= acrtc
->base
.state
->event
;
3712 /* Set the flip status */
3713 acrtc
->pflip_status
= AMDGPU_FLIP_SUBMITTED
;
3715 /* Mark this event as consumed */
3716 acrtc
->base
.state
->event
= NULL
;
3718 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3725 * Waits on all BO's fences and for proper vblank count
3727 static void amdgpu_dm_do_flip(struct drm_crtc
*crtc
,
3728 struct drm_framebuffer
*fb
,
3731 unsigned long flags
;
3732 uint32_t target_vblank
;
3734 struct amdgpu_crtc
*acrtc
= to_amdgpu_crtc(crtc
);
3735 struct amdgpu_framebuffer
*afb
= to_amdgpu_framebuffer(fb
);
3736 struct amdgpu_bo
*abo
= gem_to_amdgpu_bo(afb
->obj
);
3737 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
3738 bool async_flip
= (crtc
->state
->pageflip_flags
& DRM_MODE_PAGE_FLIP_ASYNC
) != 0;
3739 struct dc_flip_addrs addr
= { {0} };
3740 /* TODO eliminate or rename surface_update */
3741 struct dc_surface_update surface_updates
[1] = { {0} };
3742 struct dm_crtc_state
*acrtc_state
= to_dm_crtc_state(crtc
->state
);
3745 /* Prepare wait for target vblank early - before the fence-waits */
3746 target_vblank
= target
- drm_crtc_vblank_count(crtc
) +
3747 amdgpu_get_vblank_counter_kms(crtc
->dev
, acrtc
->crtc_id
);
3749 /* TODO This might fail and hence better not used, wait
3750 * explicitly on fences instead
3751 * and in general should be called for
3752 * blocking commit to as per framework helpers
3754 r
= amdgpu_bo_reserve(abo
, true);
3755 if (unlikely(r
!= 0)) {
3756 DRM_ERROR("failed to reserve buffer before flip\n");
3760 /* Wait for all fences on this FB */
3761 WARN_ON(reservation_object_wait_timeout_rcu(abo
->tbo
.resv
, true, false,
3762 MAX_SCHEDULE_TIMEOUT
) < 0);
3764 amdgpu_bo_unreserve(abo
);
3766 /* Wait until we're out of the vertical blank period before the one
3767 * targeted by the flip
3769 while ((acrtc
->enabled
&&
3770 (amdgpu_get_crtc_scanoutpos(adev
->ddev
, acrtc
->crtc_id
, 0,
3771 &vpos
, &hpos
, NULL
, NULL
,
3773 & (DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_IN_VBLANK
)) ==
3774 (DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_IN_VBLANK
) &&
3775 (int)(target_vblank
-
3776 amdgpu_get_vblank_counter_kms(adev
->ddev
, acrtc
->crtc_id
)) > 0)) {
3777 usleep_range(1000, 1100);
3781 spin_lock_irqsave(&crtc
->dev
->event_lock
, flags
);
3782 /* update crtc fb */
3783 crtc
->primary
->fb
= fb
;
3785 WARN_ON(acrtc
->pflip_status
!= AMDGPU_FLIP_NONE
);
3786 WARN_ON(!acrtc_state
->stream
);
3788 addr
.address
.grph
.addr
.low_part
= lower_32_bits(afb
->address
);
3789 addr
.address
.grph
.addr
.high_part
= upper_32_bits(afb
->address
);
3790 addr
.flip_immediate
= async_flip
;
3793 if (acrtc
->base
.state
->event
)
3794 prepare_flip_isr(acrtc
);
3796 surface_updates
->surface
= dc_stream_get_status(acrtc_state
->stream
)->plane_states
[0];
3797 surface_updates
->flip_addr
= &addr
;
3800 dc_update_planes_and_stream(adev
->dm
.dc
, surface_updates
, 1, acrtc_state
->stream
, NULL
);
3802 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3804 addr
.address
.grph
.addr
.high_part
,
3805 addr
.address
.grph
.addr
.low_part
);
3808 spin_unlock_irqrestore(&crtc
->dev
->event_lock
, flags
);
3811 static void amdgpu_dm_commit_planes(struct drm_atomic_state
*state
,
3812 struct drm_device
*dev
,
3813 struct amdgpu_display_manager
*dm
,
3814 struct drm_crtc
*pcrtc
,
3815 bool *wait_for_vblank
)
3818 struct drm_plane
*plane
;
3819 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
3820 struct dc_stream_state
*dc_stream_attach
;
3821 struct dc_plane_state
*plane_states_constructed
[MAX_SURFACES
];
3822 struct amdgpu_crtc
*acrtc_attach
= to_amdgpu_crtc(pcrtc
);
3823 struct drm_crtc_state
*new_pcrtc_state
=
3824 drm_atomic_get_new_crtc_state(state
, pcrtc
);
3825 struct dm_crtc_state
*acrtc_state
= to_dm_crtc_state(new_pcrtc_state
);
3826 int planes_count
= 0;
3827 unsigned long flags
;
3829 /* update planes when needed */
3830 for_each_oldnew_plane_in_state(state
, plane
, old_plane_state
, new_plane_state
, i
) {
3831 struct drm_crtc
*crtc
= new_plane_state
->crtc
;
3832 struct drm_crtc_state
*new_crtc_state
=
3833 drm_atomic_get_new_crtc_state(state
, crtc
);
3834 struct drm_framebuffer
*fb
= new_plane_state
->fb
;
3836 struct dm_plane_state
*dm_new_plane_state
= to_dm_plane_state(new_plane_state
);
3838 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
) {
3839 handle_cursor_update(plane
, old_plane_state
);
3843 if (!fb
|| !crtc
|| pcrtc
!= crtc
|| !new_crtc_state
->active
)
3846 pflip_needed
= !state
->allow_modeset
;
3848 spin_lock_irqsave(&crtc
->dev
->event_lock
, flags
);
3849 if (acrtc_attach
->pflip_status
!= AMDGPU_FLIP_NONE
) {
3850 DRM_ERROR("%s: acrtc %d, already busy\n",
3852 acrtc_attach
->crtc_id
);
3853 spin_unlock_irqrestore(&crtc
->dev
->event_lock
, flags
);
3854 /* In commit tail framework this cannot happen */
3857 spin_unlock_irqrestore(&crtc
->dev
->event_lock
, flags
);
3859 if (!pflip_needed
) {
3860 WARN_ON(!dm_new_plane_state
->dc_state
);
3862 plane_states_constructed
[planes_count
] = dm_new_plane_state
->dc_state
;
3864 dc_stream_attach
= acrtc_state
->stream
;
3867 } else if (new_crtc_state
->planes_changed
) {
3868 /* Assume even ONE crtc with immediate flip means
3869 * entire can't wait for VBLANK
3870 * TODO Check if it's correct
3873 new_pcrtc_state
->pageflip_flags
& DRM_MODE_PAGE_FLIP_ASYNC
?
3876 /* TODO: Needs rework for multiplane flip */
3877 if (plane
->type
== DRM_PLANE_TYPE_PRIMARY
)
3878 drm_crtc_vblank_get(crtc
);
3883 drm_crtc_vblank_count(crtc
) + *wait_for_vblank
);
3889 unsigned long flags
;
3891 if (new_pcrtc_state
->event
) {
3893 drm_crtc_vblank_get(pcrtc
);
3895 spin_lock_irqsave(&pcrtc
->dev
->event_lock
, flags
);
3896 prepare_flip_isr(acrtc_attach
);
3897 spin_unlock_irqrestore(&pcrtc
->dev
->event_lock
, flags
);
3900 if (false == dc_commit_planes_to_stream(dm
->dc
,
3901 plane_states_constructed
,
3904 dm_error("%s: Failed to attach plane!\n", __func__
);
3906 /*TODO BUG Here should go disable planes on CRTC. */
3911 static int amdgpu_dm_atomic_commit(struct drm_device
*dev
,
3912 struct drm_atomic_state
*state
,
3915 struct drm_crtc
*crtc
;
3916 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
3917 struct amdgpu_device
*adev
= dev
->dev_private
;
3921 * We evade vblanks and pflips on crtc that
3922 * should be changed. We do it here to flush & disable
3923 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
3924 * it will update crtc->dm_crtc_state->stream pointer which is used in
3927 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
3928 struct dm_crtc_state
*dm_old_crtc_state
= to_dm_crtc_state(old_crtc_state
);
3929 struct amdgpu_crtc
*acrtc
= to_amdgpu_crtc(crtc
);
3931 if (drm_atomic_crtc_needs_modeset(new_crtc_state
) && dm_old_crtc_state
->stream
)
3932 manage_dm_interrupts(adev
, acrtc
, false);
3935 return drm_atomic_helper_commit(dev
, state
, nonblock
);
3937 /*TODO Handle EINTR, reenable IRQ*/
3940 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state
*state
)
3942 struct drm_device
*dev
= state
->dev
;
3943 struct amdgpu_device
*adev
= dev
->dev_private
;
3944 struct amdgpu_display_manager
*dm
= &adev
->dm
;
3945 struct dm_atomic_state
*dm_state
;
3947 uint32_t new_crtcs_count
= 0;
3948 struct drm_crtc
*crtc
;
3949 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
3950 struct amdgpu_crtc
*new_crtcs
[MAX_STREAMS
];
3951 struct dc_stream_state
*new_stream
= NULL
;
3952 unsigned long flags
;
3953 bool wait_for_vblank
= true;
3954 struct drm_connector
*connector
;
3955 struct drm_connector_state
*old_con_state
, *new_con_state
;
3956 struct dm_crtc_state
*dm_old_crtc_state
, *dm_new_crtc_state
;
3958 drm_atomic_helper_update_legacy_modeset_state(dev
, state
);
3960 dm_state
= to_dm_atomic_state(state
);
3962 /* update changed items */
3963 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
3964 struct amdgpu_crtc
*acrtc
= to_amdgpu_crtc(crtc
);
3966 dm_new_crtc_state
= to_dm_crtc_state(new_crtc_state
);
3967 dm_old_crtc_state
= to_dm_crtc_state(old_crtc_state
);
3970 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
3971 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
3972 "connectors_changed:%d\n",
3974 new_crtc_state
->enable
,
3975 new_crtc_state
->active
,
3976 new_crtc_state
->planes_changed
,
3977 new_crtc_state
->mode_changed
,
3978 new_crtc_state
->active_changed
,
3979 new_crtc_state
->connectors_changed
);
3981 /* handles headless hotplug case, updating new_state and
3982 * aconnector as needed
3985 if (modeset_required(new_crtc_state
, dm_new_crtc_state
->stream
, dm_old_crtc_state
->stream
)) {
3987 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc
->crtc_id
, acrtc
);
3989 if (!dm_new_crtc_state
->stream
) {
3991 * this could happen because of issues with
3992 * userspace notifications delivery.
3993 * In this case userspace tries to set mode on
3994 * display which is disconnect in fact.
3995 * dc_sink in NULL in this case on aconnector.
3996 * We expect reset mode will come soon.
3998 * This can also happen when unplug is done
3999 * during resume sequence ended
4001 * In this case, we want to pretend we still
4002 * have a sink to keep the pipe running so that
4003 * hw state is consistent with the sw state
4005 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
4006 __func__
, acrtc
->base
.base
.id
);
4011 if (dm_old_crtc_state
->stream
)
4012 remove_stream(adev
, acrtc
, dm_old_crtc_state
->stream
);
4016 * this loop saves set mode crtcs
4017 * we needed to enable vblanks once all
4018 * resources acquired in dc after dc_commit_streams
4021 /*TODO move all this into dm_crtc_state, get rid of
4022 * new_crtcs array and use old and new atomic states
4025 new_crtcs
[new_crtcs_count
] = acrtc
;
4028 new_crtc_state
= drm_atomic_get_new_crtc_state(state
, crtc
);
4029 acrtc
->enabled
= true;
4030 acrtc
->hw_mode
= new_crtc_state
->mode
;
4031 crtc
->hwmode
= new_crtc_state
->mode
;
4032 } else if (modereset_required(new_crtc_state
)) {
4033 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc
->crtc_id
, acrtc
);
4035 /* i.e. reset mode */
4036 if (dm_old_crtc_state
->stream
)
4037 remove_stream(adev
, acrtc
, dm_old_crtc_state
->stream
);
4039 } /* for_each_crtc_in_state() */
4042 * Add streams after required streams from new and replaced streams
4043 * are removed from freesync module
4045 if (adev
->dm
.freesync_module
) {
4046 for (i
= 0; i
< new_crtcs_count
; i
++) {
4047 struct amdgpu_dm_connector
*aconnector
= NULL
;
4049 new_crtc_state
= drm_atomic_get_new_crtc_state(state
,
4050 &new_crtcs
[i
]->base
);
4051 dm_new_crtc_state
= to_dm_crtc_state(new_crtc_state
);
4053 new_stream
= dm_new_crtc_state
->stream
;
4054 aconnector
= amdgpu_dm_find_first_crtc_matching_connector(
4056 &new_crtcs
[i
]->base
);
4058 DRM_DEBUG_DRIVER("Atomic commit: Failed to find connector for acrtc id:%d "
4059 "skipping freesync init\n",
4060 new_crtcs
[i
]->crtc_id
);
4064 mod_freesync_add_stream(adev
->dm
.freesync_module
,
4065 new_stream
, &aconnector
->caps
);
4069 if (dm_state
->context
)
4070 WARN_ON(!dc_commit_state(dm
->dc
, dm_state
->context
));
4072 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
4073 struct amdgpu_crtc
*acrtc
= to_amdgpu_crtc(crtc
);
4075 dm_new_crtc_state
= to_dm_crtc_state(new_crtc_state
);
4077 if (dm_new_crtc_state
->stream
!= NULL
) {
4078 const struct dc_stream_status
*status
=
4079 dc_stream_get_status(dm_new_crtc_state
->stream
);
4082 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state
->stream
, acrtc
);
4084 acrtc
->otg_inst
= status
->primary_otg_inst
;
4088 /* Handle scaling and underscan changes*/
4089 for_each_oldnew_connector_in_state(state
, connector
, old_con_state
, new_con_state
, i
) {
4090 struct dm_connector_state
*dm_new_con_state
= to_dm_connector_state(new_con_state
);
4091 struct dm_connector_state
*dm_old_con_state
= to_dm_connector_state(old_con_state
);
4092 struct amdgpu_crtc
*acrtc
= to_amdgpu_crtc(dm_new_con_state
->base
.crtc
);
4093 struct dc_stream_status
*status
= NULL
;
4096 new_crtc_state
= drm_atomic_get_new_crtc_state(state
, &acrtc
->base
);
4098 /* Skip any modesets/resets */
4099 if (!acrtc
|| drm_atomic_crtc_needs_modeset(new_crtc_state
))
4102 /* Skip any thing not scale or underscan changes */
4103 if (!is_scaling_state_different(dm_new_con_state
, dm_old_con_state
))
4106 dm_new_crtc_state
= to_dm_crtc_state(new_crtc_state
);
4108 update_stream_scaling_settings(&dm_new_con_state
->base
.crtc
->mode
,
4109 dm_new_con_state
, (struct dc_stream_state
*)dm_new_crtc_state
->stream
);
4111 status
= dc_stream_get_status(dm_new_crtc_state
->stream
);
4113 WARN_ON(!status
->plane_count
);
4115 if (!dm_new_crtc_state
->stream
)
4118 /*TODO How it works with MPO ?*/
4119 if (!dc_commit_planes_to_stream(
4121 status
->plane_states
,
4122 status
->plane_count
,
4123 dm_new_crtc_state
->stream
))
4124 dm_error("%s: Failed to update stream scaling!\n", __func__
);
4127 for (i
= 0; i
< new_crtcs_count
; i
++) {
4129 * loop to enable interrupts on newly arrived crtc
4131 struct amdgpu_crtc
*acrtc
= new_crtcs
[i
];
4133 new_crtc_state
= drm_atomic_get_new_crtc_state(state
, &acrtc
->base
);
4134 dm_new_crtc_state
= to_dm_crtc_state(new_crtc_state
);
4136 if (adev
->dm
.freesync_module
)
4137 mod_freesync_notify_mode_change(
4138 adev
->dm
.freesync_module
, &dm_new_crtc_state
->stream
, 1);
4140 manage_dm_interrupts(adev
, acrtc
, true);
4143 /* update planes when needed per crtc*/
4144 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, j
) {
4145 dm_new_crtc_state
= to_dm_crtc_state(new_crtc_state
);
4147 if (dm_new_crtc_state
->stream
)
4148 amdgpu_dm_commit_planes(state
, dev
, dm
, crtc
, &wait_for_vblank
);
4153 * send vblank event on all events not handled in flip and
4154 * mark consumed event for drm_atomic_helper_commit_hw_done
4156 spin_lock_irqsave(&adev
->ddev
->event_lock
, flags
);
4157 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
4159 if (new_crtc_state
->event
)
4160 drm_send_event_locked(dev
, &new_crtc_state
->event
->base
);
4162 new_crtc_state
->event
= NULL
;
4164 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
4166 /* Signal HW programming completion */
4167 drm_atomic_helper_commit_hw_done(state
);
4169 if (wait_for_vblank
)
4170 drm_atomic_helper_wait_for_vblanks(dev
, state
);
4172 drm_atomic_helper_cleanup_planes(dev
, state
);
4176 static int dm_force_atomic_commit(struct drm_connector
*connector
)
4179 struct drm_device
*ddev
= connector
->dev
;
4180 struct drm_atomic_state
*state
= drm_atomic_state_alloc(ddev
);
4181 struct amdgpu_crtc
*disconnected_acrtc
= to_amdgpu_crtc(connector
->encoder
->crtc
);
4182 struct drm_plane
*plane
= disconnected_acrtc
->base
.primary
;
4183 struct drm_connector_state
*conn_state
;
4184 struct drm_crtc_state
*crtc_state
;
4185 struct drm_plane_state
*plane_state
;
4190 state
->acquire_ctx
= ddev
->mode_config
.acquire_ctx
;
4192 /* Construct an atomic state to restore previous display setting */
4195 * Attach connectors to drm_atomic_state
4197 conn_state
= drm_atomic_get_connector_state(state
, connector
);
4199 ret
= PTR_ERR_OR_ZERO(conn_state
);
4203 /* Attach crtc to drm_atomic_state*/
4204 crtc_state
= drm_atomic_get_crtc_state(state
, &disconnected_acrtc
->base
);
4206 ret
= PTR_ERR_OR_ZERO(crtc_state
);
4210 /* force a restore */
4211 crtc_state
->mode_changed
= true;
4213 /* Attach plane to drm_atomic_state */
4214 plane_state
= drm_atomic_get_plane_state(state
, plane
);
4216 ret
= PTR_ERR_OR_ZERO(plane_state
);
4221 /* Call commit internally with the state we just constructed */
4222 ret
= drm_atomic_commit(state
);
4227 DRM_ERROR("Restoring old state failed with %i\n", ret
);
4228 drm_atomic_state_put(state
);
4234 * This functions handle all cases when set mode does not come upon hotplug.
4235 * This include when the same display is unplugged then plugged back into the
4236 * same port and when we are running without usermode desktop manager supprot
4238 void dm_restore_drm_connector_state(struct drm_device
*dev
,
4239 struct drm_connector
*connector
)
4241 struct amdgpu_dm_connector
*aconnector
= to_amdgpu_dm_connector(connector
);
4242 struct amdgpu_crtc
*disconnected_acrtc
;
4243 struct dm_crtc_state
*acrtc_state
;
4245 if (!aconnector
->dc_sink
|| !connector
->state
|| !connector
->encoder
)
4248 disconnected_acrtc
= to_amdgpu_crtc(connector
->encoder
->crtc
);
4249 acrtc_state
= to_dm_crtc_state(disconnected_acrtc
->base
.state
);
4251 if (!disconnected_acrtc
|| !acrtc_state
->stream
)
4255 * If the previous sink is not released and different from the current,
4256 * we deduce we are in a state where we can not rely on usermode call
4257 * to turn on the display, so we do it here
4259 if (acrtc_state
->stream
->sink
!= aconnector
->dc_sink
)
4260 dm_force_atomic_commit(&aconnector
->base
);
4264 * Grabs all modesetting locks to serialize against any blocking commits,
4265 * Waits for completion of all non blocking commits.
4267 static int do_aquire_global_lock(struct drm_device
*dev
,
4268 struct drm_atomic_state
*state
)
4270 struct drm_crtc
*crtc
;
4271 struct drm_crtc_commit
*commit
;
4274 /* Adding all modeset locks to aquire_ctx will
4275 * ensure that when the framework release it the
4276 * extra locks we are locking here will get released to
4278 ret
= drm_modeset_lock_all_ctx(dev
, state
->acquire_ctx
);
4282 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4283 spin_lock(&crtc
->commit_lock
);
4284 commit
= list_first_entry_or_null(&crtc
->commit_list
,
4285 struct drm_crtc_commit
, commit_entry
);
4287 drm_crtc_commit_get(commit
);
4288 spin_unlock(&crtc
->commit_lock
);
4293 /* Make sure all pending HW programming completed and
4296 ret
= wait_for_completion_interruptible_timeout(&commit
->hw_done
, 10*HZ
);
4299 ret
= wait_for_completion_interruptible_timeout(
4300 &commit
->flip_done
, 10*HZ
);
4303 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
4304 "timed out\n", crtc
->base
.id
, crtc
->name
);
4306 drm_crtc_commit_put(commit
);
4309 return ret
< 0 ? ret
: 0;
4312 static int dm_update_crtcs_state(struct dc
*dc
,
4313 struct drm_atomic_state
*state
,
4315 bool *lock_and_validation_needed
)
4317 struct drm_crtc
*crtc
;
4318 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
4320 struct dm_crtc_state
*dm_old_crtc_state
, *dm_new_crtc_state
;
4321 struct dm_atomic_state
*dm_state
= to_dm_atomic_state(state
);
4322 struct dc_stream_state
*new_stream
;
4325 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4326 /* update changed items */
4327 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
4328 struct amdgpu_crtc
*acrtc
= NULL
;
4329 struct amdgpu_dm_connector
*aconnector
= NULL
;
4330 struct drm_connector_state
*new_con_state
= NULL
;
4331 struct dm_connector_state
*dm_conn_state
= NULL
;
4335 dm_old_crtc_state
= to_dm_crtc_state(old_crtc_state
);
4336 dm_new_crtc_state
= to_dm_crtc_state(new_crtc_state
);
4337 acrtc
= to_amdgpu_crtc(crtc
);
4339 aconnector
= amdgpu_dm_find_first_crtc_matching_connector(state
, crtc
);
4341 /* TODO This hack should go away */
4343 new_con_state
= drm_atomic_get_connector_state(state
,
4346 if (IS_ERR(new_con_state
)) {
4347 ret
= PTR_ERR_OR_ZERO(new_con_state
);
4351 dm_conn_state
= to_dm_connector_state(new_con_state
);
4353 new_stream
= create_stream_for_sink(aconnector
,
4354 &new_crtc_state
->mode
,
4358 * we can have no stream on ACTION_SET if a display
4359 * was disconnected during S3, in this case it not and
4360 * error, the OS will be updated after detection, and
4361 * do the right thing on next atomic commit
4365 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
4366 __func__
, acrtc
->base
.base
.id
);
4371 if (dc_is_stream_unchanged(new_stream
, dm_old_crtc_state
->stream
)) {
4373 new_crtc_state
->mode_changed
= false;
4375 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
4376 new_crtc_state
->mode_changed
);
4380 if (!drm_atomic_crtc_needs_modeset(new_crtc_state
))
4384 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4385 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4386 "connectors_changed:%d\n",
4388 new_crtc_state
->enable
,
4389 new_crtc_state
->active
,
4390 new_crtc_state
->planes_changed
,
4391 new_crtc_state
->mode_changed
,
4392 new_crtc_state
->active_changed
,
4393 new_crtc_state
->connectors_changed
);
4395 /* Remove stream for any changed/disabled CRTC */
4398 if (!dm_old_crtc_state
->stream
)
4401 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
4404 /* i.e. reset mode */
4405 if (!dc_remove_stream_from_ctx(
4408 dm_old_crtc_state
->stream
)) {
4413 dc_stream_release(dm_old_crtc_state
->stream
);
4414 dm_new_crtc_state
->stream
= NULL
;
4416 *lock_and_validation_needed
= true;
4418 } else {/* Add stream for any updated/enabled CRTC */
4420 if (modereset_required(new_crtc_state
))
4423 if (modeset_required(new_crtc_state
, new_stream
,
4424 dm_old_crtc_state
->stream
)) {
4426 WARN_ON(dm_new_crtc_state
->stream
);
4428 dm_new_crtc_state
->stream
= new_stream
;
4429 dc_stream_retain(new_stream
);
4431 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
4434 if (!dc_add_stream_to_ctx(
4437 dm_new_crtc_state
->stream
)) {
4442 *lock_and_validation_needed
= true;
4447 /* Release extra reference */
4449 dc_stream_release(new_stream
);
4456 dc_stream_release(new_stream
);
4460 static int dm_update_planes_state(struct dc
*dc
,
4461 struct drm_atomic_state
*state
,
4463 bool *lock_and_validation_needed
)
4465 struct drm_crtc
*new_plane_crtc
, *old_plane_crtc
;
4466 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
4467 struct drm_plane
*plane
;
4468 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
4469 struct dm_crtc_state
*dm_new_crtc_state
, *dm_old_crtc_state
;
4470 struct dm_atomic_state
*dm_state
= to_dm_atomic_state(state
);
4471 struct dm_plane_state
*dm_new_plane_state
, *dm_old_plane_state
;
4473 /* TODO return page_flip_needed() function */
4474 bool pflip_needed
= !state
->allow_modeset
;
4480 /* Add new planes */
4481 for_each_oldnew_plane_in_state(state
, plane
, old_plane_state
, new_plane_state
, i
) {
4482 new_plane_crtc
= new_plane_state
->crtc
;
4483 old_plane_crtc
= old_plane_state
->crtc
;
4484 dm_new_plane_state
= to_dm_plane_state(new_plane_state
);
4485 dm_old_plane_state
= to_dm_plane_state(old_plane_state
);
4487 /*TODO Implement atomic check for cursor plane */
4488 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
4491 /* Remove any changed/removed planes */
4494 if (!old_plane_crtc
)
4497 old_crtc_state
= drm_atomic_get_old_crtc_state(
4498 state
, old_plane_crtc
);
4499 dm_old_crtc_state
= to_dm_crtc_state(old_crtc_state
);
4501 if (!dm_old_crtc_state
->stream
)
4504 DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n",
4505 plane
->base
.id
, old_plane_crtc
->base
.id
);
4507 if (!dc_remove_plane_from_context(
4509 dm_old_crtc_state
->stream
,
4510 dm_old_plane_state
->dc_state
,
4511 dm_state
->context
)) {
4518 dc_plane_state_release(dm_old_plane_state
->dc_state
);
4519 dm_new_plane_state
->dc_state
= NULL
;
4521 *lock_and_validation_needed
= true;
4523 } else { /* Add new planes */
4525 if (drm_atomic_plane_disabling(plane
->state
, new_plane_state
))
4528 if (!new_plane_crtc
)
4531 new_crtc_state
= drm_atomic_get_new_crtc_state(state
, new_plane_crtc
);
4532 dm_new_crtc_state
= to_dm_crtc_state(new_crtc_state
);
4534 if (!dm_new_crtc_state
->stream
)
4538 WARN_ON(dm_new_plane_state
->dc_state
);
4540 dm_new_plane_state
->dc_state
= dc_create_plane_state(dc
);
4542 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
4543 plane
->base
.id
, new_plane_crtc
->base
.id
);
4545 if (!dm_new_plane_state
->dc_state
) {
4550 ret
= fill_plane_attributes(
4551 new_plane_crtc
->dev
->dev_private
,
4552 dm_new_plane_state
->dc_state
,
4560 if (!dc_add_plane_to_context(
4562 dm_new_crtc_state
->stream
,
4563 dm_new_plane_state
->dc_state
,
4564 dm_state
->context
)) {
4570 *lock_and_validation_needed
= true;
4578 static int amdgpu_dm_atomic_check(struct drm_device
*dev
,
4579 struct drm_atomic_state
*state
)
4583 struct amdgpu_device
*adev
= dev
->dev_private
;
4584 struct dc
*dc
= adev
->dm
.dc
;
4585 struct dm_atomic_state
*dm_state
= to_dm_atomic_state(state
);
4586 struct drm_connector
*connector
;
4587 struct drm_connector_state
*old_con_state
, *new_con_state
;
4588 struct drm_crtc
*crtc
;
4589 struct drm_crtc_state
*new_crtc_state
;
4592 * This bool will be set for true for any modeset/reset
4593 * or plane update which implies non fast surface update.
4595 bool lock_and_validation_needed
= false;
4597 ret
= drm_atomic_helper_check_modeset(dev
, state
);
4600 DRM_ERROR("Atomic state validation failed with error :%d !\n", ret
);
4605 * Hack: Commit needs planes right now, specifically for gamma
4606 * TODO rework commit to check CRTC for gamma change
4608 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
4609 if (new_crtc_state
->color_mgmt_changed
) {
4610 ret
= drm_atomic_add_affected_planes(state
, crtc
);
4616 dm_state
->context
= dc_create_state();
4617 ASSERT(dm_state
->context
);
4618 dc_resource_state_copy_construct_current(dc
, dm_state
->context
);
4620 /* Remove exiting planes if they are modified */
4621 ret
= dm_update_planes_state(dc
, state
, false, &lock_and_validation_needed
);
4626 /* Disable all crtcs which require disable */
4627 ret
= dm_update_crtcs_state(dc
, state
, false, &lock_and_validation_needed
);
4632 /* Enable all crtcs which require enable */
4633 ret
= dm_update_crtcs_state(dc
, state
, true, &lock_and_validation_needed
);
4638 /* Add new/modified planes */
4639 ret
= dm_update_planes_state(dc
, state
, true, &lock_and_validation_needed
);
4644 /* Run this here since we want to validate the streams we created */
4645 ret
= drm_atomic_helper_check_planes(dev
, state
);
4649 /* Check scaling and underscan changes*/
4650 /*TODO Removed scaling changes validation due to inability to commit
4651 * new stream into context w\o causing full reset. Need to
4652 * decide how to handle.
4654 for_each_oldnew_connector_in_state(state
, connector
, old_con_state
, new_con_state
, i
) {
4655 struct dm_connector_state
*dm_old_con_state
= to_dm_connector_state(old_con_state
);
4656 struct dm_connector_state
*dm_new_con_state
= to_dm_connector_state(new_con_state
);
4657 struct amdgpu_crtc
*acrtc
= to_amdgpu_crtc(dm_new_con_state
->base
.crtc
);
4659 /* Skip any modesets/resets */
4660 if (!acrtc
|| drm_atomic_crtc_needs_modeset(
4661 drm_atomic_get_new_crtc_state(state
, &acrtc
->base
)))
4664 /* Skip any thing not scale or underscan changes */
4665 if (!is_scaling_state_different(dm_new_con_state
, dm_old_con_state
))
4668 lock_and_validation_needed
= true;
4672 * For full updates case when
4673 * removing/adding/updating streams on once CRTC while flipping
4675 * acquiring global lock will guarantee that any such full
4677 * will wait for completion of any outstanding flip using DRMs
4678 * synchronization events.
4681 if (lock_and_validation_needed
) {
4683 ret
= do_aquire_global_lock(dev
, state
);
4687 if (!dc_validate_global_state(dc
, dm_state
->context
)) {
4693 /* Must be success */
4698 if (ret
== -EDEADLK
)
4699 DRM_DEBUG_DRIVER("Atomic check stopped due to to deadlock.\n");
4700 else if (ret
== -EINTR
|| ret
== -EAGAIN
|| ret
== -ERESTARTSYS
)
4701 DRM_DEBUG_DRIVER("Atomic check stopped due to to signal.\n");
4703 DRM_ERROR("Atomic check failed with err: %d \n", ret
);
4708 static bool is_dp_capable_without_timing_msa(struct dc
*dc
,
4709 struct amdgpu_dm_connector
*amdgpu_dm_connector
)
4712 bool capable
= false;
4714 if (amdgpu_dm_connector
->dc_link
&&
4715 dm_helpers_dp_read_dpcd(
4717 amdgpu_dm_connector
->dc_link
,
4718 DP_DOWN_STREAM_PORT_COUNT
,
4720 sizeof(dpcd_data
))) {
4721 capable
= (dpcd_data
& DP_MSA_TIMING_PAR_IGNORED
) ? true:false;
4726 void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector
*connector
,
4730 uint64_t val_capable
;
4731 bool edid_check_required
;
4732 struct detailed_timing
*timing
;
4733 struct detailed_non_pixel
*data
;
4734 struct detailed_data_monitor_range
*range
;
4735 struct amdgpu_dm_connector
*amdgpu_dm_connector
=
4736 to_amdgpu_dm_connector(connector
);
4738 struct drm_device
*dev
= connector
->dev
;
4739 struct amdgpu_device
*adev
= dev
->dev_private
;
4741 edid_check_required
= false;
4742 if (!amdgpu_dm_connector
->dc_sink
) {
4743 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
4746 if (!adev
->dm
.freesync_module
)
4749 * if edid non zero restrict freesync only for dp and edp
4752 if (amdgpu_dm_connector
->dc_sink
->sink_signal
== SIGNAL_TYPE_DISPLAY_PORT
4753 || amdgpu_dm_connector
->dc_sink
->sink_signal
== SIGNAL_TYPE_EDP
) {
4754 edid_check_required
= is_dp_capable_without_timing_msa(
4756 amdgpu_dm_connector
);
4760 if (edid_check_required
== true && (edid
->version
> 1 ||
4761 (edid
->version
== 1 && edid
->revision
> 1))) {
4762 for (i
= 0; i
< 4; i
++) {
4764 timing
= &edid
->detailed_timings
[i
];
4765 data
= &timing
->data
.other_data
;
4766 range
= &data
->data
.range
;
4768 * Check if monitor has continuous frequency mode
4770 if (data
->type
!= EDID_DETAIL_MONITOR_RANGE
)
4773 * Check for flag range limits only. If flag == 1 then
4774 * no additional timing information provided.
4775 * Default GTF, GTF Secondary curve and CVT are not
4778 if (range
->flags
!= 1)
4781 amdgpu_dm_connector
->min_vfreq
= range
->min_vfreq
;
4782 amdgpu_dm_connector
->max_vfreq
= range
->max_vfreq
;
4783 amdgpu_dm_connector
->pixel_clock_mhz
=
4784 range
->pixel_clock_mhz
* 10;
4788 if (amdgpu_dm_connector
->max_vfreq
-
4789 amdgpu_dm_connector
->min_vfreq
> 10) {
4790 amdgpu_dm_connector
->caps
.supported
= true;
4791 amdgpu_dm_connector
->caps
.min_refresh_in_micro_hz
=
4792 amdgpu_dm_connector
->min_vfreq
* 1000000;
4793 amdgpu_dm_connector
->caps
.max_refresh_in_micro_hz
=
4794 amdgpu_dm_connector
->max_vfreq
* 1000000;
4800 * TODO figure out how to notify user-mode or DRM of freesync caps
4801 * once we figure out how to deal with freesync in an upstreamable
4807 void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector
*connector
)
4810 * TODO fill in once we figure out how to deal with freesync in
4811 * an upstreamable fashion