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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm_types.c
1 /*
2 * Copyright 2012-13 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/types.h>
27 #include <linux/version.h>
28
29 #include <drm/drmP.h>
30 #include <drm/drm_atomic_helper.h>
31 #include <drm/drm_fb_helper.h>
32 #include <drm/drm_atomic.h>
33 #include <drm/drm_edid.h>
34
35
36 #include "amdgpu.h"
37 #include "amdgpu_pm.h"
38 #include "dm_helpers.h"
39 #include "dm_services_types.h"
40
41 // We need to #undef FRAME_SIZE and DEPRECATED because they conflict
42 // with ptrace-abi.h's #define's of them.
43 #undef FRAME_SIZE
44 #undef DEPRECATED
45
46 #include "dc.h"
47
48 #include "amdgpu_dm_types.h"
49 #include "amdgpu_dm_mst_types.h"
50
51 #include "modules/inc/mod_freesync.h"
52
53 #include "i2caux_interface.h"
54
55 struct dm_connector_state {
56 struct drm_connector_state base;
57
58 enum amdgpu_rmx_type scaling;
59 uint8_t underscan_vborder;
60 uint8_t underscan_hborder;
61 bool underscan_enable;
62 };
63
64 #define to_dm_connector_state(x)\
65 container_of((x), struct dm_connector_state, base)
66
67
68 void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
69 {
70 drm_encoder_cleanup(encoder);
71 kfree(encoder);
72 }
73
74 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
75 .destroy = amdgpu_dm_encoder_destroy,
76 };
77
78 static void dm_set_cursor(
79 struct amdgpu_crtc *amdgpu_crtc,
80 uint64_t gpu_addr,
81 uint32_t width,
82 uint32_t height)
83 {
84 struct dc_cursor_attributes attributes;
85 struct dc_cursor_position position;
86 struct drm_crtc *crtc = &amdgpu_crtc->base;
87 int x, y;
88 int xorigin = 0, yorigin = 0;
89
90 amdgpu_crtc->cursor_width = width;
91 amdgpu_crtc->cursor_height = height;
92
93 attributes.address.high_part = upper_32_bits(gpu_addr);
94 attributes.address.low_part = lower_32_bits(gpu_addr);
95 attributes.width = width;
96 attributes.height = height;
97 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
98 attributes.rotation_angle = 0;
99 attributes.attribute_flags.value = 0;
100
101 attributes.pitch = attributes.width;
102
103 x = amdgpu_crtc->cursor_x;
104 y = amdgpu_crtc->cursor_y;
105
106 /* avivo cursor are offset into the total surface */
107 x += crtc->primary->state->src_x >> 16;
108 y += crtc->primary->state->src_y >> 16;
109
110 if (x < 0) {
111 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
112 x = 0;
113 }
114 if (y < 0) {
115 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
116 y = 0;
117 }
118
119 position.enable = true;
120 position.x = x;
121 position.y = y;
122
123 position.x_hotspot = xorigin;
124 position.y_hotspot = yorigin;
125
126 if (!dc_stream_set_cursor_attributes(
127 amdgpu_crtc->stream,
128 &attributes)) {
129 DRM_ERROR("DC failed to set cursor attributes\n");
130 }
131
132 if (!dc_stream_set_cursor_position(
133 amdgpu_crtc->stream,
134 &position)) {
135 DRM_ERROR("DC failed to set cursor position\n");
136 }
137 }
138
139 static int dm_crtc_cursor_set(
140 struct drm_crtc *crtc,
141 uint64_t address,
142 uint32_t width,
143 uint32_t height)
144 {
145 struct dc_cursor_position position;
146
147 int ret;
148
149 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
150 ret = EINVAL;
151
152 DRM_DEBUG_KMS(
153 "%s: crtc_id=%d with size %d to %d \n",
154 __func__,
155 amdgpu_crtc->crtc_id,
156 width,
157 height);
158
159 if (!address) {
160 /* turn off cursor */
161 position.enable = false;
162 position.x = 0;
163 position.y = 0;
164
165 if (amdgpu_crtc->stream) {
166 /*set cursor visible false*/
167 dc_stream_set_cursor_position(
168 amdgpu_crtc->stream,
169 &position);
170 }
171 goto release;
172
173 }
174
175 if ((width > amdgpu_crtc->max_cursor_width) ||
176 (height > amdgpu_crtc->max_cursor_height)) {
177 DRM_ERROR(
178 "%s: bad cursor width or height %d x %d\n",
179 __func__,
180 width,
181 height);
182 goto release;
183 }
184
185 /*program new cursor bo to hardware*/
186 dm_set_cursor(amdgpu_crtc, address, width, height);
187
188 release:
189 return ret;
190
191 }
192
193 static int dm_crtc_cursor_move(struct drm_crtc *crtc,
194 int x, int y)
195 {
196 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
197 int xorigin = 0, yorigin = 0;
198 struct dc_cursor_position position;
199
200 amdgpu_crtc->cursor_x = x;
201 amdgpu_crtc->cursor_y = y;
202
203 /* avivo cursor are offset into the total surface */
204 x += crtc->primary->state->src_x >> 16;
205 y += crtc->primary->state->src_y >> 16;
206
207 /*
208 * TODO: for cursor debugging unguard the following
209 */
210 #if 0
211 DRM_DEBUG_KMS(
212 "%s: x %d y %d c->x %d c->y %d\n",
213 __func__,
214 x,
215 y,
216 crtc->x,
217 crtc->y);
218 #endif
219
220 if (x < 0) {
221 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
222 x = 0;
223 }
224 if (y < 0) {
225 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
226 y = 0;
227 }
228
229 position.enable = true;
230 position.x = x;
231 position.y = y;
232
233 position.x_hotspot = xorigin;
234 position.y_hotspot = yorigin;
235
236 if (amdgpu_crtc->stream) {
237 if (!dc_stream_set_cursor_position(
238 amdgpu_crtc->stream,
239 &position)) {
240 DRM_ERROR("DC failed to set cursor position\n");
241 return -EINVAL;
242 }
243 }
244
245 return 0;
246 }
247
248 static bool fill_rects_from_plane_state(
249 const struct drm_plane_state *state,
250 struct dc_surface *surface)
251 {
252 surface->src_rect.x = state->src_x >> 16;
253 surface->src_rect.y = state->src_y >> 16;
254 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
255 surface->src_rect.width = state->src_w >> 16;
256
257 if (surface->src_rect.width == 0)
258 return false;
259
260 surface->src_rect.height = state->src_h >> 16;
261 if (surface->src_rect.height == 0)
262 return false;
263
264 surface->dst_rect.x = state->crtc_x;
265 surface->dst_rect.y = state->crtc_y;
266
267 if (state->crtc_w == 0)
268 return false;
269
270 surface->dst_rect.width = state->crtc_w;
271
272 if (state->crtc_h == 0)
273 return false;
274
275 surface->dst_rect.height = state->crtc_h;
276
277 surface->clip_rect = surface->dst_rect;
278
279 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
280 case DRM_MODE_ROTATE_0:
281 surface->rotation = ROTATION_ANGLE_0;
282 break;
283 case DRM_MODE_ROTATE_90:
284 surface->rotation = ROTATION_ANGLE_90;
285 break;
286 case DRM_MODE_ROTATE_180:
287 surface->rotation = ROTATION_ANGLE_180;
288 break;
289 case DRM_MODE_ROTATE_270:
290 surface->rotation = ROTATION_ANGLE_270;
291 break;
292 default:
293 surface->rotation = ROTATION_ANGLE_0;
294 break;
295 }
296
297 return true;
298 }
299 static bool get_fb_info(
300 const struct amdgpu_framebuffer *amdgpu_fb,
301 uint64_t *tiling_flags,
302 uint64_t *fb_location)
303 {
304 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
305 int r = amdgpu_bo_reserve(rbo, false);
306 if (unlikely(r != 0)){
307 DRM_ERROR("Unable to reserve buffer\n");
308 return false;
309 }
310
311 if (fb_location)
312 *fb_location = amdgpu_bo_gpu_offset(rbo);
313
314 if (tiling_flags)
315 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
316
317 amdgpu_bo_unreserve(rbo);
318
319 return true;
320 }
321 static void fill_plane_attributes_from_fb(
322 struct amdgpu_device *adev,
323 struct dc_surface *surface,
324 const struct amdgpu_framebuffer *amdgpu_fb, bool addReq)
325 {
326 uint64_t tiling_flags;
327 uint64_t fb_location = 0;
328 unsigned int awidth;
329 const struct drm_framebuffer *fb = &amdgpu_fb->base;
330 struct drm_format_name_buf format_name;
331
332 get_fb_info(
333 amdgpu_fb,
334 &tiling_flags,
335 addReq == true ? &fb_location:NULL);
336
337
338 switch (fb->format->format) {
339 case DRM_FORMAT_C8:
340 surface->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
341 break;
342 case DRM_FORMAT_RGB565:
343 surface->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
344 break;
345 case DRM_FORMAT_XRGB8888:
346 case DRM_FORMAT_ARGB8888:
347 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
348 break;
349 case DRM_FORMAT_XRGB2101010:
350 case DRM_FORMAT_ARGB2101010:
351 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
352 break;
353 case DRM_FORMAT_XBGR2101010:
354 case DRM_FORMAT_ABGR2101010:
355 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
356 break;
357 case DRM_FORMAT_NV21:
358 surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
359 break;
360 case DRM_FORMAT_NV12:
361 surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
362 break;
363 default:
364 DRM_ERROR("Unsupported screen format %s\n",
365 drm_get_format_name(fb->format->format, &format_name));
366 return;
367 }
368
369 if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
370 surface->address.type = PLN_ADDR_TYPE_GRAPHICS;
371 surface->address.grph.addr.low_part = lower_32_bits(fb_location);
372 surface->address.grph.addr.high_part = upper_32_bits(fb_location);
373 surface->plane_size.grph.surface_size.x = 0;
374 surface->plane_size.grph.surface_size.y = 0;
375 surface->plane_size.grph.surface_size.width = fb->width;
376 surface->plane_size.grph.surface_size.height = fb->height;
377 surface->plane_size.grph.surface_pitch =
378 fb->pitches[0] / fb->format->cpp[0];
379 /* TODO: unhardcode */
380 surface->color_space = COLOR_SPACE_SRGB;
381
382 } else {
383 awidth = ALIGN(fb->width, 64);
384 surface->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
385 surface->address.video_progressive.luma_addr.low_part
386 = lower_32_bits(fb_location);
387 surface->address.video_progressive.chroma_addr.low_part
388 = lower_32_bits(fb_location) +
389 (awidth * fb->height);
390 surface->plane_size.video.luma_size.x = 0;
391 surface->plane_size.video.luma_size.y = 0;
392 surface->plane_size.video.luma_size.width = awidth;
393 surface->plane_size.video.luma_size.height = fb->height;
394 /* TODO: unhardcode */
395 surface->plane_size.video.luma_pitch = awidth;
396
397 surface->plane_size.video.chroma_size.x = 0;
398 surface->plane_size.video.chroma_size.y = 0;
399 surface->plane_size.video.chroma_size.width = awidth;
400 surface->plane_size.video.chroma_size.height = fb->height;
401 surface->plane_size.video.chroma_pitch = awidth / 2;
402
403 /* TODO: unhardcode */
404 surface->color_space = COLOR_SPACE_YCBCR709;
405 }
406
407 memset(&surface->tiling_info, 0, sizeof(surface->tiling_info));
408
409 /* Fill GFX params */
410 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1)
411 {
412 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
413
414 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
415 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
416 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
417 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
418 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
419
420 /* XXX fix me for VI */
421 surface->tiling_info.gfx8.num_banks = num_banks;
422 surface->tiling_info.gfx8.array_mode =
423 DC_ARRAY_2D_TILED_THIN1;
424 surface->tiling_info.gfx8.tile_split = tile_split;
425 surface->tiling_info.gfx8.bank_width = bankw;
426 surface->tiling_info.gfx8.bank_height = bankh;
427 surface->tiling_info.gfx8.tile_aspect = mtaspect;
428 surface->tiling_info.gfx8.tile_mode =
429 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
430 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
431 == DC_ARRAY_1D_TILED_THIN1) {
432 surface->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
433 }
434
435 surface->tiling_info.gfx8.pipe_config =
436 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
437
438 if (adev->asic_type == CHIP_VEGA10 ||
439 adev->asic_type == CHIP_RAVEN) {
440 /* Fill GFX9 params */
441 surface->tiling_info.gfx9.num_pipes =
442 adev->gfx.config.gb_addr_config_fields.num_pipes;
443 surface->tiling_info.gfx9.num_banks =
444 adev->gfx.config.gb_addr_config_fields.num_banks;
445 surface->tiling_info.gfx9.pipe_interleave =
446 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
447 surface->tiling_info.gfx9.num_shader_engines =
448 adev->gfx.config.gb_addr_config_fields.num_se;
449 surface->tiling_info.gfx9.max_compressed_frags =
450 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
451 surface->tiling_info.gfx9.num_rb_per_se =
452 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
453 surface->tiling_info.gfx9.swizzle =
454 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
455 surface->tiling_info.gfx9.shaderEnable = 1;
456 }
457
458 surface->visible = true;
459 surface->scaling_quality.h_taps_c = 0;
460 surface->scaling_quality.v_taps_c = 0;
461
462 /* is this needed? is surface zeroed at allocation? */
463 surface->scaling_quality.h_taps = 0;
464 surface->scaling_quality.v_taps = 0;
465 surface->stereo_format = PLANE_STEREO_FORMAT_NONE;
466
467 }
468
469 #define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256
470
471 static void fill_gamma_from_crtc(
472 const struct drm_crtc *crtc,
473 struct dc_surface *dc_surface)
474 {
475 int i;
476 struct dc_gamma *gamma;
477 struct drm_crtc_state *state = crtc->state;
478 struct drm_color_lut *lut = (struct drm_color_lut *) state->gamma_lut->data;
479
480 gamma = dc_create_gamma();
481
482 if (gamma == NULL)
483 return;
484
485 for (i = 0; i < NUM_OF_RAW_GAMMA_RAMP_RGB_256; i++) {
486 gamma->red[i] = lut[i].red;
487 gamma->green[i] = lut[i].green;
488 gamma->blue[i] = lut[i].blue;
489 }
490
491 dc_surface->gamma_correction = gamma;
492 }
493
494 static void fill_plane_attributes(
495 struct amdgpu_device *adev,
496 struct dc_surface *surface,
497 struct drm_plane_state *state, bool addrReq)
498 {
499 const struct amdgpu_framebuffer *amdgpu_fb =
500 to_amdgpu_framebuffer(state->fb);
501 const struct drm_crtc *crtc = state->crtc;
502 struct dc_transfer_func *input_tf;
503
504 fill_rects_from_plane_state(state, surface);
505 fill_plane_attributes_from_fb(
506 crtc->dev->dev_private,
507 surface,
508 amdgpu_fb,
509 addrReq);
510
511 input_tf = dc_create_transfer_func();
512
513 if (input_tf == NULL)
514 return;
515
516 input_tf->type = TF_TYPE_PREDEFINED;
517 input_tf->tf = TRANSFER_FUNCTION_SRGB;
518
519 surface->in_transfer_func = input_tf;
520
521 /* In case of gamma set, update gamma value */
522 if (state->crtc->state->gamma_lut) {
523 fill_gamma_from_crtc(crtc, surface);
524 }
525 }
526
527 /*****************************************************************************/
528
529 struct amdgpu_connector *aconnector_from_drm_crtc_id(
530 const struct drm_crtc *crtc)
531 {
532 struct drm_device *dev = crtc->dev;
533 struct drm_connector *connector;
534 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
535 struct amdgpu_connector *aconnector;
536
537 list_for_each_entry(connector,
538 &dev->mode_config.connector_list, head) {
539
540 aconnector = to_amdgpu_connector(connector);
541
542 if (aconnector->base.state->crtc != &acrtc->base)
543 continue;
544
545 /* Found the connector */
546 return aconnector;
547 }
548
549 /* If we get here, not found. */
550 return NULL;
551 }
552
553 static void update_stream_scaling_settings(
554 const struct drm_display_mode *mode,
555 const struct dm_connector_state *dm_state,
556 struct dc_stream *stream)
557 {
558 enum amdgpu_rmx_type rmx_type;
559
560 struct rect src = { 0 }; /* viewport in composition space*/
561 struct rect dst = { 0 }; /* stream addressable area */
562
563 /* no mode. nothing to be done */
564 if (!mode)
565 return;
566
567 /* Full screen scaling by default */
568 src.width = mode->hdisplay;
569 src.height = mode->vdisplay;
570 dst.width = stream->timing.h_addressable;
571 dst.height = stream->timing.v_addressable;
572
573 rmx_type = dm_state->scaling;
574 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
575 if (src.width * dst.height <
576 src.height * dst.width) {
577 /* height needs less upscaling/more downscaling */
578 dst.width = src.width *
579 dst.height / src.height;
580 } else {
581 /* width needs less upscaling/more downscaling */
582 dst.height = src.height *
583 dst.width / src.width;
584 }
585 } else if (rmx_type == RMX_CENTER) {
586 dst = src;
587 }
588
589 dst.x = (stream->timing.h_addressable - dst.width) / 2;
590 dst.y = (stream->timing.v_addressable - dst.height) / 2;
591
592 if (dm_state->underscan_enable) {
593 dst.x += dm_state->underscan_hborder / 2;
594 dst.y += dm_state->underscan_vborder / 2;
595 dst.width -= dm_state->underscan_hborder;
596 dst.height -= dm_state->underscan_vborder;
597 }
598
599 stream->src = src;
600 stream->dst = dst;
601
602 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
603 dst.x, dst.y, dst.width, dst.height);
604
605 }
606
607 static void add_surface(struct dc *dc,
608 struct drm_crtc *crtc,
609 struct drm_plane *plane,
610 const struct dc_surface **dc_surfaces)
611 {
612 struct dc_surface *dc_surface;
613 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
614 const struct dc_stream *dc_stream = acrtc->stream;
615 unsigned long flags;
616
617 spin_lock_irqsave(&crtc->dev->event_lock, flags);
618 if (acrtc->pflip_status != AMDGPU_FLIP_NONE) {
619 DRM_ERROR("add_surface: acrtc %d, already busy\n",
620 acrtc->crtc_id);
621 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
622 /* In comit tail framework this cannot happen */
623 BUG_ON(0);
624 }
625 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
626
627 if (!dc_stream) {
628 dm_error(
629 "%s: Failed to obtain stream on crtc (%d)!\n",
630 __func__,
631 acrtc->crtc_id);
632 goto fail;
633 }
634
635 dc_surface = dc_create_surface(dc);
636
637 if (!dc_surface) {
638 dm_error(
639 "%s: Failed to create a surface!\n",
640 __func__);
641 goto fail;
642 }
643
644 /* Surface programming */
645 fill_plane_attributes(
646 crtc->dev->dev_private,
647 dc_surface,
648 plane->state,
649 true);
650
651 *dc_surfaces = dc_surface;
652
653 fail:
654 return;
655 }
656
657 static enum dc_color_depth convert_color_depth_from_display_info(
658 const struct drm_connector *connector)
659 {
660 uint32_t bpc = connector->display_info.bpc;
661
662 /* Limited color depth to 8bit
663 * TODO: Still need to handle deep color*/
664 if (bpc > 8)
665 bpc = 8;
666
667 switch (bpc) {
668 case 0:
669 /* Temporary Work around, DRM don't parse color depth for
670 * EDID revision before 1.4
671 * TODO: Fix edid parsing
672 */
673 return COLOR_DEPTH_888;
674 case 6:
675 return COLOR_DEPTH_666;
676 case 8:
677 return COLOR_DEPTH_888;
678 case 10:
679 return COLOR_DEPTH_101010;
680 case 12:
681 return COLOR_DEPTH_121212;
682 case 14:
683 return COLOR_DEPTH_141414;
684 case 16:
685 return COLOR_DEPTH_161616;
686 default:
687 return COLOR_DEPTH_UNDEFINED;
688 }
689 }
690
691 static enum dc_aspect_ratio get_aspect_ratio(
692 const struct drm_display_mode *mode_in)
693 {
694 int32_t width = mode_in->crtc_hdisplay * 9;
695 int32_t height = mode_in->crtc_vdisplay * 16;
696 if ((width - height) < 10 && (width - height) > -10)
697 return ASPECT_RATIO_16_9;
698 else
699 return ASPECT_RATIO_4_3;
700 }
701
702 static enum dc_color_space get_output_color_space(
703 const struct dc_crtc_timing *dc_crtc_timing)
704 {
705 enum dc_color_space color_space = COLOR_SPACE_SRGB;
706
707 switch (dc_crtc_timing->pixel_encoding) {
708 case PIXEL_ENCODING_YCBCR422:
709 case PIXEL_ENCODING_YCBCR444:
710 case PIXEL_ENCODING_YCBCR420:
711 {
712 /*
713 * 27030khz is the separation point between HDTV and SDTV
714 * according to HDMI spec, we use YCbCr709 and YCbCr601
715 * respectively
716 */
717 if (dc_crtc_timing->pix_clk_khz > 27030) {
718 if (dc_crtc_timing->flags.Y_ONLY)
719 color_space =
720 COLOR_SPACE_YCBCR709_LIMITED;
721 else
722 color_space = COLOR_SPACE_YCBCR709;
723 } else {
724 if (dc_crtc_timing->flags.Y_ONLY)
725 color_space =
726 COLOR_SPACE_YCBCR601_LIMITED;
727 else
728 color_space = COLOR_SPACE_YCBCR601;
729 }
730
731 }
732 break;
733 case PIXEL_ENCODING_RGB:
734 color_space = COLOR_SPACE_SRGB;
735 break;
736
737 default:
738 WARN_ON(1);
739 break;
740 }
741
742 return color_space;
743 }
744
745 /*****************************************************************************/
746
747 static void fill_stream_properties_from_drm_display_mode(
748 struct dc_stream *stream,
749 const struct drm_display_mode *mode_in,
750 const struct drm_connector *connector)
751 {
752 struct dc_crtc_timing *timing_out = &stream->timing;
753 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
754
755 timing_out->h_border_left = 0;
756 timing_out->h_border_right = 0;
757 timing_out->v_border_top = 0;
758 timing_out->v_border_bottom = 0;
759 /* TODO: un-hardcode */
760
761 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
762 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
763 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
764 else
765 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
766
767 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
768 timing_out->display_color_depth = convert_color_depth_from_display_info(
769 connector);
770 timing_out->scan_type = SCANNING_TYPE_NODATA;
771 timing_out->hdmi_vic = 0;
772 timing_out->vic = drm_match_cea_mode(mode_in);
773
774 timing_out->h_addressable = mode_in->crtc_hdisplay;
775 timing_out->h_total = mode_in->crtc_htotal;
776 timing_out->h_sync_width =
777 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
778 timing_out->h_front_porch =
779 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
780 timing_out->v_total = mode_in->crtc_vtotal;
781 timing_out->v_addressable = mode_in->crtc_vdisplay;
782 timing_out->v_front_porch =
783 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
784 timing_out->v_sync_width =
785 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
786 timing_out->pix_clk_khz = mode_in->crtc_clock;
787 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
788 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
789 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
790 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
791 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
792
793 stream->output_color_space = get_output_color_space(timing_out);
794
795 {
796 struct dc_transfer_func *tf = dc_create_transfer_func();
797 tf->type = TF_TYPE_PREDEFINED;
798 tf->tf = TRANSFER_FUNCTION_SRGB;
799 stream->out_transfer_func = tf;
800 }
801 }
802
803 static void fill_audio_info(
804 struct audio_info *audio_info,
805 const struct drm_connector *drm_connector,
806 const struct dc_sink *dc_sink)
807 {
808 int i = 0;
809 int cea_revision = 0;
810 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
811
812 audio_info->manufacture_id = edid_caps->manufacturer_id;
813 audio_info->product_id = edid_caps->product_id;
814
815 cea_revision = drm_connector->display_info.cea_rev;
816
817 while (i < AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS &&
818 edid_caps->display_name[i]) {
819 audio_info->display_name[i] = edid_caps->display_name[i];
820 i++;
821 }
822
823 if(cea_revision >= 3) {
824 audio_info->mode_count = edid_caps->audio_mode_count;
825
826 for (i = 0; i < audio_info->mode_count; ++i) {
827 audio_info->modes[i].format_code =
828 (enum audio_format_code)
829 (edid_caps->audio_modes[i].format_code);
830 audio_info->modes[i].channel_count =
831 edid_caps->audio_modes[i].channel_count;
832 audio_info->modes[i].sample_rates.all =
833 edid_caps->audio_modes[i].sample_rate;
834 audio_info->modes[i].sample_size =
835 edid_caps->audio_modes[i].sample_size;
836 }
837 }
838
839 audio_info->flags.all = edid_caps->speaker_flags;
840
841 /* TODO: We only check for the progressive mode, check for interlace mode too */
842 if(drm_connector->latency_present[0]) {
843 audio_info->video_latency = drm_connector->video_latency[0];
844 audio_info->audio_latency = drm_connector->audio_latency[0];
845 }
846
847 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
848
849 }
850
851 static void copy_crtc_timing_for_drm_display_mode(
852 const struct drm_display_mode *src_mode,
853 struct drm_display_mode *dst_mode)
854 {
855 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
856 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
857 dst_mode->crtc_clock = src_mode->crtc_clock;
858 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
859 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
860 dst_mode->crtc_hsync_start= src_mode->crtc_hsync_start;
861 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
862 dst_mode->crtc_htotal = src_mode->crtc_htotal;
863 dst_mode->crtc_hskew = src_mode->crtc_hskew;
864 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
865 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
866 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
867 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
868 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
869 }
870
871 static void decide_crtc_timing_for_drm_display_mode(
872 struct drm_display_mode *drm_mode,
873 const struct drm_display_mode *native_mode,
874 bool scale_enabled)
875 {
876 if (scale_enabled) {
877 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
878 } else if (native_mode->clock == drm_mode->clock &&
879 native_mode->htotal == drm_mode->htotal &&
880 native_mode->vtotal == drm_mode->vtotal) {
881 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
882 } else {
883 /* no scaling nor amdgpu inserted, no need to patch */
884 }
885 }
886
887 static struct dc_stream *create_stream_for_sink(
888 struct amdgpu_connector *aconnector,
889 const struct drm_display_mode *drm_mode,
890 const struct dm_connector_state *dm_state)
891 {
892 struct drm_display_mode *preferred_mode = NULL;
893 const struct drm_connector *drm_connector;
894 struct dc_stream *stream = NULL;
895 struct drm_display_mode mode = *drm_mode;
896 bool native_mode_found = false;
897
898 if (NULL == aconnector) {
899 DRM_ERROR("aconnector is NULL!\n");
900 goto drm_connector_null;
901 }
902
903 if (NULL == dm_state) {
904 DRM_ERROR("dm_state is NULL!\n");
905 goto dm_state_null;
906 }
907
908 drm_connector = &aconnector->base;
909 stream = dc_create_stream_for_sink(aconnector->dc_sink);
910
911 if (NULL == stream) {
912 DRM_ERROR("Failed to create stream for sink!\n");
913 goto stream_create_fail;
914 }
915
916 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
917 /* Search for preferred mode */
918 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
919 native_mode_found = true;
920 break;
921 }
922 }
923 if (!native_mode_found)
924 preferred_mode = list_first_entry_or_null(
925 &aconnector->base.modes,
926 struct drm_display_mode,
927 head);
928
929 if (NULL == preferred_mode) {
930 /* This may not be an error, the use case is when we we have no
931 * usermode calls to reset and set mode upon hotplug. In this
932 * case, we call set mode ourselves to restore the previous mode
933 * and the modelist may not be filled in in time.
934 */
935 DRM_INFO("No preferred mode found\n");
936 } else {
937 decide_crtc_timing_for_drm_display_mode(
938 &mode, preferred_mode,
939 dm_state->scaling != RMX_OFF);
940 }
941
942 fill_stream_properties_from_drm_display_mode(stream,
943 &mode, &aconnector->base);
944 update_stream_scaling_settings(&mode, dm_state, stream);
945
946 fill_audio_info(
947 &stream->audio_info,
948 drm_connector,
949 aconnector->dc_sink);
950
951 stream_create_fail:
952 dm_state_null:
953 drm_connector_null:
954 return stream;
955 }
956
957 void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
958 {
959 drm_crtc_cleanup(crtc);
960 kfree(crtc);
961 }
962
963 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
964 struct drm_crtc_state *state)
965 {
966 struct dm_crtc_state *cur = to_dm_crtc_state(state);
967
968 if (cur->dc_stream) {
969 /* TODO Destroy dc_stream objects are stream object is flattened */
970 dm_free(cur->dc_stream);
971 } else
972 WARN_ON(1);
973
974 __drm_atomic_helper_crtc_destroy_state(state);
975
976
977 kfree(state);
978 }
979
980 static void dm_crtc_reset_state(struct drm_crtc *crtc)
981 {
982 struct dm_crtc_state *state;
983
984 if (crtc->state)
985 dm_crtc_destroy_state(crtc, crtc->state);
986
987 state = kzalloc(sizeof(*state), GFP_KERNEL);
988 if (WARN_ON(!state))
989 return;
990
991
992 crtc->state = &state->base;
993 crtc->state->crtc = crtc;
994
995 state->dc_stream = dm_alloc(sizeof(*state->dc_stream));
996 WARN_ON(!state->dc_stream);
997 }
998
999 static struct drm_crtc_state *
1000 dm_crtc_duplicate_state(struct drm_crtc *crtc)
1001 {
1002 struct dm_crtc_state *state, *cur;
1003 struct dc_stream *dc_stream;
1004
1005 if (WARN_ON(!crtc->state))
1006 return NULL;
1007
1008 cur = to_dm_crtc_state(crtc->state);
1009 if (WARN_ON(!cur->dc_stream))
1010 return NULL;
1011
1012 dc_stream = dm_alloc(sizeof(*dc_stream));
1013 if (WARN_ON(!dc_stream))
1014 return NULL;
1015
1016 state = dm_alloc(sizeof(*state));
1017 if (WARN_ON(!state)) {
1018 dm_free(dc_stream);
1019 return NULL;
1020 }
1021
1022 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
1023
1024 state->dc_stream = dc_stream;
1025
1026 /* TODO Duplicate dc_stream after objects are stream object is flattened */
1027
1028 return &state->base;
1029 }
1030
1031 /* Implemented only the options currently availible for the driver */
1032 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
1033 .reset = dm_crtc_reset_state,
1034 .destroy = amdgpu_dm_crtc_destroy,
1035 .gamma_set = drm_atomic_helper_legacy_gamma_set,
1036 .set_config = drm_atomic_helper_set_config,
1037 .page_flip = drm_atomic_helper_page_flip,
1038 .atomic_duplicate_state = dm_crtc_duplicate_state,
1039 .atomic_destroy_state = dm_crtc_destroy_state,
1040 };
1041
1042 static enum drm_connector_status
1043 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
1044 {
1045 bool connected;
1046 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1047
1048 /* Notes:
1049 * 1. This interface is NOT called in context of HPD irq.
1050 * 2. This interface *is called* in context of user-mode ioctl. Which
1051 * makes it a bad place for *any* MST-related activit. */
1052
1053 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1054 connected = (aconnector->dc_sink != NULL);
1055 else
1056 connected = (aconnector->base.force == DRM_FORCE_ON);
1057
1058 return (connected ? connector_status_connected :
1059 connector_status_disconnected);
1060 }
1061
1062 int amdgpu_dm_connector_atomic_set_property(
1063 struct drm_connector *connector,
1064 struct drm_connector_state *connector_state,
1065 struct drm_property *property,
1066 uint64_t val)
1067 {
1068 struct drm_device *dev = connector->dev;
1069 struct amdgpu_device *adev = dev->dev_private;
1070 struct dm_connector_state *dm_old_state =
1071 to_dm_connector_state(connector->state);
1072 struct dm_connector_state *dm_new_state =
1073 to_dm_connector_state(connector_state);
1074
1075 int ret = -EINVAL;
1076
1077 if (property == dev->mode_config.scaling_mode_property) {
1078 enum amdgpu_rmx_type rmx_type;
1079
1080 switch (val) {
1081 case DRM_MODE_SCALE_CENTER:
1082 rmx_type = RMX_CENTER;
1083 break;
1084 case DRM_MODE_SCALE_ASPECT:
1085 rmx_type = RMX_ASPECT;
1086 break;
1087 case DRM_MODE_SCALE_FULLSCREEN:
1088 rmx_type = RMX_FULL;
1089 break;
1090 case DRM_MODE_SCALE_NONE:
1091 default:
1092 rmx_type = RMX_OFF;
1093 break;
1094 }
1095
1096 if (dm_old_state->scaling == rmx_type)
1097 return 0;
1098
1099 dm_new_state->scaling = rmx_type;
1100 ret = 0;
1101 } else if (property == adev->mode_info.underscan_hborder_property) {
1102 dm_new_state->underscan_hborder = val;
1103 ret = 0;
1104 } else if (property == adev->mode_info.underscan_vborder_property) {
1105 dm_new_state->underscan_vborder = val;
1106 ret = 0;
1107 } else if (property == adev->mode_info.underscan_property) {
1108 dm_new_state->underscan_enable = val;
1109 ret = 0;
1110 }
1111
1112 return ret;
1113 }
1114
1115 int amdgpu_dm_connector_atomic_get_property(
1116 struct drm_connector *connector,
1117 const struct drm_connector_state *state,
1118 struct drm_property *property,
1119 uint64_t *val)
1120 {
1121 struct drm_device *dev = connector->dev;
1122 struct amdgpu_device *adev = dev->dev_private;
1123 struct dm_connector_state *dm_state =
1124 to_dm_connector_state(state);
1125 int ret = -EINVAL;
1126
1127 if (property == dev->mode_config.scaling_mode_property) {
1128 switch (dm_state->scaling) {
1129 case RMX_CENTER:
1130 *val = DRM_MODE_SCALE_CENTER;
1131 break;
1132 case RMX_ASPECT:
1133 *val = DRM_MODE_SCALE_ASPECT;
1134 break;
1135 case RMX_FULL:
1136 *val = DRM_MODE_SCALE_FULLSCREEN;
1137 break;
1138 case RMX_OFF:
1139 default:
1140 *val = DRM_MODE_SCALE_NONE;
1141 break;
1142 }
1143 ret = 0;
1144 } else if (property == adev->mode_info.underscan_hborder_property) {
1145 *val = dm_state->underscan_hborder;
1146 ret = 0;
1147 } else if (property == adev->mode_info.underscan_vborder_property) {
1148 *val = dm_state->underscan_vborder;
1149 ret = 0;
1150 } else if (property == adev->mode_info.underscan_property) {
1151 *val = dm_state->underscan_enable;
1152 ret = 0;
1153 }
1154 return ret;
1155 }
1156
1157 void amdgpu_dm_connector_destroy(struct drm_connector *connector)
1158 {
1159 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1160 const struct dc_link *link = aconnector->dc_link;
1161 struct amdgpu_device *adev = connector->dev->dev_private;
1162 struct amdgpu_display_manager *dm = &adev->dm;
1163 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1164 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1165
1166 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
1167 amdgpu_dm_register_backlight_device(dm);
1168
1169 if (dm->backlight_dev) {
1170 backlight_device_unregister(dm->backlight_dev);
1171 dm->backlight_dev = NULL;
1172 }
1173
1174 }
1175 #endif
1176 drm_connector_unregister(connector);
1177 drm_connector_cleanup(connector);
1178 kfree(connector);
1179 }
1180
1181 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
1182 {
1183 struct dm_connector_state *state =
1184 to_dm_connector_state(connector->state);
1185
1186 kfree(state);
1187
1188 state = kzalloc(sizeof(*state), GFP_KERNEL);
1189
1190 if (state) {
1191 state->scaling = RMX_OFF;
1192 state->underscan_enable = false;
1193 state->underscan_hborder = 0;
1194 state->underscan_vborder = 0;
1195
1196 connector->state = &state->base;
1197 connector->state->connector = connector;
1198 }
1199 }
1200
1201 struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state(
1202 struct drm_connector *connector)
1203 {
1204 struct dm_connector_state *state =
1205 to_dm_connector_state(connector->state);
1206
1207 struct dm_connector_state *new_state =
1208 kmemdup(state, sizeof(*state), GFP_KERNEL);
1209
1210 if (new_state) {
1211 __drm_atomic_helper_connector_duplicate_state(connector,
1212 &new_state->base);
1213 return &new_state->base;
1214 }
1215
1216 return NULL;
1217 }
1218
1219 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
1220 .reset = amdgpu_dm_connector_funcs_reset,
1221 .detect = amdgpu_dm_connector_detect,
1222 .fill_modes = drm_helper_probe_single_connector_modes,
1223 .destroy = amdgpu_dm_connector_destroy,
1224 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
1225 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1226 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
1227 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
1228 };
1229
1230 static struct drm_encoder *best_encoder(struct drm_connector *connector)
1231 {
1232 int enc_id = connector->encoder_ids[0];
1233 struct drm_mode_object *obj;
1234 struct drm_encoder *encoder;
1235
1236 DRM_DEBUG_KMS("Finding the best encoder\n");
1237
1238 /* pick the encoder ids */
1239 if (enc_id) {
1240 obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER);
1241 if (!obj) {
1242 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
1243 return NULL;
1244 }
1245 encoder = obj_to_encoder(obj);
1246 return encoder;
1247 }
1248 DRM_ERROR("No encoder id\n");
1249 return NULL;
1250 }
1251
1252 static int get_modes(struct drm_connector *connector)
1253 {
1254 return amdgpu_dm_connector_get_modes(connector);
1255 }
1256
1257 static void create_eml_sink(struct amdgpu_connector *aconnector)
1258 {
1259 struct dc_sink_init_data init_params = {
1260 .link = aconnector->dc_link,
1261 .sink_signal = SIGNAL_TYPE_VIRTUAL
1262 };
1263 struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
1264
1265 if (!aconnector->base.edid_blob_ptr ||
1266 !aconnector->base.edid_blob_ptr->data) {
1267 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
1268 aconnector->base.name);
1269
1270 aconnector->base.force = DRM_FORCE_OFF;
1271 aconnector->base.override_edid = false;
1272 return;
1273 }
1274
1275 aconnector->edid = edid;
1276
1277 aconnector->dc_em_sink = dc_link_add_remote_sink(
1278 aconnector->dc_link,
1279 (uint8_t *)edid,
1280 (edid->extensions + 1) * EDID_LENGTH,
1281 &init_params);
1282
1283 if (aconnector->base.force
1284 == DRM_FORCE_ON)
1285 aconnector->dc_sink = aconnector->dc_link->local_sink ?
1286 aconnector->dc_link->local_sink :
1287 aconnector->dc_em_sink;
1288 }
1289
1290 static void handle_edid_mgmt(struct amdgpu_connector *aconnector)
1291 {
1292 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
1293
1294 /* In case of headless boot with force on for DP managed connector
1295 * Those settings have to be != 0 to get initial modeset
1296 */
1297 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
1298 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
1299 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
1300 }
1301
1302
1303 aconnector->base.override_edid = true;
1304 create_eml_sink(aconnector);
1305 }
1306
1307 int amdgpu_dm_connector_mode_valid(
1308 struct drm_connector *connector,
1309 struct drm_display_mode *mode)
1310 {
1311 int result = MODE_ERROR;
1312 const struct dc_sink *dc_sink;
1313 struct amdgpu_device *adev = connector->dev->dev_private;
1314 struct dc_validation_set val_set = { 0 };
1315 /* TODO: Unhardcode stream count */
1316 struct dc_stream *stream;
1317 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1318 struct validate_context *context;
1319
1320 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1321 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
1322 return result;
1323
1324 /* Only run this the first time mode_valid is called to initilialize
1325 * EDID mgmt
1326 */
1327 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
1328 !aconnector->dc_em_sink)
1329 handle_edid_mgmt(aconnector);
1330
1331 dc_sink = to_amdgpu_connector(connector)->dc_sink;
1332
1333 if (NULL == dc_sink) {
1334 DRM_ERROR("dc_sink is NULL!\n");
1335 goto null_sink;
1336 }
1337
1338 stream = dc_create_stream_for_sink(dc_sink);
1339 if (NULL == stream) {
1340 DRM_ERROR("Failed to create stream for sink!\n");
1341 goto stream_create_fail;
1342 }
1343
1344 drm_mode_set_crtcinfo(mode, 0);
1345 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
1346
1347 val_set.stream = stream;
1348 val_set.surface_count = 0;
1349 stream->src.width = mode->hdisplay;
1350 stream->src.height = mode->vdisplay;
1351 stream->dst = stream->src;
1352
1353 context = dc_get_validate_context(adev->dm.dc, &val_set, 1);
1354
1355 if (context) {
1356 result = MODE_OK;
1357 dc_resource_validate_ctx_destruct(context);
1358 dm_free(context);
1359 }
1360
1361 dc_stream_release(stream);
1362
1363 stream_create_fail:
1364 null_sink:
1365 /* TODO: error handling*/
1366 return result;
1367 }
1368
1369 static const struct drm_connector_helper_funcs
1370 amdgpu_dm_connector_helper_funcs = {
1371 /*
1372 * If hotplug a second bigger display in FB Con mode, bigger resolution
1373 * modes will be filtered by drm_mode_validate_size(), and those modes
1374 * is missing after user start lightdm. So we need to renew modes list.
1375 * in get_modes call back, not just return the modes count
1376 */
1377 .get_modes = get_modes,
1378 .mode_valid = amdgpu_dm_connector_mode_valid,
1379 .best_encoder = best_encoder
1380 };
1381
1382 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
1383 {
1384 }
1385
1386 static int dm_crtc_helper_atomic_check(
1387 struct drm_crtc *crtc,
1388 struct drm_crtc_state *state)
1389 {
1390 return 0;
1391 }
1392
1393 static bool dm_crtc_helper_mode_fixup(
1394 struct drm_crtc *crtc,
1395 const struct drm_display_mode *mode,
1396 struct drm_display_mode *adjusted_mode)
1397 {
1398 return true;
1399 }
1400
1401 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
1402 .disable = dm_crtc_helper_disable,
1403 .atomic_check = dm_crtc_helper_atomic_check,
1404 .mode_fixup = dm_crtc_helper_mode_fixup
1405 };
1406
1407 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
1408 {
1409
1410 }
1411
1412 static int dm_encoder_helper_atomic_check(
1413 struct drm_encoder *encoder,
1414 struct drm_crtc_state *crtc_state,
1415 struct drm_connector_state *conn_state)
1416 {
1417 return 0;
1418 }
1419
1420 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
1421 .disable = dm_encoder_helper_disable,
1422 .atomic_check = dm_encoder_helper_atomic_check
1423 };
1424
1425 static void dm_drm_plane_reset(struct drm_plane *plane)
1426 {
1427 struct dm_plane_state *amdgpu_state = NULL;
1428 struct amdgpu_device *adev = plane->dev->dev_private;
1429
1430 if (plane->state)
1431 plane->funcs->atomic_destroy_state(plane, plane->state);
1432
1433 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
1434
1435 if (amdgpu_state) {
1436 plane->state = &amdgpu_state->base;
1437 plane->state->plane = plane;
1438 plane->state->rotation = DRM_MODE_ROTATE_0;
1439
1440 amdgpu_state->dc_surface = dc_create_surface(adev->dm.dc);
1441 WARN_ON(!amdgpu_state->dc_surface);
1442 }
1443 else
1444 WARN_ON(1);
1445 }
1446
1447 static struct drm_plane_state *
1448 dm_drm_plane_duplicate_state(struct drm_plane *plane)
1449 {
1450 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
1451 struct amdgpu_device *adev = plane->dev->dev_private;
1452
1453 old_dm_plane_state = to_dm_plane_state(plane->state);
1454 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
1455 if (!dm_plane_state)
1456 return NULL;
1457
1458 if (old_dm_plane_state->dc_surface) {
1459 struct dc_surface *dc_surface = dc_create_surface(adev->dm.dc);
1460 if (WARN_ON(!dc_surface))
1461 return NULL;
1462
1463 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
1464
1465 memcpy(dc_surface, old_dm_plane_state->dc_surface, sizeof(*dc_surface));
1466
1467 if (old_dm_plane_state->dc_surface->gamma_correction)
1468 dc_gamma_retain(dc_surface->gamma_correction);
1469
1470 if (old_dm_plane_state->dc_surface->in_transfer_func)
1471 dc_transfer_func_retain(dc_surface->in_transfer_func);
1472
1473 dm_plane_state->dc_surface = dc_surface;
1474
1475 /*TODO Check for inferred values to be reset */
1476 }
1477 else {
1478 WARN_ON(1);
1479 return NULL;
1480 }
1481
1482 return &dm_plane_state->base;
1483 }
1484
1485 void dm_drm_plane_destroy_state(struct drm_plane *plane,
1486 struct drm_plane_state *state)
1487 {
1488 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
1489
1490 if (dm_plane_state->dc_surface) {
1491 struct dc_surface *dc_surface = dm_plane_state->dc_surface;
1492
1493 if (dc_surface->gamma_correction)
1494 dc_gamma_release(&dc_surface->gamma_correction);
1495
1496 if (dc_surface->in_transfer_func)
1497 dc_transfer_func_release(dc_surface->in_transfer_func);
1498
1499 dc_surface_release(dc_surface);
1500 }
1501
1502 __drm_atomic_helper_plane_destroy_state(state);
1503 kfree(dm_plane_state);
1504 }
1505
1506 static const struct drm_plane_funcs dm_plane_funcs = {
1507 .update_plane = drm_atomic_helper_update_plane,
1508 .disable_plane = drm_atomic_helper_disable_plane,
1509 .destroy = drm_plane_cleanup,
1510 .reset = dm_drm_plane_reset,
1511 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
1512 .atomic_destroy_state = dm_drm_plane_destroy_state,
1513 };
1514
1515 static int dm_plane_helper_prepare_fb(
1516 struct drm_plane *plane,
1517 struct drm_plane_state *new_state)
1518 {
1519 struct amdgpu_framebuffer *afb;
1520 struct drm_gem_object *obj;
1521 struct amdgpu_bo *rbo;
1522 int r;
1523
1524 if (!new_state->fb) {
1525 DRM_DEBUG_KMS("No FB bound\n");
1526 return 0;
1527 }
1528
1529 afb = to_amdgpu_framebuffer(new_state->fb);
1530
1531 obj = afb->obj;
1532 rbo = gem_to_amdgpu_bo(obj);
1533 r = amdgpu_bo_reserve(rbo, false);
1534 if (unlikely(r != 0))
1535 return r;
1536
1537 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
1538
1539 amdgpu_bo_unreserve(rbo);
1540
1541 if (unlikely(r != 0)) {
1542 DRM_ERROR("Failed to pin framebuffer\n");
1543 return r;
1544 }
1545
1546 amdgpu_bo_ref(rbo);
1547
1548 /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
1549 * prepare and cleanup in drm_atomic_helper_prepare_planes
1550 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
1551 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
1552 * code touching fram buffers should be avoided for DC.
1553 */
1554 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
1555 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
1556
1557 acrtc->cursor_bo = obj;
1558 }
1559 return 0;
1560 }
1561
1562 static void dm_plane_helper_cleanup_fb(
1563 struct drm_plane *plane,
1564 struct drm_plane_state *old_state)
1565 {
1566 struct amdgpu_bo *rbo;
1567 struct amdgpu_framebuffer *afb;
1568 int r;
1569
1570 if (!old_state->fb)
1571 return;
1572
1573 afb = to_amdgpu_framebuffer(old_state->fb);
1574 rbo = gem_to_amdgpu_bo(afb->obj);
1575 r = amdgpu_bo_reserve(rbo, false);
1576 if (unlikely(r)) {
1577 DRM_ERROR("failed to reserve rbo before unpin\n");
1578 return;
1579 } else {
1580 amdgpu_bo_unpin(rbo);
1581 amdgpu_bo_unreserve(rbo);
1582 amdgpu_bo_unref(&rbo);
1583 };
1584 }
1585
1586 int dm_create_validation_set_for_connector(struct drm_connector *connector,
1587 struct drm_display_mode *mode, struct dc_validation_set *val_set)
1588 {
1589 int result = MODE_ERROR;
1590 const struct dc_sink *dc_sink =
1591 to_amdgpu_connector(connector)->dc_sink;
1592 /* TODO: Unhardcode stream count */
1593 struct dc_stream *stream;
1594
1595 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1596 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
1597 return result;
1598
1599 if (NULL == dc_sink) {
1600 DRM_ERROR("dc_sink is NULL!\n");
1601 return result;
1602 }
1603
1604 stream = dc_create_stream_for_sink(dc_sink);
1605
1606 if (NULL == stream) {
1607 DRM_ERROR("Failed to create stream for sink!\n");
1608 return result;
1609 }
1610
1611 drm_mode_set_crtcinfo(mode, 0);
1612
1613 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
1614
1615 val_set->stream = stream;
1616
1617 stream->src.width = mode->hdisplay;
1618 stream->src.height = mode->vdisplay;
1619 stream->dst = stream->src;
1620
1621 return MODE_OK;
1622 }
1623
1624 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
1625 .prepare_fb = dm_plane_helper_prepare_fb,
1626 .cleanup_fb = dm_plane_helper_cleanup_fb,
1627 };
1628
1629 /*
1630 * TODO: these are currently initialized to rgb formats only.
1631 * For future use cases we should either initialize them dynamically based on
1632 * plane capabilities, or initialize this array to all formats, so internal drm
1633 * check will succeed, and let DC to implement proper check
1634 */
1635 static uint32_t rgb_formats[] = {
1636 DRM_FORMAT_RGB888,
1637 DRM_FORMAT_XRGB8888,
1638 DRM_FORMAT_ARGB8888,
1639 DRM_FORMAT_RGBA8888,
1640 DRM_FORMAT_XRGB2101010,
1641 DRM_FORMAT_XBGR2101010,
1642 DRM_FORMAT_ARGB2101010,
1643 DRM_FORMAT_ABGR2101010,
1644 };
1645
1646 static uint32_t yuv_formats[] = {
1647 DRM_FORMAT_NV12,
1648 DRM_FORMAT_NV21,
1649 };
1650
1651 static const u32 cursor_formats[] = {
1652 DRM_FORMAT_ARGB8888
1653 };
1654
1655 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
1656 struct amdgpu_plane *aplane,
1657 unsigned long possible_crtcs)
1658 {
1659 int res = -EPERM;
1660
1661 switch (aplane->base.type) {
1662 case DRM_PLANE_TYPE_PRIMARY:
1663 aplane->base.format_default = true;
1664
1665 res = drm_universal_plane_init(
1666 dm->adev->ddev,
1667 &aplane->base,
1668 possible_crtcs,
1669 &dm_plane_funcs,
1670 rgb_formats,
1671 ARRAY_SIZE(rgb_formats),
1672 NULL, aplane->base.type, NULL);
1673 break;
1674 case DRM_PLANE_TYPE_OVERLAY:
1675 res = drm_universal_plane_init(
1676 dm->adev->ddev,
1677 &aplane->base,
1678 possible_crtcs,
1679 &dm_plane_funcs,
1680 yuv_formats,
1681 ARRAY_SIZE(yuv_formats),
1682 NULL, aplane->base.type, NULL);
1683 break;
1684 case DRM_PLANE_TYPE_CURSOR:
1685 res = drm_universal_plane_init(
1686 dm->adev->ddev,
1687 &aplane->base,
1688 possible_crtcs,
1689 &dm_plane_funcs,
1690 cursor_formats,
1691 ARRAY_SIZE(cursor_formats),
1692 NULL, aplane->base.type, NULL);
1693 break;
1694 }
1695
1696 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
1697
1698 return res;
1699 }
1700
1701 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
1702 struct drm_plane *plane,
1703 uint32_t crtc_index)
1704 {
1705 struct amdgpu_crtc *acrtc = NULL;
1706 struct amdgpu_plane *cursor_plane;
1707
1708 int res = -ENOMEM;
1709
1710 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
1711 if (!cursor_plane)
1712 goto fail;
1713
1714 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
1715 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
1716
1717 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
1718 if (!acrtc)
1719 goto fail;
1720
1721 res = drm_crtc_init_with_planes(
1722 dm->ddev,
1723 &acrtc->base,
1724 plane,
1725 &cursor_plane->base,
1726 &amdgpu_dm_crtc_funcs, NULL);
1727
1728 if (res)
1729 goto fail;
1730
1731 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
1732
1733 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
1734 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
1735
1736 acrtc->crtc_id = crtc_index;
1737 acrtc->base.enabled = false;
1738
1739 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
1740 drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
1741
1742 return 0;
1743
1744 fail:
1745 if (acrtc)
1746 kfree(acrtc);
1747 if (cursor_plane)
1748 kfree(cursor_plane);
1749 acrtc->crtc_id = -1;
1750 return res;
1751 }
1752
1753
1754 static int to_drm_connector_type(enum signal_type st)
1755 {
1756 switch (st) {
1757 case SIGNAL_TYPE_HDMI_TYPE_A:
1758 return DRM_MODE_CONNECTOR_HDMIA;
1759 case SIGNAL_TYPE_EDP:
1760 return DRM_MODE_CONNECTOR_eDP;
1761 case SIGNAL_TYPE_RGB:
1762 return DRM_MODE_CONNECTOR_VGA;
1763 case SIGNAL_TYPE_DISPLAY_PORT:
1764 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1765 return DRM_MODE_CONNECTOR_DisplayPort;
1766 case SIGNAL_TYPE_DVI_DUAL_LINK:
1767 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1768 return DRM_MODE_CONNECTOR_DVID;
1769 case SIGNAL_TYPE_VIRTUAL:
1770 return DRM_MODE_CONNECTOR_VIRTUAL;
1771
1772 default:
1773 return DRM_MODE_CONNECTOR_Unknown;
1774 }
1775 }
1776
1777 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
1778 {
1779 const struct drm_connector_helper_funcs *helper =
1780 connector->helper_private;
1781 struct drm_encoder *encoder;
1782 struct amdgpu_encoder *amdgpu_encoder;
1783
1784 encoder = helper->best_encoder(connector);
1785
1786 if (encoder == NULL)
1787 return;
1788
1789 amdgpu_encoder = to_amdgpu_encoder(encoder);
1790
1791 amdgpu_encoder->native_mode.clock = 0;
1792
1793 if (!list_empty(&connector->probed_modes)) {
1794 struct drm_display_mode *preferred_mode = NULL;
1795 list_for_each_entry(preferred_mode,
1796 &connector->probed_modes,
1797 head) {
1798 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
1799 amdgpu_encoder->native_mode = *preferred_mode;
1800 }
1801 break;
1802 }
1803
1804 }
1805 }
1806
1807 static struct drm_display_mode *amdgpu_dm_create_common_mode(
1808 struct drm_encoder *encoder, char *name,
1809 int hdisplay, int vdisplay)
1810 {
1811 struct drm_device *dev = encoder->dev;
1812 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1813 struct drm_display_mode *mode = NULL;
1814 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1815
1816 mode = drm_mode_duplicate(dev, native_mode);
1817
1818 if(mode == NULL)
1819 return NULL;
1820
1821 mode->hdisplay = hdisplay;
1822 mode->vdisplay = vdisplay;
1823 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1824 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
1825
1826 return mode;
1827
1828 }
1829
1830 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
1831 struct drm_connector *connector)
1832 {
1833 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1834 struct drm_display_mode *mode = NULL;
1835 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1836 struct amdgpu_connector *amdgpu_connector =
1837 to_amdgpu_connector(connector);
1838 int i;
1839 int n;
1840 struct mode_size {
1841 char name[DRM_DISPLAY_MODE_LEN];
1842 int w;
1843 int h;
1844 }common_modes[] = {
1845 { "640x480", 640, 480},
1846 { "800x600", 800, 600},
1847 { "1024x768", 1024, 768},
1848 { "1280x720", 1280, 720},
1849 { "1280x800", 1280, 800},
1850 {"1280x1024", 1280, 1024},
1851 { "1440x900", 1440, 900},
1852 {"1680x1050", 1680, 1050},
1853 {"1600x1200", 1600, 1200},
1854 {"1920x1080", 1920, 1080},
1855 {"1920x1200", 1920, 1200}
1856 };
1857
1858 n = sizeof(common_modes) / sizeof(common_modes[0]);
1859
1860 for (i = 0; i < n; i++) {
1861 struct drm_display_mode *curmode = NULL;
1862 bool mode_existed = false;
1863
1864 if (common_modes[i].w > native_mode->hdisplay ||
1865 common_modes[i].h > native_mode->vdisplay ||
1866 (common_modes[i].w == native_mode->hdisplay &&
1867 common_modes[i].h == native_mode->vdisplay))
1868 continue;
1869
1870 list_for_each_entry(curmode, &connector->probed_modes, head) {
1871 if (common_modes[i].w == curmode->hdisplay &&
1872 common_modes[i].h == curmode->vdisplay) {
1873 mode_existed = true;
1874 break;
1875 }
1876 }
1877
1878 if (mode_existed)
1879 continue;
1880
1881 mode = amdgpu_dm_create_common_mode(encoder,
1882 common_modes[i].name, common_modes[i].w,
1883 common_modes[i].h);
1884 drm_mode_probed_add(connector, mode);
1885 amdgpu_connector->num_modes++;
1886 }
1887 }
1888
1889 static void amdgpu_dm_connector_ddc_get_modes(
1890 struct drm_connector *connector,
1891 struct edid *edid)
1892 {
1893 struct amdgpu_connector *amdgpu_connector =
1894 to_amdgpu_connector(connector);
1895
1896 if (edid) {
1897 /* empty probed_modes */
1898 INIT_LIST_HEAD(&connector->probed_modes);
1899 amdgpu_connector->num_modes =
1900 drm_add_edid_modes(connector, edid);
1901
1902 drm_edid_to_eld(connector, edid);
1903
1904 amdgpu_dm_get_native_mode(connector);
1905 } else
1906 amdgpu_connector->num_modes = 0;
1907 }
1908
1909 int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
1910 {
1911 const struct drm_connector_helper_funcs *helper =
1912 connector->helper_private;
1913 struct amdgpu_connector *amdgpu_connector =
1914 to_amdgpu_connector(connector);
1915 struct drm_encoder *encoder;
1916 struct edid *edid = amdgpu_connector->edid;
1917
1918 encoder = helper->best_encoder(connector);
1919
1920 amdgpu_dm_connector_ddc_get_modes(connector, edid);
1921 amdgpu_dm_connector_add_common_modes(encoder, connector);
1922 return amdgpu_connector->num_modes;
1923 }
1924
1925 void amdgpu_dm_connector_init_helper(
1926 struct amdgpu_display_manager *dm,
1927 struct amdgpu_connector *aconnector,
1928 int connector_type,
1929 const struct dc_link *link,
1930 int link_index)
1931 {
1932 struct amdgpu_device *adev = dm->ddev->dev_private;
1933
1934 aconnector->connector_id = link_index;
1935 aconnector->dc_link = link;
1936 aconnector->base.interlace_allowed = false;
1937 aconnector->base.doublescan_allowed = false;
1938 aconnector->base.stereo_allowed = false;
1939 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
1940 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
1941
1942 mutex_init(&aconnector->hpd_lock);
1943
1944 /*configure suport HPD hot plug connector_>polled default value is 0
1945 * which means HPD hot plug not supported*/
1946 switch (connector_type) {
1947 case DRM_MODE_CONNECTOR_HDMIA:
1948 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1949 break;
1950 case DRM_MODE_CONNECTOR_DisplayPort:
1951 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1952 break;
1953 case DRM_MODE_CONNECTOR_DVID:
1954 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1955 break;
1956 default:
1957 break;
1958 }
1959
1960 drm_object_attach_property(&aconnector->base.base,
1961 dm->ddev->mode_config.scaling_mode_property,
1962 DRM_MODE_SCALE_NONE);
1963
1964 drm_object_attach_property(&aconnector->base.base,
1965 adev->mode_info.underscan_property,
1966 UNDERSCAN_OFF);
1967 drm_object_attach_property(&aconnector->base.base,
1968 adev->mode_info.underscan_hborder_property,
1969 0);
1970 drm_object_attach_property(&aconnector->base.base,
1971 adev->mode_info.underscan_vborder_property,
1972 0);
1973
1974 }
1975
1976 int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
1977 struct i2c_msg *msgs, int num)
1978 {
1979 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
1980 struct ddc_service *ddc_service = i2c->ddc_service;
1981 struct i2c_command cmd;
1982 int i;
1983 int result = -EIO;
1984
1985 cmd.payloads = kzalloc(num * sizeof(struct i2c_payload), GFP_KERNEL);
1986
1987 if (!cmd.payloads)
1988 return result;
1989
1990 cmd.number_of_payloads = num;
1991 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1992 cmd.speed = 100;
1993
1994 for (i = 0; i < num; i++) {
1995 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
1996 cmd.payloads[i].address = msgs[i].addr;
1997 cmd.payloads[i].length = msgs[i].len;
1998 cmd.payloads[i].data = msgs[i].buf;
1999 }
2000
2001 if (dal_i2caux_submit_i2c_command(
2002 ddc_service->ctx->i2caux,
2003 ddc_service->ddc_pin,
2004 &cmd))
2005 result = num;
2006
2007 kfree(cmd.payloads);
2008 return result;
2009 }
2010
2011 u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
2012 {
2013 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2014 }
2015
2016 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
2017 .master_xfer = amdgpu_dm_i2c_xfer,
2018 .functionality = amdgpu_dm_i2c_func,
2019 };
2020
2021 static struct amdgpu_i2c_adapter *create_i2c(
2022 struct ddc_service *ddc_service,
2023 int link_index,
2024 int *res)
2025 {
2026 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
2027 struct amdgpu_i2c_adapter *i2c;
2028
2029 i2c = kzalloc(sizeof (struct amdgpu_i2c_adapter), GFP_KERNEL);
2030 i2c->base.owner = THIS_MODULE;
2031 i2c->base.class = I2C_CLASS_DDC;
2032 i2c->base.dev.parent = &adev->pdev->dev;
2033 i2c->base.algo = &amdgpu_dm_i2c_algo;
2034 snprintf(i2c->base.name, sizeof (i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
2035 i2c_set_adapdata(&i2c->base, i2c);
2036 i2c->ddc_service = ddc_service;
2037
2038 return i2c;
2039 }
2040
2041 /* Note: this function assumes that dc_link_detect() was called for the
2042 * dc_link which will be represented by this aconnector. */
2043 int amdgpu_dm_connector_init(
2044 struct amdgpu_display_manager *dm,
2045 struct amdgpu_connector *aconnector,
2046 uint32_t link_index,
2047 struct amdgpu_encoder *aencoder)
2048 {
2049 int res = 0;
2050 int connector_type;
2051 struct dc *dc = dm->dc;
2052 const struct dc_link *link = dc_get_link_at_index(dc, link_index);
2053 struct amdgpu_i2c_adapter *i2c;
2054 ((struct dc_link *)link)->priv = aconnector;
2055
2056 DRM_DEBUG_KMS("%s()\n", __func__);
2057
2058 i2c = create_i2c(link->ddc, link->link_index, &res);
2059 aconnector->i2c = i2c;
2060 res = i2c_add_adapter(&i2c->base);
2061
2062 if (res) {
2063 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
2064 goto out_free;
2065 }
2066
2067 connector_type = to_drm_connector_type(link->connector_signal);
2068
2069 res = drm_connector_init(
2070 dm->ddev,
2071 &aconnector->base,
2072 &amdgpu_dm_connector_funcs,
2073 connector_type);
2074
2075 if (res) {
2076 DRM_ERROR("connector_init failed\n");
2077 aconnector->connector_id = -1;
2078 goto out_free;
2079 }
2080
2081 drm_connector_helper_add(
2082 &aconnector->base,
2083 &amdgpu_dm_connector_helper_funcs);
2084
2085 amdgpu_dm_connector_init_helper(
2086 dm,
2087 aconnector,
2088 connector_type,
2089 link,
2090 link_index);
2091
2092 drm_mode_connector_attach_encoder(
2093 &aconnector->base, &aencoder->base);
2094
2095 drm_connector_register(&aconnector->base);
2096
2097 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
2098 || connector_type == DRM_MODE_CONNECTOR_eDP)
2099 amdgpu_dm_initialize_dp_connector(dm, aconnector);
2100
2101 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2102 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2103
2104 /* NOTE: this currently will create backlight device even if a panel
2105 * is not connected to the eDP/LVDS connector.
2106 *
2107 * This is less than ideal but we don't have sink information at this
2108 * stage since detection happens after. We can't do detection earlier
2109 * since MST detection needs connectors to be created first.
2110 */
2111 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2112 /* Event if registration failed, we should continue with
2113 * DM initialization because not having a backlight control
2114 * is better then a black screen. */
2115 amdgpu_dm_register_backlight_device(dm);
2116
2117 if (dm->backlight_dev)
2118 dm->backlight_link = link;
2119 }
2120 #endif
2121
2122 out_free:
2123 if (res) {
2124 kfree(i2c);
2125 aconnector->i2c = NULL;
2126 }
2127 return res;
2128 }
2129
2130 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
2131 {
2132 switch (adev->mode_info.num_crtc) {
2133 case 1:
2134 return 0x1;
2135 case 2:
2136 return 0x3;
2137 case 3:
2138 return 0x7;
2139 case 4:
2140 return 0xf;
2141 case 5:
2142 return 0x1f;
2143 case 6:
2144 default:
2145 return 0x3f;
2146 }
2147 }
2148
2149 int amdgpu_dm_encoder_init(
2150 struct drm_device *dev,
2151 struct amdgpu_encoder *aencoder,
2152 uint32_t link_index)
2153 {
2154 struct amdgpu_device *adev = dev->dev_private;
2155
2156 int res = drm_encoder_init(dev,
2157 &aencoder->base,
2158 &amdgpu_dm_encoder_funcs,
2159 DRM_MODE_ENCODER_TMDS,
2160 NULL);
2161
2162 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
2163
2164 if (!res)
2165 aencoder->encoder_id = link_index;
2166 else
2167 aencoder->encoder_id = -1;
2168
2169 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
2170
2171 return res;
2172 }
2173
2174 static bool modeset_required(struct drm_crtc_state *crtc_state)
2175 {
2176 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2177 return false;
2178
2179 if (!crtc_state->enable)
2180 return false;
2181
2182 return crtc_state->active;
2183 }
2184
2185 static bool modereset_required(struct drm_crtc_state *crtc_state)
2186 {
2187 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2188 return false;
2189
2190 return !crtc_state->enable || !crtc_state->active;
2191 }
2192
2193 static void manage_dm_interrupts(
2194 struct amdgpu_device *adev,
2195 struct amdgpu_crtc *acrtc,
2196 bool enable)
2197 {
2198 /*
2199 * this is not correct translation but will work as soon as VBLANK
2200 * constant is the same as PFLIP
2201 */
2202 int irq_type =
2203 amdgpu_crtc_idx_to_irq_type(
2204 adev,
2205 acrtc->crtc_id);
2206
2207 if (enable) {
2208 drm_crtc_vblank_on(&acrtc->base);
2209 amdgpu_irq_get(
2210 adev,
2211 &adev->pageflip_irq,
2212 irq_type);
2213 } else {
2214
2215 amdgpu_irq_put(
2216 adev,
2217 &adev->pageflip_irq,
2218 irq_type);
2219 drm_crtc_vblank_off(&acrtc->base);
2220 }
2221 }
2222
2223 static bool is_scaling_state_different(
2224 const struct dm_connector_state *dm_state,
2225 const struct dm_connector_state *old_dm_state)
2226 {
2227 if (dm_state->scaling != old_dm_state->scaling)
2228 return true;
2229 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
2230 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
2231 return true;
2232 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
2233 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
2234 return true;
2235 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder
2236 || dm_state->underscan_vborder != old_dm_state->underscan_vborder)
2237 return true;
2238 return false;
2239 }
2240
2241 static void remove_stream(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc)
2242 {
2243 /*
2244 * we evade vblanks and pflips on crtc that
2245 * should be changed
2246 */
2247 manage_dm_interrupts(adev, acrtc, false);
2248
2249 /* this is the update mode case */
2250 if (adev->dm.freesync_module)
2251 mod_freesync_remove_stream(adev->dm.freesync_module,
2252 acrtc->stream);
2253
2254 dc_stream_release(acrtc->stream);
2255 acrtc->stream = NULL;
2256 acrtc->otg_inst = -1;
2257 acrtc->enabled = false;
2258 }
2259
2260 static void handle_cursor_update(
2261 struct drm_plane *plane,
2262 struct drm_plane_state *old_plane_state)
2263 {
2264 if (!plane->state->fb && !old_plane_state->fb)
2265 return;
2266
2267 /* Check if it's a cursor on/off update or just cursor move*/
2268 if (plane->state->fb == old_plane_state->fb)
2269 dm_crtc_cursor_move(
2270 plane->state->crtc,
2271 plane->state->crtc_x,
2272 plane->state->crtc_y);
2273 else {
2274 struct amdgpu_framebuffer *afb =
2275 to_amdgpu_framebuffer(plane->state->fb);
2276 dm_crtc_cursor_set(
2277 (!!plane->state->fb) ?
2278 plane->state->crtc :
2279 old_plane_state->crtc,
2280 (!!plane->state->fb) ?
2281 afb->address :
2282 0,
2283 plane->state->crtc_w,
2284 plane->state->crtc_h);
2285 }
2286 }
2287
2288
2289 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
2290 {
2291
2292 assert_spin_locked(&acrtc->base.dev->event_lock);
2293 WARN_ON(acrtc->event);
2294
2295 acrtc->event = acrtc->base.state->event;
2296
2297 /* Set the flip status */
2298 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
2299
2300 /* Mark this event as consumed */
2301 acrtc->base.state->event = NULL;
2302
2303 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
2304 acrtc->crtc_id);
2305 }
2306
2307 /*
2308 * Executes flip
2309 *
2310 * Waits on all BO's fences and for proper vblank count
2311 */
2312 static void amdgpu_dm_do_flip(
2313 struct drm_crtc *crtc,
2314 struct drm_framebuffer *fb,
2315 uint32_t target)
2316 {
2317 unsigned long flags;
2318 uint32_t target_vblank;
2319 int r, vpos, hpos;
2320 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2321 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
2322 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
2323 struct amdgpu_device *adev = crtc->dev->dev_private;
2324 bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
2325 struct dc_flip_addrs addr = { {0} };
2326 struct dc_surface_update surface_updates[1] = { {0} };
2327
2328 /* Prepare wait for target vblank early - before the fence-waits */
2329 target_vblank = target - drm_crtc_vblank_count(crtc) +
2330 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
2331
2332 /*TODO This might fail and hence better not used, wait
2333 * explicitly on fences instead
2334 * and in general should be called for
2335 * blocking commit to as per framework helpers
2336 * */
2337 r = amdgpu_bo_reserve(abo, true);
2338 if (unlikely(r != 0)) {
2339 DRM_ERROR("failed to reserve buffer before flip\n");
2340 WARN_ON(1);
2341 }
2342
2343 /* Wait for all fences on this FB */
2344 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
2345 MAX_SCHEDULE_TIMEOUT) < 0);
2346
2347 amdgpu_bo_unreserve(abo);
2348
2349 /* Wait until we're out of the vertical blank period before the one
2350 * targeted by the flip
2351 */
2352 while ((acrtc->enabled &&
2353 (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
2354 &vpos, &hpos, NULL, NULL,
2355 &crtc->hwmode)
2356 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
2357 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
2358 (int)(target_vblank -
2359 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
2360 usleep_range(1000, 1100);
2361 }
2362
2363 /* Flip */
2364 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2365 /* update crtc fb */
2366 crtc->primary->fb = fb;
2367
2368 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
2369 WARN_ON(!acrtc->stream);
2370
2371 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
2372 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
2373 addr.flip_immediate = async_flip;
2374
2375
2376 if (acrtc->base.state->event)
2377 prepare_flip_isr(acrtc);
2378
2379 surface_updates->surface = dc_stream_get_status(acrtc->stream)->surfaces[0];
2380 surface_updates->flip_addr = &addr;
2381
2382
2383 dc_update_surfaces_for_stream(adev->dm.dc, surface_updates, 1, acrtc->stream);
2384
2385 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
2386 __func__,
2387 addr.address.grph.addr.high_part,
2388 addr.address.grph.addr.low_part);
2389
2390
2391 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2392 }
2393
2394 static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state,
2395 struct drm_device *dev,
2396 struct amdgpu_display_manager *dm,
2397 struct drm_crtc *pcrtc,
2398 bool *wait_for_vblank)
2399 {
2400 uint32_t i;
2401 struct drm_plane *plane;
2402 struct drm_plane_state *old_plane_state;
2403 const struct dc_stream *dc_stream_attach;
2404 const struct dc_surface *dc_surfaces_constructed[MAX_SURFACES];
2405 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
2406 int planes_count = 0;
2407
2408 /* update planes when needed */
2409 for_each_plane_in_state(state, plane, old_plane_state, i) {
2410 struct drm_plane_state *plane_state = plane->state;
2411 struct drm_crtc *crtc = plane_state->crtc;
2412 struct drm_framebuffer *fb = plane_state->fb;
2413 struct drm_connector *connector;
2414 struct dm_connector_state *con_state = NULL;
2415 bool pflip_needed;
2416
2417 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
2418 handle_cursor_update(plane, old_plane_state);
2419 continue;
2420 }
2421
2422 if (!fb || !crtc || pcrtc != crtc || !crtc->state->active)
2423 continue;
2424
2425 pflip_needed = !state->allow_modeset;
2426 if (!pflip_needed) {
2427 list_for_each_entry(connector,
2428 &dev->mode_config.connector_list,
2429 head) {
2430 if (connector->state->crtc == crtc) {
2431 con_state = to_dm_connector_state(
2432 connector->state);
2433 break;
2434 }
2435 }
2436
2437 /*
2438 * This situation happens in the following case:
2439 * we are about to get set mode for connector who's only
2440 * possible crtc (in encoder crtc mask) is used by
2441 * another connector, that is why it will try to
2442 * re-assing crtcs in order to make configuration
2443 * supported. For our implementation we need to make all
2444 * encoders support all crtcs, then this issue will
2445 * never arise again. But to guard code from this issue
2446 * check is left.
2447 *
2448 * Also it should be needed when used with actual
2449 * drm_atomic_commit ioctl in future
2450 */
2451 if (!con_state)
2452 continue;
2453
2454 add_surface(dm->dc, crtc, plane,
2455 &dc_surfaces_constructed[planes_count]);
2456 if (dc_surfaces_constructed[planes_count] == NULL) {
2457 dm_error("%s: Failed to add surface!\n", __func__);
2458 continue;
2459 }
2460 dc_stream_attach = acrtc_attach->stream;
2461 planes_count++;
2462
2463 } else if (crtc->state->planes_changed) {
2464 /* Assume even ONE crtc with immediate flip means
2465 * entire can't wait for VBLANK
2466 * TODO Check if it's correct
2467 */
2468 *wait_for_vblank =
2469 acrtc_attach->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
2470 false : true;
2471
2472 /* TODO: Needs rework for multiplane flip */
2473 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2474 drm_crtc_vblank_get(crtc);
2475
2476 amdgpu_dm_do_flip(
2477 crtc,
2478 fb,
2479 drm_crtc_vblank_count(crtc) + *wait_for_vblank);
2480
2481 /*TODO BUG remove ASAP in 4.12 to avoid race between worker and flip IOCTL */
2482
2483 /*clean up the flags for next usage*/
2484 acrtc_attach->flip_flags = 0;
2485 }
2486
2487 }
2488
2489 if (planes_count) {
2490 unsigned long flags;
2491
2492 if (pcrtc->state->event) {
2493
2494 drm_crtc_vblank_get(pcrtc);
2495
2496 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
2497 prepare_flip_isr(acrtc_attach);
2498 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
2499 }
2500
2501 if (false == dc_commit_surfaces_to_stream(dm->dc,
2502 dc_surfaces_constructed,
2503 planes_count,
2504 dc_stream_attach))
2505 dm_error("%s: Failed to attach surface!\n", __func__);
2506
2507 for (i = 0; i < planes_count; i++)
2508 dc_surface_release(dc_surfaces_constructed[i]);
2509 } else {
2510 /*TODO BUG Here should go disable planes on CRTC. */
2511 }
2512 }
2513
2514 void amdgpu_dm_atomic_commit_tail(
2515 struct drm_atomic_state *state)
2516 {
2517 struct drm_device *dev = state->dev;
2518 struct amdgpu_device *adev = dev->dev_private;
2519 struct amdgpu_display_manager *dm = &adev->dm;
2520 uint32_t i, j;
2521 uint32_t commit_streams_count = 0;
2522 uint32_t new_crtcs_count = 0;
2523 struct drm_crtc *crtc, *pcrtc;
2524 struct drm_crtc_state *old_crtc_state;
2525 const struct dc_stream *commit_streams[MAX_STREAMS];
2526 struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
2527 const struct dc_stream *new_stream;
2528 unsigned long flags;
2529 bool wait_for_vblank = true;
2530 struct drm_connector *connector;
2531 struct drm_connector_state *old_conn_state;
2532
2533 drm_atomic_helper_update_legacy_modeset_state(dev, state);
2534 /* update changed items */
2535 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
2536 struct amdgpu_crtc *acrtc;
2537 struct amdgpu_connector *aconnector = NULL;
2538 struct drm_crtc_state *new_state = crtc->state;
2539
2540 acrtc = to_amdgpu_crtc(crtc);
2541 aconnector =
2542 amdgpu_dm_find_first_crct_matching_connector(
2543 state,
2544 crtc,
2545 false);
2546
2547 DRM_DEBUG_KMS(
2548 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
2549 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
2550 "connectors_changed:%d\n",
2551 acrtc->crtc_id,
2552 new_state->enable,
2553 new_state->active,
2554 new_state->planes_changed,
2555 new_state->mode_changed,
2556 new_state->active_changed,
2557 new_state->connectors_changed);
2558
2559 /* handles headless hotplug case, updating new_state and
2560 * aconnector as needed
2561 */
2562
2563 if (modeset_required(new_state)) {
2564 struct dm_connector_state *dm_state = NULL;
2565 new_stream = NULL;
2566
2567 if (aconnector)
2568 dm_state = to_dm_connector_state(aconnector->base.state);
2569
2570 new_stream = create_stream_for_sink(
2571 aconnector,
2572 &crtc->state->mode,
2573 dm_state);
2574
2575 DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
2576
2577 if (!new_stream) {
2578 /*
2579 * this could happen because of issues with
2580 * userspace notifications delivery.
2581 * In this case userspace tries to set mode on
2582 * display which is disconnect in fact.
2583 * dc_sink in NULL in this case on aconnector.
2584 * We expect reset mode will come soon.
2585 *
2586 * This can also happen when unplug is done
2587 * during resume sequence ended
2588 *
2589 * In this case, we want to pretend we still
2590 * have a sink to keep the pipe running so that
2591 * hw state is consistent with the sw state
2592 */
2593 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
2594 __func__, acrtc->base.base.id);
2595 break;
2596 }
2597
2598 if (acrtc->stream)
2599 remove_stream(adev, acrtc);
2600
2601 /*
2602 * this loop saves set mode crtcs
2603 * we needed to enable vblanks once all
2604 * resources acquired in dc after dc_commit_streams
2605 */
2606 new_crtcs[new_crtcs_count] = acrtc;
2607 new_crtcs_count++;
2608
2609 acrtc->stream = new_stream;
2610 acrtc->enabled = true;
2611 acrtc->hw_mode = crtc->state->mode;
2612 crtc->hwmode = crtc->state->mode;
2613 } else if (modereset_required(new_state)) {
2614
2615 DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
2616 /* i.e. reset mode */
2617 if (acrtc->stream)
2618 remove_stream(adev, acrtc);
2619 }
2620 } /* for_each_crtc_in_state() */
2621
2622 /* Handle scaling and undersacn changes*/
2623 for_each_connector_in_state(state, connector, old_conn_state, i) {
2624 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2625 struct dm_connector_state *con_new_state =
2626 to_dm_connector_state(aconnector->base.state);
2627 struct dm_connector_state *con_old_state =
2628 to_dm_connector_state(old_conn_state);
2629 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc);
2630 const struct dc_stream_status *status = NULL;
2631
2632 /* Skip any modesets/resets */
2633 if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state))
2634 continue;
2635
2636 /* Skip any thing not scale or underscan chnages */
2637 if (!is_scaling_state_different(con_new_state, con_old_state))
2638 continue;
2639
2640 update_stream_scaling_settings(&con_new_state->base.crtc->mode,
2641 con_new_state, (struct dc_stream *)acrtc->stream);
2642
2643 status = dc_stream_get_status(acrtc->stream);
2644 WARN_ON(!status);
2645 WARN_ON(!status->surface_count);
2646
2647 if (!acrtc->stream)
2648 continue;
2649
2650 /*TODO How it works with MPO ?*/
2651 if (!dc_commit_surfaces_to_stream(
2652 dm->dc,
2653 (const struct dc_surface **)status->surfaces,
2654 status->surface_count,
2655 acrtc->stream))
2656 dm_error("%s: Failed to update stream scaling!\n", __func__);
2657 }
2658
2659 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2660
2661 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2662
2663 if (acrtc->stream) {
2664 commit_streams[commit_streams_count] = acrtc->stream;
2665 ++commit_streams_count;
2666 }
2667 }
2668
2669 /*
2670 * Add streams after required streams from new and replaced streams
2671 * are removed from freesync module
2672 */
2673 if (adev->dm.freesync_module) {
2674 for (i = 0; i < new_crtcs_count; i++) {
2675 struct amdgpu_connector *aconnector = NULL;
2676 new_stream = new_crtcs[i]->stream;
2677 aconnector =
2678 amdgpu_dm_find_first_crct_matching_connector(
2679 state,
2680 &new_crtcs[i]->base,
2681 false);
2682 if (!aconnector) {
2683 DRM_INFO(
2684 "Atomic commit: Failed to find connector for acrtc id:%d "
2685 "skipping freesync init\n",
2686 new_crtcs[i]->crtc_id);
2687 continue;
2688 }
2689
2690 mod_freesync_add_stream(adev->dm.freesync_module,
2691 new_stream, &aconnector->caps);
2692 }
2693 }
2694
2695 /* DC is optimized not to do anything if 'streams' didn't change. */
2696 WARN_ON(!dc_commit_streams(dm->dc, commit_streams, commit_streams_count));
2697
2698 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2699 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2700
2701 if (acrtc->stream != NULL)
2702 acrtc->otg_inst =
2703 dc_stream_get_status(acrtc->stream)->primary_otg_inst;
2704 }
2705
2706 for (i = 0; i < new_crtcs_count; i++) {
2707 /*
2708 * loop to enable interrupts on newly arrived crtc
2709 */
2710 struct amdgpu_crtc *acrtc = new_crtcs[i];
2711
2712 if (adev->dm.freesync_module)
2713 mod_freesync_notify_mode_change(
2714 adev->dm.freesync_module, &acrtc->stream, 1);
2715
2716 manage_dm_interrupts(adev, acrtc, true);
2717 }
2718
2719 /* update planes when needed per crtc*/
2720 for_each_crtc_in_state(state, pcrtc, old_crtc_state, j) {
2721 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(pcrtc);
2722
2723 if (acrtc->stream)
2724 amdgpu_dm_commit_surfaces(state, dev, dm, pcrtc, &wait_for_vblank);
2725 }
2726
2727
2728 /*
2729 * send vblank event on all events not handled in flip and
2730 * mark consumed event for drm_atomic_helper_commit_hw_done
2731 */
2732 spin_lock_irqsave(&adev->ddev->event_lock, flags);
2733 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
2734 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2735
2736 if (acrtc->base.state->event)
2737 drm_send_event_locked(dev, &crtc->state->event->base);
2738
2739 acrtc->base.state->event = NULL;
2740 }
2741 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
2742
2743 /* Signal HW programming completion */
2744 drm_atomic_helper_commit_hw_done(state);
2745
2746 if (wait_for_vblank)
2747 drm_atomic_helper_wait_for_vblanks(dev, state);
2748
2749 drm_atomic_helper_cleanup_planes(dev, state);
2750 }
2751
2752
2753 static int dm_force_atomic_commit(struct drm_connector *connector)
2754 {
2755 int ret = 0;
2756 struct drm_device *ddev = connector->dev;
2757 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
2758 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
2759 struct drm_plane *plane = disconnected_acrtc->base.primary;
2760 struct drm_connector_state *conn_state;
2761 struct drm_crtc_state *crtc_state;
2762 struct drm_plane_state *plane_state;
2763
2764 if (!state)
2765 return -ENOMEM;
2766
2767 state->acquire_ctx = ddev->mode_config.acquire_ctx;
2768
2769 /* Construct an atomic state to restore previous display setting */
2770
2771 /*
2772 * Attach connectors to drm_atomic_state
2773 */
2774 conn_state = drm_atomic_get_connector_state(state, connector);
2775
2776 ret = PTR_ERR_OR_ZERO(conn_state);
2777 if (ret)
2778 goto err;
2779
2780 /* Attach crtc to drm_atomic_state*/
2781 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
2782
2783 ret = PTR_ERR_OR_ZERO(crtc_state);
2784 if (ret)
2785 goto err;
2786
2787 /* force a restore */
2788 crtc_state->mode_changed = true;
2789
2790 /* Attach plane to drm_atomic_state */
2791 plane_state = drm_atomic_get_plane_state(state, plane);
2792
2793 ret = PTR_ERR_OR_ZERO(plane_state);
2794 if (ret)
2795 goto err;
2796
2797
2798 /* Call commit internally with the state we just constructed */
2799 ret = drm_atomic_commit(state);
2800 if (!ret)
2801 return 0;
2802
2803 err:
2804 DRM_ERROR("Restoring old state failed with %i\n", ret);
2805 drm_atomic_state_put(state);
2806
2807 return ret;
2808 }
2809
2810 /*
2811 * This functions handle all cases when set mode does not come upon hotplug.
2812 * This include when the same display is unplugged then plugged back into the
2813 * same port and when we are running without usermode desktop manager supprot
2814 */
2815 void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector)
2816 {
2817 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2818 struct amdgpu_crtc *disconnected_acrtc;
2819
2820 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
2821 return;
2822
2823 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
2824
2825 if (!disconnected_acrtc || !disconnected_acrtc->stream)
2826 return;
2827
2828 /*
2829 * If the previous sink is not released and different from the current,
2830 * we deduce we are in a state where we can not rely on usermode call
2831 * to turn on the display, so we do it here
2832 */
2833 if (disconnected_acrtc->stream->sink != aconnector->dc_sink)
2834 dm_force_atomic_commit(&aconnector->base);
2835 }
2836
2837 static uint32_t add_val_sets_surface(
2838 struct dc_validation_set *val_sets,
2839 uint32_t set_count,
2840 const struct dc_stream *stream,
2841 const struct dc_surface *surface)
2842 {
2843 uint32_t i = 0, j = 0;
2844
2845 while (i < set_count) {
2846 if (val_sets[i].stream == stream) {
2847 while (val_sets[i].surfaces[j])
2848 j++;
2849 break;
2850 }
2851 ++i;
2852 }
2853
2854 val_sets[i].surfaces[j] = surface;
2855 val_sets[i].surface_count++;
2856
2857 return val_sets[i].surface_count;
2858 }
2859
2860 static uint32_t update_in_val_sets_stream(
2861 struct dc_validation_set *val_sets,
2862 struct drm_crtc **crtcs,
2863 uint32_t set_count,
2864 const struct dc_stream *old_stream,
2865 const struct dc_stream *new_stream,
2866 struct drm_crtc *crtc)
2867 {
2868 uint32_t i = 0;
2869
2870 while (i < set_count) {
2871 if (val_sets[i].stream == old_stream)
2872 break;
2873 ++i;
2874 }
2875
2876 val_sets[i].stream = new_stream;
2877 crtcs[i] = crtc;
2878
2879 if (i == set_count) {
2880 /* nothing found. add new one to the end */
2881 return set_count + 1;
2882 }
2883
2884 return set_count;
2885 }
2886
2887 static uint32_t remove_from_val_sets(
2888 struct dc_validation_set *val_sets,
2889 uint32_t set_count,
2890 const struct dc_stream *stream)
2891 {
2892 int i;
2893
2894 for (i = 0; i < set_count; i++)
2895 if (val_sets[i].stream == stream)
2896 break;
2897
2898 if (i == set_count) {
2899 /* nothing found */
2900 return set_count;
2901 }
2902
2903 set_count--;
2904
2905 for (; i < set_count; i++) {
2906 val_sets[i] = val_sets[i + 1];
2907 }
2908
2909 return set_count;
2910 }
2911
2912 /*`
2913 * Grabs all modesetting locks to serialize against any blocking commits,
2914 * Waits for completion of all non blocking commits.
2915 */
2916 static int do_aquire_global_lock(
2917 struct drm_device *dev,
2918 struct drm_atomic_state *state)
2919 {
2920 struct drm_crtc *crtc;
2921 struct drm_crtc_commit *commit;
2922 long ret;
2923
2924 /* Adding all modeset locks to aquire_ctx will
2925 * ensure that when the framework release it the
2926 * extra locks we are locking here will get released to
2927 */
2928 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
2929 if (ret)
2930 return ret;
2931
2932 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2933 spin_lock(&crtc->commit_lock);
2934 commit = list_first_entry_or_null(&crtc->commit_list,
2935 struct drm_crtc_commit, commit_entry);
2936 if (commit)
2937 drm_crtc_commit_get(commit);
2938 spin_unlock(&crtc->commit_lock);
2939
2940 if (!commit)
2941 continue;
2942
2943 /* Make sure all pending HW programming completed and
2944 * page flips done
2945 */
2946 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
2947
2948 if (ret > 0)
2949 ret = wait_for_completion_interruptible_timeout(
2950 &commit->flip_done, 10*HZ);
2951
2952 if (ret == 0)
2953 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
2954 "timed out\n", crtc->base.id, crtc->name);
2955
2956 drm_crtc_commit_put(commit);
2957 }
2958
2959 return ret < 0 ? ret : 0;
2960 }
2961
2962 int amdgpu_dm_atomic_check(struct drm_device *dev,
2963 struct drm_atomic_state *state)
2964 {
2965 struct drm_crtc *crtc;
2966 struct drm_crtc_state *crtc_state;
2967 struct drm_plane *plane;
2968 struct drm_plane_state *plane_state;
2969 int i, j;
2970 int ret;
2971 int set_count;
2972 int new_stream_count;
2973 struct dc_validation_set set[MAX_STREAMS] = {{ 0 }};
2974 struct dc_stream *new_streams[MAX_STREAMS] = { 0 };
2975 struct drm_crtc *crtc_set[MAX_STREAMS] = { 0 };
2976 struct amdgpu_device *adev = dev->dev_private;
2977 struct dc *dc = adev->dm.dc;
2978 bool need_to_validate = false;
2979 struct validate_context *context;
2980 struct drm_connector *connector;
2981 struct drm_connector_state *conn_state;
2982 /*
2983 * This bool will be set for true for any modeset/reset
2984 * or surface update which implies non fast surfae update.
2985 */
2986 bool aquire_global_lock = false;
2987
2988 ret = drm_atomic_helper_check(dev, state);
2989
2990 if (ret) {
2991 DRM_ERROR("Atomic state validation failed with error :%d !\n",
2992 ret);
2993 return ret;
2994 }
2995
2996 ret = -EINVAL;
2997
2998 /* copy existing configuration */
2999 new_stream_count = 0;
3000 set_count = 0;
3001 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3002
3003 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3004
3005 if (acrtc->stream) {
3006 set[set_count].stream = acrtc->stream;
3007 crtc_set[set_count] = crtc;
3008 ++set_count;
3009 }
3010 }
3011
3012 /* update changed items */
3013 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3014 struct amdgpu_crtc *acrtc = NULL;
3015 struct amdgpu_connector *aconnector = NULL;
3016
3017 acrtc = to_amdgpu_crtc(crtc);
3018
3019 aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc, true);
3020
3021 DRM_DEBUG_KMS(
3022 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
3023 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
3024 "connectors_changed:%d\n",
3025 acrtc->crtc_id,
3026 crtc_state->enable,
3027 crtc_state->active,
3028 crtc_state->planes_changed,
3029 crtc_state->mode_changed,
3030 crtc_state->active_changed,
3031 crtc_state->connectors_changed);
3032
3033 if (modeset_required(crtc_state)) {
3034
3035 struct dc_stream *new_stream = NULL;
3036 struct drm_connector_state *conn_state = NULL;
3037 struct dm_connector_state *dm_state = NULL;
3038
3039 if (aconnector) {
3040 conn_state = drm_atomic_get_connector_state(state, &aconnector->base);
3041 if (IS_ERR(conn_state))
3042 return ret;
3043 dm_state = to_dm_connector_state(conn_state);
3044 }
3045
3046 new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_state);
3047
3048 /*
3049 * we can have no stream on ACTION_SET if a display
3050 * was disconnected during S3, in this case it not and
3051 * error, the OS will be updated after detection, and
3052 * do the right thing on next atomic commit
3053 */
3054 if (!new_stream) {
3055 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
3056 __func__, acrtc->base.base.id);
3057 break;
3058 }
3059
3060 new_streams[new_stream_count] = new_stream;
3061 set_count = update_in_val_sets_stream(
3062 set,
3063 crtc_set,
3064 set_count,
3065 acrtc->stream,
3066 new_stream,
3067 crtc);
3068
3069 new_stream_count++;
3070 need_to_validate = true;
3071 aquire_global_lock = true;
3072
3073 } else if (modereset_required(crtc_state)) {
3074
3075 /* i.e. reset mode */
3076 if (acrtc->stream) {
3077 set_count = remove_from_val_sets(
3078 set,
3079 set_count,
3080 acrtc->stream);
3081 aquire_global_lock = true;
3082 }
3083 }
3084
3085
3086 /*
3087 * Hack: Commit needs planes right now, specifically for gamma
3088 * TODO rework commit to check CRTC for gamma change
3089 */
3090 if (crtc_state->color_mgmt_changed) {
3091
3092 ret = drm_atomic_add_affected_planes(state, crtc);
3093 if (ret)
3094 return ret;
3095
3096 ret = -EINVAL;
3097 }
3098 }
3099
3100 /* Check scaling and undersacn changes*/
3101 for_each_connector_in_state(state, connector, conn_state, i) {
3102 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
3103 struct dm_connector_state *con_old_state =
3104 to_dm_connector_state(aconnector->base.state);
3105 struct dm_connector_state *con_new_state =
3106 to_dm_connector_state(conn_state);
3107 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc);
3108 struct dc_stream *new_stream;
3109
3110 /* Skip any modesets/resets */
3111 if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state))
3112 continue;
3113
3114 /* Skip any thing not scale or underscan chnages */
3115 if (!is_scaling_state_different(con_new_state, con_old_state))
3116 continue;
3117
3118 new_stream = create_stream_for_sink(
3119 aconnector,
3120 &acrtc->base.state->mode,
3121 con_new_state);
3122
3123 if (!new_stream) {
3124 DRM_ERROR("%s: Failed to create new stream for crtc %d\n",
3125 __func__, acrtc->base.base.id);
3126 continue;
3127 }
3128
3129 new_streams[new_stream_count] = new_stream;
3130 set_count = update_in_val_sets_stream(
3131 set,
3132 crtc_set,
3133 set_count,
3134 acrtc->stream,
3135 new_stream,
3136 &acrtc->base);
3137
3138 new_stream_count++;
3139 need_to_validate = true;
3140 aquire_global_lock = true;
3141 }
3142
3143 for (i = 0; i < set_count; i++) {
3144 for_each_plane_in_state(state, plane, plane_state, j) {
3145 struct drm_crtc *crtc = plane_state->crtc;
3146 struct drm_framebuffer *fb = plane_state->fb;
3147 struct drm_connector *connector;
3148 struct dm_connector_state *dm_state = NULL;
3149 struct drm_crtc_state *crtc_state;
3150 bool pflip_needed;
3151
3152 /*TODO Implement atomic check for cursor plane */
3153 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3154 continue;
3155
3156 if (!fb || !crtc || crtc_set[i] != crtc ||
3157 !crtc->state->planes_changed || !crtc->state->active)
3158 continue;
3159
3160
3161 crtc_state = drm_atomic_get_crtc_state(state, crtc);
3162 pflip_needed = !state->allow_modeset;
3163 if (!pflip_needed) {
3164 struct dc_surface *surface;
3165
3166 list_for_each_entry(connector,
3167 &dev->mode_config.connector_list, head) {
3168 if (connector->state->crtc == crtc) {
3169 dm_state = to_dm_connector_state(
3170 connector->state);
3171 break;
3172 }
3173 }
3174
3175 /*
3176 * This situation happens in the following case:
3177 * we are about to get set mode for connector who's only
3178 * possible crtc (in encoder crtc mask) is used by
3179 * another connector, that is why it will try to
3180 * re-assing crtcs in order to make configuration
3181 * supported. For our implementation we need to make all
3182 * encoders support all crtcs, then this issue will
3183 * never arise again. But to guard code from this issue
3184 * check is left.
3185 *
3186 * Also it should be needed when used with actual
3187 * drm_atomic_commit ioctl in future
3188 */
3189 if (!dm_state)
3190 continue;
3191
3192 surface = dc_create_surface(dc);
3193 fill_plane_attributes(
3194 crtc->dev->dev_private,
3195 surface,
3196 plane_state,
3197 false);
3198
3199 add_val_sets_surface(
3200 set,
3201 set_count,
3202 set[i].stream,
3203 surface);
3204
3205 need_to_validate = true;
3206 aquire_global_lock = true;
3207 }
3208 }
3209 }
3210
3211 context = dc_get_validate_context(dc, set, set_count);
3212
3213 if (need_to_validate == false || set_count == 0 || context) {
3214
3215 ret = 0;
3216 /*
3217 * For full updates case when
3218 * removing/adding/updateding streams on once CRTC while flipping
3219 * on another CRTC,
3220 * acquiring global lock will guarantee that any such full
3221 * update commit
3222 * will wait for completion of any outstanding flip using DRMs
3223 * synchronization events.
3224 */
3225 if (aquire_global_lock)
3226 ret = do_aquire_global_lock(dev, state);
3227
3228 }
3229
3230 if (context) {
3231 dc_resource_validate_ctx_destruct(context);
3232 dm_free(context);
3233 }
3234
3235 for (i = 0; i < set_count; i++)
3236 for (j = 0; j < set[i].surface_count; j++)
3237 dc_surface_release(set[i].surfaces[j]);
3238
3239 for (i = 0; i < new_stream_count; i++)
3240 dc_stream_release(new_streams[i]);
3241
3242 if (ret != 0) {
3243 if (ret == -EDEADLK)
3244 DRM_DEBUG_KMS("Atomic check stopped due to to deadlock.\n");
3245 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
3246 DRM_DEBUG_KMS("Atomic check stopped due to to signal.\n");
3247 else
3248 DRM_ERROR("Atomic check failed.\n");
3249 }
3250
3251 return ret;
3252 }
3253
3254 static bool is_dp_capable_without_timing_msa(
3255 struct dc *dc,
3256 struct amdgpu_connector *amdgpu_connector)
3257 {
3258 uint8_t dpcd_data;
3259 bool capable = false;
3260
3261 if (amdgpu_connector->dc_link &&
3262 dm_helpers_dp_read_dpcd(
3263 NULL,
3264 amdgpu_connector->dc_link,
3265 DP_DOWN_STREAM_PORT_COUNT,
3266 &dpcd_data,
3267 sizeof(dpcd_data))) {
3268 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
3269 }
3270
3271 return capable;
3272 }
3273 void amdgpu_dm_add_sink_to_freesync_module(
3274 struct drm_connector *connector,
3275 struct edid *edid)
3276 {
3277 int i;
3278 uint64_t val_capable;
3279 bool edid_check_required;
3280 struct detailed_timing *timing;
3281 struct detailed_non_pixel *data;
3282 struct detailed_data_monitor_range *range;
3283 struct amdgpu_connector *amdgpu_connector =
3284 to_amdgpu_connector(connector);
3285
3286 struct drm_device *dev = connector->dev;
3287 struct amdgpu_device *adev = dev->dev_private;
3288 edid_check_required = false;
3289 if (!amdgpu_connector->dc_sink) {
3290 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
3291 return;
3292 }
3293 if (!adev->dm.freesync_module)
3294 return;
3295 /*
3296 * if edid non zero restrict freesync only for dp and edp
3297 */
3298 if (edid) {
3299 if (amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
3300 || amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
3301 edid_check_required = is_dp_capable_without_timing_msa(
3302 adev->dm.dc,
3303 amdgpu_connector);
3304 }
3305 }
3306 val_capable = 0;
3307 if (edid_check_required == true && (edid->version > 1 ||
3308 (edid->version == 1 && edid->revision > 1))) {
3309 for (i = 0; i < 4; i++) {
3310
3311 timing = &edid->detailed_timings[i];
3312 data = &timing->data.other_data;
3313 range = &data->data.range;
3314 /*
3315 * Check if monitor has continuous frequency mode
3316 */
3317 if (data->type != EDID_DETAIL_MONITOR_RANGE)
3318 continue;
3319 /*
3320 * Check for flag range limits only. If flag == 1 then
3321 * no additional timing information provided.
3322 * Default GTF, GTF Secondary curve and CVT are not
3323 * supported
3324 */
3325 if (range->flags != 1)
3326 continue;
3327
3328 amdgpu_connector->min_vfreq = range->min_vfreq;
3329 amdgpu_connector->max_vfreq = range->max_vfreq;
3330 amdgpu_connector->pixel_clock_mhz =
3331 range->pixel_clock_mhz * 10;
3332 break;
3333 }
3334
3335 if (amdgpu_connector->max_vfreq -
3336 amdgpu_connector->min_vfreq > 10) {
3337 amdgpu_connector->caps.supported = true;
3338 amdgpu_connector->caps.min_refresh_in_micro_hz =
3339 amdgpu_connector->min_vfreq * 1000000;
3340 amdgpu_connector->caps.max_refresh_in_micro_hz =
3341 amdgpu_connector->max_vfreq * 1000000;
3342 val_capable = 1;
3343 }
3344 }
3345
3346 /*
3347 * TODO figure out how to notify user-mode or DRM of freesync caps
3348 * once we figure out how to deal with freesync in an upstreamable
3349 * fashion
3350 */
3351
3352 }
3353
3354 void amdgpu_dm_remove_sink_from_freesync_module(
3355 struct drm_connector *connector)
3356 {
3357 /*
3358 * TODO fill in once we figure out how to deal with freesync in
3359 * an upstreamable fashion
3360 */
3361 }
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