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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm_types.c
1 /*
2 * Copyright 2012-13 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/types.h>
27 #include <linux/version.h>
28
29 #include <drm/drmP.h>
30 #include <drm/drm_atomic_helper.h>
31 #include <drm/drm_fb_helper.h>
32 #include <drm/drm_atomic.h>
33 #include <drm/drm_edid.h>
34
35 #include "amdgpu.h"
36 #include "amdgpu_pm.h"
37 #include "dm_services_types.h"
38
39 // We need to #undef FRAME_SIZE and DEPRECATED because they conflict
40 // with ptrace-abi.h's #define's of them.
41 #undef FRAME_SIZE
42 #undef DEPRECATED
43
44 #include "dc.h"
45
46 #include "amdgpu_dm_types.h"
47 #include "amdgpu_dm_mst_types.h"
48
49 #include "modules/inc/mod_freesync.h"
50
51 struct dm_connector_state {
52 struct drm_connector_state base;
53
54 enum amdgpu_rmx_type scaling;
55 uint8_t underscan_vborder;
56 uint8_t underscan_hborder;
57 bool underscan_enable;
58 };
59
60 #define to_dm_connector_state(x)\
61 container_of((x), struct dm_connector_state, base)
62
63
64 void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
65 {
66 drm_encoder_cleanup(encoder);
67 kfree(encoder);
68 }
69
70 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
71 .destroy = amdgpu_dm_encoder_destroy,
72 };
73
74 static void dm_set_cursor(
75 struct amdgpu_crtc *amdgpu_crtc,
76 uint64_t gpu_addr,
77 uint32_t width,
78 uint32_t height)
79 {
80 struct dc_cursor_attributes attributes;
81 struct dc_cursor_position position;
82 struct drm_crtc *crtc = &amdgpu_crtc->base;
83 int x, y;
84 int xorigin = 0, yorigin = 0;
85
86 amdgpu_crtc->cursor_width = width;
87 amdgpu_crtc->cursor_height = height;
88
89 attributes.address.high_part = upper_32_bits(gpu_addr);
90 attributes.address.low_part = lower_32_bits(gpu_addr);
91 attributes.width = width;
92 attributes.height = height;
93 attributes.x_hot = 0;
94 attributes.y_hot = 0;
95 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
96 attributes.rotation_angle = 0;
97 attributes.attribute_flags.value = 0;
98
99 attributes.pitch = attributes.width;
100
101 x = amdgpu_crtc->cursor_x;
102 y = amdgpu_crtc->cursor_y;
103
104 /* avivo cursor are offset into the total surface */
105 x += crtc->primary->state->src_x >> 16;
106 y += crtc->primary->state->src_y >> 16;
107
108 if (x < 0) {
109 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
110 x = 0;
111 }
112 if (y < 0) {
113 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
114 y = 0;
115 }
116
117 position.enable = true;
118 position.x = x;
119 position.y = y;
120
121 position.hot_spot_enable = true;
122 position.x_hotspot = xorigin;
123 position.y_hotspot = yorigin;
124
125 if (!dc_stream_set_cursor_attributes(
126 amdgpu_crtc->stream,
127 &attributes)) {
128 DRM_ERROR("DC failed to set cursor attributes\n");
129 }
130
131 if (!dc_stream_set_cursor_position(
132 amdgpu_crtc->stream,
133 &position)) {
134 DRM_ERROR("DC failed to set cursor position\n");
135 }
136 }
137
138 static int dm_crtc_unpin_cursor_bo_old(
139 struct amdgpu_crtc *amdgpu_crtc)
140 {
141 struct amdgpu_bo *robj;
142 int ret = 0;
143
144 if (NULL != amdgpu_crtc && NULL != amdgpu_crtc->cursor_bo) {
145 robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
146
147 ret = amdgpu_bo_reserve(robj, false);
148
149 if (likely(ret == 0)) {
150 ret = amdgpu_bo_unpin(robj);
151
152 if (unlikely(ret != 0)) {
153 DRM_ERROR(
154 "%s: unpin failed (ret=%d), bo %p\n",
155 __func__,
156 ret,
157 amdgpu_crtc->cursor_bo);
158 }
159
160 amdgpu_bo_unreserve(robj);
161 } else {
162 DRM_ERROR(
163 "%s: reserve failed (ret=%d), bo %p\n",
164 __func__,
165 ret,
166 amdgpu_crtc->cursor_bo);
167 }
168
169 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
170 amdgpu_crtc->cursor_bo = NULL;
171 }
172
173 return ret;
174 }
175
176 static int dm_crtc_pin_cursor_bo_new(
177 struct drm_crtc *crtc,
178 struct drm_file *file_priv,
179 uint32_t handle,
180 struct amdgpu_bo **ret_obj)
181 {
182 struct amdgpu_crtc *amdgpu_crtc;
183 struct amdgpu_bo *robj;
184 struct drm_gem_object *obj;
185 int ret = -EINVAL;
186
187 if (NULL != crtc) {
188 struct drm_device *dev = crtc->dev;
189 struct amdgpu_device *adev = dev->dev_private;
190 uint64_t gpu_addr;
191
192 amdgpu_crtc = to_amdgpu_crtc(crtc);
193
194 obj = drm_gem_object_lookup(file_priv, handle);
195
196 if (!obj) {
197 DRM_ERROR(
198 "Cannot find cursor object %x for crtc %d\n",
199 handle,
200 amdgpu_crtc->crtc_id);
201 goto release;
202 }
203 robj = gem_to_amdgpu_bo(obj);
204
205 ret = amdgpu_bo_reserve(robj, false);
206
207 if (unlikely(ret != 0)) {
208 drm_gem_object_unreference_unlocked(obj);
209 DRM_ERROR("dm_crtc_pin_cursor_bo_new ret %x, handle %x\n",
210 ret, handle);
211 goto release;
212 }
213
214 ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, 0,
215 adev->mc.visible_vram_size,
216 &gpu_addr);
217
218 if (ret == 0) {
219 amdgpu_crtc->cursor_addr = gpu_addr;
220 *ret_obj = robj;
221 }
222 amdgpu_bo_unreserve(robj);
223 if (ret)
224 drm_gem_object_unreference_unlocked(obj);
225
226 }
227 release:
228
229 return ret;
230 }
231
232 static int dm_crtc_cursor_set(
233 struct drm_crtc *crtc,
234 struct drm_file *file_priv,
235 uint32_t handle,
236 uint32_t width,
237 uint32_t height)
238 {
239 struct amdgpu_bo *new_cursor_bo;
240 struct dc_cursor_position position;
241
242 int ret;
243
244 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
245
246 ret = EINVAL;
247 new_cursor_bo = NULL;
248
249 DRM_DEBUG_KMS(
250 "%s: crtc_id=%d with handle %d and size %d to %d, bo_object %p\n",
251 __func__,
252 amdgpu_crtc->crtc_id,
253 handle,
254 width,
255 height,
256 amdgpu_crtc->cursor_bo);
257
258 if (!handle) {
259 /* turn off cursor */
260 position.enable = false;
261 position.x = 0;
262 position.y = 0;
263 position.hot_spot_enable = false;
264
265 if (amdgpu_crtc->stream) {
266 /*set cursor visible false*/
267 dc_stream_set_cursor_position(
268 amdgpu_crtc->stream,
269 &position);
270 }
271 /*unpin old cursor buffer and update cache*/
272 ret = dm_crtc_unpin_cursor_bo_old(amdgpu_crtc);
273 goto release;
274
275 }
276
277 if ((width > amdgpu_crtc->max_cursor_width) ||
278 (height > amdgpu_crtc->max_cursor_height)) {
279 DRM_ERROR(
280 "%s: bad cursor width or height %d x %d\n",
281 __func__,
282 width,
283 height);
284 goto release;
285 }
286 /*try to pin new cursor bo*/
287 ret = dm_crtc_pin_cursor_bo_new(crtc, file_priv, handle, &new_cursor_bo);
288 /*if map not successful then return an error*/
289 if (ret)
290 goto release;
291
292 /*program new cursor bo to hardware*/
293 dm_set_cursor(amdgpu_crtc, amdgpu_crtc->cursor_addr, width, height);
294
295 /*un map old, not used anymore cursor bo ,
296 * return memory and mapping back */
297 dm_crtc_unpin_cursor_bo_old(amdgpu_crtc);
298
299 /*assign new cursor bo to our internal cache*/
300 amdgpu_crtc->cursor_bo = &new_cursor_bo->gem_base;
301
302 release:
303 return ret;
304
305 }
306
307 static int dm_crtc_cursor_move(struct drm_crtc *crtc,
308 int x, int y)
309 {
310 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
311 int xorigin = 0, yorigin = 0;
312 struct dc_cursor_position position;
313
314 amdgpu_crtc->cursor_x = x;
315 amdgpu_crtc->cursor_y = y;
316
317 /* avivo cursor are offset into the total surface */
318 x += crtc->primary->state->src_x >> 16;
319 y += crtc->primary->state->src_y >> 16;
320
321 /*
322 * TODO: for cursor debugging unguard the following
323 */
324 #if 0
325 DRM_DEBUG_KMS(
326 "%s: x %d y %d c->x %d c->y %d\n",
327 __func__,
328 x,
329 y,
330 crtc->x,
331 crtc->y);
332 #endif
333
334 if (x < 0) {
335 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
336 x = 0;
337 }
338 if (y < 0) {
339 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
340 y = 0;
341 }
342
343 position.enable = true;
344 position.x = x;
345 position.y = y;
346
347 position.hot_spot_enable = true;
348 position.x_hotspot = xorigin;
349 position.y_hotspot = yorigin;
350
351 if (amdgpu_crtc->stream) {
352 if (!dc_stream_set_cursor_position(
353 amdgpu_crtc->stream,
354 &position)) {
355 DRM_ERROR("DC failed to set cursor position\n");
356 return -EINVAL;
357 }
358 }
359
360 return 0;
361 }
362
363 static void dm_crtc_cursor_reset(struct drm_crtc *crtc)
364 {
365 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
366
367 DRM_DEBUG_KMS(
368 "%s: with cursor_bo %p\n",
369 __func__,
370 amdgpu_crtc->cursor_bo);
371
372 if (amdgpu_crtc->cursor_bo && amdgpu_crtc->stream) {
373 dm_set_cursor(
374 amdgpu_crtc,
375 amdgpu_crtc->cursor_addr,
376 amdgpu_crtc->cursor_width,
377 amdgpu_crtc->cursor_height);
378 }
379 }
380 static bool fill_rects_from_plane_state(
381 const struct drm_plane_state *state,
382 struct dc_surface *surface)
383 {
384 surface->src_rect.x = state->src_x >> 16;
385 surface->src_rect.y = state->src_y >> 16;
386 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
387 surface->src_rect.width = state->src_w >> 16;
388
389 if (surface->src_rect.width == 0)
390 return false;
391
392 surface->src_rect.height = state->src_h >> 16;
393 if (surface->src_rect.height == 0)
394 return false;
395
396 surface->dst_rect.x = state->crtc_x;
397 surface->dst_rect.y = state->crtc_y;
398
399 if (state->crtc_w == 0)
400 return false;
401
402 surface->dst_rect.width = state->crtc_w;
403
404 if (state->crtc_h == 0)
405 return false;
406
407 surface->dst_rect.height = state->crtc_h;
408
409 surface->clip_rect = surface->dst_rect;
410
411 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
412 case DRM_MODE_ROTATE_0:
413 surface->rotation = ROTATION_ANGLE_0;
414 break;
415 case DRM_MODE_ROTATE_90:
416 surface->rotation = ROTATION_ANGLE_90;
417 break;
418 case DRM_MODE_ROTATE_180:
419 surface->rotation = ROTATION_ANGLE_180;
420 break;
421 case DRM_MODE_ROTATE_270:
422 surface->rotation = ROTATION_ANGLE_270;
423 break;
424 default:
425 surface->rotation = ROTATION_ANGLE_0;
426 break;
427 }
428
429 return true;
430 }
431 static bool get_fb_info(
432 const struct amdgpu_framebuffer *amdgpu_fb,
433 uint64_t *tiling_flags,
434 uint64_t *fb_location)
435 {
436 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
437 int r = amdgpu_bo_reserve(rbo, false);
438 if (unlikely(r != 0)){
439 DRM_ERROR("Unable to reserve buffer\n");
440 return false;
441 }
442
443 if (fb_location)
444 *fb_location = amdgpu_bo_gpu_offset(rbo);
445
446 if (tiling_flags)
447 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
448
449 amdgpu_bo_unreserve(rbo);
450
451 return true;
452 }
453 static void fill_plane_attributes_from_fb(
454 struct amdgpu_device *adev,
455 struct dc_surface *surface,
456 const struct amdgpu_framebuffer *amdgpu_fb, bool addReq)
457 {
458 uint64_t tiling_flags;
459 uint64_t fb_location = 0;
460 const struct drm_framebuffer *fb = &amdgpu_fb->base;
461 struct drm_format_name_buf format_name;
462
463 get_fb_info(
464 amdgpu_fb,
465 &tiling_flags,
466 addReq == true ? &fb_location:NULL);
467
468 surface->address.type = PLN_ADDR_TYPE_GRAPHICS;
469 surface->address.grph.addr.low_part = lower_32_bits(fb_location);
470 surface->address.grph.addr.high_part = upper_32_bits(fb_location);
471
472 switch (fb->format->format) {
473 case DRM_FORMAT_C8:
474 surface->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
475 break;
476 case DRM_FORMAT_RGB565:
477 surface->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
478 break;
479 case DRM_FORMAT_XRGB8888:
480 case DRM_FORMAT_ARGB8888:
481 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
482 break;
483 case DRM_FORMAT_XRGB2101010:
484 case DRM_FORMAT_ARGB2101010:
485 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
486 break;
487 case DRM_FORMAT_XBGR2101010:
488 case DRM_FORMAT_ABGR2101010:
489 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
490 break;
491 default:
492 DRM_ERROR("Unsupported screen format %s\n",
493 drm_get_format_name(fb->format->format, &format_name));
494 return;
495 }
496
497 memset(&surface->tiling_info, 0, sizeof(surface->tiling_info));
498
499 /* Fill GFX params */
500 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1)
501 {
502 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
503
504 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
505 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
506 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
507 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
508 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
509
510 /* XXX fix me for VI */
511 surface->tiling_info.gfx8.num_banks = num_banks;
512 surface->tiling_info.gfx8.array_mode =
513 DC_ARRAY_2D_TILED_THIN1;
514 surface->tiling_info.gfx8.tile_split = tile_split;
515 surface->tiling_info.gfx8.bank_width = bankw;
516 surface->tiling_info.gfx8.bank_height = bankh;
517 surface->tiling_info.gfx8.tile_aspect = mtaspect;
518 surface->tiling_info.gfx8.tile_mode =
519 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
520 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
521 == DC_ARRAY_1D_TILED_THIN1) {
522 surface->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
523 }
524
525 surface->tiling_info.gfx8.pipe_config =
526 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
527
528 if (adev->asic_type == CHIP_VEGA10) {
529 /* Fill GFX9 params */
530 surface->tiling_info.gfx9.num_pipes =
531 adev->gfx.config.gb_addr_config_fields.num_pipes;
532 surface->tiling_info.gfx9.num_banks =
533 adev->gfx.config.gb_addr_config_fields.num_banks;
534 surface->tiling_info.gfx9.pipe_interleave =
535 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
536 surface->tiling_info.gfx9.num_shader_engines =
537 adev->gfx.config.gb_addr_config_fields.num_se;
538 surface->tiling_info.gfx9.max_compressed_frags =
539 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
540 surface->tiling_info.gfx9.num_rb_per_se =
541 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
542 surface->tiling_info.gfx9.swizzle =
543 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
544 surface->tiling_info.gfx9.shaderEnable = 1;
545 }
546
547
548 surface->plane_size.grph.surface_size.x = 0;
549 surface->plane_size.grph.surface_size.y = 0;
550 surface->plane_size.grph.surface_size.width = fb->width;
551 surface->plane_size.grph.surface_size.height = fb->height;
552 surface->plane_size.grph.surface_pitch =
553 fb->pitches[0] / fb->format->cpp[0];
554
555 surface->visible = true;
556 surface->scaling_quality.h_taps_c = 0;
557 surface->scaling_quality.v_taps_c = 0;
558
559 /* TODO: unhardcode */
560 surface->color_space = COLOR_SPACE_SRGB;
561 /* is this needed? is surface zeroed at allocation? */
562 surface->scaling_quality.h_taps = 0;
563 surface->scaling_quality.v_taps = 0;
564 surface->stereo_format = PLANE_STEREO_FORMAT_NONE;
565
566 }
567
568 #define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256
569
570 static void fill_gamma_from_crtc(
571 const struct drm_crtc *crtc,
572 struct dc_surface *dc_surface)
573 {
574 int i;
575 struct dc_gamma *gamma;
576 struct drm_crtc_state *state = crtc->state;
577 struct drm_color_lut *lut = (struct drm_color_lut *) state->gamma_lut->data;
578
579 gamma = dc_create_gamma();
580
581 if (gamma == NULL)
582 return;
583
584 for (i = 0; i < NUM_OF_RAW_GAMMA_RAMP_RGB_256; i++) {
585 gamma->red[i] = lut[i].red;
586 gamma->green[i] = lut[i].green;
587 gamma->blue[i] = lut[i].blue;
588 }
589
590 dc_surface->gamma_correction = gamma;
591 }
592
593 static void fill_plane_attributes(
594 struct amdgpu_device *adev,
595 struct dc_surface *surface,
596 struct drm_plane_state *state, bool addrReq)
597 {
598 const struct amdgpu_framebuffer *amdgpu_fb =
599 to_amdgpu_framebuffer(state->fb);
600 const struct drm_crtc *crtc = state->crtc;
601 struct dc_transfer_func *input_tf;
602
603 fill_rects_from_plane_state(state, surface);
604 fill_plane_attributes_from_fb(
605 crtc->dev->dev_private,
606 surface,
607 amdgpu_fb,
608 addrReq);
609
610 input_tf = dc_create_transfer_func();
611
612 if (input_tf == NULL)
613 return;
614
615 input_tf->type = TF_TYPE_PREDEFINED;
616 input_tf->tf = TRANSFER_FUNCTION_SRGB;
617
618 surface->in_transfer_func = input_tf;
619
620 /* In case of gamma set, update gamma value */
621 if (state->crtc->state->gamma_lut) {
622 fill_gamma_from_crtc(crtc, surface);
623 }
624 }
625
626 /*****************************************************************************/
627
628 struct amdgpu_connector *aconnector_from_drm_crtc_id(
629 const struct drm_crtc *crtc)
630 {
631 struct drm_device *dev = crtc->dev;
632 struct drm_connector *connector;
633 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
634 struct amdgpu_connector *aconnector;
635
636 list_for_each_entry(connector,
637 &dev->mode_config.connector_list, head) {
638
639 aconnector = to_amdgpu_connector(connector);
640
641 if (aconnector->base.state->crtc != &acrtc->base)
642 continue;
643
644 /* Found the connector */
645 return aconnector;
646 }
647
648 /* If we get here, not found. */
649 return NULL;
650 }
651
652 static void update_stream_scaling_settings(
653 const struct drm_display_mode *mode,
654 const struct dm_connector_state *dm_state,
655 const struct dc_stream *stream)
656 {
657 struct amdgpu_device *adev = dm_state->base.crtc->dev->dev_private;
658 enum amdgpu_rmx_type rmx_type;
659
660 struct rect src = { 0 }; /* viewport in composition space*/
661 struct rect dst = { 0 }; /* stream addressable area */
662
663 /* no mode. nothing to be done */
664 if (!mode)
665 return;
666
667 /* Full screen scaling by default */
668 src.width = mode->hdisplay;
669 src.height = mode->vdisplay;
670 dst.width = stream->timing.h_addressable;
671 dst.height = stream->timing.v_addressable;
672
673 rmx_type = dm_state->scaling;
674 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
675 if (src.width * dst.height <
676 src.height * dst.width) {
677 /* height needs less upscaling/more downscaling */
678 dst.width = src.width *
679 dst.height / src.height;
680 } else {
681 /* width needs less upscaling/more downscaling */
682 dst.height = src.height *
683 dst.width / src.width;
684 }
685 } else if (rmx_type == RMX_CENTER) {
686 dst = src;
687 }
688
689 dst.x = (stream->timing.h_addressable - dst.width) / 2;
690 dst.y = (stream->timing.v_addressable - dst.height) / 2;
691
692 if (dm_state->underscan_enable) {
693 dst.x += dm_state->underscan_hborder / 2;
694 dst.y += dm_state->underscan_vborder / 2;
695 dst.width -= dm_state->underscan_hborder;
696 dst.height -= dm_state->underscan_vborder;
697 }
698
699 adev->dm.dc->stream_funcs.stream_update_scaling(adev->dm.dc, stream, &src, &dst);
700
701 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
702 dst.x, dst.y, dst.width, dst.height);
703
704 }
705
706 static void dm_dc_surface_commit(
707 struct dc *dc,
708 struct drm_crtc *crtc)
709 {
710 struct dc_surface *dc_surface;
711 const struct dc_surface *dc_surfaces[1];
712 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
713 const struct dc_stream *dc_stream = acrtc->stream;
714 unsigned long flags;
715
716 spin_lock_irqsave(&crtc->dev->event_lock, flags);
717 if (acrtc->pflip_status != AMDGPU_FLIP_NONE) {
718 DRM_ERROR("dm_dc_surface_commit: acrtc %d, already busy\n", acrtc->crtc_id);
719 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
720 /* In comit tail framework this cannot happen */
721 BUG_ON(0);
722 }
723 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
724
725 if (!dc_stream) {
726 dm_error(
727 "%s: Failed to obtain stream on crtc (%d)!\n",
728 __func__,
729 acrtc->crtc_id);
730 goto fail;
731 }
732
733 dc_surface = dc_create_surface(dc);
734
735 if (!dc_surface) {
736 dm_error(
737 "%s: Failed to create a surface!\n",
738 __func__);
739 goto fail;
740 }
741
742 /* Surface programming */
743 fill_plane_attributes(
744 crtc->dev->dev_private,
745 dc_surface,
746 crtc->primary->state,
747 true);
748
749 dc_surfaces[0] = dc_surface;
750
751 if (false == dc_commit_surfaces_to_stream(
752 dc,
753 dc_surfaces,
754 1,
755 dc_stream)) {
756 dm_error(
757 "%s: Failed to attach surface!\n",
758 __func__);
759 }
760
761 dc_surface_release(dc_surface);
762 fail:
763 return;
764 }
765
766 static enum dc_color_depth convert_color_depth_from_display_info(
767 const struct drm_connector *connector)
768 {
769 uint32_t bpc = connector->display_info.bpc;
770
771 /* Limited color depth to 8bit
772 * TODO: Still need to handle deep color*/
773 if (bpc > 8)
774 bpc = 8;
775
776 switch (bpc) {
777 case 0:
778 /* Temporary Work around, DRM don't parse color depth for
779 * EDID revision before 1.4
780 * TODO: Fix edid parsing
781 */
782 return COLOR_DEPTH_888;
783 case 6:
784 return COLOR_DEPTH_666;
785 case 8:
786 return COLOR_DEPTH_888;
787 case 10:
788 return COLOR_DEPTH_101010;
789 case 12:
790 return COLOR_DEPTH_121212;
791 case 14:
792 return COLOR_DEPTH_141414;
793 case 16:
794 return COLOR_DEPTH_161616;
795 default:
796 return COLOR_DEPTH_UNDEFINED;
797 }
798 }
799
800 static enum dc_aspect_ratio get_aspect_ratio(
801 const struct drm_display_mode *mode_in)
802 {
803 int32_t width = mode_in->crtc_hdisplay * 9;
804 int32_t height = mode_in->crtc_vdisplay * 16;
805 if ((width - height) < 10 && (width - height) > -10)
806 return ASPECT_RATIO_16_9;
807 else
808 return ASPECT_RATIO_4_3;
809 }
810
811 static enum dc_color_space get_output_color_space(
812 const struct dc_crtc_timing *dc_crtc_timing)
813 {
814 enum dc_color_space color_space = COLOR_SPACE_SRGB;
815
816 switch (dc_crtc_timing->pixel_encoding) {
817 case PIXEL_ENCODING_YCBCR422:
818 case PIXEL_ENCODING_YCBCR444:
819 case PIXEL_ENCODING_YCBCR420:
820 {
821 /*
822 * 27030khz is the separation point between HDTV and SDTV
823 * according to HDMI spec, we use YCbCr709 and YCbCr601
824 * respectively
825 */
826 if (dc_crtc_timing->pix_clk_khz > 27030) {
827 if (dc_crtc_timing->flags.Y_ONLY)
828 color_space =
829 COLOR_SPACE_YCBCR709_LIMITED;
830 else
831 color_space = COLOR_SPACE_YCBCR709;
832 } else {
833 if (dc_crtc_timing->flags.Y_ONLY)
834 color_space =
835 COLOR_SPACE_YCBCR601_LIMITED;
836 else
837 color_space = COLOR_SPACE_YCBCR601;
838 }
839
840 }
841 break;
842 case PIXEL_ENCODING_RGB:
843 color_space = COLOR_SPACE_SRGB;
844 break;
845
846 default:
847 WARN_ON(1);
848 break;
849 }
850
851 return color_space;
852 }
853
854 /*****************************************************************************/
855
856 static void fill_stream_properties_from_drm_display_mode(
857 struct dc_stream *stream,
858 const struct drm_display_mode *mode_in,
859 const struct drm_connector *connector)
860 {
861 struct dc_crtc_timing *timing_out = &stream->timing;
862 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
863
864 timing_out->h_border_left = 0;
865 timing_out->h_border_right = 0;
866 timing_out->v_border_top = 0;
867 timing_out->v_border_bottom = 0;
868 /* TODO: un-hardcode */
869
870 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
871 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
872 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
873 else
874 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
875
876 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
877 timing_out->display_color_depth = convert_color_depth_from_display_info(
878 connector);
879 timing_out->scan_type = SCANNING_TYPE_NODATA;
880 timing_out->hdmi_vic = 0;
881 timing_out->vic = drm_match_cea_mode(mode_in);
882
883 timing_out->h_addressable = mode_in->crtc_hdisplay;
884 timing_out->h_total = mode_in->crtc_htotal;
885 timing_out->h_sync_width =
886 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
887 timing_out->h_front_porch =
888 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
889 timing_out->v_total = mode_in->crtc_vtotal;
890 timing_out->v_addressable = mode_in->crtc_vdisplay;
891 timing_out->v_front_porch =
892 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
893 timing_out->v_sync_width =
894 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
895 timing_out->pix_clk_khz = mode_in->crtc_clock;
896 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
897 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
898 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
899 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
900 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
901
902 stream->output_color_space = get_output_color_space(timing_out);
903
904 {
905 struct dc_transfer_func *tf = dc_create_transfer_func();
906 tf->type = TF_TYPE_PREDEFINED;
907 tf->tf = TRANSFER_FUNCTION_SRGB;
908 stream->out_transfer_func = tf;
909 }
910 }
911
912 static void fill_audio_info(
913 struct audio_info *audio_info,
914 const struct drm_connector *drm_connector,
915 const struct dc_sink *dc_sink)
916 {
917 int i = 0;
918 int cea_revision = 0;
919 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
920
921 audio_info->manufacture_id = edid_caps->manufacturer_id;
922 audio_info->product_id = edid_caps->product_id;
923
924 cea_revision = drm_connector->display_info.cea_rev;
925
926 while (i < AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS &&
927 edid_caps->display_name[i]) {
928 audio_info->display_name[i] = edid_caps->display_name[i];
929 i++;
930 }
931
932 if(cea_revision >= 3) {
933 audio_info->mode_count = edid_caps->audio_mode_count;
934
935 for (i = 0; i < audio_info->mode_count; ++i) {
936 audio_info->modes[i].format_code =
937 (enum audio_format_code)
938 (edid_caps->audio_modes[i].format_code);
939 audio_info->modes[i].channel_count =
940 edid_caps->audio_modes[i].channel_count;
941 audio_info->modes[i].sample_rates.all =
942 edid_caps->audio_modes[i].sample_rate;
943 audio_info->modes[i].sample_size =
944 edid_caps->audio_modes[i].sample_size;
945 }
946 }
947
948 audio_info->flags.all = edid_caps->speaker_flags;
949
950 /* TODO: We only check for the progressive mode, check for interlace mode too */
951 if(drm_connector->latency_present[0]) {
952 audio_info->video_latency = drm_connector->video_latency[0];
953 audio_info->audio_latency = drm_connector->audio_latency[0];
954 }
955
956 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
957
958 }
959
960 static void copy_crtc_timing_for_drm_display_mode(
961 const struct drm_display_mode *src_mode,
962 struct drm_display_mode *dst_mode)
963 {
964 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
965 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
966 dst_mode->crtc_clock = src_mode->crtc_clock;
967 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
968 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
969 dst_mode->crtc_hsync_start= src_mode->crtc_hsync_start;
970 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
971 dst_mode->crtc_htotal = src_mode->crtc_htotal;
972 dst_mode->crtc_hskew = src_mode->crtc_hskew;
973 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
974 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
975 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
976 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
977 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
978 }
979
980 static void decide_crtc_timing_for_drm_display_mode(
981 struct drm_display_mode *drm_mode,
982 const struct drm_display_mode *native_mode,
983 bool scale_enabled)
984 {
985 if (scale_enabled) {
986 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
987 } else if (native_mode->clock == drm_mode->clock &&
988 native_mode->htotal == drm_mode->htotal &&
989 native_mode->vtotal == drm_mode->vtotal) {
990 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
991 } else {
992 /* no scaling nor amdgpu inserted, no need to patch */
993 }
994 }
995
996 static struct dc_stream *create_stream_for_sink(
997 struct amdgpu_connector *aconnector,
998 const struct drm_display_mode *drm_mode,
999 const struct dm_connector_state *dm_state)
1000 {
1001 struct drm_display_mode *preferred_mode = NULL;
1002 const struct drm_connector *drm_connector;
1003 struct dc_stream *stream = NULL;
1004 struct drm_display_mode mode = *drm_mode;
1005 bool native_mode_found = false;
1006
1007 if (NULL == aconnector) {
1008 DRM_ERROR("aconnector is NULL!\n");
1009 goto drm_connector_null;
1010 }
1011
1012 if (NULL == dm_state) {
1013 DRM_ERROR("dm_state is NULL!\n");
1014 goto dm_state_null;
1015 }
1016
1017 drm_connector = &aconnector->base;
1018 stream = dc_create_stream_for_sink(aconnector->dc_sink);
1019
1020 if (NULL == stream) {
1021 DRM_ERROR("Failed to create stream for sink!\n");
1022 goto stream_create_fail;
1023 }
1024
1025 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
1026 /* Search for preferred mode */
1027 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
1028 native_mode_found = true;
1029 break;
1030 }
1031 }
1032 if (!native_mode_found)
1033 preferred_mode = list_first_entry_or_null(
1034 &aconnector->base.modes,
1035 struct drm_display_mode,
1036 head);
1037
1038 if (NULL == preferred_mode) {
1039 /* This may not be an error, the use case is when we we have no
1040 * usermode calls to reset and set mode upon hotplug. In this
1041 * case, we call set mode ourselves to restore the previous mode
1042 * and the modelist may not be filled in in time.
1043 */
1044 DRM_INFO("No preferred mode found\n");
1045 } else {
1046 decide_crtc_timing_for_drm_display_mode(
1047 &mode, preferred_mode,
1048 dm_state->scaling != RMX_OFF);
1049 }
1050
1051 fill_stream_properties_from_drm_display_mode(stream,
1052 &mode, &aconnector->base);
1053 update_stream_scaling_settings(&mode, dm_state, stream);
1054
1055 fill_audio_info(
1056 &stream->audio_info,
1057 drm_connector,
1058 aconnector->dc_sink);
1059
1060 stream_create_fail:
1061 dm_state_null:
1062 drm_connector_null:
1063 return stream;
1064 }
1065
1066 void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
1067 {
1068 drm_crtc_cleanup(crtc);
1069 kfree(crtc);
1070 }
1071
1072 /* Implemented only the options currently availible for the driver */
1073 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
1074 .reset = drm_atomic_helper_crtc_reset,
1075 .cursor_set = dm_crtc_cursor_set,
1076 .cursor_move = dm_crtc_cursor_move,
1077 .destroy = amdgpu_dm_crtc_destroy,
1078 .gamma_set = drm_atomic_helper_legacy_gamma_set,
1079 .set_config = drm_atomic_helper_set_config,
1080 .page_flip = drm_atomic_helper_page_flip,
1081 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1082 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1083 };
1084
1085 static enum drm_connector_status
1086 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
1087 {
1088 bool connected;
1089 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1090
1091 /* Notes:
1092 * 1. This interface is NOT called in context of HPD irq.
1093 * 2. This interface *is called* in context of user-mode ioctl. Which
1094 * makes it a bad place for *any* MST-related activit. */
1095
1096 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1097 connected = (aconnector->dc_sink != NULL);
1098 else
1099 connected = (aconnector->base.force == DRM_FORCE_ON);
1100
1101 return (connected ? connector_status_connected :
1102 connector_status_disconnected);
1103 }
1104
1105 int amdgpu_dm_connector_atomic_set_property(
1106 struct drm_connector *connector,
1107 struct drm_connector_state *connector_state,
1108 struct drm_property *property,
1109 uint64_t val)
1110 {
1111 struct drm_device *dev = connector->dev;
1112 struct amdgpu_device *adev = dev->dev_private;
1113 struct dm_connector_state *dm_old_state =
1114 to_dm_connector_state(connector->state);
1115 struct dm_connector_state *dm_new_state =
1116 to_dm_connector_state(connector_state);
1117
1118 struct drm_crtc_state *new_crtc_state;
1119 struct drm_crtc *crtc;
1120 int i;
1121 int ret = -EINVAL;
1122
1123 if (property == dev->mode_config.scaling_mode_property) {
1124 enum amdgpu_rmx_type rmx_type;
1125
1126 switch (val) {
1127 case DRM_MODE_SCALE_CENTER:
1128 rmx_type = RMX_CENTER;
1129 break;
1130 case DRM_MODE_SCALE_ASPECT:
1131 rmx_type = RMX_ASPECT;
1132 break;
1133 case DRM_MODE_SCALE_FULLSCREEN:
1134 rmx_type = RMX_FULL;
1135 break;
1136 case DRM_MODE_SCALE_NONE:
1137 default:
1138 rmx_type = RMX_OFF;
1139 break;
1140 }
1141
1142 if (dm_old_state->scaling == rmx_type)
1143 return 0;
1144
1145 dm_new_state->scaling = rmx_type;
1146 ret = 0;
1147 } else if (property == adev->mode_info.underscan_hborder_property) {
1148 dm_new_state->underscan_hborder = val;
1149 ret = 0;
1150 } else if (property == adev->mode_info.underscan_vborder_property) {
1151 dm_new_state->underscan_vborder = val;
1152 ret = 0;
1153 } else if (property == adev->mode_info.underscan_property) {
1154 dm_new_state->underscan_enable = val;
1155 ret = 0;
1156 }
1157
1158 for_each_crtc_in_state(
1159 connector_state->state,
1160 crtc,
1161 new_crtc_state,
1162 i) {
1163
1164 if (crtc == connector_state->crtc) {
1165 struct drm_plane_state *plane_state;
1166
1167 /*
1168 * Bit of magic done here. We need to ensure
1169 * that planes get update after mode is set.
1170 * So, we need to add primary plane to state,
1171 * and this way atomic_update would be called
1172 * for it
1173 */
1174 plane_state =
1175 drm_atomic_get_plane_state(
1176 connector_state->state,
1177 crtc->primary);
1178
1179 if (!plane_state)
1180 return -EINVAL;
1181 }
1182 }
1183
1184 return ret;
1185 }
1186
1187 void amdgpu_dm_connector_destroy(struct drm_connector *connector)
1188 {
1189 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1190 const struct dc_link *link = aconnector->dc_link;
1191 struct amdgpu_device *adev = connector->dev->dev_private;
1192 struct amdgpu_display_manager *dm = &adev->dm;
1193 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1194 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1195
1196 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
1197 amdgpu_dm_register_backlight_device(dm);
1198
1199 if (dm->backlight_dev) {
1200 backlight_device_unregister(dm->backlight_dev);
1201 dm->backlight_dev = NULL;
1202 }
1203
1204 }
1205 #endif
1206 drm_connector_unregister(connector);
1207 drm_connector_cleanup(connector);
1208 kfree(connector);
1209 }
1210
1211 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
1212 {
1213 struct dm_connector_state *state =
1214 to_dm_connector_state(connector->state);
1215
1216 kfree(state);
1217
1218 state = kzalloc(sizeof(*state), GFP_KERNEL);
1219
1220 if (state) {
1221 state->scaling = RMX_OFF;
1222 state->underscan_enable = false;
1223 state->underscan_hborder = 0;
1224 state->underscan_vborder = 0;
1225
1226 connector->state = &state->base;
1227 connector->state->connector = connector;
1228 }
1229 }
1230
1231 struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state(
1232 struct drm_connector *connector)
1233 {
1234 struct dm_connector_state *state =
1235 to_dm_connector_state(connector->state);
1236
1237 struct dm_connector_state *new_state =
1238 kmemdup(state, sizeof(*state), GFP_KERNEL);
1239
1240 if (new_state) {
1241 __drm_atomic_helper_connector_duplicate_state(connector,
1242 &new_state->base);
1243 return &new_state->base;
1244 }
1245
1246 return NULL;
1247 }
1248
1249
1250 /**
1251 * amdgpu_dm_atomic_get_property - fetch connector property value
1252 * @connector: connector to fetch property for
1253 * @state: state containing the property value
1254 * @property: property to look up
1255 * @val: pointer to write property value into
1256 *
1257 * The DRM core does not store shadow copies of properties for
1258 * atomic-capable drivers. This entrypoint is used to fetch
1259 * the current value of a driver-specific connector property.
1260 */
1261 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
1262 const struct drm_connector_state *state,
1263 struct drm_property *property,
1264 uint64_t *val)
1265 {
1266 int i;
1267
1268 /*
1269 * TODO: Get properties from atomic state or objs. Until it's ready,
1270 * continue to look up all property values in the DRM's shadow copy
1271 * in obj->properties->values[].
1272 *
1273 * When the crtc/connector state work matures, this function should
1274 * be updated to read the values out of the state structure instead.
1275 */
1276 for (i = 0; i < connector->base.properties->count; i++) {
1277 if (connector->base.properties->properties[i] == property) {
1278 *val = connector->base.properties->values[i];
1279 return 0;
1280 }
1281 }
1282
1283 return -EINVAL;
1284 }
1285
1286 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
1287 .reset = amdgpu_dm_connector_funcs_reset,
1288 .detect = amdgpu_dm_connector_detect,
1289 .fill_modes = drm_helper_probe_single_connector_modes,
1290 .destroy = amdgpu_dm_connector_destroy,
1291 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
1292 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1293 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
1294 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
1295 };
1296
1297 static struct drm_encoder *best_encoder(struct drm_connector *connector)
1298 {
1299 int enc_id = connector->encoder_ids[0];
1300 struct drm_mode_object *obj;
1301 struct drm_encoder *encoder;
1302
1303 DRM_DEBUG_KMS("Finding the best encoder\n");
1304
1305 /* pick the encoder ids */
1306 if (enc_id) {
1307 obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER);
1308 if (!obj) {
1309 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
1310 return NULL;
1311 }
1312 encoder = obj_to_encoder(obj);
1313 return encoder;
1314 }
1315 DRM_ERROR("No encoder id\n");
1316 return NULL;
1317 }
1318
1319 static int get_modes(struct drm_connector *connector)
1320 {
1321 return amdgpu_dm_connector_get_modes(connector);
1322 }
1323
1324 static void create_eml_sink(struct amdgpu_connector *aconnector)
1325 {
1326 struct dc_sink_init_data init_params = {
1327 .link = aconnector->dc_link,
1328 .sink_signal = SIGNAL_TYPE_VIRTUAL
1329 };
1330 struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
1331
1332 if (!aconnector->base.edid_blob_ptr ||
1333 !aconnector->base.edid_blob_ptr->data) {
1334 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
1335 aconnector->base.name);
1336
1337 aconnector->base.force = DRM_FORCE_OFF;
1338 aconnector->base.override_edid = false;
1339 return;
1340 }
1341
1342 aconnector->edid = edid;
1343
1344 aconnector->dc_em_sink = dc_link_add_remote_sink(
1345 aconnector->dc_link,
1346 (uint8_t *)edid,
1347 (edid->extensions + 1) * EDID_LENGTH,
1348 &init_params);
1349
1350 if (aconnector->base.force
1351 == DRM_FORCE_ON)
1352 aconnector->dc_sink = aconnector->dc_link->local_sink ?
1353 aconnector->dc_link->local_sink :
1354 aconnector->dc_em_sink;
1355 }
1356
1357 static void handle_edid_mgmt(struct amdgpu_connector *aconnector)
1358 {
1359 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
1360
1361 /* In case of headless boot with force on for DP managed connector
1362 * Those settings have to be != 0 to get initial modeset
1363 */
1364 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
1365 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
1366 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
1367 }
1368
1369
1370 aconnector->base.override_edid = true;
1371 create_eml_sink(aconnector);
1372 }
1373
1374 int amdgpu_dm_connector_mode_valid(
1375 struct drm_connector *connector,
1376 struct drm_display_mode *mode)
1377 {
1378 int result = MODE_ERROR;
1379 const struct dc_sink *dc_sink;
1380 struct amdgpu_device *adev = connector->dev->dev_private;
1381 struct dc_validation_set val_set = { 0 };
1382 /* TODO: Unhardcode stream count */
1383 struct dc_stream *stream;
1384 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1385
1386 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1387 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
1388 return result;
1389
1390 /* Only run this the first time mode_valid is called to initilialize
1391 * EDID mgmt
1392 */
1393 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
1394 !aconnector->dc_em_sink)
1395 handle_edid_mgmt(aconnector);
1396
1397 dc_sink = to_amdgpu_connector(connector)->dc_sink;
1398
1399 if (NULL == dc_sink) {
1400 DRM_ERROR("dc_sink is NULL!\n");
1401 goto null_sink;
1402 }
1403
1404 stream = dc_create_stream_for_sink(dc_sink);
1405 if (NULL == stream) {
1406 DRM_ERROR("Failed to create stream for sink!\n");
1407 goto stream_create_fail;
1408 }
1409
1410 drm_mode_set_crtcinfo(mode, 0);
1411 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
1412
1413 val_set.stream = stream;
1414 val_set.surface_count = 0;
1415 stream->src.width = mode->hdisplay;
1416 stream->src.height = mode->vdisplay;
1417 stream->dst = stream->src;
1418
1419 if (dc_validate_resources(adev->dm.dc, &val_set, 1))
1420 result = MODE_OK;
1421
1422 dc_stream_release(stream);
1423
1424 stream_create_fail:
1425 null_sink:
1426 /* TODO: error handling*/
1427 return result;
1428 }
1429
1430 static const struct drm_connector_helper_funcs
1431 amdgpu_dm_connector_helper_funcs = {
1432 /*
1433 * If hotplug a second bigger display in FB Con mode, bigger resolution
1434 * modes will be filtered by drm_mode_validate_size(), and those modes
1435 * is missing after user start lightdm. So we need to renew modes list.
1436 * in get_modes call back, not just return the modes count
1437 */
1438 .get_modes = get_modes,
1439 .mode_valid = amdgpu_dm_connector_mode_valid,
1440 .best_encoder = best_encoder
1441 };
1442
1443 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
1444 {
1445 }
1446
1447 static int dm_crtc_helper_atomic_check(
1448 struct drm_crtc *crtc,
1449 struct drm_crtc_state *state)
1450 {
1451 return 0;
1452 }
1453
1454 static bool dm_crtc_helper_mode_fixup(
1455 struct drm_crtc *crtc,
1456 const struct drm_display_mode *mode,
1457 struct drm_display_mode *adjusted_mode)
1458 {
1459 return true;
1460 }
1461
1462 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
1463 .disable = dm_crtc_helper_disable,
1464 .atomic_check = dm_crtc_helper_atomic_check,
1465 .mode_fixup = dm_crtc_helper_mode_fixup
1466 };
1467
1468 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
1469 {
1470
1471 }
1472
1473 static int dm_encoder_helper_atomic_check(
1474 struct drm_encoder *encoder,
1475 struct drm_crtc_state *crtc_state,
1476 struct drm_connector_state *conn_state)
1477 {
1478 return 0;
1479 }
1480
1481 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
1482 .disable = dm_encoder_helper_disable,
1483 .atomic_check = dm_encoder_helper_atomic_check
1484 };
1485
1486 static void dm_drm_plane_reset(struct drm_plane *plane)
1487 {
1488 struct amdgpu_drm_plane_state *amdgpu_state;
1489
1490 if (plane->state) {
1491 amdgpu_state = to_amdgpu_plane_state(plane->state);
1492 if (amdgpu_state->base.fb)
1493 drm_framebuffer_unreference(amdgpu_state->base.fb);
1494 kfree(amdgpu_state);
1495 plane->state = NULL;
1496 }
1497
1498 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
1499 if (amdgpu_state) {
1500 plane->state = &amdgpu_state->base;
1501 plane->state->plane = plane;
1502 }
1503 }
1504
1505 static struct drm_plane_state *
1506 dm_drm_plane_duplicate_state(struct drm_plane *plane)
1507 {
1508 struct amdgpu_drm_plane_state *amdgpu_state;
1509 struct amdgpu_drm_plane_state *copy;
1510
1511 amdgpu_state = to_amdgpu_plane_state(plane->state);
1512 copy = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
1513 if (!copy)
1514 return NULL;
1515
1516 __drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
1517 return &copy->base;
1518 }
1519
1520 static void dm_drm_plane_destroy_state(struct drm_plane *plane,
1521 struct drm_plane_state *old_state)
1522 {
1523 struct amdgpu_drm_plane_state *old_amdgpu_state =
1524 to_amdgpu_plane_state(old_state);
1525 __drm_atomic_helper_plane_destroy_state(old_state);
1526 kfree(old_amdgpu_state);
1527 }
1528
1529 static const struct drm_plane_funcs dm_plane_funcs = {
1530 .update_plane = drm_atomic_helper_update_plane,
1531 .disable_plane = drm_atomic_helper_disable_plane,
1532 .destroy = drm_plane_cleanup,
1533 .reset = dm_drm_plane_reset,
1534 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
1535 .atomic_destroy_state = dm_drm_plane_destroy_state,
1536 };
1537
1538 static int dm_plane_helper_prepare_fb(
1539 struct drm_plane *plane,
1540 struct drm_plane_state *new_state)
1541 {
1542 struct amdgpu_framebuffer *afb;
1543 struct drm_gem_object *obj;
1544 struct amdgpu_bo *rbo;
1545 int r;
1546
1547 if (!new_state->fb) {
1548 DRM_DEBUG_KMS("No FB bound\n");
1549 return 0;
1550 }
1551
1552 afb = to_amdgpu_framebuffer(new_state->fb);
1553
1554 obj = afb->obj;
1555 rbo = gem_to_amdgpu_bo(obj);
1556 r = amdgpu_bo_reserve(rbo, false);
1557 if (unlikely(r != 0))
1558 return r;
1559
1560 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
1561
1562 amdgpu_bo_unreserve(rbo);
1563
1564 if (unlikely(r != 0)) {
1565 DRM_ERROR("Failed to pin framebuffer\n");
1566 return r;
1567 }
1568
1569 amdgpu_bo_ref(rbo);
1570 return 0;
1571 }
1572
1573 static void dm_plane_helper_cleanup_fb(
1574 struct drm_plane *plane,
1575 struct drm_plane_state *old_state)
1576 {
1577 struct amdgpu_bo *rbo;
1578 struct amdgpu_framebuffer *afb;
1579 int r;
1580
1581 if (!old_state->fb)
1582 return;
1583
1584 afb = to_amdgpu_framebuffer(old_state->fb);
1585 rbo = gem_to_amdgpu_bo(afb->obj);
1586 r = amdgpu_bo_reserve(rbo, false);
1587 if (unlikely(r)) {
1588 DRM_ERROR("failed to reserve rbo before unpin\n");
1589 return;
1590 } else {
1591 amdgpu_bo_unpin(rbo);
1592 amdgpu_bo_unreserve(rbo);
1593 amdgpu_bo_unref(&rbo);
1594 }
1595
1596 afb->address = 0;
1597 }
1598
1599 int dm_create_validation_set_for_connector(struct drm_connector *connector,
1600 struct drm_display_mode *mode, struct dc_validation_set *val_set)
1601 {
1602 int result = MODE_ERROR;
1603 const struct dc_sink *dc_sink =
1604 to_amdgpu_connector(connector)->dc_sink;
1605 /* TODO: Unhardcode stream count */
1606 struct dc_stream *stream;
1607
1608 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1609 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
1610 return result;
1611
1612 if (NULL == dc_sink) {
1613 DRM_ERROR("dc_sink is NULL!\n");
1614 return result;
1615 }
1616
1617 stream = dc_create_stream_for_sink(dc_sink);
1618
1619 if (NULL == stream) {
1620 DRM_ERROR("Failed to create stream for sink!\n");
1621 return result;
1622 }
1623
1624 drm_mode_set_crtcinfo(mode, 0);
1625
1626 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
1627
1628 val_set->stream = stream;
1629
1630 stream->src.width = mode->hdisplay;
1631 stream->src.height = mode->vdisplay;
1632 stream->dst = stream->src;
1633
1634 return MODE_OK;
1635 }
1636
1637 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
1638 .prepare_fb = dm_plane_helper_prepare_fb,
1639 .cleanup_fb = dm_plane_helper_cleanup_fb,
1640 };
1641
1642 /*
1643 * TODO: these are currently initialized to rgb formats only.
1644 * For future use cases we should either initialize them dynamically based on
1645 * plane capabilities, or initialize this array to all formats, so internal drm
1646 * check will succeed, and let DC to implement proper check
1647 */
1648 static uint32_t rgb_formats[] = {
1649 DRM_FORMAT_XRGB4444,
1650 DRM_FORMAT_ARGB4444,
1651 DRM_FORMAT_RGBA4444,
1652 DRM_FORMAT_ARGB1555,
1653 DRM_FORMAT_RGB565,
1654 DRM_FORMAT_RGB888,
1655 DRM_FORMAT_XRGB8888,
1656 DRM_FORMAT_ARGB8888,
1657 DRM_FORMAT_RGBA8888,
1658 DRM_FORMAT_XRGB2101010,
1659 DRM_FORMAT_XBGR2101010,
1660 DRM_FORMAT_ARGB2101010,
1661 DRM_FORMAT_ABGR2101010,
1662 };
1663
1664 static uint32_t yuv_formats[] = {
1665 DRM_FORMAT_YUYV,
1666 DRM_FORMAT_YVYU,
1667 DRM_FORMAT_UYVY,
1668 DRM_FORMAT_VYUY,
1669 };
1670
1671 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
1672 struct amdgpu_plane *aplane,
1673 unsigned long possible_crtcs)
1674 {
1675 int res = -EPERM;
1676
1677 switch (aplane->plane_type) {
1678 case DRM_PLANE_TYPE_PRIMARY:
1679 aplane->base.format_default = true;
1680
1681 res = drm_universal_plane_init(
1682 dm->adev->ddev,
1683 &aplane->base,
1684 possible_crtcs,
1685 &dm_plane_funcs,
1686 rgb_formats,
1687 ARRAY_SIZE(rgb_formats),
1688 NULL, aplane->plane_type, NULL);
1689 break;
1690 case DRM_PLANE_TYPE_OVERLAY:
1691 res = drm_universal_plane_init(
1692 dm->adev->ddev,
1693 &aplane->base,
1694 possible_crtcs,
1695 &dm_plane_funcs,
1696 yuv_formats,
1697 ARRAY_SIZE(yuv_formats),
1698 NULL, aplane->plane_type, NULL);
1699 break;
1700 case DRM_PLANE_TYPE_CURSOR:
1701 DRM_ERROR("KMS: Cursor plane not implemented.");
1702 break;
1703 }
1704
1705 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
1706
1707 return res;
1708 }
1709
1710 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
1711 struct drm_plane *plane,
1712 uint32_t crtc_index)
1713 {
1714 struct amdgpu_crtc *acrtc;
1715 int res = -ENOMEM;
1716
1717 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
1718 if (!acrtc)
1719 goto fail;
1720
1721 res = drm_crtc_init_with_planes(
1722 dm->ddev,
1723 &acrtc->base,
1724 plane,
1725 NULL,
1726 &amdgpu_dm_crtc_funcs, NULL);
1727
1728 if (res)
1729 goto fail;
1730
1731 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
1732
1733 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
1734 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
1735
1736 acrtc->crtc_id = crtc_index;
1737 acrtc->base.enabled = false;
1738
1739 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
1740 drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
1741
1742 return 0;
1743 fail:
1744 kfree(acrtc);
1745 acrtc->crtc_id = -1;
1746 return res;
1747 }
1748
1749 static int to_drm_connector_type(enum signal_type st)
1750 {
1751 switch (st) {
1752 case SIGNAL_TYPE_HDMI_TYPE_A:
1753 return DRM_MODE_CONNECTOR_HDMIA;
1754 case SIGNAL_TYPE_EDP:
1755 return DRM_MODE_CONNECTOR_eDP;
1756 case SIGNAL_TYPE_RGB:
1757 return DRM_MODE_CONNECTOR_VGA;
1758 case SIGNAL_TYPE_DISPLAY_PORT:
1759 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1760 return DRM_MODE_CONNECTOR_DisplayPort;
1761 case SIGNAL_TYPE_DVI_DUAL_LINK:
1762 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1763 return DRM_MODE_CONNECTOR_DVID;
1764 case SIGNAL_TYPE_VIRTUAL:
1765 return DRM_MODE_CONNECTOR_VIRTUAL;
1766
1767 default:
1768 return DRM_MODE_CONNECTOR_Unknown;
1769 }
1770 }
1771
1772 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
1773 {
1774 const struct drm_connector_helper_funcs *helper =
1775 connector->helper_private;
1776 struct drm_encoder *encoder;
1777 struct amdgpu_encoder *amdgpu_encoder;
1778
1779 encoder = helper->best_encoder(connector);
1780
1781 if (encoder == NULL)
1782 return;
1783
1784 amdgpu_encoder = to_amdgpu_encoder(encoder);
1785
1786 amdgpu_encoder->native_mode.clock = 0;
1787
1788 if (!list_empty(&connector->probed_modes)) {
1789 struct drm_display_mode *preferred_mode = NULL;
1790 list_for_each_entry(preferred_mode,
1791 &connector->probed_modes,
1792 head) {
1793 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
1794 amdgpu_encoder->native_mode = *preferred_mode;
1795 }
1796 break;
1797 }
1798
1799 }
1800 }
1801
1802 static struct drm_display_mode *amdgpu_dm_create_common_mode(
1803 struct drm_encoder *encoder, char *name,
1804 int hdisplay, int vdisplay)
1805 {
1806 struct drm_device *dev = encoder->dev;
1807 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1808 struct drm_display_mode *mode = NULL;
1809 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1810
1811 mode = drm_mode_duplicate(dev, native_mode);
1812
1813 if(mode == NULL)
1814 return NULL;
1815
1816 mode->hdisplay = hdisplay;
1817 mode->vdisplay = vdisplay;
1818 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1819 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
1820
1821 return mode;
1822
1823 }
1824
1825 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
1826 struct drm_connector *connector)
1827 {
1828 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1829 struct drm_display_mode *mode = NULL;
1830 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1831 struct amdgpu_connector *amdgpu_connector =
1832 to_amdgpu_connector(connector);
1833 int i;
1834 int n;
1835 struct mode_size {
1836 char name[DRM_DISPLAY_MODE_LEN];
1837 int w;
1838 int h;
1839 }common_modes[] = {
1840 { "640x480", 640, 480},
1841 { "800x600", 800, 600},
1842 { "1024x768", 1024, 768},
1843 { "1280x720", 1280, 720},
1844 { "1280x800", 1280, 800},
1845 {"1280x1024", 1280, 1024},
1846 { "1440x900", 1440, 900},
1847 {"1680x1050", 1680, 1050},
1848 {"1600x1200", 1600, 1200},
1849 {"1920x1080", 1920, 1080},
1850 {"1920x1200", 1920, 1200}
1851 };
1852
1853 n = sizeof(common_modes) / sizeof(common_modes[0]);
1854
1855 for (i = 0; i < n; i++) {
1856 struct drm_display_mode *curmode = NULL;
1857 bool mode_existed = false;
1858
1859 if (common_modes[i].w > native_mode->hdisplay ||
1860 common_modes[i].h > native_mode->vdisplay ||
1861 (common_modes[i].w == native_mode->hdisplay &&
1862 common_modes[i].h == native_mode->vdisplay))
1863 continue;
1864
1865 list_for_each_entry(curmode, &connector->probed_modes, head) {
1866 if (common_modes[i].w == curmode->hdisplay &&
1867 common_modes[i].h == curmode->vdisplay) {
1868 mode_existed = true;
1869 break;
1870 }
1871 }
1872
1873 if (mode_existed)
1874 continue;
1875
1876 mode = amdgpu_dm_create_common_mode(encoder,
1877 common_modes[i].name, common_modes[i].w,
1878 common_modes[i].h);
1879 drm_mode_probed_add(connector, mode);
1880 amdgpu_connector->num_modes++;
1881 }
1882 }
1883
1884 static void amdgpu_dm_connector_ddc_get_modes(
1885 struct drm_connector *connector,
1886 struct edid *edid)
1887 {
1888 struct amdgpu_connector *amdgpu_connector =
1889 to_amdgpu_connector(connector);
1890
1891 if (edid) {
1892 /* empty probed_modes */
1893 INIT_LIST_HEAD(&connector->probed_modes);
1894 amdgpu_connector->num_modes =
1895 drm_add_edid_modes(connector, edid);
1896
1897 drm_edid_to_eld(connector, edid);
1898
1899 amdgpu_dm_get_native_mode(connector);
1900 } else
1901 amdgpu_connector->num_modes = 0;
1902 }
1903
1904 int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
1905 {
1906 const struct drm_connector_helper_funcs *helper =
1907 connector->helper_private;
1908 struct amdgpu_connector *amdgpu_connector =
1909 to_amdgpu_connector(connector);
1910 struct drm_encoder *encoder;
1911 struct edid *edid = amdgpu_connector->edid;
1912
1913 encoder = helper->best_encoder(connector);
1914
1915 amdgpu_dm_connector_ddc_get_modes(connector, edid);
1916 amdgpu_dm_connector_add_common_modes(encoder, connector);
1917 return amdgpu_connector->num_modes;
1918 }
1919
1920 void amdgpu_dm_connector_init_helper(
1921 struct amdgpu_display_manager *dm,
1922 struct amdgpu_connector *aconnector,
1923 int connector_type,
1924 const struct dc_link *link,
1925 int link_index)
1926 {
1927 struct amdgpu_device *adev = dm->ddev->dev_private;
1928
1929 aconnector->connector_id = link_index;
1930 aconnector->dc_link = link;
1931 aconnector->base.interlace_allowed = false;
1932 aconnector->base.doublescan_allowed = false;
1933 aconnector->base.stereo_allowed = false;
1934 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
1935 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
1936
1937 mutex_init(&aconnector->hpd_lock);
1938
1939 /*configure suport HPD hot plug connector_>polled default value is 0
1940 * which means HPD hot plug not supported*/
1941 switch (connector_type) {
1942 case DRM_MODE_CONNECTOR_HDMIA:
1943 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1944 break;
1945 case DRM_MODE_CONNECTOR_DisplayPort:
1946 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1947 break;
1948 case DRM_MODE_CONNECTOR_DVID:
1949 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1950 break;
1951 default:
1952 break;
1953 }
1954
1955 drm_object_attach_property(&aconnector->base.base,
1956 dm->ddev->mode_config.scaling_mode_property,
1957 DRM_MODE_SCALE_NONE);
1958
1959 drm_object_attach_property(&aconnector->base.base,
1960 adev->mode_info.underscan_property,
1961 UNDERSCAN_OFF);
1962 drm_object_attach_property(&aconnector->base.base,
1963 adev->mode_info.underscan_hborder_property,
1964 0);
1965 drm_object_attach_property(&aconnector->base.base,
1966 adev->mode_info.underscan_vborder_property,
1967 0);
1968
1969 }
1970
1971 int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
1972 struct i2c_msg *msgs, int num)
1973 {
1974 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
1975 struct i2c_command cmd;
1976 int i;
1977 int result = -EIO;
1978
1979 cmd.payloads = kzalloc(num * sizeof(struct i2c_payload), GFP_KERNEL);
1980
1981 if (!cmd.payloads)
1982 return result;
1983
1984 cmd.number_of_payloads = num;
1985 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1986 cmd.speed = 100;
1987
1988 for (i = 0; i < num; i++) {
1989 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
1990 cmd.payloads[i].address = msgs[i].addr;
1991 cmd.payloads[i].length = msgs[i].len;
1992 cmd.payloads[i].data = msgs[i].buf;
1993 }
1994
1995 if (dc_submit_i2c(i2c->dm->dc, i2c->link_index, &cmd))
1996 result = num;
1997
1998 kfree(cmd.payloads);
1999
2000 return result;
2001 }
2002
2003 u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
2004 {
2005 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2006 }
2007
2008 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
2009 .master_xfer = amdgpu_dm_i2c_xfer,
2010 .functionality = amdgpu_dm_i2c_func,
2011 };
2012
2013 struct amdgpu_i2c_adapter *create_i2c(unsigned int link_index, struct amdgpu_display_manager *dm, int *res)
2014 {
2015 struct amdgpu_i2c_adapter *i2c;
2016
2017 i2c = kzalloc(sizeof (struct amdgpu_i2c_adapter), GFP_KERNEL);
2018 i2c->dm = dm;
2019 i2c->base.owner = THIS_MODULE;
2020 i2c->base.class = I2C_CLASS_DDC;
2021 i2c->base.dev.parent = &dm->adev->pdev->dev;
2022 i2c->base.algo = &amdgpu_dm_i2c_algo;
2023 snprintf(i2c->base.name, sizeof (i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
2024 i2c->link_index = link_index;
2025 i2c_set_adapdata(&i2c->base, i2c);
2026
2027 return i2c;
2028 }
2029
2030 /* Note: this function assumes that dc_link_detect() was called for the
2031 * dc_link which will be represented by this aconnector. */
2032 int amdgpu_dm_connector_init(
2033 struct amdgpu_display_manager *dm,
2034 struct amdgpu_connector *aconnector,
2035 uint32_t link_index,
2036 struct amdgpu_encoder *aencoder)
2037 {
2038 int res = 0;
2039 int connector_type;
2040 struct dc *dc = dm->dc;
2041 const struct dc_link *link = dc_get_link_at_index(dc, link_index);
2042 struct amdgpu_i2c_adapter *i2c;
2043 ((struct dc_link *)link)->priv = aconnector;
2044
2045 DRM_DEBUG_KMS("%s()\n", __func__);
2046
2047 i2c = create_i2c(link->link_index, dm, &res);
2048 aconnector->i2c = i2c;
2049 res = i2c_add_adapter(&i2c->base);
2050
2051 if (res) {
2052 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
2053 goto out_free;
2054 }
2055
2056 connector_type = to_drm_connector_type(link->connector_signal);
2057
2058 res = drm_connector_init(
2059 dm->ddev,
2060 &aconnector->base,
2061 &amdgpu_dm_connector_funcs,
2062 connector_type);
2063
2064 if (res) {
2065 DRM_ERROR("connector_init failed\n");
2066 aconnector->connector_id = -1;
2067 goto out_free;
2068 }
2069
2070 drm_connector_helper_add(
2071 &aconnector->base,
2072 &amdgpu_dm_connector_helper_funcs);
2073
2074 amdgpu_dm_connector_init_helper(
2075 dm,
2076 aconnector,
2077 connector_type,
2078 link,
2079 link_index);
2080
2081 drm_mode_connector_attach_encoder(
2082 &aconnector->base, &aencoder->base);
2083
2084 drm_connector_register(&aconnector->base);
2085
2086 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
2087 || connector_type == DRM_MODE_CONNECTOR_eDP)
2088 amdgpu_dm_initialize_dp_connector(dm, aconnector);
2089
2090 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2091 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2092
2093 /* NOTE: this currently will create backlight device even if a panel
2094 * is not connected to the eDP/LVDS connector.
2095 *
2096 * This is less than ideal but we don't have sink information at this
2097 * stage since detection happens after. We can't do detection earlier
2098 * since MST detection needs connectors to be created first.
2099 */
2100 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2101 /* Event if registration failed, we should continue with
2102 * DM initialization because not having a backlight control
2103 * is better then a black screen. */
2104 amdgpu_dm_register_backlight_device(dm);
2105
2106 if (dm->backlight_dev)
2107 dm->backlight_link = link;
2108 }
2109 #endif
2110
2111 out_free:
2112 if (res) {
2113 kfree(i2c);
2114 aconnector->i2c = NULL;
2115 }
2116 return res;
2117 }
2118
2119 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
2120 {
2121 switch (adev->mode_info.num_crtc) {
2122 case 1:
2123 return 0x1;
2124 case 2:
2125 return 0x3;
2126 case 3:
2127 return 0x7;
2128 case 4:
2129 return 0xf;
2130 case 5:
2131 return 0x1f;
2132 case 6:
2133 default:
2134 return 0x3f;
2135 }
2136 }
2137
2138 int amdgpu_dm_encoder_init(
2139 struct drm_device *dev,
2140 struct amdgpu_encoder *aencoder,
2141 uint32_t link_index)
2142 {
2143 struct amdgpu_device *adev = dev->dev_private;
2144
2145 int res = drm_encoder_init(dev,
2146 &aencoder->base,
2147 &amdgpu_dm_encoder_funcs,
2148 DRM_MODE_ENCODER_TMDS,
2149 NULL);
2150
2151 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
2152
2153 if (!res)
2154 aencoder->encoder_id = link_index;
2155 else
2156 aencoder->encoder_id = -1;
2157
2158 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
2159
2160 return res;
2161 }
2162
2163 enum dm_commit_action {
2164 DM_COMMIT_ACTION_NOTHING,
2165 DM_COMMIT_ACTION_RESET,
2166 DM_COMMIT_ACTION_DPMS_ON,
2167 DM_COMMIT_ACTION_DPMS_OFF,
2168 DM_COMMIT_ACTION_SET
2169 };
2170
2171 static enum dm_commit_action get_dm_commit_action(struct drm_crtc_state *state)
2172 {
2173 /* mode changed means either actually mode changed or enabled changed */
2174 /* active changed means dpms changed */
2175
2176 DRM_DEBUG_KMS("crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
2177 state->enable,
2178 state->active,
2179 state->planes_changed,
2180 state->mode_changed,
2181 state->active_changed,
2182 state->connectors_changed);
2183
2184 if (state->mode_changed) {
2185 /* if it is got disabled - call reset mode */
2186 if (!state->enable)
2187 return DM_COMMIT_ACTION_RESET;
2188
2189 if (state->active)
2190 return DM_COMMIT_ACTION_SET;
2191 else
2192 return DM_COMMIT_ACTION_RESET;
2193 } else {
2194 /* ! mode_changed */
2195
2196 /* if it is remain disable - skip it */
2197 if (!state->enable)
2198 return DM_COMMIT_ACTION_NOTHING;
2199
2200 if (state->active && state->connectors_changed)
2201 return DM_COMMIT_ACTION_SET;
2202
2203 if (state->active_changed) {
2204 if (state->active) {
2205 return DM_COMMIT_ACTION_DPMS_ON;
2206 } else {
2207 return DM_COMMIT_ACTION_DPMS_OFF;
2208 }
2209 } else {
2210 /* ! active_changed */
2211 return DM_COMMIT_ACTION_NOTHING;
2212 }
2213 }
2214 }
2215
2216 static void manage_dm_interrupts(
2217 struct amdgpu_device *adev,
2218 struct amdgpu_crtc *acrtc,
2219 bool enable)
2220 {
2221 /*
2222 * this is not correct translation but will work as soon as VBLANK
2223 * constant is the same as PFLIP
2224 */
2225 int irq_type =
2226 amdgpu_crtc_idx_to_irq_type(
2227 adev,
2228 acrtc->crtc_id);
2229
2230 if (enable) {
2231 drm_crtc_vblank_on(&acrtc->base);
2232 amdgpu_irq_get(
2233 adev,
2234 &adev->pageflip_irq,
2235 irq_type);
2236 } else {
2237
2238 amdgpu_irq_put(
2239 adev,
2240 &adev->pageflip_irq,
2241 irq_type);
2242 drm_crtc_vblank_off(&acrtc->base);
2243 }
2244 }
2245
2246 static bool is_scaling_state_different(
2247 const struct dm_connector_state *dm_state,
2248 const struct dm_connector_state *old_dm_state)
2249 {
2250 if (dm_state->scaling != old_dm_state->scaling)
2251 return true;
2252 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
2253 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
2254 return true;
2255 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
2256 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
2257 return true;
2258 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder
2259 || dm_state->underscan_vborder != old_dm_state->underscan_vborder)
2260 return true;
2261 return false;
2262 }
2263
2264 static void remove_stream(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc)
2265 {
2266 /*
2267 * we evade vblanks and pflips on crtc that
2268 * should be changed
2269 */
2270 manage_dm_interrupts(adev, acrtc, false);
2271
2272 /* this is the update mode case */
2273 if (adev->dm.freesync_module)
2274 mod_freesync_remove_stream(adev->dm.freesync_module,
2275 acrtc->stream);
2276
2277 dc_stream_release(acrtc->stream);
2278 acrtc->stream = NULL;
2279 acrtc->otg_inst = -1;
2280 acrtc->enabled = false;
2281 }
2282
2283
2284 /*
2285 * Executes flip
2286 *
2287 * Waits on all BO's fences and for proper vblank count
2288 */
2289 static void amdgpu_dm_do_flip(
2290 struct drm_crtc *crtc,
2291 struct drm_framebuffer *fb,
2292 uint32_t target)
2293 {
2294 unsigned long flags;
2295 uint32_t target_vblank;
2296 int r, vpos, hpos;
2297 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2298 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
2299 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
2300 struct amdgpu_device *adev = crtc->dev->dev_private;
2301 bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
2302
2303
2304 /*TODO This might fail and hence better not used, wait
2305 * explicitly on fences instead
2306 * and in general should be called for
2307 * blocking commit to as per framework helpers
2308 * */
2309 r = amdgpu_bo_reserve(abo, true);
2310 if (unlikely(r != 0)) {
2311 DRM_ERROR("failed to reserve buffer before flip\n");
2312 BUG_ON(0);
2313 }
2314
2315 /* Wait for all fences on this FB */
2316 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
2317 MAX_SCHEDULE_TIMEOUT) < 0);
2318
2319 amdgpu_bo_unreserve(abo);
2320
2321 /* Wait for target vblank */
2322 /* Wait until we're out of the vertical blank period before the one
2323 * targeted by the flip
2324 */
2325 target_vblank = target - drm_crtc_vblank_count(crtc) +
2326 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
2327
2328 while ((acrtc->enabled &&
2329 (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
2330 &vpos, &hpos, NULL, NULL,
2331 &crtc->hwmode)
2332 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
2333 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
2334 (int)(target_vblank -
2335 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
2336 usleep_range(1000, 1100);
2337 }
2338
2339 /* Flip */
2340 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2341 /* update crtc fb */
2342 crtc->primary->fb = fb;
2343
2344 /* Do the flip (mmio) */
2345 adev->mode_info.funcs->page_flip(adev, acrtc->crtc_id, afb->address, async_flip);
2346
2347 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2348 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
2349 acrtc->crtc_id);
2350 }
2351
2352 void amdgpu_dm_atomic_commit_tail(
2353 struct drm_atomic_state *state)
2354 {
2355 struct drm_device *dev = state->dev;
2356 struct amdgpu_device *adev = dev->dev_private;
2357 struct amdgpu_display_manager *dm = &adev->dm;
2358 struct drm_plane *plane;
2359 struct drm_plane_state *old_plane_state;
2360 uint32_t i;
2361 uint32_t commit_streams_count = 0;
2362 uint32_t new_crtcs_count = 0;
2363 struct drm_crtc *crtc;
2364 struct drm_crtc_state *old_crtc_state;
2365 const struct dc_stream *commit_streams[MAX_STREAMS];
2366 struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
2367 const struct dc_stream *new_stream;
2368 unsigned long flags;
2369 bool wait_for_vblank = true;
2370
2371
2372 drm_atomic_helper_update_legacy_modeset_state(dev, state);
2373
2374 /* update changed items */
2375 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
2376 struct amdgpu_crtc *acrtc;
2377 struct amdgpu_connector *aconnector = NULL;
2378 enum dm_commit_action action;
2379 struct drm_crtc_state *new_state = crtc->state;
2380
2381 acrtc = to_amdgpu_crtc(crtc);
2382
2383 aconnector =
2384 amdgpu_dm_find_first_crct_matching_connector(
2385 state,
2386 crtc,
2387 false);
2388
2389 /* handles headless hotplug case, updating new_state and
2390 * aconnector as needed
2391 */
2392
2393 action = get_dm_commit_action(new_state);
2394
2395 switch (action) {
2396 case DM_COMMIT_ACTION_DPMS_ON:
2397 case DM_COMMIT_ACTION_SET: {
2398 struct dm_connector_state *dm_state = NULL;
2399 new_stream = NULL;
2400
2401 if (aconnector)
2402 dm_state = to_dm_connector_state(aconnector->base.state);
2403
2404 new_stream = create_stream_for_sink(
2405 aconnector,
2406 &crtc->state->mode,
2407 dm_state);
2408
2409 DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
2410
2411 if (!new_stream) {
2412 /*
2413 * this could happen because of issues with
2414 * userspace notifications delivery.
2415 * In this case userspace tries to set mode on
2416 * display which is disconnect in fact.
2417 * dc_sink in NULL in this case on aconnector.
2418 * We expect reset mode will come soon.
2419 *
2420 * This can also happen when unplug is done
2421 * during resume sequence ended
2422 *
2423 * In this case, we want to pretend we still
2424 * have a sink to keep the pipe running so that
2425 * hw state is consistent with the sw state
2426 */
2427 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
2428 __func__, acrtc->base.base.id);
2429 break;
2430 }
2431
2432 if (acrtc->stream)
2433 remove_stream(adev, acrtc);
2434
2435 /*
2436 * this loop saves set mode crtcs
2437 * we needed to enable vblanks once all
2438 * resources acquired in dc after dc_commit_streams
2439 */
2440 new_crtcs[new_crtcs_count] = acrtc;
2441 new_crtcs_count++;
2442
2443 acrtc->stream = new_stream;
2444 acrtc->enabled = true;
2445 acrtc->hw_mode = crtc->state->mode;
2446 crtc->hwmode = crtc->state->mode;
2447
2448 break;
2449 }
2450
2451 case DM_COMMIT_ACTION_NOTHING: {
2452 struct dm_connector_state *dm_state = NULL;
2453
2454 if (!aconnector)
2455 break;
2456
2457 dm_state = to_dm_connector_state(aconnector->base.state);
2458
2459 /* Scaling update */
2460 update_stream_scaling_settings(&crtc->state->mode,
2461 dm_state, acrtc->stream);
2462
2463 break;
2464 }
2465 case DM_COMMIT_ACTION_DPMS_OFF:
2466 case DM_COMMIT_ACTION_RESET:
2467 DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
2468 /* i.e. reset mode */
2469 if (acrtc->stream)
2470 remove_stream(adev, acrtc);
2471 break;
2472 } /* switch() */
2473 } /* for_each_crtc_in_state() */
2474
2475 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2476
2477 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2478
2479 if (acrtc->stream) {
2480 commit_streams[commit_streams_count] = acrtc->stream;
2481 ++commit_streams_count;
2482 }
2483 }
2484
2485 /*
2486 * Add streams after required streams from new and replaced streams
2487 * are removed from freesync module
2488 */
2489 if (adev->dm.freesync_module) {
2490 for (i = 0; i < new_crtcs_count; i++) {
2491 struct amdgpu_connector *aconnector = NULL;
2492 new_stream = new_crtcs[i]->stream;
2493 aconnector =
2494 amdgpu_dm_find_first_crct_matching_connector(
2495 state,
2496 &new_crtcs[i]->base,
2497 false);
2498 if (!aconnector) {
2499 DRM_INFO(
2500 "Atomic commit: Failed to find connector for acrtc id:%d "
2501 "skipping freesync init\n",
2502 new_crtcs[i]->crtc_id);
2503 continue;
2504 }
2505
2506 mod_freesync_add_stream(adev->dm.freesync_module,
2507 new_stream, &aconnector->caps);
2508 }
2509 }
2510
2511 /* DC is optimized not to do anything if 'streams' didn't change. */
2512 WARN_ON(!dc_commit_streams(dm->dc, commit_streams, commit_streams_count));
2513
2514 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2515 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2516
2517 if (acrtc->stream != NULL)
2518 acrtc->otg_inst =
2519 dc_stream_get_status(acrtc->stream)->primary_otg_inst;
2520 }
2521
2522 /* update planes when needed */
2523 for_each_plane_in_state(state, plane, old_plane_state, i) {
2524 struct drm_plane_state *plane_state = plane->state;
2525 struct drm_crtc *crtc = plane_state->crtc;
2526 struct drm_framebuffer *fb = plane_state->fb;
2527 struct drm_connector *connector;
2528 struct dm_connector_state *dm_state = NULL;
2529 enum dm_commit_action action;
2530 bool pflip_needed;
2531
2532 if (!fb || !crtc || !crtc->state->active)
2533 continue;
2534
2535 action = get_dm_commit_action(crtc->state);
2536
2537 /* Surfaces are created under two scenarios:
2538 * 1. This commit is not a page flip.
2539 * 2. This commit is a page flip, and streams are created.
2540 */
2541 pflip_needed = !state->allow_modeset;
2542 if (!pflip_needed ||
2543 action == DM_COMMIT_ACTION_DPMS_ON ||
2544 action == DM_COMMIT_ACTION_SET) {
2545 list_for_each_entry(connector,
2546 &dev->mode_config.connector_list, head) {
2547 if (connector->state->crtc == crtc) {
2548 dm_state = to_dm_connector_state(
2549 connector->state);
2550 break;
2551 }
2552 }
2553
2554 /*
2555 * This situation happens in the following case:
2556 * we are about to get set mode for connector who's only
2557 * possible crtc (in encoder crtc mask) is used by
2558 * another connector, that is why it will try to
2559 * re-assing crtcs in order to make configuration
2560 * supported. For our implementation we need to make all
2561 * encoders support all crtcs, then this issue will
2562 * never arise again. But to guard code from this issue
2563 * check is left.
2564 *
2565 * Also it should be needed when used with actual
2566 * drm_atomic_commit ioctl in future
2567 */
2568 if (!dm_state)
2569 continue;
2570
2571 dm_dc_surface_commit(dm->dc, crtc);
2572 }
2573 }
2574
2575 for (i = 0; i < new_crtcs_count; i++) {
2576 /*
2577 * loop to enable interrupts on newly arrived crtc
2578 */
2579 struct amdgpu_crtc *acrtc = new_crtcs[i];
2580
2581 if (adev->dm.freesync_module)
2582 mod_freesync_notify_mode_change(
2583 adev->dm.freesync_module, &acrtc->stream, 1);
2584
2585 manage_dm_interrupts(adev, acrtc, true);
2586 dm_crtc_cursor_reset(&acrtc->base);
2587
2588 }
2589
2590 for_each_plane_in_state(state, plane, old_plane_state, i) {
2591 struct drm_plane_state *plane_state = plane->state;
2592 struct drm_crtc *crtc = plane_state->crtc;
2593 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2594 struct drm_framebuffer *fb = plane_state->fb;
2595 bool pflip_needed;
2596
2597 if (!fb || !crtc || !crtc->state->planes_changed ||
2598 !crtc->state->active)
2599 continue;
2600 pflip_needed = !state->allow_modeset;
2601
2602 if (pflip_needed) {
2603 amdgpu_dm_do_flip(
2604 crtc,
2605 fb,
2606 drm_crtc_vblank_count(crtc));
2607
2608 wait_for_vblank =
2609 acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
2610 false : true;
2611 /*clean up the flags for next usage*/
2612 acrtc->flip_flags = 0;
2613 }
2614 }
2615
2616
2617 /*TODO mark consumed event on all crtc assigned event
2618 * in drm_atomic_helper_setup_commit just to signal completion
2619 */
2620 spin_lock_irqsave(&adev->ddev->event_lock, flags);
2621 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
2622 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2623
2624 if (acrtc->base.state->event &&
2625 acrtc->base.state->event->event.base.type != DRM_EVENT_FLIP_COMPLETE) {
2626 acrtc->event = acrtc->base.state->event;
2627 acrtc->base.state->event = NULL;
2628 }
2629 }
2630 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
2631
2632 /* Signal HW programming completion */
2633 drm_atomic_helper_commit_hw_done(state);
2634
2635 if (wait_for_vblank)
2636 drm_atomic_helper_wait_for_vblanks(dev, state);
2637
2638 /*TODO send vblank event on all crtc assigned event
2639 * in drm_atomic_helper_setup_commit just to signal completion
2640 */
2641 spin_lock_irqsave(&adev->ddev->event_lock, flags);
2642 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
2643 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2644
2645 if (acrtc->event &&
2646 acrtc->event->event.base.type != DRM_EVENT_FLIP_COMPLETE) {
2647 drm_send_event_locked(dev, &acrtc->event->base);
2648 acrtc->event = NULL;
2649 }
2650 }
2651 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
2652
2653 /*TODO Is it to early if actual flip haven't happened yet ?*/
2654 /* Release old FB */
2655 drm_atomic_helper_cleanup_planes(dev, state);
2656 }
2657
2658
2659 static int dm_force_atomic_commit(struct drm_connector *connector)
2660 {
2661 int ret = 0;
2662 struct drm_device *ddev = connector->dev;
2663 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
2664 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
2665 struct drm_plane *plane = disconnected_acrtc->base.primary;
2666 struct drm_connector_state *conn_state;
2667 struct drm_crtc_state *crtc_state;
2668 struct drm_plane_state *plane_state;
2669
2670 if (!state)
2671 return -ENOMEM;
2672
2673 state->acquire_ctx = ddev->mode_config.acquire_ctx;
2674
2675 /* Construct an atomic state to restore previous display setting */
2676
2677 /*
2678 * Attach connectors to drm_atomic_state
2679 */
2680 conn_state = drm_atomic_get_connector_state(state, connector);
2681
2682 ret = PTR_ERR_OR_ZERO(conn_state);
2683 if (ret)
2684 goto err;
2685
2686 /* Attach crtc to drm_atomic_state*/
2687 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
2688
2689 ret = PTR_ERR_OR_ZERO(crtc_state);
2690 if (ret)
2691 goto err;
2692
2693 /* force a restore */
2694 crtc_state->mode_changed = true;
2695
2696 /* Attach plane to drm_atomic_state */
2697 plane_state = drm_atomic_get_plane_state(state, plane);
2698
2699 ret = PTR_ERR_OR_ZERO(plane_state);
2700 if (ret)
2701 goto err;
2702
2703
2704 /* Call commit internally with the state we just constructed */
2705 ret = drm_atomic_commit(state);
2706 if (!ret)
2707 return 0;
2708
2709 err:
2710 DRM_ERROR("Restoring old state failed with %i\n", ret);
2711 drm_atomic_state_put(state);
2712
2713 return ret;
2714 }
2715
2716 /*
2717 * This functions handle all cases when set mode does not come upon hotplug.
2718 * This include when the same display is unplugged then plugged back into the
2719 * same port and when we are running without usermode desktop manager supprot
2720 */
2721 void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector)
2722 {
2723 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2724 struct amdgpu_crtc *disconnected_acrtc;
2725
2726 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
2727 return;
2728
2729 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
2730
2731 if (!disconnected_acrtc || !disconnected_acrtc->stream)
2732 return;
2733
2734 /*
2735 * If the previous sink is not released and different from the current,
2736 * we deduce we are in a state where we can not rely on usermode call
2737 * to turn on the display, so we do it here
2738 */
2739 if (disconnected_acrtc->stream->sink != aconnector->dc_sink)
2740 dm_force_atomic_commit(&aconnector->base);
2741 }
2742
2743 static uint32_t add_val_sets_surface(
2744 struct dc_validation_set *val_sets,
2745 uint32_t set_count,
2746 const struct dc_stream *stream,
2747 const struct dc_surface *surface)
2748 {
2749 uint32_t i = 0;
2750
2751 while (i < set_count) {
2752 if (val_sets[i].stream == stream)
2753 break;
2754 ++i;
2755 }
2756
2757 val_sets[i].surfaces[val_sets[i].surface_count] = surface;
2758 val_sets[i].surface_count++;
2759
2760 return val_sets[i].surface_count;
2761 }
2762
2763 static uint32_t update_in_val_sets_stream(
2764 struct dc_validation_set *val_sets,
2765 struct drm_crtc **crtcs,
2766 uint32_t set_count,
2767 const struct dc_stream *old_stream,
2768 const struct dc_stream *new_stream,
2769 struct drm_crtc *crtc)
2770 {
2771 uint32_t i = 0;
2772
2773 while (i < set_count) {
2774 if (val_sets[i].stream == old_stream)
2775 break;
2776 ++i;
2777 }
2778
2779 val_sets[i].stream = new_stream;
2780 crtcs[i] = crtc;
2781
2782 if (i == set_count) {
2783 /* nothing found. add new one to the end */
2784 return set_count + 1;
2785 }
2786
2787 return set_count;
2788 }
2789
2790 static uint32_t remove_from_val_sets(
2791 struct dc_validation_set *val_sets,
2792 uint32_t set_count,
2793 const struct dc_stream *stream)
2794 {
2795 int i;
2796
2797 for (i = 0; i < set_count; i++)
2798 if (val_sets[i].stream == stream)
2799 break;
2800
2801 if (i == set_count) {
2802 /* nothing found */
2803 return set_count;
2804 }
2805
2806 set_count--;
2807
2808 for (; i < set_count; i++) {
2809 val_sets[i] = val_sets[i + 1];
2810 }
2811
2812 return set_count;
2813 }
2814
2815 int amdgpu_dm_atomic_check(struct drm_device *dev,
2816 struct drm_atomic_state *state)
2817 {
2818 struct drm_crtc *crtc;
2819 struct drm_crtc_state *crtc_state;
2820 struct drm_plane *plane;
2821 struct drm_plane_state *plane_state;
2822 int i, j;
2823 int ret;
2824 int set_count;
2825 int new_stream_count;
2826 struct dc_validation_set set[MAX_STREAMS] = {{ 0 }};
2827 struct dc_stream *new_streams[MAX_STREAMS] = { 0 };
2828 struct drm_crtc *crtc_set[MAX_STREAMS] = { 0 };
2829 struct amdgpu_device *adev = dev->dev_private;
2830 struct dc *dc = adev->dm.dc;
2831 bool need_to_validate = false;
2832
2833 ret = drm_atomic_helper_check(dev, state);
2834
2835 if (ret) {
2836 DRM_ERROR("Atomic state validation failed with error :%d !\n",
2837 ret);
2838 return ret;
2839 }
2840
2841 ret = -EINVAL;
2842
2843 /* copy existing configuration */
2844 new_stream_count = 0;
2845 set_count = 0;
2846 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2847
2848 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2849
2850 if (acrtc->stream) {
2851 set[set_count].stream = acrtc->stream;
2852 crtc_set[set_count] = crtc;
2853 ++set_count;
2854 }
2855 }
2856
2857 /* update changed items */
2858 for_each_crtc_in_state(state, crtc, crtc_state, i) {
2859 struct amdgpu_crtc *acrtc = NULL;
2860 struct amdgpu_connector *aconnector = NULL;
2861 enum dm_commit_action action;
2862
2863 acrtc = to_amdgpu_crtc(crtc);
2864
2865 aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc, true);
2866
2867 action = get_dm_commit_action(crtc_state);
2868
2869 switch (action) {
2870 case DM_COMMIT_ACTION_DPMS_ON:
2871 case DM_COMMIT_ACTION_SET: {
2872 struct dc_stream *new_stream = NULL;
2873 struct drm_connector_state *conn_state = NULL;
2874 struct dm_connector_state *dm_state = NULL;
2875
2876 if (aconnector) {
2877 conn_state = drm_atomic_get_connector_state(state, &aconnector->base);
2878 if (IS_ERR(conn_state))
2879 return ret;
2880 dm_state = to_dm_connector_state(conn_state);
2881 }
2882
2883 new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_state);
2884
2885 /*
2886 * we can have no stream on ACTION_SET if a display
2887 * was disconnected during S3, in this case it not and
2888 * error, the OS will be updated after detection, and
2889 * do the right thing on next atomic commit
2890 */
2891 if (!new_stream) {
2892 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
2893 __func__, acrtc->base.base.id);
2894 break;
2895 }
2896
2897 new_streams[new_stream_count] = new_stream;
2898 set_count = update_in_val_sets_stream(
2899 set,
2900 crtc_set,
2901 set_count,
2902 acrtc->stream,
2903 new_stream,
2904 crtc);
2905
2906 new_stream_count++;
2907 need_to_validate = true;
2908 break;
2909 }
2910
2911 case DM_COMMIT_ACTION_NOTHING: {
2912 const struct drm_connector *drm_connector = NULL;
2913 struct drm_connector_state *conn_state = NULL;
2914 struct dm_connector_state *dm_state = NULL;
2915 struct dm_connector_state *old_dm_state = NULL;
2916 struct dc_stream *new_stream;
2917
2918 if (!aconnector)
2919 break;
2920
2921 for_each_connector_in_state(
2922 state, drm_connector, conn_state, j) {
2923 if (&aconnector->base == drm_connector)
2924 break;
2925 }
2926
2927 old_dm_state = to_dm_connector_state(drm_connector->state);
2928 dm_state = to_dm_connector_state(conn_state);
2929
2930 /* Support underscan adjustment*/
2931 if (!is_scaling_state_different(dm_state, old_dm_state))
2932 break;
2933
2934 new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_state);
2935
2936 if (!new_stream) {
2937 DRM_ERROR("%s: Failed to create new stream for crtc %d\n",
2938 __func__, acrtc->base.base.id);
2939 break;
2940 }
2941
2942 new_streams[new_stream_count] = new_stream;
2943 set_count = update_in_val_sets_stream(
2944 set,
2945 crtc_set,
2946 set_count,
2947 acrtc->stream,
2948 new_stream,
2949 crtc);
2950
2951 new_stream_count++;
2952 need_to_validate = true;
2953
2954 break;
2955 }
2956 case DM_COMMIT_ACTION_DPMS_OFF:
2957 case DM_COMMIT_ACTION_RESET:
2958 /* i.e. reset mode */
2959 if (acrtc->stream) {
2960 set_count = remove_from_val_sets(
2961 set,
2962 set_count,
2963 acrtc->stream);
2964 }
2965 break;
2966 }
2967
2968 /*
2969 * TODO revisit when removing commit action
2970 * and looking at atomic flags directly
2971 */
2972
2973 /* commit needs planes right now (for gamma, eg.) */
2974 /* TODO rework commit to chack crtc for gamma change */
2975 ret = drm_atomic_add_affected_planes(state, crtc);
2976 if (ret)
2977 return ret;
2978
2979 ret = -EINVAL;
2980 }
2981
2982 for (i = 0; i < set_count; i++) {
2983 for_each_plane_in_state(state, plane, plane_state, j) {
2984 struct drm_crtc *crtc = plane_state->crtc;
2985 struct drm_framebuffer *fb = plane_state->fb;
2986 struct drm_connector *connector;
2987 struct dm_connector_state *dm_state = NULL;
2988 enum dm_commit_action action;
2989 struct drm_crtc_state *crtc_state;
2990 bool pflip_needed;
2991
2992
2993 if (!fb || !crtc || crtc_set[i] != crtc ||
2994 !crtc->state->planes_changed || !crtc->state->active)
2995 continue;
2996
2997 action = get_dm_commit_action(crtc->state);
2998
2999 /* Surfaces are created under two scenarios:
3000 * 1. This commit is not a page flip.
3001 * 2. This commit is a page flip, and streams are created.
3002 */
3003 crtc_state = drm_atomic_get_crtc_state(state, crtc);
3004 pflip_needed = !state->allow_modeset;
3005 if (!pflip_needed ||
3006 action == DM_COMMIT_ACTION_DPMS_ON ||
3007 action == DM_COMMIT_ACTION_SET) {
3008 struct dc_surface *surface;
3009
3010 list_for_each_entry(connector,
3011 &dev->mode_config.connector_list, head) {
3012 if (connector->state->crtc == crtc) {
3013 dm_state = to_dm_connector_state(
3014 connector->state);
3015 break;
3016 }
3017 }
3018
3019 /*
3020 * This situation happens in the following case:
3021 * we are about to get set mode for connector who's only
3022 * possible crtc (in encoder crtc mask) is used by
3023 * another connector, that is why it will try to
3024 * re-assing crtcs in order to make configuration
3025 * supported. For our implementation we need to make all
3026 * encoders support all crtcs, then this issue will
3027 * never arise again. But to guard code from this issue
3028 * check is left.
3029 *
3030 * Also it should be needed when used with actual
3031 * drm_atomic_commit ioctl in future
3032 */
3033 if (!dm_state)
3034 continue;
3035
3036 surface = dc_create_surface(dc);
3037 fill_plane_attributes(
3038 crtc->dev->dev_private,
3039 surface,
3040 plane_state,
3041 false);
3042
3043 add_val_sets_surface(
3044 set,
3045 set_count,
3046 set[i].stream,
3047 surface);
3048
3049 need_to_validate = true;
3050 }
3051 }
3052 }
3053
3054 if (need_to_validate == false || set_count == 0 ||
3055 dc_validate_resources(dc, set, set_count))
3056 ret = 0;
3057
3058 for (i = 0; i < set_count; i++) {
3059 for (j = 0; j < set[i].surface_count; j++) {
3060 dc_surface_release(set[i].surfaces[j]);
3061 }
3062 }
3063 for (i = 0; i < new_stream_count; i++)
3064 dc_stream_release(new_streams[i]);
3065
3066 if (ret != 0)
3067 DRM_ERROR("Atomic check failed.\n");
3068
3069 return ret;
3070 }
3071
3072 static bool is_dp_capable_without_timing_msa(
3073 struct dc *dc,
3074 struct amdgpu_connector *amdgpu_connector)
3075 {
3076 uint8_t dpcd_data;
3077 bool capable = false;
3078 if (amdgpu_connector->dc_link &&
3079 dc_read_aux_dpcd(
3080 dc,
3081 amdgpu_connector->dc_link->link_index,
3082 DP_DOWN_STREAM_PORT_COUNT,
3083 &dpcd_data, sizeof(dpcd_data)))
3084 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
3085
3086 return capable;
3087 }
3088 void amdgpu_dm_add_sink_to_freesync_module(
3089 struct drm_connector *connector,
3090 struct edid *edid)
3091 {
3092 int i;
3093 uint64_t val_capable;
3094 bool edid_check_required;
3095 struct detailed_timing *timing;
3096 struct detailed_non_pixel *data;
3097 struct detailed_data_monitor_range *range;
3098 struct amdgpu_connector *amdgpu_connector =
3099 to_amdgpu_connector(connector);
3100
3101 struct drm_device *dev = connector->dev;
3102 struct amdgpu_device *adev = dev->dev_private;
3103 edid_check_required = false;
3104 if (!amdgpu_connector->dc_sink) {
3105 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
3106 return;
3107 }
3108 if (!adev->dm.freesync_module)
3109 return;
3110 /*
3111 * if edid non zero restrict freesync only for dp and edp
3112 */
3113 if (edid) {
3114 if (amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
3115 || amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
3116 edid_check_required = is_dp_capable_without_timing_msa(
3117 adev->dm.dc,
3118 amdgpu_connector);
3119 }
3120 }
3121 val_capable = 0;
3122 if (edid_check_required == true && (edid->version > 1 ||
3123 (edid->version == 1 && edid->revision > 1))) {
3124 for (i = 0; i < 4; i++) {
3125
3126 timing = &edid->detailed_timings[i];
3127 data = &timing->data.other_data;
3128 range = &data->data.range;
3129 /*
3130 * Check if monitor has continuous frequency mode
3131 */
3132 if (data->type != EDID_DETAIL_MONITOR_RANGE)
3133 continue;
3134 /*
3135 * Check for flag range limits only. If flag == 1 then
3136 * no additional timing information provided.
3137 * Default GTF, GTF Secondary curve and CVT are not
3138 * supported
3139 */
3140 if (range->flags != 1)
3141 continue;
3142
3143 amdgpu_connector->min_vfreq = range->min_vfreq;
3144 amdgpu_connector->max_vfreq = range->max_vfreq;
3145 amdgpu_connector->pixel_clock_mhz =
3146 range->pixel_clock_mhz * 10;
3147 break;
3148 }
3149
3150 if (amdgpu_connector->max_vfreq -
3151 amdgpu_connector->min_vfreq > 10) {
3152 amdgpu_connector->caps.supported = true;
3153 amdgpu_connector->caps.min_refresh_in_micro_hz =
3154 amdgpu_connector->min_vfreq * 1000000;
3155 amdgpu_connector->caps.max_refresh_in_micro_hz =
3156 amdgpu_connector->max_vfreq * 1000000;
3157 val_capable = 1;
3158 }
3159 }
3160
3161 /*
3162 * TODO figure out how to notify user-mode or DRM of freesync caps
3163 * once we figure out how to deal with freesync in an upstreamable
3164 * fashion
3165 */
3166
3167 }
3168
3169 void amdgpu_dm_remove_sink_from_freesync_module(
3170 struct drm_connector *connector)
3171 {
3172 /*
3173 * TODO fill in once we figure out how to deal with freesync in
3174 * an upstreamable fashion
3175 */
3176 }
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