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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm_types.c
1 /*
2 * Copyright 2012-13 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/types.h>
27 #include <linux/version.h>
28
29 #include <drm/drmP.h>
30 #include <drm/drm_atomic_helper.h>
31 #include <drm/drm_fb_helper.h>
32 #include <drm/drm_atomic.h>
33 #include <drm/drm_edid.h>
34
35 #include "amdgpu.h"
36 #include "amdgpu_pm.h"
37 #include "dm_services_types.h"
38
39 // We need to #undef FRAME_SIZE and DEPRECATED because they conflict
40 // with ptrace-abi.h's #define's of them.
41 #undef FRAME_SIZE
42 #undef DEPRECATED
43
44 #include "dc.h"
45
46 #include "amdgpu_dm_types.h"
47 #include "amdgpu_dm_mst_types.h"
48
49 #include "modules/inc/mod_freesync.h"
50
51 struct dm_connector_state {
52 struct drm_connector_state base;
53
54 enum amdgpu_rmx_type scaling;
55 uint8_t underscan_vborder;
56 uint8_t underscan_hborder;
57 bool underscan_enable;
58 };
59
60 #define to_dm_connector_state(x)\
61 container_of((x), struct dm_connector_state, base)
62
63
64 void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
65 {
66 drm_encoder_cleanup(encoder);
67 kfree(encoder);
68 }
69
70 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
71 .destroy = amdgpu_dm_encoder_destroy,
72 };
73
74 static void dm_set_cursor(
75 struct amdgpu_crtc *amdgpu_crtc,
76 uint64_t gpu_addr,
77 uint32_t width,
78 uint32_t height)
79 {
80 struct dc_cursor_attributes attributes;
81 struct dc_cursor_position position;
82 struct drm_crtc *crtc = &amdgpu_crtc->base;
83 int x, y;
84 int xorigin = 0, yorigin = 0;
85
86 amdgpu_crtc->cursor_width = width;
87 amdgpu_crtc->cursor_height = height;
88
89 attributes.address.high_part = upper_32_bits(gpu_addr);
90 attributes.address.low_part = lower_32_bits(gpu_addr);
91 attributes.width = width;
92 attributes.height = height;
93 attributes.x_hot = 0;
94 attributes.y_hot = 0;
95 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
96 attributes.rotation_angle = 0;
97 attributes.attribute_flags.value = 0;
98
99 x = amdgpu_crtc->cursor_x;
100 y = amdgpu_crtc->cursor_y;
101
102 /* avivo cursor are offset into the total surface */
103 x += crtc->primary->state->src_x >> 16;
104 y += crtc->primary->state->src_y >> 16;
105
106 if (x < 0) {
107 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
108 x = 0;
109 }
110 if (y < 0) {
111 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
112 y = 0;
113 }
114
115 position.enable = true;
116 position.x = x;
117 position.y = y;
118
119 position.hot_spot_enable = true;
120 position.x_hotspot = xorigin;
121 position.y_hotspot = yorigin;
122
123 if (!dc_stream_set_cursor_attributes(
124 amdgpu_crtc->stream,
125 &attributes)) {
126 DRM_ERROR("DC failed to set cursor attributes\n");
127 }
128
129 if (!dc_stream_set_cursor_position(
130 amdgpu_crtc->stream,
131 &position)) {
132 DRM_ERROR("DC failed to set cursor position\n");
133 }
134 }
135
136 static int dm_crtc_unpin_cursor_bo_old(
137 struct amdgpu_crtc *amdgpu_crtc)
138 {
139 struct amdgpu_bo *robj;
140 int ret = 0;
141
142 if (NULL != amdgpu_crtc && NULL != amdgpu_crtc->cursor_bo) {
143 robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
144
145 ret = amdgpu_bo_reserve(robj, false);
146
147 if (likely(ret == 0)) {
148 ret = amdgpu_bo_unpin(robj);
149
150 if (unlikely(ret != 0)) {
151 DRM_ERROR(
152 "%s: unpin failed (ret=%d), bo %p\n",
153 __func__,
154 ret,
155 amdgpu_crtc->cursor_bo);
156 }
157
158 amdgpu_bo_unreserve(robj);
159 } else {
160 DRM_ERROR(
161 "%s: reserve failed (ret=%d), bo %p\n",
162 __func__,
163 ret,
164 amdgpu_crtc->cursor_bo);
165 }
166
167 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
168 amdgpu_crtc->cursor_bo = NULL;
169 }
170
171 return ret;
172 }
173
174 static int dm_crtc_pin_cursor_bo_new(
175 struct drm_crtc *crtc,
176 struct drm_file *file_priv,
177 uint32_t handle,
178 struct amdgpu_bo **ret_obj)
179 {
180 struct amdgpu_crtc *amdgpu_crtc;
181 struct amdgpu_bo *robj;
182 struct drm_gem_object *obj;
183 int ret = -EINVAL;
184
185 if (NULL != crtc) {
186 struct drm_device *dev = crtc->dev;
187 struct amdgpu_device *adev = dev->dev_private;
188 uint64_t gpu_addr;
189
190 amdgpu_crtc = to_amdgpu_crtc(crtc);
191
192 obj = drm_gem_object_lookup(file_priv, handle);
193
194 if (!obj) {
195 DRM_ERROR(
196 "Cannot find cursor object %x for crtc %d\n",
197 handle,
198 amdgpu_crtc->crtc_id);
199 goto release;
200 }
201 robj = gem_to_amdgpu_bo(obj);
202
203 ret = amdgpu_bo_reserve(robj, false);
204
205 if (unlikely(ret != 0)) {
206 drm_gem_object_unreference_unlocked(obj);
207 DRM_ERROR("dm_crtc_pin_cursor_bo_new ret %x, handle %x\n",
208 ret, handle);
209 goto release;
210 }
211
212 ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, 0,
213 adev->mc.visible_vram_size,
214 &gpu_addr);
215
216 if (ret == 0) {
217 amdgpu_crtc->cursor_addr = gpu_addr;
218 *ret_obj = robj;
219 }
220 amdgpu_bo_unreserve(robj);
221 if (ret)
222 drm_gem_object_unreference_unlocked(obj);
223
224 }
225 release:
226
227 return ret;
228 }
229
230 static int dm_crtc_cursor_set(
231 struct drm_crtc *crtc,
232 struct drm_file *file_priv,
233 uint32_t handle,
234 uint32_t width,
235 uint32_t height)
236 {
237 struct amdgpu_bo *new_cursor_bo;
238 struct dc_cursor_position position;
239
240 int ret;
241
242 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
243
244 ret = EINVAL;
245 new_cursor_bo = NULL;
246
247 DRM_DEBUG_KMS(
248 "%s: crtc_id=%d with handle %d and size %d to %d, bo_object %p\n",
249 __func__,
250 amdgpu_crtc->crtc_id,
251 handle,
252 width,
253 height,
254 amdgpu_crtc->cursor_bo);
255
256 if (!handle) {
257 /* turn off cursor */
258 position.enable = false;
259 position.x = 0;
260 position.y = 0;
261 position.hot_spot_enable = false;
262
263 if (amdgpu_crtc->stream) {
264 /*set cursor visible false*/
265 dc_stream_set_cursor_position(
266 amdgpu_crtc->stream,
267 &position);
268 }
269 /*unpin old cursor buffer and update cache*/
270 ret = dm_crtc_unpin_cursor_bo_old(amdgpu_crtc);
271 goto release;
272
273 }
274
275 if ((width > amdgpu_crtc->max_cursor_width) ||
276 (height > amdgpu_crtc->max_cursor_height)) {
277 DRM_ERROR(
278 "%s: bad cursor width or height %d x %d\n",
279 __func__,
280 width,
281 height);
282 goto release;
283 }
284 /*try to pin new cursor bo*/
285 ret = dm_crtc_pin_cursor_bo_new(crtc, file_priv, handle, &new_cursor_bo);
286 /*if map not successful then return an error*/
287 if (ret)
288 goto release;
289
290 /*program new cursor bo to hardware*/
291 dm_set_cursor(amdgpu_crtc, amdgpu_crtc->cursor_addr, width, height);
292
293 /*un map old, not used anymore cursor bo ,
294 * return memory and mapping back */
295 dm_crtc_unpin_cursor_bo_old(amdgpu_crtc);
296
297 /*assign new cursor bo to our internal cache*/
298 amdgpu_crtc->cursor_bo = &new_cursor_bo->gem_base;
299
300 release:
301 return ret;
302
303 }
304
305 static int dm_crtc_cursor_move(struct drm_crtc *crtc,
306 int x, int y)
307 {
308 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
309 int xorigin = 0, yorigin = 0;
310 struct dc_cursor_position position;
311
312 amdgpu_crtc->cursor_x = x;
313 amdgpu_crtc->cursor_y = y;
314
315 /* avivo cursor are offset into the total surface */
316 x += crtc->primary->state->src_x >> 16;
317 y += crtc->primary->state->src_y >> 16;
318
319 /*
320 * TODO: for cursor debugging unguard the following
321 */
322 #if 0
323 DRM_DEBUG_KMS(
324 "%s: x %d y %d c->x %d c->y %d\n",
325 __func__,
326 x,
327 y,
328 crtc->x,
329 crtc->y);
330 #endif
331
332 if (x < 0) {
333 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
334 x = 0;
335 }
336 if (y < 0) {
337 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
338 y = 0;
339 }
340
341 position.enable = true;
342 position.x = x;
343 position.y = y;
344
345 position.hot_spot_enable = true;
346 position.x_hotspot = xorigin;
347 position.y_hotspot = yorigin;
348
349 if (amdgpu_crtc->stream) {
350 if (!dc_stream_set_cursor_position(
351 amdgpu_crtc->stream,
352 &position)) {
353 DRM_ERROR("DC failed to set cursor position\n");
354 return -EINVAL;
355 }
356 }
357
358 return 0;
359 }
360
361 static void dm_crtc_cursor_reset(struct drm_crtc *crtc)
362 {
363 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
364
365 DRM_DEBUG_KMS(
366 "%s: with cursor_bo %p\n",
367 __func__,
368 amdgpu_crtc->cursor_bo);
369
370 if (amdgpu_crtc->cursor_bo && amdgpu_crtc->stream) {
371 dm_set_cursor(
372 amdgpu_crtc,
373 amdgpu_crtc->cursor_addr,
374 amdgpu_crtc->cursor_width,
375 amdgpu_crtc->cursor_height);
376 }
377 }
378 static bool fill_rects_from_plane_state(
379 const struct drm_plane_state *state,
380 struct dc_surface *surface)
381 {
382 surface->src_rect.x = state->src_x >> 16;
383 surface->src_rect.y = state->src_y >> 16;
384 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
385 surface->src_rect.width = state->src_w >> 16;
386
387 if (surface->src_rect.width == 0)
388 return false;
389
390 surface->src_rect.height = state->src_h >> 16;
391 if (surface->src_rect.height == 0)
392 return false;
393
394 surface->dst_rect.x = state->crtc_x;
395 surface->dst_rect.y = state->crtc_y;
396
397 if (state->crtc_w == 0)
398 return false;
399
400 surface->dst_rect.width = state->crtc_w;
401
402 if (state->crtc_h == 0)
403 return false;
404
405 surface->dst_rect.height = state->crtc_h;
406
407 surface->clip_rect = surface->dst_rect;
408
409 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
410 case DRM_MODE_ROTATE_0:
411 surface->rotation = ROTATION_ANGLE_0;
412 break;
413 case DRM_MODE_ROTATE_90:
414 surface->rotation = ROTATION_ANGLE_90;
415 break;
416 case DRM_MODE_ROTATE_180:
417 surface->rotation = ROTATION_ANGLE_180;
418 break;
419 case DRM_MODE_ROTATE_270:
420 surface->rotation = ROTATION_ANGLE_270;
421 break;
422 default:
423 surface->rotation = ROTATION_ANGLE_0;
424 break;
425 }
426
427 return true;
428 }
429 static bool get_fb_info(
430 const struct amdgpu_framebuffer *amdgpu_fb,
431 uint64_t *tiling_flags,
432 uint64_t *fb_location)
433 {
434 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
435 int r = amdgpu_bo_reserve(rbo, false);
436 if (unlikely(r != 0)){
437 DRM_ERROR("Unable to reserve buffer\n");
438 return false;
439 }
440
441 if (fb_location)
442 *fb_location = amdgpu_bo_gpu_offset(rbo);
443
444 if (tiling_flags)
445 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
446
447 amdgpu_bo_unreserve(rbo);
448
449 return true;
450 }
451 static void fill_plane_attributes_from_fb(
452 struct amdgpu_device *adev,
453 struct dc_surface *surface,
454 const struct amdgpu_framebuffer *amdgpu_fb, bool addReq)
455 {
456 uint64_t tiling_flags;
457 uint64_t fb_location = 0;
458 const struct drm_framebuffer *fb = &amdgpu_fb->base;
459 struct drm_format_name_buf format_name;
460
461 get_fb_info(
462 amdgpu_fb,
463 &tiling_flags,
464 addReq == true ? &fb_location:NULL);
465
466 surface->address.type = PLN_ADDR_TYPE_GRAPHICS;
467 surface->address.grph.addr.low_part = lower_32_bits(fb_location);
468 surface->address.grph.addr.high_part = upper_32_bits(fb_location);
469
470 switch (fb->format->format) {
471 case DRM_FORMAT_C8:
472 surface->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
473 break;
474 case DRM_FORMAT_RGB565:
475 surface->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
476 break;
477 case DRM_FORMAT_XRGB8888:
478 case DRM_FORMAT_ARGB8888:
479 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
480 break;
481 case DRM_FORMAT_XRGB2101010:
482 case DRM_FORMAT_ARGB2101010:
483 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
484 break;
485 case DRM_FORMAT_XBGR2101010:
486 case DRM_FORMAT_ABGR2101010:
487 surface->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
488 break;
489 default:
490 DRM_ERROR("Unsupported screen format %s\n",
491 drm_get_format_name(fb->format->format, &format_name));
492 return;
493 }
494
495 memset(&surface->tiling_info, 0, sizeof(surface->tiling_info));
496
497 /* Fill GFX8 params */
498 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1)
499 {
500 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
501
502 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
503 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
504 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
505 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
506 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
507
508 /* XXX fix me for VI */
509 surface->tiling_info.gfx8.num_banks = num_banks;
510 surface->tiling_info.gfx8.array_mode =
511 DC_ARRAY_2D_TILED_THIN1;
512 surface->tiling_info.gfx8.tile_split = tile_split;
513 surface->tiling_info.gfx8.bank_width = bankw;
514 surface->tiling_info.gfx8.bank_height = bankh;
515 surface->tiling_info.gfx8.tile_aspect = mtaspect;
516 surface->tiling_info.gfx8.tile_mode =
517 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
518 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
519 == DC_ARRAY_1D_TILED_THIN1) {
520 surface->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
521 }
522
523 surface->tiling_info.gfx8.pipe_config =
524 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
525
526 surface->plane_size.grph.surface_size.x = 0;
527 surface->plane_size.grph.surface_size.y = 0;
528 surface->plane_size.grph.surface_size.width = fb->width;
529 surface->plane_size.grph.surface_size.height = fb->height;
530 surface->plane_size.grph.surface_pitch =
531 fb->pitches[0] / fb->format->cpp[0];
532
533 surface->visible = true;
534 surface->scaling_quality.h_taps_c = 0;
535 surface->scaling_quality.v_taps_c = 0;
536
537 /* TODO: unhardcode */
538 surface->color_space = COLOR_SPACE_SRGB;
539 /* is this needed? is surface zeroed at allocation? */
540 surface->scaling_quality.h_taps = 0;
541 surface->scaling_quality.v_taps = 0;
542 surface->stereo_format = PLANE_STEREO_FORMAT_NONE;
543
544 }
545
546 #define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256
547
548 static void fill_gamma_from_crtc(
549 const struct drm_crtc *crtc,
550 struct dc_surface *dc_surface)
551 {
552 int i;
553 struct dc_gamma *gamma;
554 struct drm_crtc_state *state = crtc->state;
555 struct drm_color_lut *lut = (struct drm_color_lut *) state->gamma_lut->data;
556
557 gamma = dc_create_gamma();
558
559 if (gamma == NULL)
560 return;
561
562 for (i = 0; i < NUM_OF_RAW_GAMMA_RAMP_RGB_256; i++) {
563 gamma->red[i] = lut[i].red;
564 gamma->green[i] = lut[i].green;
565 gamma->blue[i] = lut[i].blue;
566 }
567
568 dc_surface->gamma_correction = gamma;
569 }
570
571 static void fill_plane_attributes(
572 struct amdgpu_device *adev,
573 struct dc_surface *surface,
574 struct drm_plane_state *state, bool addrReq)
575 {
576 const struct amdgpu_framebuffer *amdgpu_fb =
577 to_amdgpu_framebuffer(state->fb);
578 const struct drm_crtc *crtc = state->crtc;
579 struct dc_transfer_func *input_tf;
580
581 fill_rects_from_plane_state(state, surface);
582 fill_plane_attributes_from_fb(
583 crtc->dev->dev_private,
584 surface,
585 amdgpu_fb,
586 addrReq);
587
588 input_tf = dc_create_transfer_func();
589
590 if (input_tf == NULL)
591 return;
592
593 input_tf->type = TF_TYPE_PREDEFINED;
594 input_tf->tf = TRANSFER_FUNCTION_SRGB;
595
596 surface->in_transfer_func = input_tf;
597
598 /* In case of gamma set, update gamma value */
599 if (state->crtc->state->gamma_lut) {
600 fill_gamma_from_crtc(crtc, surface);
601 }
602 }
603
604 /*****************************************************************************/
605
606 struct amdgpu_connector *aconnector_from_drm_crtc_id(
607 const struct drm_crtc *crtc)
608 {
609 struct drm_device *dev = crtc->dev;
610 struct drm_connector *connector;
611 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
612 struct amdgpu_connector *aconnector;
613
614 list_for_each_entry(connector,
615 &dev->mode_config.connector_list, head) {
616
617 aconnector = to_amdgpu_connector(connector);
618
619 if (aconnector->base.state->crtc != &acrtc->base)
620 continue;
621
622 /* Found the connector */
623 return aconnector;
624 }
625
626 /* If we get here, not found. */
627 return NULL;
628 }
629
630 static void update_stream_scaling_settings(
631 const struct drm_display_mode *mode,
632 const struct dm_connector_state *dm_state,
633 const struct dc_stream *stream)
634 {
635 struct amdgpu_device *adev = dm_state->base.crtc->dev->dev_private;
636 enum amdgpu_rmx_type rmx_type;
637
638 struct rect src = { 0 }; /* viewport in composition space*/
639 struct rect dst = { 0 }; /* stream addressable area */
640
641 /* Full screen scaling by default */
642 src.width = mode->hdisplay;
643 src.height = mode->vdisplay;
644 dst.width = stream->timing.h_addressable;
645 dst.height = stream->timing.v_addressable;
646
647 rmx_type = dm_state->scaling;
648 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
649 if (src.width * dst.height <
650 src.height * dst.width) {
651 /* height needs less upscaling/more downscaling */
652 dst.width = src.width *
653 dst.height / src.height;
654 } else {
655 /* width needs less upscaling/more downscaling */
656 dst.height = src.height *
657 dst.width / src.width;
658 }
659 } else if (rmx_type == RMX_CENTER) {
660 dst = src;
661 }
662
663 dst.x = (stream->timing.h_addressable - dst.width) / 2;
664 dst.y = (stream->timing.v_addressable - dst.height) / 2;
665
666 if (dm_state->underscan_enable) {
667 dst.x += dm_state->underscan_hborder / 2;
668 dst.y += dm_state->underscan_vborder / 2;
669 dst.width -= dm_state->underscan_hborder;
670 dst.height -= dm_state->underscan_vborder;
671 }
672
673 adev->dm.dc->stream_funcs.stream_update_scaling(adev->dm.dc, stream, &src, &dst);
674
675 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
676 dst.x, dst.y, dst.width, dst.height);
677
678 }
679
680 static void dm_dc_surface_commit(
681 struct dc *dc,
682 struct drm_crtc *crtc)
683 {
684 struct dc_surface *dc_surface;
685 const struct dc_surface *dc_surfaces[1];
686 const struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
687 const struct dc_stream *dc_stream = acrtc->stream;
688
689 if (!dc_stream) {
690 dm_error(
691 "%s: Failed to obtain stream on crtc (%d)!\n",
692 __func__,
693 acrtc->crtc_id);
694 goto fail;
695 }
696
697 dc_surface = dc_create_surface(dc);
698
699 if (!dc_surface) {
700 dm_error(
701 "%s: Failed to create a surface!\n",
702 __func__);
703 goto fail;
704 }
705
706 /* Surface programming */
707 fill_plane_attributes(
708 crtc->dev->dev_private,
709 dc_surface,
710 crtc->primary->state,
711 true);
712
713 dc_surfaces[0] = dc_surface;
714
715 if (false == dc_commit_surfaces_to_stream(
716 dc,
717 dc_surfaces,
718 1,
719 dc_stream)) {
720 dm_error(
721 "%s: Failed to attach surface!\n",
722 __func__);
723 }
724
725 dc_surface_release(dc_surface);
726 fail:
727 return;
728 }
729
730 static enum dc_color_depth convert_color_depth_from_display_info(
731 const struct drm_connector *connector)
732 {
733 uint32_t bpc = connector->display_info.bpc;
734
735 /* Limited color depth to 8bit
736 * TODO: Still need to handle deep color*/
737 if (bpc > 8)
738 bpc = 8;
739
740 switch (bpc) {
741 case 0:
742 /* Temporary Work around, DRM don't parse color depth for
743 * EDID revision before 1.4
744 * TODO: Fix edid parsing
745 */
746 return COLOR_DEPTH_888;
747 case 6:
748 return COLOR_DEPTH_666;
749 case 8:
750 return COLOR_DEPTH_888;
751 case 10:
752 return COLOR_DEPTH_101010;
753 case 12:
754 return COLOR_DEPTH_121212;
755 case 14:
756 return COLOR_DEPTH_141414;
757 case 16:
758 return COLOR_DEPTH_161616;
759 default:
760 return COLOR_DEPTH_UNDEFINED;
761 }
762 }
763
764 static enum dc_aspect_ratio get_aspect_ratio(
765 const struct drm_display_mode *mode_in)
766 {
767 int32_t width = mode_in->crtc_hdisplay * 9;
768 int32_t height = mode_in->crtc_vdisplay * 16;
769 if ((width - height) < 10 && (width - height) > -10)
770 return ASPECT_RATIO_16_9;
771 else
772 return ASPECT_RATIO_4_3;
773 }
774
775 static enum dc_color_space get_output_color_space(
776 const struct dc_crtc_timing *dc_crtc_timing)
777 {
778 enum dc_color_space color_space = COLOR_SPACE_SRGB;
779
780 switch (dc_crtc_timing->pixel_encoding) {
781 case PIXEL_ENCODING_YCBCR422:
782 case PIXEL_ENCODING_YCBCR444:
783 case PIXEL_ENCODING_YCBCR420:
784 {
785 /*
786 * 27030khz is the separation point between HDTV and SDTV
787 * according to HDMI spec, we use YCbCr709 and YCbCr601
788 * respectively
789 */
790 if (dc_crtc_timing->pix_clk_khz > 27030) {
791 if (dc_crtc_timing->flags.Y_ONLY)
792 color_space =
793 COLOR_SPACE_YCBCR709_LIMITED;
794 else
795 color_space = COLOR_SPACE_YCBCR709;
796 } else {
797 if (dc_crtc_timing->flags.Y_ONLY)
798 color_space =
799 COLOR_SPACE_YCBCR601_LIMITED;
800 else
801 color_space = COLOR_SPACE_YCBCR601;
802 }
803
804 }
805 break;
806 case PIXEL_ENCODING_RGB:
807 color_space = COLOR_SPACE_SRGB;
808 break;
809
810 default:
811 WARN_ON(1);
812 break;
813 }
814
815 return color_space;
816 }
817
818 /*****************************************************************************/
819
820 static void fill_stream_properties_from_drm_display_mode(
821 struct dc_stream *stream,
822 const struct drm_display_mode *mode_in,
823 const struct drm_connector *connector)
824 {
825 struct dc_crtc_timing *timing_out = &stream->timing;
826 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
827
828 timing_out->h_border_left = 0;
829 timing_out->h_border_right = 0;
830 timing_out->v_border_top = 0;
831 timing_out->v_border_bottom = 0;
832 /* TODO: un-hardcode */
833
834 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
835 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
836 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
837 else
838 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
839
840 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
841 timing_out->display_color_depth = convert_color_depth_from_display_info(
842 connector);
843 timing_out->scan_type = SCANNING_TYPE_NODATA;
844 timing_out->hdmi_vic = 0;
845 timing_out->vic = drm_match_cea_mode(mode_in);
846
847 timing_out->h_addressable = mode_in->crtc_hdisplay;
848 timing_out->h_total = mode_in->crtc_htotal;
849 timing_out->h_sync_width =
850 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
851 timing_out->h_front_porch =
852 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
853 timing_out->v_total = mode_in->crtc_vtotal;
854 timing_out->v_addressable = mode_in->crtc_vdisplay;
855 timing_out->v_front_porch =
856 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
857 timing_out->v_sync_width =
858 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
859 timing_out->pix_clk_khz = mode_in->crtc_clock;
860 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
861 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
862 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
863 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
864 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
865
866 stream->output_color_space = get_output_color_space(timing_out);
867
868 {
869 struct dc_transfer_func *tf = dc_create_transfer_func();
870 tf->type = TF_TYPE_PREDEFINED;
871 tf->tf = TRANSFER_FUNCTION_SRGB;
872 stream->out_transfer_func = tf;
873 }
874 }
875
876 static void fill_audio_info(
877 struct audio_info *audio_info,
878 const struct drm_connector *drm_connector,
879 const struct dc_sink *dc_sink)
880 {
881 int i = 0;
882 int cea_revision = 0;
883 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
884
885 audio_info->manufacture_id = edid_caps->manufacturer_id;
886 audio_info->product_id = edid_caps->product_id;
887
888 cea_revision = drm_connector->display_info.cea_rev;
889
890 while (i < AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS &&
891 edid_caps->display_name[i]) {
892 audio_info->display_name[i] = edid_caps->display_name[i];
893 i++;
894 }
895
896 if(cea_revision >= 3) {
897 audio_info->mode_count = edid_caps->audio_mode_count;
898
899 for (i = 0; i < audio_info->mode_count; ++i) {
900 audio_info->modes[i].format_code =
901 (enum audio_format_code)
902 (edid_caps->audio_modes[i].format_code);
903 audio_info->modes[i].channel_count =
904 edid_caps->audio_modes[i].channel_count;
905 audio_info->modes[i].sample_rates.all =
906 edid_caps->audio_modes[i].sample_rate;
907 audio_info->modes[i].sample_size =
908 edid_caps->audio_modes[i].sample_size;
909 }
910 }
911
912 audio_info->flags.all = edid_caps->speaker_flags;
913
914 /* TODO: We only check for the progressive mode, check for interlace mode too */
915 if(drm_connector->latency_present[0]) {
916 audio_info->video_latency = drm_connector->video_latency[0];
917 audio_info->audio_latency = drm_connector->audio_latency[0];
918 }
919
920 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
921
922 }
923
924 static void copy_crtc_timing_for_drm_display_mode(
925 const struct drm_display_mode *src_mode,
926 struct drm_display_mode *dst_mode)
927 {
928 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
929 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
930 dst_mode->crtc_clock = src_mode->crtc_clock;
931 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
932 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
933 dst_mode->crtc_hsync_start= src_mode->crtc_hsync_start;
934 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
935 dst_mode->crtc_htotal = src_mode->crtc_htotal;
936 dst_mode->crtc_hskew = src_mode->crtc_hskew;
937 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;;
938 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;;
939 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;;
940 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;;
941 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;;
942 }
943
944 static void decide_crtc_timing_for_drm_display_mode(
945 struct drm_display_mode *drm_mode,
946 const struct drm_display_mode *native_mode,
947 bool scale_enabled)
948 {
949 if (scale_enabled) {
950 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
951 } else if (native_mode->clock == drm_mode->clock &&
952 native_mode->htotal == drm_mode->htotal &&
953 native_mode->vtotal == drm_mode->vtotal) {
954 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
955 } else {
956 /* no scaling nor amdgpu inserted, no need to patch */
957 }
958 }
959
960 static struct dc_stream *create_stream_for_sink(
961 const struct amdgpu_connector *aconnector,
962 const struct drm_display_mode *drm_mode,
963 const struct dm_connector_state *dm_state)
964 {
965 struct drm_display_mode *preferred_mode = NULL;
966 const struct drm_connector *drm_connector;
967 struct dc_stream *stream = NULL;
968 struct drm_display_mode mode = *drm_mode;
969 bool native_mode_found = false;
970
971 if (NULL == aconnector) {
972 DRM_ERROR("aconnector is NULL!\n");
973 goto drm_connector_null;
974 }
975
976 if (NULL == dm_state) {
977 DRM_ERROR("dm_state is NULL!\n");
978 goto dm_state_null;
979 }
980
981 drm_connector = &aconnector->base;
982 stream = dc_create_stream_for_sink(aconnector->dc_sink);
983
984 if (NULL == stream) {
985 DRM_ERROR("Failed to create stream for sink!\n");
986 goto stream_create_fail;
987 }
988
989 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
990 /* Search for preferred mode */
991 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
992 native_mode_found = true;
993 break;
994 }
995 }
996 if (!native_mode_found)
997 preferred_mode = list_first_entry_or_null(
998 &aconnector->base.modes,
999 struct drm_display_mode,
1000 head);
1001
1002 if (NULL == preferred_mode) {
1003 /* This may not be an error, the use case is when we we have no
1004 * usermode calls to reset and set mode upon hotplug. In this
1005 * case, we call set mode ourselves to restore the previous mode
1006 * and the modelist may not be filled in in time.
1007 */
1008 DRM_INFO("No preferred mode found\n");
1009 } else {
1010 decide_crtc_timing_for_drm_display_mode(
1011 &mode, preferred_mode,
1012 dm_state->scaling != RMX_OFF);
1013 }
1014
1015 fill_stream_properties_from_drm_display_mode(stream,
1016 &mode, &aconnector->base);
1017 update_stream_scaling_settings(&mode, dm_state, stream);
1018
1019 fill_audio_info(
1020 &stream->audio_info,
1021 drm_connector,
1022 aconnector->dc_sink);
1023
1024 stream_create_fail:
1025 dm_state_null:
1026 drm_connector_null:
1027 return stream;
1028 }
1029
1030 void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
1031 {
1032 drm_crtc_cleanup(crtc);
1033 kfree(crtc);
1034 }
1035
1036 /* Implemented only the options currently availible for the driver */
1037 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
1038 .reset = drm_atomic_helper_crtc_reset,
1039 .cursor_set = dm_crtc_cursor_set,
1040 .cursor_move = dm_crtc_cursor_move,
1041 .destroy = amdgpu_dm_crtc_destroy,
1042 .gamma_set = drm_atomic_helper_legacy_gamma_set,
1043 .set_config = drm_atomic_helper_set_config,
1044 .page_flip = drm_atomic_helper_page_flip,
1045 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1046 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1047 };
1048
1049 static enum drm_connector_status
1050 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
1051 {
1052 bool connected;
1053 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1054
1055 /* Notes:
1056 * 1. This interface is NOT called in context of HPD irq.
1057 * 2. This interface *is called* in context of user-mode ioctl. Which
1058 * makes it a bad place for *any* MST-related activit. */
1059
1060 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1061 connected = (aconnector->dc_sink != NULL);
1062 else
1063 connected = (aconnector->base.force == DRM_FORCE_ON);
1064
1065 return (connected ? connector_status_connected :
1066 connector_status_disconnected);
1067 }
1068
1069 int amdgpu_dm_connector_atomic_set_property(
1070 struct drm_connector *connector,
1071 struct drm_connector_state *connector_state,
1072 struct drm_property *property,
1073 uint64_t val)
1074 {
1075 struct drm_device *dev = connector->dev;
1076 struct amdgpu_device *adev = dev->dev_private;
1077 struct dm_connector_state *dm_old_state =
1078 to_dm_connector_state(connector->state);
1079 struct dm_connector_state *dm_new_state =
1080 to_dm_connector_state(connector_state);
1081
1082 struct drm_crtc_state *new_crtc_state;
1083 struct drm_crtc *crtc;
1084 int i;
1085 int ret = -EINVAL;
1086
1087 if (property == dev->mode_config.scaling_mode_property) {
1088 enum amdgpu_rmx_type rmx_type;
1089
1090 switch (val) {
1091 case DRM_MODE_SCALE_CENTER:
1092 rmx_type = RMX_CENTER;
1093 break;
1094 case DRM_MODE_SCALE_ASPECT:
1095 rmx_type = RMX_ASPECT;
1096 break;
1097 case DRM_MODE_SCALE_FULLSCREEN:
1098 rmx_type = RMX_FULL;
1099 break;
1100 case DRM_MODE_SCALE_NONE:
1101 default:
1102 rmx_type = RMX_OFF;
1103 break;
1104 }
1105
1106 if (dm_old_state->scaling == rmx_type)
1107 return 0;
1108
1109 dm_new_state->scaling = rmx_type;
1110 ret = 0;
1111 } else if (property == adev->mode_info.underscan_hborder_property) {
1112 dm_new_state->underscan_hborder = val;
1113 ret = 0;
1114 } else if (property == adev->mode_info.underscan_vborder_property) {
1115 dm_new_state->underscan_vborder = val;
1116 ret = 0;
1117 } else if (property == adev->mode_info.underscan_property) {
1118 dm_new_state->underscan_enable = val;
1119 ret = 0;
1120 }
1121
1122 for_each_crtc_in_state(
1123 connector_state->state,
1124 crtc,
1125 new_crtc_state,
1126 i) {
1127
1128 if (crtc == connector_state->crtc) {
1129 struct drm_plane_state *plane_state;
1130
1131 /*
1132 * Bit of magic done here. We need to ensure
1133 * that planes get update after mode is set.
1134 * So, we need to add primary plane to state,
1135 * and this way atomic_update would be called
1136 * for it
1137 */
1138 plane_state =
1139 drm_atomic_get_plane_state(
1140 connector_state->state,
1141 crtc->primary);
1142
1143 if (!plane_state)
1144 return -EINVAL;
1145 }
1146 }
1147
1148 return ret;
1149 }
1150
1151 void amdgpu_dm_connector_destroy(struct drm_connector *connector)
1152 {
1153 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1154 const struct dc_link *link = aconnector->dc_link;
1155 struct amdgpu_device *adev = connector->dev->dev_private;
1156 struct amdgpu_display_manager *dm = &adev->dm;
1157 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1158 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1159
1160 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
1161 amdgpu_dm_register_backlight_device(dm);
1162
1163 if (dm->backlight_dev) {
1164 backlight_device_unregister(dm->backlight_dev);
1165 dm->backlight_dev = NULL;
1166 }
1167
1168 }
1169 #endif
1170 drm_connector_unregister(connector);
1171 drm_connector_cleanup(connector);
1172 kfree(connector);
1173 }
1174
1175 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
1176 {
1177 struct dm_connector_state *state =
1178 to_dm_connector_state(connector->state);
1179
1180 kfree(state);
1181
1182 state = kzalloc(sizeof(*state), GFP_KERNEL);
1183
1184 if (state) {
1185 state->scaling = RMX_OFF;
1186 state->underscan_enable = false;
1187 state->underscan_hborder = 0;
1188 state->underscan_vborder = 0;
1189
1190 connector->state = &state->base;
1191 connector->state->connector = connector;
1192 }
1193 }
1194
1195 struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state(
1196 struct drm_connector *connector)
1197 {
1198 struct dm_connector_state *state =
1199 to_dm_connector_state(connector->state);
1200
1201 struct dm_connector_state *new_state =
1202 kmemdup(state, sizeof(*state), GFP_KERNEL);
1203
1204 if (new_state) {
1205 __drm_atomic_helper_connector_duplicate_state(connector,
1206 &new_state->base);
1207 return &new_state->base;
1208 }
1209
1210 return NULL;
1211 }
1212
1213 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
1214 .reset = amdgpu_dm_connector_funcs_reset,
1215 .detect = amdgpu_dm_connector_detect,
1216 .fill_modes = drm_helper_probe_single_connector_modes,
1217 .destroy = amdgpu_dm_connector_destroy,
1218 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
1219 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1220 .atomic_set_property = amdgpu_dm_connector_atomic_set_property
1221 };
1222
1223 static struct drm_encoder *best_encoder(struct drm_connector *connector)
1224 {
1225 int enc_id = connector->encoder_ids[0];
1226 struct drm_mode_object *obj;
1227 struct drm_encoder *encoder;
1228
1229 DRM_DEBUG_KMS("Finding the best encoder\n");
1230
1231 /* pick the encoder ids */
1232 if (enc_id) {
1233 obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER);
1234 if (!obj) {
1235 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
1236 return NULL;
1237 }
1238 encoder = obj_to_encoder(obj);
1239 return encoder;
1240 }
1241 DRM_ERROR("No encoder id\n");
1242 return NULL;
1243 }
1244
1245 static int get_modes(struct drm_connector *connector)
1246 {
1247 return amdgpu_dm_connector_get_modes(connector);
1248 }
1249
1250 static void create_eml_sink(struct amdgpu_connector *aconnector)
1251 {
1252 struct dc_sink_init_data init_params = {
1253 .link = aconnector->dc_link,
1254 .sink_signal = SIGNAL_TYPE_VIRTUAL
1255 };
1256 struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
1257
1258 if (!aconnector->base.edid_blob_ptr ||
1259 !aconnector->base.edid_blob_ptr->data) {
1260 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
1261 aconnector->base.name);
1262
1263 aconnector->base.force = DRM_FORCE_OFF;
1264 aconnector->base.override_edid = false;
1265 return;
1266 }
1267
1268 aconnector->edid = edid;
1269
1270 aconnector->dc_em_sink = dc_link_add_remote_sink(
1271 aconnector->dc_link,
1272 (uint8_t *)edid,
1273 (edid->extensions + 1) * EDID_LENGTH,
1274 &init_params);
1275
1276 if (aconnector->base.force
1277 == DRM_FORCE_ON)
1278 aconnector->dc_sink = aconnector->dc_link->local_sink ?
1279 aconnector->dc_link->local_sink :
1280 aconnector->dc_em_sink;
1281 }
1282
1283 static void handle_edid_mgmt(struct amdgpu_connector *aconnector)
1284 {
1285 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
1286
1287 /* In case of headless boot with force on for DP managed connector
1288 * Those settings have to be != 0 to get initial modeset
1289 */
1290 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
1291 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
1292 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
1293 }
1294
1295
1296 aconnector->base.override_edid = true;
1297 create_eml_sink(aconnector);
1298 }
1299
1300 int amdgpu_dm_connector_mode_valid(
1301 struct drm_connector *connector,
1302 struct drm_display_mode *mode)
1303 {
1304 int result = MODE_ERROR;
1305 const struct dc_sink *dc_sink;
1306 struct amdgpu_device *adev = connector->dev->dev_private;
1307 struct dc_validation_set val_set = { 0 };
1308 /* TODO: Unhardcode stream count */
1309 struct dc_stream *stream;
1310 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
1311
1312 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1313 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
1314 return result;
1315
1316 /* Only run this the first time mode_valid is called to initilialize
1317 * EDID mgmt
1318 */
1319 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
1320 !aconnector->dc_em_sink)
1321 handle_edid_mgmt(aconnector);
1322
1323 dc_sink = to_amdgpu_connector(connector)->dc_sink;
1324
1325 if (NULL == dc_sink) {
1326 DRM_ERROR("dc_sink is NULL!\n");
1327 goto null_sink;
1328 }
1329
1330 stream = dc_create_stream_for_sink(dc_sink);
1331 if (NULL == stream) {
1332 DRM_ERROR("Failed to create stream for sink!\n");
1333 goto stream_create_fail;
1334 }
1335
1336 drm_mode_set_crtcinfo(mode, 0);
1337 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
1338
1339 val_set.stream = stream;
1340 val_set.surface_count = 0;
1341 stream->src.width = mode->hdisplay;
1342 stream->src.height = mode->vdisplay;
1343 stream->dst = stream->src;
1344
1345 if (dc_validate_resources(adev->dm.dc, &val_set, 1))
1346 result = MODE_OK;
1347
1348 dc_stream_release(stream);
1349
1350 stream_create_fail:
1351 null_sink:
1352 /* TODO: error handling*/
1353 return result;
1354 }
1355
1356 static const struct drm_connector_helper_funcs
1357 amdgpu_dm_connector_helper_funcs = {
1358 /*
1359 * If hotplug a second bigger display in FB Con mode, bigger resolution
1360 * modes will be filtered by drm_mode_validate_size(), and those modes
1361 * is missing after user start lightdm. So we need to renew modes list.
1362 * in get_modes call back, not just return the modes count
1363 */
1364 .get_modes = get_modes,
1365 .mode_valid = amdgpu_dm_connector_mode_valid,
1366 .best_encoder = best_encoder
1367 };
1368
1369 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
1370 {
1371 }
1372
1373 static int dm_crtc_helper_atomic_check(
1374 struct drm_crtc *crtc,
1375 struct drm_crtc_state *state)
1376 {
1377 return 0;
1378 }
1379
1380 static bool dm_crtc_helper_mode_fixup(
1381 struct drm_crtc *crtc,
1382 const struct drm_display_mode *mode,
1383 struct drm_display_mode *adjusted_mode)
1384 {
1385 return true;
1386 }
1387
1388 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
1389 .disable = dm_crtc_helper_disable,
1390 .atomic_check = dm_crtc_helper_atomic_check,
1391 .mode_fixup = dm_crtc_helper_mode_fixup
1392 };
1393
1394 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
1395 {
1396
1397 }
1398
1399 static int dm_encoder_helper_atomic_check(
1400 struct drm_encoder *encoder,
1401 struct drm_crtc_state *crtc_state,
1402 struct drm_connector_state *conn_state)
1403 {
1404 return 0;
1405 }
1406
1407 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
1408 .disable = dm_encoder_helper_disable,
1409 .atomic_check = dm_encoder_helper_atomic_check
1410 };
1411
1412 static const struct drm_plane_funcs dm_plane_funcs = {
1413 .reset = drm_atomic_helper_plane_reset,
1414 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1415 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state
1416 };
1417
1418 static void clear_unrelated_fields(struct drm_plane_state *state)
1419 {
1420 state->crtc = NULL;
1421 state->fb = NULL;
1422 state->state = NULL;
1423 state->fence = NULL;
1424 }
1425
1426 static bool page_flip_needed(
1427 const struct drm_plane_state *new_state,
1428 const struct drm_plane_state *old_state,
1429 struct drm_pending_vblank_event *event,
1430 bool commit_surface_required)
1431 {
1432 struct drm_plane_state old_state_tmp;
1433 struct drm_plane_state new_state_tmp;
1434
1435 struct amdgpu_framebuffer *amdgpu_fb_old;
1436 struct amdgpu_framebuffer *amdgpu_fb_new;
1437 struct amdgpu_crtc *acrtc_new;
1438
1439 uint64_t old_tiling_flags;
1440 uint64_t new_tiling_flags;
1441
1442 bool page_flip_required;
1443
1444 if (!old_state)
1445 return false;
1446
1447 if (!old_state->fb)
1448 return false;
1449
1450 if (!new_state)
1451 return false;
1452
1453 if (!new_state->fb)
1454 return false;
1455
1456 old_state_tmp = *old_state;
1457 new_state_tmp = *new_state;
1458
1459 if (!event)
1460 return false;
1461
1462 amdgpu_fb_old = to_amdgpu_framebuffer(old_state->fb);
1463 amdgpu_fb_new = to_amdgpu_framebuffer(new_state->fb);
1464
1465 if (!get_fb_info(amdgpu_fb_old, &old_tiling_flags, NULL))
1466 return false;
1467
1468 if (!get_fb_info(amdgpu_fb_new, &new_tiling_flags, NULL))
1469 return false;
1470
1471 if (commit_surface_required == true &&
1472 old_tiling_flags != new_tiling_flags)
1473 return false;
1474
1475 clear_unrelated_fields(&old_state_tmp);
1476 clear_unrelated_fields(&new_state_tmp);
1477
1478 page_flip_required = memcmp(&old_state_tmp,
1479 &new_state_tmp,
1480 sizeof(old_state_tmp)) == 0 ? true:false;
1481 if (new_state->crtc && page_flip_required == false) {
1482 acrtc_new = to_amdgpu_crtc(new_state->crtc);
1483 if (acrtc_new->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
1484 page_flip_required = true;
1485 }
1486 return page_flip_required;
1487 }
1488
1489 static int dm_plane_helper_prepare_fb(
1490 struct drm_plane *plane,
1491 struct drm_plane_state *new_state)
1492 {
1493 struct amdgpu_framebuffer *afb;
1494 struct drm_gem_object *obj;
1495 struct amdgpu_bo *rbo;
1496 int r;
1497
1498 if (!new_state->fb) {
1499 DRM_DEBUG_KMS("No FB bound\n");
1500 return 0;
1501 }
1502
1503 afb = to_amdgpu_framebuffer(new_state->fb);
1504
1505 obj = afb->obj;
1506 rbo = gem_to_amdgpu_bo(obj);
1507 r = amdgpu_bo_reserve(rbo, false);
1508 if (unlikely(r != 0))
1509 return r;
1510
1511 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, NULL);
1512
1513 amdgpu_bo_unreserve(rbo);
1514
1515 if (unlikely(r != 0)) {
1516 DRM_ERROR("Failed to pin framebuffer\n");
1517 return r;
1518 }
1519
1520 return 0;
1521 }
1522
1523 static void dm_plane_helper_cleanup_fb(
1524 struct drm_plane *plane,
1525 struct drm_plane_state *old_state)
1526 {
1527 struct amdgpu_bo *rbo;
1528 struct amdgpu_framebuffer *afb;
1529 int r;
1530
1531 if (!old_state->fb)
1532 return;
1533
1534 afb = to_amdgpu_framebuffer(old_state->fb);
1535 rbo = gem_to_amdgpu_bo(afb->obj);
1536 r = amdgpu_bo_reserve(rbo, false);
1537 if (unlikely(r)) {
1538 DRM_ERROR("failed to reserve rbo before unpin\n");
1539 return;
1540 } else {
1541 amdgpu_bo_unpin(rbo);
1542 amdgpu_bo_unreserve(rbo);
1543 }
1544 }
1545
1546 int dm_create_validation_set_for_connector(struct drm_connector *connector,
1547 struct drm_display_mode *mode, struct dc_validation_set *val_set)
1548 {
1549 int result = MODE_ERROR;
1550 const struct dc_sink *dc_sink =
1551 to_amdgpu_connector(connector)->dc_sink;
1552 /* TODO: Unhardcode stream count */
1553 struct dc_stream *stream;
1554
1555 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1556 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
1557 return result;
1558
1559 if (NULL == dc_sink) {
1560 DRM_ERROR("dc_sink is NULL!\n");
1561 return result;
1562 }
1563
1564 stream = dc_create_stream_for_sink(dc_sink);
1565
1566 if (NULL == stream) {
1567 DRM_ERROR("Failed to create stream for sink!\n");
1568 return result;
1569 }
1570
1571 drm_mode_set_crtcinfo(mode, 0);
1572
1573 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
1574
1575 val_set->stream = stream;
1576
1577 stream->src.width = mode->hdisplay;
1578 stream->src.height = mode->vdisplay;
1579 stream->dst = stream->src;
1580
1581 return MODE_OK;
1582 }
1583
1584 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
1585 .prepare_fb = dm_plane_helper_prepare_fb,
1586 .cleanup_fb = dm_plane_helper_cleanup_fb,
1587 };
1588
1589 /*
1590 * TODO: these are currently initialized to rgb formats only.
1591 * For future use cases we should either initialize them dynamically based on
1592 * plane capabilities, or initialize this array to all formats, so internal drm
1593 * check will succeed, and let DC to implement proper check
1594 */
1595 static uint32_t rgb_formats[] = {
1596 DRM_FORMAT_XRGB4444,
1597 DRM_FORMAT_ARGB4444,
1598 DRM_FORMAT_RGBA4444,
1599 DRM_FORMAT_ARGB1555,
1600 DRM_FORMAT_RGB565,
1601 DRM_FORMAT_RGB888,
1602 DRM_FORMAT_XRGB8888,
1603 DRM_FORMAT_ARGB8888,
1604 DRM_FORMAT_RGBA8888,
1605 DRM_FORMAT_XRGB2101010,
1606 DRM_FORMAT_XBGR2101010,
1607 DRM_FORMAT_ARGB2101010,
1608 DRM_FORMAT_ABGR2101010,
1609 };
1610
1611 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
1612 struct amdgpu_crtc *acrtc,
1613 uint32_t crtc_index)
1614 {
1615 int res = -ENOMEM;
1616
1617 struct drm_plane *primary_plane =
1618 kzalloc(sizeof(*primary_plane), GFP_KERNEL);
1619
1620 if (!primary_plane)
1621 goto fail_plane;
1622
1623 primary_plane->format_default = true;
1624
1625 res = drm_universal_plane_init(
1626 dm->adev->ddev,
1627 primary_plane,
1628 0,
1629 &dm_plane_funcs,
1630 rgb_formats,
1631 ARRAY_SIZE(rgb_formats),
1632 NULL,
1633 DRM_PLANE_TYPE_PRIMARY, NULL);
1634
1635 primary_plane->crtc = &acrtc->base;
1636
1637 drm_plane_helper_add(primary_plane, &dm_plane_helper_funcs);
1638
1639 res = drm_crtc_init_with_planes(
1640 dm->ddev,
1641 &acrtc->base,
1642 primary_plane,
1643 NULL,
1644 &amdgpu_dm_crtc_funcs, NULL);
1645
1646 if (res)
1647 goto fail;
1648
1649 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
1650
1651 acrtc->max_cursor_width = 128;
1652 acrtc->max_cursor_height = 128;
1653
1654 acrtc->crtc_id = crtc_index;
1655 acrtc->base.enabled = false;
1656
1657 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
1658 drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
1659
1660 return 0;
1661 fail:
1662 kfree(primary_plane);
1663 fail_plane:
1664 acrtc->crtc_id = -1;
1665 return res;
1666 }
1667
1668 static int to_drm_connector_type(enum signal_type st)
1669 {
1670 switch (st) {
1671 case SIGNAL_TYPE_HDMI_TYPE_A:
1672 return DRM_MODE_CONNECTOR_HDMIA;
1673 case SIGNAL_TYPE_EDP:
1674 return DRM_MODE_CONNECTOR_eDP;
1675 case SIGNAL_TYPE_RGB:
1676 return DRM_MODE_CONNECTOR_VGA;
1677 case SIGNAL_TYPE_DISPLAY_PORT:
1678 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1679 return DRM_MODE_CONNECTOR_DisplayPort;
1680 case SIGNAL_TYPE_DVI_DUAL_LINK:
1681 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1682 return DRM_MODE_CONNECTOR_DVID;
1683 case SIGNAL_TYPE_VIRTUAL:
1684 return DRM_MODE_CONNECTOR_VIRTUAL;
1685
1686 default:
1687 return DRM_MODE_CONNECTOR_Unknown;
1688 }
1689 }
1690
1691 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
1692 {
1693 const struct drm_connector_helper_funcs *helper =
1694 connector->helper_private;
1695 struct drm_encoder *encoder;
1696 struct amdgpu_encoder *amdgpu_encoder;
1697
1698 encoder = helper->best_encoder(connector);
1699
1700 if (encoder == NULL)
1701 return;
1702
1703 amdgpu_encoder = to_amdgpu_encoder(encoder);
1704
1705 amdgpu_encoder->native_mode.clock = 0;
1706
1707 if (!list_empty(&connector->probed_modes)) {
1708 struct drm_display_mode *preferred_mode = NULL;
1709 list_for_each_entry(preferred_mode,
1710 &connector->probed_modes,
1711 head) {
1712 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
1713 amdgpu_encoder->native_mode = *preferred_mode;
1714 }
1715 break;
1716 }
1717
1718 }
1719 }
1720
1721 static struct drm_display_mode *amdgpu_dm_create_common_mode(
1722 struct drm_encoder *encoder, char *name,
1723 int hdisplay, int vdisplay)
1724 {
1725 struct drm_device *dev = encoder->dev;
1726 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1727 struct drm_display_mode *mode = NULL;
1728 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1729
1730 mode = drm_mode_duplicate(dev, native_mode);
1731
1732 if(mode == NULL)
1733 return NULL;
1734
1735 mode->hdisplay = hdisplay;
1736 mode->vdisplay = vdisplay;
1737 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1738 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
1739
1740 return mode;
1741
1742 }
1743
1744 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
1745 struct drm_connector *connector)
1746 {
1747 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1748 struct drm_display_mode *mode = NULL;
1749 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1750 struct amdgpu_connector *amdgpu_connector =
1751 to_amdgpu_connector(connector);
1752 int i;
1753 int n;
1754 struct mode_size {
1755 char name[DRM_DISPLAY_MODE_LEN];
1756 int w;
1757 int h;
1758 }common_modes[] = {
1759 { "640x480", 640, 480},
1760 { "800x600", 800, 600},
1761 { "1024x768", 1024, 768},
1762 { "1280x720", 1280, 720},
1763 { "1280x800", 1280, 800},
1764 {"1280x1024", 1280, 1024},
1765 { "1440x900", 1440, 900},
1766 {"1680x1050", 1680, 1050},
1767 {"1600x1200", 1600, 1200},
1768 {"1920x1080", 1920, 1080},
1769 {"1920x1200", 1920, 1200}
1770 };
1771
1772 n = sizeof(common_modes) / sizeof(common_modes[0]);
1773
1774 for (i = 0; i < n; i++) {
1775 struct drm_display_mode *curmode = NULL;
1776 bool mode_existed = false;
1777
1778 if (common_modes[i].w > native_mode->hdisplay ||
1779 common_modes[i].h > native_mode->vdisplay ||
1780 (common_modes[i].w == native_mode->hdisplay &&
1781 common_modes[i].h == native_mode->vdisplay))
1782 continue;
1783
1784 list_for_each_entry(curmode, &connector->probed_modes, head) {
1785 if (common_modes[i].w == curmode->hdisplay &&
1786 common_modes[i].h == curmode->vdisplay) {
1787 mode_existed = true;
1788 break;
1789 }
1790 }
1791
1792 if (mode_existed)
1793 continue;
1794
1795 mode = amdgpu_dm_create_common_mode(encoder,
1796 common_modes[i].name, common_modes[i].w,
1797 common_modes[i].h);
1798 drm_mode_probed_add(connector, mode);
1799 amdgpu_connector->num_modes++;
1800 }
1801 }
1802
1803 static void amdgpu_dm_connector_ddc_get_modes(
1804 struct drm_connector *connector,
1805 struct edid *edid)
1806 {
1807 struct amdgpu_connector *amdgpu_connector =
1808 to_amdgpu_connector(connector);
1809
1810 if (edid) {
1811 /* empty probed_modes */
1812 INIT_LIST_HEAD(&connector->probed_modes);
1813 amdgpu_connector->num_modes =
1814 drm_add_edid_modes(connector, edid);
1815
1816 drm_edid_to_eld(connector, edid);
1817
1818 amdgpu_dm_get_native_mode(connector);
1819 } else
1820 amdgpu_connector->num_modes = 0;
1821 }
1822
1823 int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
1824 {
1825 const struct drm_connector_helper_funcs *helper =
1826 connector->helper_private;
1827 struct amdgpu_connector *amdgpu_connector =
1828 to_amdgpu_connector(connector);
1829 struct drm_encoder *encoder;
1830 struct edid *edid = amdgpu_connector->edid;
1831
1832 encoder = helper->best_encoder(connector);
1833
1834 amdgpu_dm_connector_ddc_get_modes(connector, edid);
1835 amdgpu_dm_connector_add_common_modes(encoder, connector);
1836 return amdgpu_connector->num_modes;
1837 }
1838
1839 void amdgpu_dm_connector_init_helper(
1840 struct amdgpu_display_manager *dm,
1841 struct amdgpu_connector *aconnector,
1842 int connector_type,
1843 const struct dc_link *link,
1844 int link_index)
1845 {
1846 struct amdgpu_device *adev = dm->ddev->dev_private;
1847
1848 aconnector->connector_id = link_index;
1849 aconnector->dc_link = link;
1850 aconnector->base.interlace_allowed = true;
1851 aconnector->base.doublescan_allowed = true;
1852 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
1853 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
1854
1855 mutex_init(&aconnector->hpd_lock);
1856
1857 /*configure suport HPD hot plug connector_>polled default value is 0
1858 * which means HPD hot plug not supported*/
1859 switch (connector_type) {
1860 case DRM_MODE_CONNECTOR_HDMIA:
1861 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1862 break;
1863 case DRM_MODE_CONNECTOR_DisplayPort:
1864 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1865 break;
1866 case DRM_MODE_CONNECTOR_DVID:
1867 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
1868 break;
1869 default:
1870 break;
1871 }
1872
1873 drm_object_attach_property(&aconnector->base.base,
1874 dm->ddev->mode_config.scaling_mode_property,
1875 DRM_MODE_SCALE_NONE);
1876
1877 drm_object_attach_property(&aconnector->base.base,
1878 adev->mode_info.underscan_property,
1879 UNDERSCAN_OFF);
1880 drm_object_attach_property(&aconnector->base.base,
1881 adev->mode_info.underscan_hborder_property,
1882 0);
1883 drm_object_attach_property(&aconnector->base.base,
1884 adev->mode_info.underscan_vborder_property,
1885 0);
1886
1887 }
1888
1889 int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
1890 struct i2c_msg *msgs, int num)
1891 {
1892 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
1893 struct i2c_command cmd;
1894 int i;
1895 int result = -EIO;
1896
1897 cmd.payloads = kzalloc(num * sizeof(struct i2c_payload), GFP_KERNEL);
1898
1899 if (!cmd.payloads)
1900 return result;
1901
1902 cmd.number_of_payloads = num;
1903 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1904 cmd.speed = 100;
1905
1906 for (i = 0; i < num; i++) {
1907 cmd.payloads[i].write = (msgs[i].flags & I2C_M_RD);
1908 cmd.payloads[i].address = msgs[i].addr;
1909 cmd.payloads[i].length = msgs[i].len;
1910 cmd.payloads[i].data = msgs[i].buf;
1911 }
1912
1913 if (dc_submit_i2c(i2c->dm->dc, i2c->link_index, &cmd))
1914 result = num;
1915
1916 kfree(cmd.payloads);
1917
1918 return result;
1919 }
1920
1921 u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
1922 {
1923 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1924 }
1925
1926 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
1927 .master_xfer = amdgpu_dm_i2c_xfer,
1928 .functionality = amdgpu_dm_i2c_func,
1929 };
1930
1931 struct amdgpu_i2c_adapter *create_i2c(unsigned int link_index, struct amdgpu_display_manager *dm, int *res)
1932 {
1933 struct amdgpu_i2c_adapter *i2c;
1934
1935 i2c = kzalloc(sizeof (struct amdgpu_i2c_adapter), GFP_KERNEL);
1936 i2c->dm = dm;
1937 i2c->base.owner = THIS_MODULE;
1938 i2c->base.class = I2C_CLASS_DDC;
1939 i2c->base.dev.parent = &dm->adev->pdev->dev;
1940 i2c->base.algo = &amdgpu_dm_i2c_algo;
1941 snprintf(i2c->base.name, sizeof (i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
1942 i2c->link_index = link_index;
1943 i2c_set_adapdata(&i2c->base, i2c);
1944
1945 return i2c;
1946 }
1947
1948 /* Note: this function assumes that dc_link_detect() was called for the
1949 * dc_link which will be represented by this aconnector. */
1950 int amdgpu_dm_connector_init(
1951 struct amdgpu_display_manager *dm,
1952 struct amdgpu_connector *aconnector,
1953 uint32_t link_index,
1954 struct amdgpu_encoder *aencoder)
1955 {
1956 int res = 0;
1957 int connector_type;
1958 struct dc *dc = dm->dc;
1959 const struct dc_link *link = dc_get_link_at_index(dc, link_index);
1960 struct amdgpu_i2c_adapter *i2c;
1961
1962 DRM_DEBUG_KMS("%s()\n", __func__);
1963
1964 i2c = create_i2c(link->link_index, dm, &res);
1965 aconnector->i2c = i2c;
1966 res = i2c_add_adapter(&i2c->base);
1967
1968 if (res) {
1969 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
1970 goto out_free;
1971 }
1972
1973 connector_type = to_drm_connector_type(link->connector_signal);
1974
1975 res = drm_connector_init(
1976 dm->ddev,
1977 &aconnector->base,
1978 &amdgpu_dm_connector_funcs,
1979 connector_type);
1980
1981 if (res) {
1982 DRM_ERROR("connector_init failed\n");
1983 aconnector->connector_id = -1;
1984 goto out_free;
1985 }
1986
1987 drm_connector_helper_add(
1988 &aconnector->base,
1989 &amdgpu_dm_connector_helper_funcs);
1990
1991 amdgpu_dm_connector_init_helper(
1992 dm,
1993 aconnector,
1994 connector_type,
1995 link,
1996 link_index);
1997
1998 drm_mode_connector_attach_encoder(
1999 &aconnector->base, &aencoder->base);
2000
2001 drm_connector_register(&aconnector->base);
2002
2003 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
2004 || connector_type == DRM_MODE_CONNECTOR_eDP)
2005 amdgpu_dm_initialize_mst_connector(dm, aconnector);
2006
2007 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2008 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2009
2010 /* NOTE: this currently will create backlight device even if a panel
2011 * is not connected to the eDP/LVDS connector.
2012 *
2013 * This is less than ideal but we don't have sink information at this
2014 * stage since detection happens after. We can't do detection earlier
2015 * since MST detection needs connectors to be created first.
2016 */
2017 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2018 /* Event if registration failed, we should continue with
2019 * DM initialization because not having a backlight control
2020 * is better then a black screen. */
2021 amdgpu_dm_register_backlight_device(dm);
2022
2023 if (dm->backlight_dev)
2024 dm->backlight_link = link;
2025 }
2026 #endif
2027
2028 out_free:
2029 if (res) {
2030 kfree(i2c);
2031 aconnector->i2c = NULL;
2032 }
2033 return res;
2034 }
2035
2036 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
2037 {
2038 switch (adev->mode_info.num_crtc) {
2039 case 1:
2040 return 0x1;
2041 case 2:
2042 return 0x3;
2043 case 3:
2044 return 0x7;
2045 case 4:
2046 return 0xf;
2047 case 5:
2048 return 0x1f;
2049 case 6:
2050 default:
2051 return 0x3f;
2052 }
2053 }
2054
2055 int amdgpu_dm_encoder_init(
2056 struct drm_device *dev,
2057 struct amdgpu_encoder *aencoder,
2058 uint32_t link_index)
2059 {
2060 struct amdgpu_device *adev = dev->dev_private;
2061
2062 int res = drm_encoder_init(dev,
2063 &aencoder->base,
2064 &amdgpu_dm_encoder_funcs,
2065 DRM_MODE_ENCODER_TMDS,
2066 NULL);
2067
2068 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
2069
2070 if (!res)
2071 aencoder->encoder_id = link_index;
2072 else
2073 aencoder->encoder_id = -1;
2074
2075 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
2076
2077 return res;
2078 }
2079
2080 enum dm_commit_action {
2081 DM_COMMIT_ACTION_NOTHING,
2082 DM_COMMIT_ACTION_RESET,
2083 DM_COMMIT_ACTION_DPMS_ON,
2084 DM_COMMIT_ACTION_DPMS_OFF,
2085 DM_COMMIT_ACTION_SET
2086 };
2087
2088 static enum dm_commit_action get_dm_commit_action(struct drm_crtc_state *state)
2089 {
2090 /* mode changed means either actually mode changed or enabled changed */
2091 /* active changed means dpms changed */
2092
2093 DRM_DEBUG_KMS("crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
2094 state->enable,
2095 state->active,
2096 state->planes_changed,
2097 state->mode_changed,
2098 state->active_changed,
2099 state->connectors_changed);
2100
2101 if (state->mode_changed) {
2102 /* if it is got disabled - call reset mode */
2103 if (!state->enable)
2104 return DM_COMMIT_ACTION_RESET;
2105
2106 if (state->active)
2107 return DM_COMMIT_ACTION_SET;
2108 else
2109 return DM_COMMIT_ACTION_RESET;
2110 } else {
2111 /* ! mode_changed */
2112
2113 /* if it is remain disable - skip it */
2114 if (!state->enable)
2115 return DM_COMMIT_ACTION_NOTHING;
2116
2117 if (state->active && state->connectors_changed)
2118 return DM_COMMIT_ACTION_SET;
2119
2120 if (state->active_changed) {
2121 if (state->active) {
2122 return DM_COMMIT_ACTION_DPMS_ON;
2123 } else {
2124 return DM_COMMIT_ACTION_DPMS_OFF;
2125 }
2126 } else {
2127 /* ! active_changed */
2128 return DM_COMMIT_ACTION_NOTHING;
2129 }
2130 }
2131 }
2132
2133
2134 typedef bool (*predicate)(struct amdgpu_crtc *acrtc);
2135
2136 static void wait_while_pflip_status(struct amdgpu_device *adev,
2137 struct amdgpu_crtc *acrtc, predicate f) {
2138 int count = 0;
2139 while (f(acrtc)) {
2140 /* Spin Wait*/
2141 msleep(1);
2142 count++;
2143 if (count == 1000) {
2144 DRM_ERROR("%s - crtc:%d[%p], pflip_stat:%d, probable hang!\n",
2145 __func__, acrtc->crtc_id,
2146 acrtc,
2147 acrtc->pflip_status);
2148
2149 /* we do not expect to hit this case except on Polaris with PHY PLL
2150 * 1. DP to HDMI passive dongle connected
2151 * 2. unplug (headless)
2152 * 3. plug in DP
2153 * 3a. on plug in, DP will try verify link by training, and training
2154 * would disable PHY PLL which HDMI rely on to drive TG
2155 * 3b. this will cause flip interrupt cannot be generated, and we
2156 * exit when timeout expired. however we do not have code to clean
2157 * up flip, flip clean up will happen when the address is written
2158 * with the restore mode change
2159 */
2160 WARN_ON(1);
2161 break;
2162 }
2163 }
2164
2165 DRM_DEBUG_DRIVER("%s - Finished waiting for:%d msec, crtc:%d[%p], pflip_stat:%d \n",
2166 __func__,
2167 count,
2168 acrtc->crtc_id,
2169 acrtc,
2170 acrtc->pflip_status);
2171 }
2172
2173 static bool pflip_in_progress_predicate(struct amdgpu_crtc *acrtc)
2174 {
2175 return acrtc->pflip_status != AMDGPU_FLIP_NONE;
2176 }
2177
2178 static void manage_dm_interrupts(
2179 struct amdgpu_device *adev,
2180 struct amdgpu_crtc *acrtc,
2181 bool enable)
2182 {
2183 /*
2184 * this is not correct translation but will work as soon as VBLANK
2185 * constant is the same as PFLIP
2186 */
2187 int irq_type =
2188 amdgpu_crtc_idx_to_irq_type(
2189 adev,
2190 acrtc->crtc_id);
2191
2192 if (enable) {
2193 drm_crtc_vblank_on(&acrtc->base);
2194 amdgpu_irq_get(
2195 adev,
2196 &adev->pageflip_irq,
2197 irq_type);
2198 } else {
2199 wait_while_pflip_status(adev, acrtc,
2200 pflip_in_progress_predicate);
2201
2202 amdgpu_irq_put(
2203 adev,
2204 &adev->pageflip_irq,
2205 irq_type);
2206 drm_crtc_vblank_off(&acrtc->base);
2207 }
2208 }
2209
2210
2211 static bool pflip_pending_predicate(struct amdgpu_crtc *acrtc)
2212 {
2213 return acrtc->pflip_status == AMDGPU_FLIP_PENDING;
2214 }
2215
2216 static bool is_scaling_state_different(
2217 const struct dm_connector_state *dm_state,
2218 const struct dm_connector_state *old_dm_state)
2219 {
2220 if (dm_state->scaling != old_dm_state->scaling)
2221 return true;
2222 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
2223 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
2224 return true;
2225 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
2226 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
2227 return true;
2228 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder
2229 || dm_state->underscan_vborder != old_dm_state->underscan_vborder)
2230 return true;
2231 return false;
2232 }
2233
2234 static void remove_stream(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc)
2235 {
2236 /*
2237 * we evade vblanks and pflips on crtc that
2238 * should be changed
2239 */
2240 manage_dm_interrupts(adev, acrtc, false);
2241
2242 /* this is the update mode case */
2243 if (adev->dm.freesync_module)
2244 mod_freesync_remove_stream(adev->dm.freesync_module,
2245 acrtc->stream);
2246
2247 dc_stream_release(acrtc->stream);
2248 acrtc->stream = NULL;
2249 acrtc->otg_inst = -1;
2250 acrtc->enabled = false;
2251 }
2252
2253 int amdgpu_dm_atomic_commit(
2254 struct drm_device *dev,
2255 struct drm_atomic_state *state,
2256 bool nonblock)
2257 {
2258 struct amdgpu_device *adev = dev->dev_private;
2259 struct amdgpu_display_manager *dm = &adev->dm;
2260 struct drm_plane *plane;
2261 struct drm_plane_state *new_plane_state;
2262 struct drm_plane_state *old_plane_state;
2263 uint32_t i;
2264 int32_t ret = 0;
2265 uint32_t commit_streams_count = 0;
2266 uint32_t new_crtcs_count = 0;
2267 uint32_t flip_crtcs_count = 0;
2268 struct drm_crtc *crtc;
2269 struct drm_crtc_state *old_crtc_state;
2270 const struct dc_stream *commit_streams[MAX_STREAMS];
2271 struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
2272 const struct dc_stream *new_stream;
2273 struct drm_crtc *flip_crtcs[MAX_STREAMS];
2274 struct amdgpu_flip_work *work[MAX_STREAMS] = {0};
2275 struct amdgpu_bo *new_abo[MAX_STREAMS] = {0};
2276
2277 /* In this step all new fb would be pinned */
2278
2279 /*
2280 * TODO: Revisit when we support true asynchronous commit.
2281 * Right now we receive async commit only from pageflip, in which case
2282 * we should not pin/unpin the fb here, it should be done in
2283 * amdgpu_crtc_flip and from the vblank irq handler.
2284 */
2285 if (!nonblock) {
2286 ret = drm_atomic_helper_prepare_planes(dev, state);
2287 if (ret)
2288 return ret;
2289 }
2290
2291 /* Page flip if needed */
2292 for_each_plane_in_state(state, plane, new_plane_state, i) {
2293 struct drm_plane_state *old_plane_state = plane->state;
2294 struct drm_crtc *crtc = new_plane_state->crtc;
2295 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2296 struct drm_framebuffer *fb = new_plane_state->fb;
2297 struct drm_crtc_state *crtc_state;
2298
2299 if (!fb || !crtc)
2300 continue;
2301
2302 crtc_state = drm_atomic_get_crtc_state(state, crtc);
2303
2304 if (!crtc_state->planes_changed || !crtc_state->active)
2305 continue;
2306
2307 if (page_flip_needed(
2308 new_plane_state,
2309 old_plane_state,
2310 crtc_state->event,
2311 false)) {
2312 ret = amdgpu_crtc_prepare_flip(crtc,
2313 fb,
2314 crtc_state->event,
2315 acrtc->flip_flags,
2316 drm_crtc_vblank_count(crtc),
2317 &work[flip_crtcs_count],
2318 &new_abo[flip_crtcs_count]);
2319
2320 if (ret) {
2321 /* According to atomic_commit hook API, EINVAL is not allowed */
2322 if (unlikely(ret == -EINVAL))
2323 ret = -ENOMEM;
2324
2325 DRM_ERROR("Atomic commit: Flip for crtc id %d: [%p], "
2326 "failed, errno = %d\n",
2327 acrtc->crtc_id,
2328 acrtc,
2329 ret);
2330 /* cleanup all flip configurations which
2331 * succeeded in this commit
2332 */
2333 for (i = 0; i < flip_crtcs_count; i++)
2334 amdgpu_crtc_cleanup_flip_ctx(
2335 work[i],
2336 new_abo[i]);
2337
2338 return ret;
2339 }
2340
2341 flip_crtcs[flip_crtcs_count] = crtc;
2342 flip_crtcs_count++;
2343 }
2344 }
2345
2346 /*
2347 * This is the point of no return - everything below never fails except
2348 * when the hw goes bonghits. Which means we can commit the new state on
2349 * the software side now.
2350 */
2351
2352 drm_atomic_helper_swap_state(state, true);
2353
2354 /*
2355 * From this point state become old state really. New state is
2356 * initialized to appropriate objects and could be accessed from there
2357 */
2358
2359 /*
2360 * there is no fences usage yet in state. We can skip the following line
2361 * wait_for_fences(dev, state);
2362 */
2363
2364 drm_atomic_helper_update_legacy_modeset_state(dev, state);
2365
2366 /* update changed items */
2367 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
2368 struct amdgpu_crtc *acrtc;
2369 struct amdgpu_connector *aconnector = NULL;
2370 enum dm_commit_action action;
2371 struct drm_crtc_state *new_state = crtc->state;
2372
2373 acrtc = to_amdgpu_crtc(crtc);
2374
2375 aconnector =
2376 amdgpu_dm_find_first_crct_matching_connector(
2377 state,
2378 crtc,
2379 false);
2380
2381 /* handles headless hotplug case, updating new_state and
2382 * aconnector as needed
2383 */
2384
2385 action = get_dm_commit_action(new_state);
2386
2387 switch (action) {
2388 case DM_COMMIT_ACTION_DPMS_ON:
2389 case DM_COMMIT_ACTION_SET: {
2390 struct dm_connector_state *dm_state = NULL;
2391 new_stream = NULL;
2392
2393 if (aconnector)
2394 dm_state = to_dm_connector_state(aconnector->base.state);
2395
2396 new_stream = create_stream_for_sink(
2397 aconnector,
2398 &crtc->state->mode,
2399 dm_state);
2400
2401 DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
2402
2403 if (!new_stream) {
2404 /*
2405 * this could happen because of issues with
2406 * userspace notifications delivery.
2407 * In this case userspace tries to set mode on
2408 * display which is disconnect in fact.
2409 * dc_sink in NULL in this case on aconnector.
2410 * We expect reset mode will come soon.
2411 *
2412 * This can also happen when unplug is done
2413 * during resume sequence ended
2414 *
2415 * In this case, we want to pretend we still
2416 * have a sink to keep the pipe running so that
2417 * hw state is consistent with the sw state
2418 */
2419 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
2420 __func__, acrtc->base.base.id);
2421 break;
2422 }
2423
2424 if (acrtc->stream)
2425 remove_stream(adev, acrtc);
2426
2427 /*
2428 * this loop saves set mode crtcs
2429 * we needed to enable vblanks once all
2430 * resources acquired in dc after dc_commit_streams
2431 */
2432 new_crtcs[new_crtcs_count] = acrtc;
2433 new_crtcs_count++;
2434
2435 acrtc->stream = new_stream;
2436 acrtc->enabled = true;
2437 acrtc->hw_mode = crtc->state->mode;
2438 crtc->hwmode = crtc->state->mode;
2439
2440 break;
2441 }
2442
2443 case DM_COMMIT_ACTION_NOTHING: {
2444 struct dm_connector_state *dm_state = NULL;
2445
2446 if (!aconnector)
2447 break;
2448
2449 dm_state = to_dm_connector_state(aconnector->base.state);
2450
2451 /* Scaling update */
2452 update_stream_scaling_settings(&crtc->state->mode,
2453 dm_state, acrtc->stream);
2454
2455 break;
2456 }
2457 case DM_COMMIT_ACTION_DPMS_OFF:
2458 case DM_COMMIT_ACTION_RESET:
2459 DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
2460 /* i.e. reset mode */
2461 if (acrtc->stream)
2462 remove_stream(adev, acrtc);
2463 break;
2464 } /* switch() */
2465 } /* for_each_crtc_in_state() */
2466
2467 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2468
2469 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2470
2471 if (acrtc->stream) {
2472 commit_streams[commit_streams_count] = acrtc->stream;
2473 ++commit_streams_count;
2474 }
2475 }
2476
2477 /*
2478 * Add streams after required streams from new and replaced streams
2479 * are removed from freesync module
2480 */
2481 if (adev->dm.freesync_module) {
2482 for (i = 0; i < new_crtcs_count; i++) {
2483 struct amdgpu_connector *aconnector = NULL;
2484 new_stream = new_crtcs[i]->stream;
2485 aconnector =
2486 amdgpu_dm_find_first_crct_matching_connector(
2487 state,
2488 &new_crtcs[i]->base,
2489 false);
2490 if (!aconnector) {
2491 DRM_INFO(
2492 "Atomic commit: Failed to find connector for acrtc id:%d "
2493 "skipping freesync init\n",
2494 new_crtcs[i]->crtc_id);
2495 continue;
2496 }
2497
2498 mod_freesync_add_stream(adev->dm.freesync_module,
2499 new_stream, &aconnector->caps);
2500 }
2501 }
2502
2503 /* DC is optimized not to do anything if 'streams' didn't change. */
2504 dc_commit_streams(dm->dc, commit_streams, commit_streams_count);
2505
2506 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2507 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2508
2509 if (acrtc->stream != NULL)
2510 acrtc->otg_inst =
2511 dc_stream_get_status(acrtc->stream)->primary_otg_inst;
2512 }
2513
2514 /* update planes when needed */
2515 for_each_plane_in_state(state, plane, old_plane_state, i) {
2516 struct drm_plane_state *plane_state = plane->state;
2517 struct drm_crtc *crtc = plane_state->crtc;
2518 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2519 struct drm_framebuffer *fb = plane_state->fb;
2520 struct drm_connector *connector;
2521 struct dm_connector_state *dm_state = NULL;
2522 enum dm_commit_action action;
2523
2524 if (!fb || !crtc || !crtc->state->active)
2525 continue;
2526
2527 action = get_dm_commit_action(crtc->state);
2528
2529 /* Surfaces are created under two scenarios:
2530 * 1. This commit is not a page flip.
2531 * 2. This commit is a page flip, and streams are created.
2532 */
2533 if (!page_flip_needed(
2534 plane_state,
2535 old_plane_state,
2536 crtc->state->event, true) ||
2537 action == DM_COMMIT_ACTION_DPMS_ON ||
2538 action == DM_COMMIT_ACTION_SET) {
2539 list_for_each_entry(connector,
2540 &dev->mode_config.connector_list, head) {
2541 if (connector->state->crtc == crtc) {
2542 dm_state = to_dm_connector_state(
2543 connector->state);
2544 break;
2545 }
2546 }
2547
2548 /*
2549 * This situation happens in the following case:
2550 * we are about to get set mode for connector who's only
2551 * possible crtc (in encoder crtc mask) is used by
2552 * another connector, that is why it will try to
2553 * re-assing crtcs in order to make configuration
2554 * supported. For our implementation we need to make all
2555 * encoders support all crtcs, then this issue will
2556 * never arise again. But to guard code from this issue
2557 * check is left.
2558 *
2559 * Also it should be needed when used with actual
2560 * drm_atomic_commit ioctl in future
2561 */
2562 if (!dm_state)
2563 continue;
2564
2565 /*
2566 * if flip is pending (ie, still waiting for fence to return
2567 * before address is submitted) here, we cannot commit_surface
2568 * as commit_surface will pre-maturely write out the future
2569 * address. wait until flip is submitted before proceeding.
2570 */
2571 wait_while_pflip_status(adev, acrtc, pflip_pending_predicate);
2572
2573 dm_dc_surface_commit(dm->dc, crtc);
2574 }
2575 }
2576
2577 for (i = 0; i < new_crtcs_count; i++) {
2578 /*
2579 * loop to enable interrupts on newly arrived crtc
2580 */
2581 struct amdgpu_crtc *acrtc = new_crtcs[i];
2582
2583 if (adev->dm.freesync_module)
2584 mod_freesync_notify_mode_change(
2585 adev->dm.freesync_module, &acrtc->stream, 1);
2586
2587 manage_dm_interrupts(adev, acrtc, true);
2588 dm_crtc_cursor_reset(&acrtc->base);
2589
2590 }
2591
2592 /* Do actual flip */
2593 flip_crtcs_count = 0;
2594 for_each_plane_in_state(state, plane, old_plane_state, i) {
2595 struct drm_plane_state *plane_state = plane->state;
2596 struct drm_crtc *crtc = plane_state->crtc;
2597 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2598 struct drm_framebuffer *fb = plane_state->fb;
2599
2600 if (!fb || !crtc || !crtc->state->planes_changed ||
2601 !crtc->state->active)
2602 continue;
2603
2604 if (page_flip_needed(
2605 plane_state,
2606 old_plane_state,
2607 crtc->state->event,
2608 false)) {
2609 amdgpu_crtc_submit_flip(
2610 crtc,
2611 fb,
2612 work[flip_crtcs_count],
2613 new_abo[i]);
2614 flip_crtcs_count++;
2615 /*clean up the flags for next usage*/
2616 acrtc->flip_flags = 0;
2617 }
2618 }
2619
2620 /* In this state all old framebuffers would be unpinned */
2621
2622 /* TODO: Revisit when we support true asynchronous commit.*/
2623 if (!nonblock)
2624 drm_atomic_helper_cleanup_planes(dev, state);
2625
2626 drm_atomic_state_put(state);
2627
2628 return ret;
2629 }
2630 /*
2631 * This functions handle all cases when set mode does not come upon hotplug.
2632 * This include when the same display is unplugged then plugged back into the
2633 * same port and when we are running without usermode desktop manager supprot
2634 */
2635 void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector)
2636 {
2637 struct drm_crtc *crtc;
2638 struct amdgpu_device *adev = dev->dev_private;
2639 struct dc *dc = adev->dm.dc;
2640 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2641 struct amdgpu_crtc *disconnected_acrtc;
2642 const struct dc_sink *sink;
2643 const struct dc_stream *commit_streams[MAX_STREAMS];
2644 const struct dc_stream *current_stream;
2645 uint32_t commit_streams_count = 0;
2646
2647 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
2648 return;
2649
2650 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
2651
2652 if (!disconnected_acrtc || !disconnected_acrtc->stream)
2653 return;
2654
2655 sink = disconnected_acrtc->stream->sink;
2656
2657 /*
2658 * If the previous sink is not released and different from the current,
2659 * we deduce we are in a state where we can not rely on usermode call
2660 * to turn on the display, so we do it here
2661 */
2662 if (sink != aconnector->dc_sink) {
2663 struct dm_connector_state *dm_state =
2664 to_dm_connector_state(aconnector->base.state);
2665
2666 struct dc_stream *new_stream =
2667 create_stream_for_sink(
2668 aconnector,
2669 &disconnected_acrtc->base.state->mode,
2670 dm_state);
2671
2672 DRM_INFO("Headless hotplug, restoring connector state\n");
2673 /*
2674 * we evade vblanks and pflips on crtc that
2675 * should be changed
2676 */
2677 manage_dm_interrupts(adev, disconnected_acrtc, false);
2678 /* this is the update mode case */
2679
2680 current_stream = disconnected_acrtc->stream;
2681
2682 disconnected_acrtc->stream = new_stream;
2683 disconnected_acrtc->enabled = true;
2684 disconnected_acrtc->hw_mode = disconnected_acrtc->base.state->mode;
2685
2686 commit_streams_count = 0;
2687
2688 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2689 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2690
2691 if (acrtc->stream) {
2692 commit_streams[commit_streams_count] = acrtc->stream;
2693 ++commit_streams_count;
2694 }
2695 }
2696
2697 /* DC is optimized not to do anything if 'streams' didn't change. */
2698 if (!dc_commit_streams(dc, commit_streams,
2699 commit_streams_count)) {
2700 DRM_INFO("Failed to restore connector state!\n");
2701 dc_stream_release(disconnected_acrtc->stream);
2702 disconnected_acrtc->stream = current_stream;
2703 manage_dm_interrupts(adev, disconnected_acrtc, true);
2704 return;
2705 }
2706
2707 if (adev->dm.freesync_module) {
2708 mod_freesync_remove_stream(adev->dm.freesync_module,
2709 current_stream);
2710
2711 mod_freesync_add_stream(adev->dm.freesync_module,
2712 new_stream, &aconnector->caps);
2713 }
2714
2715 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2716 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2717
2718 if (acrtc->stream != NULL) {
2719 acrtc->otg_inst =
2720 dc_stream_get_status(acrtc->stream)->primary_otg_inst;
2721 }
2722 }
2723
2724 dc_stream_release(current_stream);
2725
2726 dm_dc_surface_commit(dc, &disconnected_acrtc->base);
2727
2728 manage_dm_interrupts(adev, disconnected_acrtc, true);
2729 dm_crtc_cursor_reset(&disconnected_acrtc->base);
2730
2731 }
2732 }
2733
2734 static uint32_t add_val_sets_surface(
2735 struct dc_validation_set *val_sets,
2736 uint32_t set_count,
2737 const struct dc_stream *stream,
2738 const struct dc_surface *surface)
2739 {
2740 uint32_t i = 0;
2741
2742 while (i < set_count) {
2743 if (val_sets[i].stream == stream)
2744 break;
2745 ++i;
2746 }
2747
2748 val_sets[i].surfaces[val_sets[i].surface_count] = surface;
2749 val_sets[i].surface_count++;
2750
2751 return val_sets[i].surface_count;
2752 }
2753
2754 static uint32_t update_in_val_sets_stream(
2755 struct dc_validation_set *val_sets,
2756 struct drm_crtc **crtcs,
2757 uint32_t set_count,
2758 const struct dc_stream *old_stream,
2759 const struct dc_stream *new_stream,
2760 struct drm_crtc *crtc)
2761 {
2762 uint32_t i = 0;
2763
2764 while (i < set_count) {
2765 if (val_sets[i].stream == old_stream)
2766 break;
2767 ++i;
2768 }
2769
2770 val_sets[i].stream = new_stream;
2771 crtcs[i] = crtc;
2772
2773 if (i == set_count) {
2774 /* nothing found. add new one to the end */
2775 return set_count + 1;
2776 }
2777
2778 return set_count;
2779 }
2780
2781 static uint32_t remove_from_val_sets(
2782 struct dc_validation_set *val_sets,
2783 uint32_t set_count,
2784 const struct dc_stream *stream)
2785 {
2786 int i;
2787
2788 for (i = 0; i < set_count; i++)
2789 if (val_sets[i].stream == stream)
2790 break;
2791
2792 if (i == set_count) {
2793 /* nothing found */
2794 return set_count;
2795 }
2796
2797 set_count--;
2798
2799 for (; i < set_count; i++) {
2800 val_sets[i] = val_sets[i + 1];
2801 }
2802
2803 return set_count;
2804 }
2805
2806 int amdgpu_dm_atomic_check(struct drm_device *dev,
2807 struct drm_atomic_state *state)
2808 {
2809 struct drm_crtc *crtc;
2810 struct drm_crtc_state *crtc_state;
2811 struct drm_plane *plane;
2812 struct drm_plane_state *plane_state;
2813 int i, j;
2814 int ret;
2815 int set_count;
2816 int new_stream_count;
2817 struct dc_validation_set set[MAX_STREAMS] = {{ 0 }};
2818 struct dc_stream *new_streams[MAX_STREAMS] = { 0 };
2819 struct drm_crtc *crtc_set[MAX_STREAMS] = { 0 };
2820 struct amdgpu_device *adev = dev->dev_private;
2821 struct dc *dc = adev->dm.dc;
2822 bool need_to_validate = false;
2823
2824 ret = drm_atomic_helper_check(dev, state);
2825
2826 if (ret) {
2827 DRM_ERROR("Atomic state validation failed with error :%d !\n",
2828 ret);
2829 return ret;
2830 }
2831
2832 ret = -EINVAL;
2833
2834 /* copy existing configuration */
2835 new_stream_count = 0;
2836 set_count = 0;
2837 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2838
2839 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2840
2841 if (acrtc->stream) {
2842 set[set_count].stream = acrtc->stream;
2843 crtc_set[set_count] = crtc;
2844 ++set_count;
2845 }
2846 }
2847
2848 /* update changed items */
2849 for_each_crtc_in_state(state, crtc, crtc_state, i) {
2850 struct amdgpu_crtc *acrtc = NULL;
2851 struct amdgpu_connector *aconnector = NULL;
2852 enum dm_commit_action action;
2853
2854 acrtc = to_amdgpu_crtc(crtc);
2855
2856 aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc, true);
2857
2858 action = get_dm_commit_action(crtc_state);
2859
2860 switch (action) {
2861 case DM_COMMIT_ACTION_DPMS_ON:
2862 case DM_COMMIT_ACTION_SET: {
2863 struct dc_stream *new_stream = NULL;
2864 struct drm_connector_state *conn_state = NULL;
2865 struct dm_connector_state *dm_state = NULL;
2866
2867 if (aconnector) {
2868 conn_state = drm_atomic_get_connector_state(state, &aconnector->base);
2869 if (IS_ERR(conn_state))
2870 return ret;
2871 dm_state = to_dm_connector_state(conn_state);
2872 }
2873
2874 new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_state);
2875
2876 /*
2877 * we can have no stream on ACTION_SET if a display
2878 * was disconnected during S3, in this case it not and
2879 * error, the OS will be updated after detection, and
2880 * do the right thing on next atomic commit
2881 */
2882 if (!new_stream) {
2883 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
2884 __func__, acrtc->base.base.id);
2885 break;
2886 }
2887
2888 new_streams[new_stream_count] = new_stream;
2889 set_count = update_in_val_sets_stream(
2890 set,
2891 crtc_set,
2892 set_count,
2893 acrtc->stream,
2894 new_stream,
2895 crtc);
2896
2897 new_stream_count++;
2898 need_to_validate = true;
2899 break;
2900 }
2901
2902 case DM_COMMIT_ACTION_NOTHING: {
2903 const struct drm_connector *drm_connector = NULL;
2904 struct drm_connector_state *conn_state = NULL;
2905 struct dm_connector_state *dm_state = NULL;
2906 struct dm_connector_state *old_dm_state = NULL;
2907 struct dc_stream *new_stream;
2908
2909 if (!aconnector)
2910 break;
2911
2912 for_each_connector_in_state(
2913 state, drm_connector, conn_state, j) {
2914 if (&aconnector->base == drm_connector)
2915 break;
2916 }
2917
2918 old_dm_state = to_dm_connector_state(drm_connector->state);
2919 dm_state = to_dm_connector_state(conn_state);
2920
2921 /* Support underscan adjustment*/
2922 if (!is_scaling_state_different(dm_state, old_dm_state))
2923 break;
2924
2925 new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_state);
2926
2927 if (!new_stream) {
2928 DRM_ERROR("%s: Failed to create new stream for crtc %d\n",
2929 __func__, acrtc->base.base.id);
2930 break;
2931 }
2932
2933 new_streams[new_stream_count] = new_stream;
2934 set_count = update_in_val_sets_stream(
2935 set,
2936 crtc_set,
2937 set_count,
2938 acrtc->stream,
2939 new_stream,
2940 crtc);
2941
2942 new_stream_count++;
2943 need_to_validate = true;
2944
2945 break;
2946 }
2947 case DM_COMMIT_ACTION_DPMS_OFF:
2948 case DM_COMMIT_ACTION_RESET:
2949 /* i.e. reset mode */
2950 if (acrtc->stream) {
2951 set_count = remove_from_val_sets(
2952 set,
2953 set_count,
2954 acrtc->stream);
2955 }
2956 break;
2957 }
2958
2959 /*
2960 * TODO revisit when removing commit action
2961 * and looking at atomic flags directly
2962 */
2963
2964 /* commit needs planes right now (for gamma, eg.) */
2965 /* TODO rework commit to chack crtc for gamma change */
2966 ret = drm_atomic_add_affected_planes(state, crtc);
2967 if (ret)
2968 return ret;
2969 }
2970
2971 for (i = 0; i < set_count; i++) {
2972 for_each_plane_in_state(state, plane, plane_state, j) {
2973 struct drm_plane_state *old_plane_state = plane->state;
2974 struct drm_crtc *crtc = plane_state->crtc;
2975 struct drm_framebuffer *fb = plane_state->fb;
2976 struct drm_connector *connector;
2977 struct dm_connector_state *dm_state = NULL;
2978 enum dm_commit_action action;
2979 struct drm_crtc_state *crtc_state;
2980
2981
2982 if (!fb || !crtc || crtc_set[i] != crtc ||
2983 !crtc->state->planes_changed || !crtc->state->active)
2984 continue;
2985
2986 action = get_dm_commit_action(crtc->state);
2987
2988 /* Surfaces are created under two scenarios:
2989 * 1. This commit is not a page flip.
2990 * 2. This commit is a page flip, and streams are created.
2991 */
2992 crtc_state = drm_atomic_get_crtc_state(state, crtc);
2993 if (!page_flip_needed(plane_state, old_plane_state,
2994 crtc_state->event, true) ||
2995 action == DM_COMMIT_ACTION_DPMS_ON ||
2996 action == DM_COMMIT_ACTION_SET) {
2997 struct dc_surface *surface;
2998
2999 list_for_each_entry(connector,
3000 &dev->mode_config.connector_list, head) {
3001 if (connector->state->crtc == crtc) {
3002 dm_state = to_dm_connector_state(
3003 connector->state);
3004 break;
3005 }
3006 }
3007
3008 /*
3009 * This situation happens in the following case:
3010 * we are about to get set mode for connector who's only
3011 * possible crtc (in encoder crtc mask) is used by
3012 * another connector, that is why it will try to
3013 * re-assing crtcs in order to make configuration
3014 * supported. For our implementation we need to make all
3015 * encoders support all crtcs, then this issue will
3016 * never arise again. But to guard code from this issue
3017 * check is left.
3018 *
3019 * Also it should be needed when used with actual
3020 * drm_atomic_commit ioctl in future
3021 */
3022 if (!dm_state)
3023 continue;
3024
3025 surface = dc_create_surface(dc);
3026 fill_plane_attributes(
3027 crtc->dev->dev_private,
3028 surface,
3029 plane_state,
3030 false);
3031
3032 add_val_sets_surface(
3033 set,
3034 set_count,
3035 set[i].stream,
3036 surface);
3037
3038 need_to_validate = true;
3039 }
3040 }
3041 }
3042
3043 if (need_to_validate == false || set_count == 0 ||
3044 dc_validate_resources(dc, set, set_count))
3045 ret = 0;
3046
3047 for (i = 0; i < set_count; i++) {
3048 for (j = 0; j < set[i].surface_count; j++) {
3049 dc_surface_release(set[i].surfaces[j]);
3050 }
3051 }
3052 for (i = 0; i < new_stream_count; i++)
3053 dc_stream_release(new_streams[i]);
3054
3055 if (ret != 0)
3056 DRM_ERROR("Atomic check failed.\n");
3057
3058 return ret;
3059 }
3060
3061 static bool is_dp_capable_without_timing_msa(
3062 struct dc *dc,
3063 struct amdgpu_connector *amdgpu_connector)
3064 {
3065 uint8_t dpcd_data;
3066 bool capable = false;
3067 if (amdgpu_connector->dc_link &&
3068 dc_read_dpcd(dc, amdgpu_connector->dc_link->link_index,
3069 DP_DOWN_STREAM_PORT_COUNT,
3070 &dpcd_data, sizeof(dpcd_data)) )
3071 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
3072
3073 return capable;
3074 }
3075 void amdgpu_dm_add_sink_to_freesync_module(
3076 struct drm_connector *connector,
3077 struct edid *edid)
3078 {
3079 int i;
3080 uint64_t val_capable;
3081 bool edid_check_required;
3082 struct detailed_timing *timing;
3083 struct detailed_non_pixel *data;
3084 struct detailed_data_monitor_range *range;
3085 struct amdgpu_connector *amdgpu_connector =
3086 to_amdgpu_connector(connector);
3087
3088 struct drm_device *dev = connector->dev;
3089 struct amdgpu_device *adev = dev->dev_private;
3090 edid_check_required = false;
3091 if (!amdgpu_connector->dc_sink) {
3092 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
3093 return;
3094 }
3095 if (!adev->dm.freesync_module)
3096 return;
3097 /*
3098 * if edid non zero restrict freesync only for dp and edp
3099 */
3100 if (edid) {
3101 if (amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
3102 || amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
3103 edid_check_required = is_dp_capable_without_timing_msa(
3104 adev->dm.dc,
3105 amdgpu_connector);
3106 }
3107 }
3108 val_capable = 0;
3109 if (edid_check_required == true && (edid->version > 1 ||
3110 (edid->version == 1 && edid->revision > 1))) {
3111 for (i = 0; i < 4; i++) {
3112
3113 timing = &edid->detailed_timings[i];
3114 data = &timing->data.other_data;
3115 range = &data->data.range;
3116 /*
3117 * Check if monitor has continuous frequency mode
3118 */
3119 if (data->type != EDID_DETAIL_MONITOR_RANGE)
3120 continue;
3121 /*
3122 * Check for flag range limits only. If flag == 1 then
3123 * no additional timing information provided.
3124 * Default GTF, GTF Secondary curve and CVT are not
3125 * supported
3126 */
3127 if (range->flags != 1)
3128 continue;
3129
3130 amdgpu_connector->min_vfreq = range->min_vfreq;
3131 amdgpu_connector->max_vfreq = range->max_vfreq;
3132 amdgpu_connector->pixel_clock_mhz =
3133 range->pixel_clock_mhz * 10;
3134 break;
3135 }
3136
3137 if (amdgpu_connector->max_vfreq -
3138 amdgpu_connector->min_vfreq > 10) {
3139 amdgpu_connector->caps.supported = true;
3140 amdgpu_connector->caps.min_refresh_in_micro_hz =
3141 amdgpu_connector->min_vfreq * 1000000;
3142 amdgpu_connector->caps.max_refresh_in_micro_hz =
3143 amdgpu_connector->max_vfreq * 1000000;
3144 val_capable = 1;
3145 }
3146 }
3147
3148 /*
3149 * TODO figure out how to notify user-mode or DRM of freesync caps
3150 * once we figure out how to deal with freesync in an upstreamable
3151 * fashion
3152 */
3153
3154 }
3155
3156 void amdgpu_dm_remove_sink_from_freesync_module(
3157 struct drm_connector *connector)
3158 {
3159 /*
3160 * TODO fill in once we figure out how to deal with freesync in
3161 * an upstreamable fashion
3162 */
3163 }
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