drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "atom.h"
  29
  30 #include "include/bios_parser_types.h"
  31
  32 #include "command_table_helper.h"
  33
  34 bool dal_bios_parser_init_cmd_tbl_helper(
  35         const struct command_table_helper **h,
  36         enum dce_version dce)
  37 {
  38         switch (dce) {
  39         case DCE_VERSION_8_0:
  40                 *h = dal_cmd_tbl_helper_dce80_get_table();
  41                 return true;
  42
  43         case DCE_VERSION_10_0:
  44                 *h = dal_cmd_tbl_helper_dce110_get_table();
  45                 return true;
  46
  47         case DCE_VERSION_11_0:
  48                 *h = dal_cmd_tbl_helper_dce110_get_table();
  49                 return true;
  50
  51         case DCE_VERSION_11_2:
  52                 *h = dal_cmd_tbl_helper_dce112_get_table();
  53                 return true;
  54
  55         default:
  56                 /* Unsupported DCE */
  57                 BREAK_TO_DEBUGGER();
  58                 return false;
  59         }
  60 }
  61
  62 /* real implementations */
  63
  64 bool dal_cmd_table_helper_controller_id_to_atom(
  65         enum controller_id id,
  66         uint8_t *atom_id)
  67 {
  68         if (atom_id == NULL) {
  69                 BREAK_TO_DEBUGGER();
  70                 return false;
  71         }
  72
  73         switch (id) {
  74         case CONTROLLER_ID_D0:
  75                 *atom_id = ATOM_CRTC1;
  76                 return true;
  77         case CONTROLLER_ID_D1:
  78                 *atom_id = ATOM_CRTC2;
  79                 return true;
  80         case CONTROLLER_ID_D2:
  81                 *atom_id = ATOM_CRTC3;
  82                 return true;
  83         case CONTROLLER_ID_D3:
  84                 *atom_id = ATOM_CRTC4;
  85                 return true;
  86         case CONTROLLER_ID_D4:
  87                 *atom_id = ATOM_CRTC5;
  88                 return true;
  89         case CONTROLLER_ID_D5:
  90                 *atom_id = ATOM_CRTC6;
  91                 return true;
  92         case CONTROLLER_ID_UNDERLAY0:
  93                 *atom_id = ATOM_UNDERLAY_PIPE0;
  94                 return true;
  95         case CONTROLLER_ID_UNDEFINED:
  96                 *atom_id = ATOM_CRTC_INVALID;
  97                 return true;
  98         default:
  99                 /* Wrong controller id */
 100                 BREAK_TO_DEBUGGER();
 101                 return false;
 102         }
 103 }
 104
 105 /**
 106 * translate_transmitter_bp_to_atom
 107 *
 108 * @brief
 109 *  Translate the Transmitter to the corresponding ATOM BIOS value
 110 *
 111 * @param
 112 *   input transmitter
 113 *   output digitalTransmitter
 114 *    // =00: Digital Transmitter1 ( UNIPHY linkAB )
 115 *    // =01: Digital Transmitter2 ( UNIPHY linkCD )
 116 *    // =02: Digital Transmitter3 ( UNIPHY linkEF )
 117 */
 118 uint8_t dal_cmd_table_helper_transmitter_bp_to_atom(
 119         enum transmitter t)
 120 {
 121         switch (t) {
 122         case TRANSMITTER_UNIPHY_A:
 123         case TRANSMITTER_UNIPHY_B:
 124         case TRANSMITTER_TRAVIS_LCD:
 125                 return 0;
 126         case TRANSMITTER_UNIPHY_C:
 127         case TRANSMITTER_UNIPHY_D:
 128                 return 1;
 129         case TRANSMITTER_UNIPHY_E:
 130         case TRANSMITTER_UNIPHY_F:
 131                 return 2;
 132         default:
 133                 /* Invalid Transmitter Type! */
 134                 BREAK_TO_DEBUGGER();
 135                 return 0;
 136         }
 137 }
 138
 139 uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom(
 140         enum signal_type s,
 141         bool enable_dp_audio)
 142 {
 143         switch (s) {
 144         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 145         case SIGNAL_TYPE_DVI_DUAL_LINK:
 146                 return ATOM_ENCODER_MODE_DVI;
 147         case SIGNAL_TYPE_HDMI_TYPE_A:
 148                 return ATOM_ENCODER_MODE_HDMI;
 149         case SIGNAL_TYPE_LVDS:
 150                 return ATOM_ENCODER_MODE_LVDS;
 151         case SIGNAL_TYPE_EDP:
 152         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 153         case SIGNAL_TYPE_DISPLAY_PORT:
 154         case SIGNAL_TYPE_VIRTUAL:
 155                 if (enable_dp_audio)
 156                         return ATOM_ENCODER_MODE_DP_AUDIO;
 157                 else
 158                         return ATOM_ENCODER_MODE_DP;
 159         case SIGNAL_TYPE_RGB:
 160                 return ATOM_ENCODER_MODE_CRT;
 161         default:
 162                 return ATOM_ENCODER_MODE_CRT;
 163         }
 164 }
 165
 166 void dal_cmd_table_helper_assign_control_parameter(
 167         const struct command_table_helper *h,
 168         struct bp_encoder_control *control,
 169         DIG_ENCODER_CONTROL_PARAMETERS_V2 *ctrl_param)
 170 {
 171         /* there are three transmitter blocks, each one has two links 4-lanes
 172          * each, A+B, C+D, E+F, Uniphy A, C and E are enumerated as link 0 in
 173          * each transmitter block B, D and F as link 1, third transmitter block
 174          * has non splitable links (UniphyE and UniphyF can not be configured
 175          * separately to drive two different streams)
 176          */
 177         if ((control->transmitter == TRANSMITTER_UNIPHY_B) ||
 178                 (control->transmitter == TRANSMITTER_UNIPHY_D) ||
 179                 (control->transmitter == TRANSMITTER_UNIPHY_F)) {
 180                 /* Bit2: Link Select
 181                  * =0: PHY linkA/C/E
 182                  * =1: PHY linkB/D/F
 183                  */
 184                 ctrl_param->acConfig.ucLinkSel = 1;
 185         }
 186
 187         /* Bit[4:3]: Transmitter Selection
 188          * =00: Digital Transmitter1 ( UNIPHY linkAB )
 189          * =01: Digital Transmitter2 ( UNIPHY linkCD )
 190          * =02: Digital Transmitter3 ( UNIPHY linkEF )
 191          * =03: Reserved
 192          */
 193         ctrl_param->acConfig.ucTransmitterSel =
 194                 (uint8_t)(h->transmitter_bp_to_atom(control->transmitter));
 195
 196         /* We need to convert from KHz units into 10KHz units */
 197         ctrl_param->ucAction = h->encoder_action_to_atom(control->action);
 198         ctrl_param->usPixelClock = cpu_to_le16((uint16_t)(control->pixel_clock / 10));
 199         ctrl_param->ucEncoderMode =
 200                 (uint8_t)(h->encoder_mode_bp_to_atom(
 201                         control->signal, control->enable_dp_audio));
 202         ctrl_param->ucLaneNum = (uint8_t)(control->lanes_number);
 203 }
 204
 205 bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src(
 206         enum clock_source_id id,
 207         uint32_t *ref_clk_src_id)
 208 {
 209         if (ref_clk_src_id == NULL) {
 210                 BREAK_TO_DEBUGGER();
 211                 return false;
 212         }
 213
 214         switch (id) {
 215         case CLOCK_SOURCE_ID_PLL1:
 216                 *ref_clk_src_id = ENCODER_REFCLK_SRC_P1PLL;
 217                 return true;
 218         case CLOCK_SOURCE_ID_PLL2:
 219                 *ref_clk_src_id = ENCODER_REFCLK_SRC_P2PLL;
 220                 return true;
 221         case CLOCK_SOURCE_ID_DCPLL:
 222                 *ref_clk_src_id = ENCODER_REFCLK_SRC_DCPLL;
 223                 return true;
 224         case CLOCK_SOURCE_ID_EXTERNAL:
 225                 *ref_clk_src_id = ENCODER_REFCLK_SRC_EXTCLK;
 226                 return true;
 227         case CLOCK_SOURCE_ID_UNDEFINED:
 228                 *ref_clk_src_id = ENCODER_REFCLK_SRC_INVALID;
 229                 return true;
 230         default:
 231                 /* Unsupported clock source id */
 232                 BREAK_TO_DEBUGGER();
 233                 return false;
 234         }
 235 }
 236
 237 uint8_t dal_cmd_table_helper_encoder_id_to_atom(
 238         enum encoder_id id)
 239 {
 240         switch (id) {
 241         case ENCODER_ID_INTERNAL_LVDS:
 242                 return ENCODER_OBJECT_ID_INTERNAL_LVDS;
 243         case ENCODER_ID_INTERNAL_TMDS1:
 244                 return ENCODER_OBJECT_ID_INTERNAL_TMDS1;
 245         case ENCODER_ID_INTERNAL_TMDS2:
 246                 return ENCODER_OBJECT_ID_INTERNAL_TMDS2;
 247         case ENCODER_ID_INTERNAL_DAC1:
 248                 return ENCODER_OBJECT_ID_INTERNAL_DAC1;
 249         case ENCODER_ID_INTERNAL_DAC2:
 250                 return ENCODER_OBJECT_ID_INTERNAL_DAC2;
 251         case ENCODER_ID_INTERNAL_LVTM1:
 252                 return ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 253         case ENCODER_ID_INTERNAL_HDMI:
 254                 return ENCODER_OBJECT_ID_HDMI_INTERNAL;
 255         case ENCODER_ID_EXTERNAL_TRAVIS:
 256                 return ENCODER_OBJECT_ID_TRAVIS;
 257         case ENCODER_ID_EXTERNAL_NUTMEG:
 258                 return ENCODER_OBJECT_ID_NUTMEG;
 259         case ENCODER_ID_INTERNAL_KLDSCP_TMDS1:
 260                 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
 261         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 262                 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
 263         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 264                 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
 265         case ENCODER_ID_EXTERNAL_MVPU_FPGA:
 266                 return ENCODER_OBJECT_ID_MVPU_FPGA;
 267         case ENCODER_ID_INTERNAL_DDI:
 268                 return ENCODER_OBJECT_ID_INTERNAL_DDI;
 269         case ENCODER_ID_INTERNAL_UNIPHY:
 270                 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY;
 271         case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
 272                 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA;
 273         case ENCODER_ID_INTERNAL_UNIPHY1:
 274                 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1;
 275         case ENCODER_ID_INTERNAL_UNIPHY2:
 276                 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2;
 277         case ENCODER_ID_INTERNAL_UNIPHY3:
 278                 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3;
 279         case ENCODER_ID_INTERNAL_WIRELESS:
 280                 return ENCODER_OBJECT_ID_INTERNAL_VCE;
 281         case ENCODER_ID_UNKNOWN:
 282                 return ENCODER_OBJECT_ID_NONE;
 283         default:
 284                 /* Invalid encoder id */
 285                 BREAK_TO_DEBUGGER();
 286                 return ENCODER_OBJECT_ID_NONE;
 287         }
 288 }