2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dm_services.h"
27 #include "dcn_calcs.h"
28 #include "dcn_calc_auto.h"
30 #include "dal_asic_id.h"
33 #include "dcn10/dcn10_resource.h"
34 #include "dcn_calc_math.h"
36 /* Defaults from spreadsheet rev#247 */
37 const struct dcn_soc_bounding_box dcn10_soc_defaults
= {
39 .sr_exit_time
= 17, /*us*/
40 .sr_enter_plus_exit_time
= 19, /*us*/
41 .urgent_latency
= 4, /*us*/
42 .dram_clock_change_latency
= 17, /*us*/
43 .write_back_latency
= 12, /*us*/
44 .percent_of_ideal_drambw_received_after_urg_latency
= 80, /*%*/
46 /* below default clocks derived from STA target base on
47 * slow-slow corner + 10% margin with voltages aligned to FCLK.
49 * Use these value if fused value doesn't make sense as earlier
50 * part don't have correct value fused */
51 /* default DCF CLK DPM on RV*/
52 .dcfclkv_max0p9
= 655, /* MHz, = 3600/5.5 */
53 .dcfclkv_nom0p8
= 626, /* MHz, = 3600/5.75 */
54 .dcfclkv_mid0p72
= 600, /* MHz, = 3600/6, bypass */
55 .dcfclkv_min0p65
= 300, /* MHz, = 3600/12, bypass */
57 /* default DISP CLK voltage state on RV */
58 .max_dispclk_vmax0p9
= 1108, /* MHz, = 3600/3.25 */
59 .max_dispclk_vnom0p8
= 1029, /* MHz, = 3600/3.5 */
60 .max_dispclk_vmid0p72
= 960, /* MHz, = 3600/3.75 */
61 .max_dispclk_vmin0p65
= 626, /* MHz, = 3600/5.75 */
63 /* default DPP CLK voltage state on RV */
64 .max_dppclk_vmax0p9
= 720, /* MHz, = 3600/5 */
65 .max_dppclk_vnom0p8
= 686, /* MHz, = 3600/5.25 */
66 .max_dppclk_vmid0p72
= 626, /* MHz, = 3600/5.75 */
67 .max_dppclk_vmin0p65
= 400, /* MHz, = 3600/9 */
69 /* default PHY CLK voltage state on RV */
70 .phyclkv_max0p9
= 900, /*MHz*/
71 .phyclkv_nom0p8
= 847, /*MHz*/
72 .phyclkv_mid0p72
= 800, /*MHz*/
73 .phyclkv_min0p65
= 600, /*MHz*/
75 /* BW depend on FCLK, MCLK, # of channels */
77 .fabric_and_dram_bandwidth_vmax0p9
= 38.4f
, /*GB/s*/
78 .fabric_and_dram_bandwidth_vnom0p8
= 34.133f
, /*GB/s*/
79 .fabric_and_dram_bandwidth_vmid0p72
= 29.866f
, /*GB/s*/
80 .fabric_and_dram_bandwidth_vmin0p65
= 12.8f
, /*GB/s*/
82 .fabric_and_dram_bandwidth_vmax0p9 = 19.2f,
83 .fabric_and_dram_bandwidth_vnom0p8 = 17.066f,
84 .fabric_and_dram_bandwidth_vmid0p72 = 14.933f,
85 .fabric_and_dram_bandwidth_vmin0p65 = 12.8f,
88 .number_of_channels
= 2,
90 .socclk
= 208, /*MHz*/
91 .downspreading
= 0.5f
, /*%*/
92 .round_trip_ping_latency_cycles
= 128, /*DCFCLK Cycles*/
93 .urgent_out_of_order_return_per_channel
= 256, /*bytes*/
94 .vmm_page_size
= 4096, /*bytes*/
95 .return_bus_width
= 64, /*bytes*/
96 .max_request_size
= 256, /*bytes*/
98 /* Depends on user class (client vs embedded, workstation, etc) */
99 .percent_disp_bw_limit
= 0.3f
/*%*/
102 const struct dcn_ip_params dcn10_ip_defaults
= {
103 .rob_buffer_size_in_kbyte
= 64,
104 .det_buffer_size_in_kbyte
= 164,
105 .dpp_output_buffer_pixels
= 2560,
106 .opp_output_buffer_lines
= 1,
107 .pixel_chunk_size_in_kbyte
= 8,
108 .pte_enable
= dcn_bw_yes
,
109 .pte_chunk_size
= 2, /*kbytes*/
110 .meta_chunk_size
= 2, /*kbytes*/
111 .writeback_chunk_size
= 2, /*kbytes*/
112 .odm_capability
= dcn_bw_no
,
113 .dsc_capability
= dcn_bw_no
,
114 .line_buffer_size
= 589824, /*bit*/
115 .max_line_buffer_lines
= 12,
116 .is_line_buffer_bpp_fixed
= dcn_bw_no
,
117 .line_buffer_fixed_bpp
= dcn_bw_na
,
118 .writeback_luma_buffer_size
= 12, /*kbytes*/
119 .writeback_chroma_buffer_size
= 8, /*kbytes*/
121 .max_num_writeback
= 2,
122 .max_dchub_topscl_throughput
= 4, /*pixels/dppclk*/
123 .max_pscl_tolb_throughput
= 2, /*pixels/dppclk*/
124 .max_lb_tovscl_throughput
= 4, /*pixels/dppclk*/
125 .max_vscl_tohscl_throughput
= 4, /*pixels/dppclk*/
130 .pte_buffer_size_in_requests
= 42,
131 .dispclk_ramping_margin
= 1, /*%*/
132 .under_scan_factor
= 1.11f
,
133 .max_inter_dcn_tile_repeaters
= 8,
134 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one
= dcn_bw_no
,
135 .bug_forcing_luma_and_chroma_request_to_same_size_fixed
= dcn_bw_no
,
136 .dcfclk_cstate_latency
= 10 /*TODO clone of something else? sr_enter_plus_exit_time?*/
139 static enum dcn_bw_defs
tl_sw_mode_to_bw_defs(enum swizzle_mode_values sw_mode
)
143 return dcn_bw_sw_linear
;
145 return dcn_bw_sw_4_kb_s
;
147 return dcn_bw_sw_4_kb_d
;
149 return dcn_bw_sw_64_kb_s
;
151 return dcn_bw_sw_64_kb_d
;
153 return dcn_bw_sw_var_s
;
155 return dcn_bw_sw_var_d
;
157 return dcn_bw_sw_64_kb_s_t
;
159 return dcn_bw_sw_64_kb_d_t
;
161 return dcn_bw_sw_4_kb_s_x
;
163 return dcn_bw_sw_4_kb_d_x
;
165 return dcn_bw_sw_64_kb_s_x
;
167 return dcn_bw_sw_64_kb_d_x
;
169 return dcn_bw_sw_var_s_x
;
171 return dcn_bw_sw_var_d_x
;
182 BREAK_TO_DEBUGGER(); /*not in formula*/
183 return dcn_bw_sw_4_kb_s
;
187 static int tl_lb_bpp_to_int(enum lb_pixel_depth depth
)
190 case LB_PIXEL_DEPTH_18BPP
:
192 case LB_PIXEL_DEPTH_24BPP
:
194 case LB_PIXEL_DEPTH_30BPP
:
196 case LB_PIXEL_DEPTH_36BPP
:
203 static enum dcn_bw_defs
tl_pixel_format_to_bw_defs(enum surface_pixel_format format
)
206 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555
:
207 case SURFACE_PIXEL_FORMAT_GRPH_RGB565
:
208 return dcn_bw_rgb_sub_16
;
209 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888
:
210 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
:
211 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010
:
212 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
:
213 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
:
214 return dcn_bw_rgb_sub_32
;
215 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616
:
216 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F
:
217 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
:
218 return dcn_bw_rgb_sub_64
;
219 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr
:
220 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb
:
221 return dcn_bw_yuv420_sub_8
;
222 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr
:
223 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb
:
224 return dcn_bw_yuv420_sub_10
;
226 return dcn_bw_rgb_sub_32
;
230 static void pipe_ctx_to_e2e_pipe_params (
231 const struct pipe_ctx
*pipe
,
232 struct _vcs_dpi_display_pipe_params_st
*input
)
234 input
->src
.is_hsplit
= false;
235 if (pipe
->top_pipe
!= NULL
&& pipe
->top_pipe
->plane_state
== pipe
->plane_state
)
236 input
->src
.is_hsplit
= true;
237 else if (pipe
->bottom_pipe
!= NULL
&& pipe
->bottom_pipe
->plane_state
== pipe
->plane_state
)
238 input
->src
.is_hsplit
= true;
240 input
->src
.dcc
= pipe
->plane_state
->dcc
.enable
;
241 input
->src
.dcc_rate
= 1;
242 input
->src
.meta_pitch
= pipe
->plane_state
->dcc
.grph
.meta_pitch
;
243 input
->src
.source_scan
= dm_horz
;
244 input
->src
.sw_mode
= pipe
->plane_state
->tiling_info
.gfx9
.swizzle
;
246 input
->src
.viewport_width
= pipe
->plane_res
.scl_data
.viewport
.width
;
247 input
->src
.viewport_height
= pipe
->plane_res
.scl_data
.viewport
.height
;
248 input
->src
.data_pitch
= pipe
->plane_res
.scl_data
.viewport
.width
;
249 input
->src
.data_pitch_c
= pipe
->plane_res
.scl_data
.viewport
.width
;
250 input
->src
.cur0_src_width
= 128; /* TODO: Cursor calcs, not curently stored */
251 input
->src
.cur0_bpp
= 32;
253 switch (pipe
->plane_state
->tiling_info
.gfx9
.swizzle
) {
254 /* for 4/8/16 high tiles */
256 input
->src
.is_display_sw
= 1;
257 input
->src
.macro_tile_size
= dm_4k_tile
;
261 input
->src
.is_display_sw
= 0;
262 input
->src
.macro_tile_size
= dm_4k_tile
;
267 input
->src
.is_display_sw
= 0;
268 input
->src
.macro_tile_size
= dm_64k_tile
;
272 input
->src
.is_display_sw
= 0;
273 input
->src
.macro_tile_size
= dm_256k_tile
;
276 /* For 64bpp 2 high tiles */
279 input
->src
.is_display_sw
= 1;
280 input
->src
.macro_tile_size
= dm_4k_tile
;
285 input
->src
.is_display_sw
= 1;
286 input
->src
.macro_tile_size
= dm_64k_tile
;
290 input
->src
.is_display_sw
= 1;
291 input
->src
.macro_tile_size
= dm_256k_tile
;
294 /* Unsupported swizzle modes for dcn */
297 ASSERT(0); /* Not supported */
301 switch (pipe
->plane_state
->rotation
) {
302 case ROTATION_ANGLE_0
:
303 case ROTATION_ANGLE_180
:
304 input
->src
.source_scan
= dm_horz
;
306 case ROTATION_ANGLE_90
:
307 case ROTATION_ANGLE_270
:
308 input
->src
.source_scan
= dm_vert
;
311 ASSERT(0); /* Not supported */
315 /* TODO: Fix pixel format mappings */
316 switch (pipe
->plane_state
->format
) {
317 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr
:
318 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb
:
319 input
->src
.source_format
= dm_420_8
;
320 input
->src
.viewport_width_c
= input
->src
.viewport_width
/ 2;
321 input
->src
.viewport_height_c
= input
->src
.viewport_height
/ 2;
323 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr
:
324 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb
:
325 input
->src
.source_format
= dm_420_10
;
326 input
->src
.viewport_width_c
= input
->src
.viewport_width
/ 2;
327 input
->src
.viewport_height_c
= input
->src
.viewport_height
/ 2;
329 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616
:
330 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F
:
331 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
:
332 input
->src
.source_format
= dm_444_64
;
333 input
->src
.viewport_width_c
= input
->src
.viewport_width
;
334 input
->src
.viewport_height_c
= input
->src
.viewport_height
;
337 input
->src
.source_format
= dm_444_32
;
338 input
->src
.viewport_width_c
= input
->src
.viewport_width
;
339 input
->src
.viewport_height_c
= input
->src
.viewport_height
;
343 input
->scale_taps
.htaps
= pipe
->plane_res
.scl_data
.taps
.h_taps
;
344 input
->scale_ratio_depth
.hscl_ratio
= pipe
->plane_res
.scl_data
.ratios
.horz
.value
/4294967296.0;
345 input
->scale_ratio_depth
.vscl_ratio
= pipe
->plane_res
.scl_data
.ratios
.vert
.value
/4294967296.0;
346 input
->scale_ratio_depth
.vinit
= pipe
->plane_res
.scl_data
.inits
.v
.value
/4294967296.0;
347 if (input
->scale_ratio_depth
.vinit
< 1.0)
348 input
->scale_ratio_depth
.vinit
= 1;
349 input
->scale_taps
.vtaps
= pipe
->plane_res
.scl_data
.taps
.v_taps
;
350 input
->scale_taps
.vtaps_c
= pipe
->plane_res
.scl_data
.taps
.v_taps_c
;
351 input
->scale_taps
.htaps_c
= pipe
->plane_res
.scl_data
.taps
.h_taps_c
;
352 input
->scale_ratio_depth
.hscl_ratio_c
= pipe
->plane_res
.scl_data
.ratios
.horz_c
.value
/4294967296.0;
353 input
->scale_ratio_depth
.vscl_ratio_c
= pipe
->plane_res
.scl_data
.ratios
.vert_c
.value
/4294967296.0;
354 input
->scale_ratio_depth
.vinit_c
= pipe
->plane_res
.scl_data
.inits
.v_c
.value
/4294967296.0;
355 if (input
->scale_ratio_depth
.vinit_c
< 1.0)
356 input
->scale_ratio_depth
.vinit_c
= 1;
357 switch (pipe
->plane_res
.scl_data
.lb_params
.depth
) {
358 case LB_PIXEL_DEPTH_30BPP
:
359 input
->scale_ratio_depth
.lb_depth
= 30; break;
360 case LB_PIXEL_DEPTH_36BPP
:
361 input
->scale_ratio_depth
.lb_depth
= 36; break;
363 input
->scale_ratio_depth
.lb_depth
= 24; break;
367 input
->dest
.vactive
= pipe
->stream
->timing
.v_addressable
+ pipe
->stream
->timing
.v_border_top
368 + pipe
->stream
->timing
.v_border_bottom
;
370 input
->dest
.recout_width
= pipe
->plane_res
.scl_data
.recout
.width
;
371 input
->dest
.recout_height
= pipe
->plane_res
.scl_data
.recout
.height
;
373 input
->dest
.full_recout_width
= pipe
->plane_res
.scl_data
.recout
.width
;
374 input
->dest
.full_recout_height
= pipe
->plane_res
.scl_data
.recout
.height
;
376 input
->dest
.htotal
= pipe
->stream
->timing
.h_total
;
377 input
->dest
.hblank_start
= input
->dest
.htotal
- pipe
->stream
->timing
.h_front_porch
;
378 input
->dest
.hblank_end
= input
->dest
.hblank_start
379 - pipe
->stream
->timing
.h_addressable
380 - pipe
->stream
->timing
.h_border_left
381 - pipe
->stream
->timing
.h_border_right
;
383 input
->dest
.vtotal
= pipe
->stream
->timing
.v_total
;
384 input
->dest
.vblank_start
= input
->dest
.vtotal
- pipe
->stream
->timing
.v_front_porch
;
385 input
->dest
.vblank_end
= input
->dest
.vblank_start
386 - pipe
->stream
->timing
.v_addressable
387 - pipe
->stream
->timing
.v_border_bottom
388 - pipe
->stream
->timing
.v_border_top
;
389 input
->dest
.pixel_rate_mhz
= pipe
->stream
->timing
.pix_clk_khz
/1000.0;
390 input
->dest
.vstartup_start
= pipe
->pipe_dlg_param
.vstartup_start
;
391 input
->dest
.vupdate_offset
= pipe
->pipe_dlg_param
.vupdate_offset
;
392 input
->dest
.vupdate_offset
= pipe
->pipe_dlg_param
.vupdate_offset
;
393 input
->dest
.vupdate_width
= pipe
->pipe_dlg_param
.vupdate_width
;
397 static void dcn_bw_calc_rq_dlg_ttu(
399 const struct dcn_bw_internal_vars
*v
,
400 struct pipe_ctx
*pipe
,
403 struct display_mode_lib
*dml
= (struct display_mode_lib
*)(&dc
->dml
);
404 struct _vcs_dpi_display_dlg_regs_st
*dlg_regs
= &pipe
->dlg_regs
;
405 struct _vcs_dpi_display_ttu_regs_st
*ttu_regs
= &pipe
->ttu_regs
;
406 struct _vcs_dpi_display_rq_regs_st
*rq_regs
= &pipe
->rq_regs
;
407 struct _vcs_dpi_display_rq_params_st rq_param
= {0};
408 struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param
= {0};
409 struct _vcs_dpi_display_e2e_pipe_params_st input
= { { { 0 } } };
410 float total_active_bw
= 0;
411 float total_prefetch_bw
= 0;
412 int total_flip_bytes
= 0;
415 for (i
= 0; i
< number_of_planes
; i
++) {
416 total_active_bw
+= v
->read_bandwidth
[i
];
417 total_prefetch_bw
+= v
->prefetch_bandwidth
[i
];
418 total_flip_bytes
+= v
->total_immediate_flip_bytes
[i
];
420 dlg_sys_param
.total_flip_bw
= v
->return_bw
- dcn_bw_max2(total_active_bw
, total_prefetch_bw
);
421 if (dlg_sys_param
.total_flip_bw
< 0.0)
422 dlg_sys_param
.total_flip_bw
= 0;
424 dlg_sys_param
.t_mclk_wm_us
= v
->dram_clock_change_watermark
;
425 dlg_sys_param
.t_sr_wm_us
= v
->stutter_enter_plus_exit_watermark
;
426 dlg_sys_param
.t_urg_wm_us
= v
->urgent_watermark
;
427 dlg_sys_param
.t_extra_us
= v
->urgent_extra_latency
;
428 dlg_sys_param
.deepsleep_dcfclk_mhz
= v
->dcf_clk_deep_sleep
;
429 dlg_sys_param
.total_flip_bytes
= total_flip_bytes
;
431 pipe_ctx_to_e2e_pipe_params(pipe
, &input
.pipe
);
432 input
.clks_cfg
.dcfclk_mhz
= v
->dcfclk
;
433 input
.clks_cfg
.dispclk_mhz
= v
->dispclk
;
434 input
.clks_cfg
.dppclk_mhz
= v
->dppclk
;
435 input
.clks_cfg
.refclk_mhz
= dc
->res_pool
->ref_clock_inKhz
/1000;
436 input
.clks_cfg
.socclk_mhz
= v
->socclk
;
437 input
.clks_cfg
.voltage
= v
->voltage_level
;
438 // dc->dml.logger = pool->base.logger;
439 input
.dout
.output_format
= (v
->output_format
[in_idx
] == dcn_bw_420
) ? dm_420
: dm_444
;
440 input
.dout
.output_type
= (v
->output
[in_idx
] == dcn_bw_hdmi
) ? dm_hdmi
: dm_dp
;
441 //input[in_idx].dout.output_standard;
442 switch (v
->output_deep_color
[in_idx
]) {
443 case dcn_bw_encoder_12bpc
:
444 input
.dout
.output_bpc
= dm_out_12
;
446 case dcn_bw_encoder_10bpc
:
447 input
.dout
.output_bpc
= dm_out_10
;
449 case dcn_bw_encoder_8bpc
:
451 input
.dout
.output_bpc
= dm_out_8
;
455 /*todo: soc->sr_enter_plus_exit_time??*/
456 dlg_sys_param
.t_srx_delay_us
= dc
->dcn_ip
->dcfclk_cstate_latency
/ v
->dcf_clk_deep_sleep
;
458 dml1_rq_dlg_get_rq_params(dml
, &rq_param
, input
.pipe
.src
);
459 dml1_extract_rq_regs(dml
, rq_regs
, rq_param
);
460 dml1_rq_dlg_get_dlg_params(
469 v
->pte_enable
== dcn_bw_yes
,
470 pipe
->plane_state
->flip_immediate
);
473 static void split_stream_across_pipes(
474 struct resource_context
*res_ctx
,
475 const struct resource_pool
*pool
,
476 struct pipe_ctx
*primary_pipe
,
477 struct pipe_ctx
*secondary_pipe
)
479 int pipe_idx
= secondary_pipe
->pipe_idx
;
481 if (!primary_pipe
->plane_state
)
484 *secondary_pipe
= *primary_pipe
;
486 secondary_pipe
->pipe_idx
= pipe_idx
;
487 secondary_pipe
->plane_res
.mi
= pool
->mis
[secondary_pipe
->pipe_idx
];
488 secondary_pipe
->plane_res
.hubp
= pool
->hubps
[secondary_pipe
->pipe_idx
];
489 secondary_pipe
->plane_res
.ipp
= pool
->ipps
[secondary_pipe
->pipe_idx
];
490 secondary_pipe
->plane_res
.xfm
= pool
->transforms
[secondary_pipe
->pipe_idx
];
491 secondary_pipe
->plane_res
.dpp
= pool
->dpps
[secondary_pipe
->pipe_idx
];
492 if (primary_pipe
->bottom_pipe
) {
493 ASSERT(primary_pipe
->bottom_pipe
!= secondary_pipe
);
494 secondary_pipe
->bottom_pipe
= primary_pipe
->bottom_pipe
;
495 secondary_pipe
->bottom_pipe
->top_pipe
= secondary_pipe
;
497 primary_pipe
->bottom_pipe
= secondary_pipe
;
498 secondary_pipe
->top_pipe
= primary_pipe
;
500 resource_build_scaling_params(primary_pipe
);
501 resource_build_scaling_params(secondary_pipe
);
504 static void calc_wm_sets_and_perf_params(
505 struct dc_state
*context
,
506 struct dcn_bw_internal_vars
*v
)
508 /* Calculate set A last to keep internal var state consistent for required config */
509 if (v
->voltage_level
< 2) {
510 v
->fabric_and_dram_bandwidth_per_state
[1] = v
->fabric_and_dram_bandwidth_vnom0p8
;
511 v
->fabric_and_dram_bandwidth_per_state
[0] = v
->fabric_and_dram_bandwidth_vnom0p8
;
512 v
->fabric_and_dram_bandwidth
= v
->fabric_and_dram_bandwidth_vnom0p8
;
513 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v
);
515 context
->bw
.dcn
.watermarks
.b
.cstate_pstate
.cstate_exit_ns
=
516 v
->stutter_exit_watermark
* 1000;
517 context
->bw
.dcn
.watermarks
.b
.cstate_pstate
.cstate_enter_plus_exit_ns
=
518 v
->stutter_enter_plus_exit_watermark
* 1000;
519 context
->bw
.dcn
.watermarks
.b
.cstate_pstate
.pstate_change_ns
=
520 v
->dram_clock_change_watermark
* 1000;
521 context
->bw
.dcn
.watermarks
.b
.pte_meta_urgent_ns
= v
->ptemeta_urgent_watermark
* 1000;
522 context
->bw
.dcn
.watermarks
.b
.urgent_ns
= v
->urgent_watermark
* 1000;
524 v
->dcfclk_per_state
[1] = v
->dcfclkv_nom0p8
;
525 v
->dcfclk_per_state
[0] = v
->dcfclkv_nom0p8
;
526 v
->dcfclk
= v
->dcfclkv_nom0p8
;
527 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v
);
529 context
->bw
.dcn
.watermarks
.c
.cstate_pstate
.cstate_exit_ns
=
530 v
->stutter_exit_watermark
* 1000;
531 context
->bw
.dcn
.watermarks
.c
.cstate_pstate
.cstate_enter_plus_exit_ns
=
532 v
->stutter_enter_plus_exit_watermark
* 1000;
533 context
->bw
.dcn
.watermarks
.c
.cstate_pstate
.pstate_change_ns
=
534 v
->dram_clock_change_watermark
* 1000;
535 context
->bw
.dcn
.watermarks
.c
.pte_meta_urgent_ns
= v
->ptemeta_urgent_watermark
* 1000;
536 context
->bw
.dcn
.watermarks
.c
.urgent_ns
= v
->urgent_watermark
* 1000;
539 if (v
->voltage_level
< 3) {
540 v
->fabric_and_dram_bandwidth_per_state
[2] = v
->fabric_and_dram_bandwidth_vmax0p9
;
541 v
->fabric_and_dram_bandwidth_per_state
[1] = v
->fabric_and_dram_bandwidth_vmax0p9
;
542 v
->fabric_and_dram_bandwidth_per_state
[0] = v
->fabric_and_dram_bandwidth_vmax0p9
;
543 v
->fabric_and_dram_bandwidth
= v
->fabric_and_dram_bandwidth_vmax0p9
;
544 v
->dcfclk_per_state
[2] = v
->dcfclkv_max0p9
;
545 v
->dcfclk_per_state
[1] = v
->dcfclkv_max0p9
;
546 v
->dcfclk_per_state
[0] = v
->dcfclkv_max0p9
;
547 v
->dcfclk
= v
->dcfclkv_max0p9
;
548 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v
);
550 context
->bw
.dcn
.watermarks
.d
.cstate_pstate
.cstate_exit_ns
=
551 v
->stutter_exit_watermark
* 1000;
552 context
->bw
.dcn
.watermarks
.d
.cstate_pstate
.cstate_enter_plus_exit_ns
=
553 v
->stutter_enter_plus_exit_watermark
* 1000;
554 context
->bw
.dcn
.watermarks
.d
.cstate_pstate
.pstate_change_ns
=
555 v
->dram_clock_change_watermark
* 1000;
556 context
->bw
.dcn
.watermarks
.d
.pte_meta_urgent_ns
= v
->ptemeta_urgent_watermark
* 1000;
557 context
->bw
.dcn
.watermarks
.d
.urgent_ns
= v
->urgent_watermark
* 1000;
560 v
->fabric_and_dram_bandwidth_per_state
[2] = v
->fabric_and_dram_bandwidth_vnom0p8
;
561 v
->fabric_and_dram_bandwidth_per_state
[1] = v
->fabric_and_dram_bandwidth_vmid0p72
;
562 v
->fabric_and_dram_bandwidth_per_state
[0] = v
->fabric_and_dram_bandwidth_vmin0p65
;
563 v
->fabric_and_dram_bandwidth
= v
->fabric_and_dram_bandwidth_per_state
[v
->voltage_level
];
564 v
->dcfclk_per_state
[2] = v
->dcfclkv_nom0p8
;
565 v
->dcfclk_per_state
[1] = v
->dcfclkv_mid0p72
;
566 v
->dcfclk_per_state
[0] = v
->dcfclkv_min0p65
;
567 v
->dcfclk
= v
->dcfclk_per_state
[v
->voltage_level
];
568 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v
);
570 context
->bw
.dcn
.watermarks
.a
.cstate_pstate
.cstate_exit_ns
=
571 v
->stutter_exit_watermark
* 1000;
572 context
->bw
.dcn
.watermarks
.a
.cstate_pstate
.cstate_enter_plus_exit_ns
=
573 v
->stutter_enter_plus_exit_watermark
* 1000;
574 context
->bw
.dcn
.watermarks
.a
.cstate_pstate
.pstate_change_ns
=
575 v
->dram_clock_change_watermark
* 1000;
576 context
->bw
.dcn
.watermarks
.a
.pte_meta_urgent_ns
= v
->ptemeta_urgent_watermark
* 1000;
577 context
->bw
.dcn
.watermarks
.a
.urgent_ns
= v
->urgent_watermark
* 1000;
578 if (v
->voltage_level
>= 2) {
579 context
->bw
.dcn
.watermarks
.b
= context
->bw
.dcn
.watermarks
.a
;
580 context
->bw
.dcn
.watermarks
.c
= context
->bw
.dcn
.watermarks
.a
;
582 if (v
->voltage_level
>= 3)
583 context
->bw
.dcn
.watermarks
.d
= context
->bw
.dcn
.watermarks
.a
;
586 static bool dcn_bw_apply_registry_override(struct dc
*dc
)
588 bool updated
= false;
591 if ((int)(dc
->dcn_soc
->sr_exit_time
* 1000) != dc
->debug
.sr_exit_time_ns
592 && dc
->debug
.sr_exit_time_ns
) {
594 dc
->dcn_soc
->sr_exit_time
= dc
->debug
.sr_exit_time_ns
/ 1000.0;
597 if ((int)(dc
->dcn_soc
->sr_enter_plus_exit_time
* 1000)
598 != dc
->debug
.sr_enter_plus_exit_time_ns
599 && dc
->debug
.sr_enter_plus_exit_time_ns
) {
601 dc
->dcn_soc
->sr_enter_plus_exit_time
=
602 dc
->debug
.sr_enter_plus_exit_time_ns
/ 1000.0;
605 if ((int)(dc
->dcn_soc
->urgent_latency
* 1000) != dc
->debug
.urgent_latency_ns
606 && dc
->debug
.urgent_latency_ns
) {
608 dc
->dcn_soc
->urgent_latency
= dc
->debug
.urgent_latency_ns
/ 1000.0;
611 if ((int)(dc
->dcn_soc
->percent_of_ideal_drambw_received_after_urg_latency
* 1000)
612 != dc
->debug
.percent_of_ideal_drambw
613 && dc
->debug
.percent_of_ideal_drambw
) {
615 dc
->dcn_soc
->percent_of_ideal_drambw_received_after_urg_latency
=
616 dc
->debug
.percent_of_ideal_drambw
;
619 if ((int)(dc
->dcn_soc
->dram_clock_change_latency
* 1000)
620 != dc
->debug
.dram_clock_change_latency_ns
621 && dc
->debug
.dram_clock_change_latency_ns
) {
623 dc
->dcn_soc
->dram_clock_change_latency
=
624 dc
->debug
.dram_clock_change_latency_ns
/ 1000.0;
631 void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars
*v
)
634 * disable optional pipe split by lower dispclk bounding box
637 v
->max_dispclk
[0] = v
->max_dppclk_vmin0p65
;
640 void hack_force_pipe_split(struct dcn_bw_internal_vars
*v
,
641 unsigned int pixel_rate_khz
)
643 float pixel_rate_mhz
= pixel_rate_khz
/ 1000;
646 * force enabling pipe split by lower dpp clock for DPM0 to just
647 * below the specify pixel_rate, so bw calc would split pipe.
649 if (pixel_rate_mhz
< v
->max_dppclk
[0])
650 v
->max_dppclk
[0] = pixel_rate_mhz
;
653 void hack_bounding_box(struct dcn_bw_internal_vars
*v
,
654 struct dc_debug
*dbg
,
655 struct dc_state
*context
)
657 if (dbg
->pipe_split_policy
== MPC_SPLIT_AVOID
) {
658 hack_disable_optional_pipe_split(v
);
661 if (dbg
->pipe_split_policy
== MPC_SPLIT_AVOID_MULT_DISP
&&
662 context
->stream_count
>= 2) {
663 hack_disable_optional_pipe_split(v
);
666 if (context
->stream_count
== 1 &&
667 dbg
->force_single_disp_pipe_split
) {
668 struct dc_stream_state
*stream0
= context
->streams
[0];
670 hack_force_pipe_split(v
, stream0
->timing
.pix_clk_khz
);
674 bool dcn_validate_bandwidth(
676 struct dc_state
*context
)
678 const struct resource_pool
*pool
= dc
->res_pool
;
679 struct dcn_bw_internal_vars
*v
= &context
->dcn_bw_vars
;
681 int vesa_sync_start
, asic_blank_end
, asic_blank_start
;
685 PERFORMANCE_TRACE_START();
686 if (dcn_bw_apply_registry_override(dc
))
687 dcn_bw_sync_calcs_and_dml(dc
);
689 memset(v
, 0, sizeof(*v
));
691 v
->sr_exit_time
= dc
->dcn_soc
->sr_exit_time
;
692 v
->sr_enter_plus_exit_time
= dc
->dcn_soc
->sr_enter_plus_exit_time
;
693 v
->urgent_latency
= dc
->dcn_soc
->urgent_latency
;
694 v
->write_back_latency
= dc
->dcn_soc
->write_back_latency
;
695 v
->percent_of_ideal_drambw_received_after_urg_latency
=
696 dc
->dcn_soc
->percent_of_ideal_drambw_received_after_urg_latency
;
698 v
->dcfclkv_min0p65
= dc
->dcn_soc
->dcfclkv_min0p65
;
699 v
->dcfclkv_mid0p72
= dc
->dcn_soc
->dcfclkv_mid0p72
;
700 v
->dcfclkv_nom0p8
= dc
->dcn_soc
->dcfclkv_nom0p8
;
701 v
->dcfclkv_max0p9
= dc
->dcn_soc
->dcfclkv_max0p9
;
703 v
->max_dispclk_vmin0p65
= dc
->dcn_soc
->max_dispclk_vmin0p65
;
704 v
->max_dispclk_vmid0p72
= dc
->dcn_soc
->max_dispclk_vmid0p72
;
705 v
->max_dispclk_vnom0p8
= dc
->dcn_soc
->max_dispclk_vnom0p8
;
706 v
->max_dispclk_vmax0p9
= dc
->dcn_soc
->max_dispclk_vmax0p9
;
708 v
->max_dppclk_vmin0p65
= dc
->dcn_soc
->max_dppclk_vmin0p65
;
709 v
->max_dppclk_vmid0p72
= dc
->dcn_soc
->max_dppclk_vmid0p72
;
710 v
->max_dppclk_vnom0p8
= dc
->dcn_soc
->max_dppclk_vnom0p8
;
711 v
->max_dppclk_vmax0p9
= dc
->dcn_soc
->max_dppclk_vmax0p9
;
713 v
->socclk
= dc
->dcn_soc
->socclk
;
715 v
->fabric_and_dram_bandwidth_vmin0p65
= dc
->dcn_soc
->fabric_and_dram_bandwidth_vmin0p65
;
716 v
->fabric_and_dram_bandwidth_vmid0p72
= dc
->dcn_soc
->fabric_and_dram_bandwidth_vmid0p72
;
717 v
->fabric_and_dram_bandwidth_vnom0p8
= dc
->dcn_soc
->fabric_and_dram_bandwidth_vnom0p8
;
718 v
->fabric_and_dram_bandwidth_vmax0p9
= dc
->dcn_soc
->fabric_and_dram_bandwidth_vmax0p9
;
720 v
->phyclkv_min0p65
= dc
->dcn_soc
->phyclkv_min0p65
;
721 v
->phyclkv_mid0p72
= dc
->dcn_soc
->phyclkv_mid0p72
;
722 v
->phyclkv_nom0p8
= dc
->dcn_soc
->phyclkv_nom0p8
;
723 v
->phyclkv_max0p9
= dc
->dcn_soc
->phyclkv_max0p9
;
725 v
->downspreading
= dc
->dcn_soc
->downspreading
;
726 v
->round_trip_ping_latency_cycles
= dc
->dcn_soc
->round_trip_ping_latency_cycles
;
727 v
->urgent_out_of_order_return_per_channel
= dc
->dcn_soc
->urgent_out_of_order_return_per_channel
;
728 v
->number_of_channels
= dc
->dcn_soc
->number_of_channels
;
729 v
->vmm_page_size
= dc
->dcn_soc
->vmm_page_size
;
730 v
->dram_clock_change_latency
= dc
->dcn_soc
->dram_clock_change_latency
;
731 v
->return_bus_width
= dc
->dcn_soc
->return_bus_width
;
733 v
->rob_buffer_size_in_kbyte
= dc
->dcn_ip
->rob_buffer_size_in_kbyte
;
734 v
->det_buffer_size_in_kbyte
= dc
->dcn_ip
->det_buffer_size_in_kbyte
;
735 v
->dpp_output_buffer_pixels
= dc
->dcn_ip
->dpp_output_buffer_pixels
;
736 v
->opp_output_buffer_lines
= dc
->dcn_ip
->opp_output_buffer_lines
;
737 v
->pixel_chunk_size_in_kbyte
= dc
->dcn_ip
->pixel_chunk_size_in_kbyte
;
738 v
->pte_enable
= dc
->dcn_ip
->pte_enable
;
739 v
->pte_chunk_size
= dc
->dcn_ip
->pte_chunk_size
;
740 v
->meta_chunk_size
= dc
->dcn_ip
->meta_chunk_size
;
741 v
->writeback_chunk_size
= dc
->dcn_ip
->writeback_chunk_size
;
742 v
->odm_capability
= dc
->dcn_ip
->odm_capability
;
743 v
->dsc_capability
= dc
->dcn_ip
->dsc_capability
;
744 v
->line_buffer_size
= dc
->dcn_ip
->line_buffer_size
;
745 v
->is_line_buffer_bpp_fixed
= dc
->dcn_ip
->is_line_buffer_bpp_fixed
;
746 v
->line_buffer_fixed_bpp
= dc
->dcn_ip
->line_buffer_fixed_bpp
;
747 v
->max_line_buffer_lines
= dc
->dcn_ip
->max_line_buffer_lines
;
748 v
->writeback_luma_buffer_size
= dc
->dcn_ip
->writeback_luma_buffer_size
;
749 v
->writeback_chroma_buffer_size
= dc
->dcn_ip
->writeback_chroma_buffer_size
;
750 v
->max_num_dpp
= dc
->dcn_ip
->max_num_dpp
;
751 v
->max_num_writeback
= dc
->dcn_ip
->max_num_writeback
;
752 v
->max_dchub_topscl_throughput
= dc
->dcn_ip
->max_dchub_topscl_throughput
;
753 v
->max_pscl_tolb_throughput
= dc
->dcn_ip
->max_pscl_tolb_throughput
;
754 v
->max_lb_tovscl_throughput
= dc
->dcn_ip
->max_lb_tovscl_throughput
;
755 v
->max_vscl_tohscl_throughput
= dc
->dcn_ip
->max_vscl_tohscl_throughput
;
756 v
->max_hscl_ratio
= dc
->dcn_ip
->max_hscl_ratio
;
757 v
->max_vscl_ratio
= dc
->dcn_ip
->max_vscl_ratio
;
758 v
->max_hscl_taps
= dc
->dcn_ip
->max_hscl_taps
;
759 v
->max_vscl_taps
= dc
->dcn_ip
->max_vscl_taps
;
760 v
->under_scan_factor
= dc
->dcn_ip
->under_scan_factor
;
761 v
->pte_buffer_size_in_requests
= dc
->dcn_ip
->pte_buffer_size_in_requests
;
762 v
->dispclk_ramping_margin
= dc
->dcn_ip
->dispclk_ramping_margin
;
763 v
->max_inter_dcn_tile_repeaters
= dc
->dcn_ip
->max_inter_dcn_tile_repeaters
;
764 v
->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one
=
765 dc
->dcn_ip
->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one
;
766 v
->bug_forcing_luma_and_chroma_request_to_same_size_fixed
=
767 dc
->dcn_ip
->bug_forcing_luma_and_chroma_request_to_same_size_fixed
;
769 v
->voltage
[5] = dcn_bw_no_support
;
770 v
->voltage
[4] = dcn_bw_v_max0p9
;
771 v
->voltage
[3] = dcn_bw_v_max0p9
;
772 v
->voltage
[2] = dcn_bw_v_nom0p8
;
773 v
->voltage
[1] = dcn_bw_v_mid0p72
;
774 v
->voltage
[0] = dcn_bw_v_min0p65
;
775 v
->fabric_and_dram_bandwidth_per_state
[5] = v
->fabric_and_dram_bandwidth_vmax0p9
;
776 v
->fabric_and_dram_bandwidth_per_state
[4] = v
->fabric_and_dram_bandwidth_vmax0p9
;
777 v
->fabric_and_dram_bandwidth_per_state
[3] = v
->fabric_and_dram_bandwidth_vmax0p9
;
778 v
->fabric_and_dram_bandwidth_per_state
[2] = v
->fabric_and_dram_bandwidth_vnom0p8
;
779 v
->fabric_and_dram_bandwidth_per_state
[1] = v
->fabric_and_dram_bandwidth_vmid0p72
;
780 v
->fabric_and_dram_bandwidth_per_state
[0] = v
->fabric_and_dram_bandwidth_vmin0p65
;
781 v
->dcfclk_per_state
[5] = v
->dcfclkv_max0p9
;
782 v
->dcfclk_per_state
[4] = v
->dcfclkv_max0p9
;
783 v
->dcfclk_per_state
[3] = v
->dcfclkv_max0p9
;
784 v
->dcfclk_per_state
[2] = v
->dcfclkv_nom0p8
;
785 v
->dcfclk_per_state
[1] = v
->dcfclkv_mid0p72
;
786 v
->dcfclk_per_state
[0] = v
->dcfclkv_min0p65
;
787 v
->max_dispclk
[5] = v
->max_dispclk_vmax0p9
;
788 v
->max_dispclk
[4] = v
->max_dispclk_vmax0p9
;
789 v
->max_dispclk
[3] = v
->max_dispclk_vmax0p9
;
790 v
->max_dispclk
[2] = v
->max_dispclk_vnom0p8
;
791 v
->max_dispclk
[1] = v
->max_dispclk_vmid0p72
;
792 v
->max_dispclk
[0] = v
->max_dispclk_vmin0p65
;
793 v
->max_dppclk
[5] = v
->max_dppclk_vmax0p9
;
794 v
->max_dppclk
[4] = v
->max_dppclk_vmax0p9
;
795 v
->max_dppclk
[3] = v
->max_dppclk_vmax0p9
;
796 v
->max_dppclk
[2] = v
->max_dppclk_vnom0p8
;
797 v
->max_dppclk
[1] = v
->max_dppclk_vmid0p72
;
798 v
->max_dppclk
[0] = v
->max_dppclk_vmin0p65
;
799 v
->phyclk_per_state
[5] = v
->phyclkv_max0p9
;
800 v
->phyclk_per_state
[4] = v
->phyclkv_max0p9
;
801 v
->phyclk_per_state
[3] = v
->phyclkv_max0p9
;
802 v
->phyclk_per_state
[2] = v
->phyclkv_nom0p8
;
803 v
->phyclk_per_state
[1] = v
->phyclkv_mid0p72
;
804 v
->phyclk_per_state
[0] = v
->phyclkv_min0p65
;
806 hack_bounding_box(v
, &dc
->debug
, context
);
808 if (v
->voltage_override
== dcn_bw_v_max0p9
) {
809 v
->voltage_override_level
= number_of_states
- 1;
810 } else if (v
->voltage_override
== dcn_bw_v_nom0p8
) {
811 v
->voltage_override_level
= number_of_states
- 2;
812 } else if (v
->voltage_override
== dcn_bw_v_mid0p72
) {
813 v
->voltage_override_level
= number_of_states
- 3;
815 v
->voltage_override_level
= 0;
817 v
->synchronized_vblank
= dcn_bw_no
;
818 v
->ta_pscalculation
= dcn_bw_override
;
819 v
->allow_different_hratio_vratio
= dcn_bw_yes
;
822 for (i
= 0, input_idx
= 0; i
< pool
->pipe_count
; i
++) {
823 struct pipe_ctx
*pipe
= &context
->res_ctx
.pipe_ctx
[i
];
827 /* skip all but first of split pipes */
828 if (pipe
->top_pipe
&& pipe
->top_pipe
->plane_state
== pipe
->plane_state
)
831 v
->underscan_output
[input_idx
] = false; /* taken care of in recout already*/
832 v
->interlace_output
[input_idx
] = false;
834 v
->htotal
[input_idx
] = pipe
->stream
->timing
.h_total
;
835 v
->vtotal
[input_idx
] = pipe
->stream
->timing
.v_total
;
836 v
->vactive
[input_idx
] = pipe
->stream
->timing
.v_addressable
+
837 pipe
->stream
->timing
.v_border_top
+ pipe
->stream
->timing
.v_border_bottom
;
838 v
->v_sync_plus_back_porch
[input_idx
] = pipe
->stream
->timing
.v_total
839 - v
->vactive
[input_idx
]
840 - pipe
->stream
->timing
.v_front_porch
;
841 v
->pixel_clock
[input_idx
] = pipe
->stream
->timing
.pix_clk_khz
/ 1000.0f
;
843 if (!pipe
->plane_state
) {
844 v
->dcc_enable
[input_idx
] = dcn_bw_yes
;
845 v
->source_pixel_format
[input_idx
] = dcn_bw_rgb_sub_32
;
846 v
->source_surface_mode
[input_idx
] = dcn_bw_sw_4_kb_s
;
847 v
->lb_bit_per_pixel
[input_idx
] = 30;
848 v
->viewport_width
[input_idx
] = pipe
->stream
->timing
.h_addressable
;
849 v
->viewport_height
[input_idx
] = pipe
->stream
->timing
.v_addressable
;
850 v
->scaler_rec_out_width
[input_idx
] = pipe
->stream
->timing
.h_addressable
;
851 v
->scaler_recout_height
[input_idx
] = pipe
->stream
->timing
.v_addressable
;
852 v
->override_hta_ps
[input_idx
] = 1;
853 v
->override_vta_ps
[input_idx
] = 1;
854 v
->override_hta_pschroma
[input_idx
] = 1;
855 v
->override_vta_pschroma
[input_idx
] = 1;
856 v
->source_scan
[input_idx
] = dcn_bw_hor
;
859 v
->viewport_height
[input_idx
] = pipe
->plane_res
.scl_data
.viewport
.height
;
860 v
->viewport_width
[input_idx
] = pipe
->plane_res
.scl_data
.viewport
.width
;
861 v
->scaler_rec_out_width
[input_idx
] = pipe
->plane_res
.scl_data
.recout
.width
;
862 v
->scaler_recout_height
[input_idx
] = pipe
->plane_res
.scl_data
.recout
.height
;
863 if (pipe
->bottom_pipe
&& pipe
->bottom_pipe
->plane_state
== pipe
->plane_state
) {
864 if (pipe
->plane_state
->rotation
% 2 == 0) {
865 int viewport_end
= pipe
->plane_res
.scl_data
.viewport
.width
866 + pipe
->plane_res
.scl_data
.viewport
.x
;
867 int viewport_b_end
= pipe
->bottom_pipe
->plane_res
.scl_data
.viewport
.width
868 + pipe
->bottom_pipe
->plane_res
.scl_data
.viewport
.x
;
870 if (viewport_end
> viewport_b_end
)
871 v
->viewport_width
[input_idx
] = viewport_end
872 - pipe
->bottom_pipe
->plane_res
.scl_data
.viewport
.x
;
874 v
->viewport_width
[input_idx
] = viewport_b_end
875 - pipe
->plane_res
.scl_data
.viewport
.x
;
877 int viewport_end
= pipe
->plane_res
.scl_data
.viewport
.height
878 + pipe
->plane_res
.scl_data
.viewport
.y
;
879 int viewport_b_end
= pipe
->bottom_pipe
->plane_res
.scl_data
.viewport
.height
880 + pipe
->bottom_pipe
->plane_res
.scl_data
.viewport
.y
;
882 if (viewport_end
> viewport_b_end
)
883 v
->viewport_height
[input_idx
] = viewport_end
884 - pipe
->bottom_pipe
->plane_res
.scl_data
.viewport
.y
;
886 v
->viewport_height
[input_idx
] = viewport_b_end
887 - pipe
->plane_res
.scl_data
.viewport
.y
;
889 v
->scaler_rec_out_width
[input_idx
] = pipe
->plane_res
.scl_data
.recout
.width
890 + pipe
->bottom_pipe
->plane_res
.scl_data
.recout
.width
;
893 v
->dcc_enable
[input_idx
] = pipe
->plane_state
->dcc
.enable
? dcn_bw_yes
: dcn_bw_no
;
894 v
->source_pixel_format
[input_idx
] = tl_pixel_format_to_bw_defs(
895 pipe
->plane_state
->format
);
896 v
->source_surface_mode
[input_idx
] = tl_sw_mode_to_bw_defs(
897 pipe
->plane_state
->tiling_info
.gfx9
.swizzle
);
898 v
->lb_bit_per_pixel
[input_idx
] = tl_lb_bpp_to_int(pipe
->plane_res
.scl_data
.lb_params
.depth
);
899 v
->override_hta_ps
[input_idx
] = pipe
->plane_res
.scl_data
.taps
.h_taps
;
900 v
->override_vta_ps
[input_idx
] = pipe
->plane_res
.scl_data
.taps
.v_taps
;
901 v
->override_hta_pschroma
[input_idx
] = pipe
->plane_res
.scl_data
.taps
.h_taps_c
;
902 v
->override_vta_pschroma
[input_idx
] = pipe
->plane_res
.scl_data
.taps
.v_taps_c
;
904 * Spreadsheet doesn't handle taps_c is one properly,
905 * need to force Chroma to always be scaled to pass
906 * bandwidth validation.
908 if (v
->override_hta_pschroma
[input_idx
] == 1)
909 v
->override_hta_pschroma
[input_idx
] = 2;
910 if (v
->override_vta_pschroma
[input_idx
] == 1)
911 v
->override_vta_pschroma
[input_idx
] = 2;
912 v
->source_scan
[input_idx
] = (pipe
->plane_state
->rotation
% 2) ? dcn_bw_vert
: dcn_bw_hor
;
914 if (v
->is_line_buffer_bpp_fixed
== dcn_bw_yes
)
915 v
->lb_bit_per_pixel
[input_idx
] = v
->line_buffer_fixed_bpp
;
916 v
->dcc_rate
[input_idx
] = 1; /*TODO: Worst case? does this change?*/
917 v
->output_format
[input_idx
] = pipe
->stream
->timing
.pixel_encoding
==
918 PIXEL_ENCODING_YCBCR420
? dcn_bw_420
: dcn_bw_444
;
919 v
->output
[input_idx
] = pipe
->stream
->sink
->sink_signal
==
920 SIGNAL_TYPE_HDMI_TYPE_A
? dcn_bw_hdmi
: dcn_bw_dp
;
921 v
->output_deep_color
[input_idx
] = dcn_bw_encoder_8bpc
;
922 if (v
->output
[input_idx
] == dcn_bw_hdmi
) {
923 switch (pipe
->stream
->timing
.display_color_depth
) {
924 case COLOR_DEPTH_101010
:
925 v
->output_deep_color
[input_idx
] = dcn_bw_encoder_10bpc
;
927 case COLOR_DEPTH_121212
:
928 v
->output_deep_color
[input_idx
] = dcn_bw_encoder_12bpc
;
930 case COLOR_DEPTH_161616
:
931 v
->output_deep_color
[input_idx
] = dcn_bw_encoder_16bpc
;
940 v
->number_of_active_planes
= input_idx
;
942 scaler_settings_calculation(v
);
943 mode_support_and_system_configuration(v
);
945 if (v
->voltage_level
== 0 &&
946 (dc
->debug
.sr_exit_time_dpm0_ns
947 || dc
->debug
.sr_enter_plus_exit_time_dpm0_ns
)) {
949 if (dc
->debug
.sr_enter_plus_exit_time_dpm0_ns
)
950 v
->sr_enter_plus_exit_time
=
951 dc
->debug
.sr_enter_plus_exit_time_dpm0_ns
/ 1000.0f
;
952 if (dc
->debug
.sr_exit_time_dpm0_ns
)
953 v
->sr_exit_time
= dc
->debug
.sr_exit_time_dpm0_ns
/ 1000.0f
;
954 dc
->dml
.soc
.sr_enter_plus_exit_time_us
= v
->sr_enter_plus_exit_time
;
955 dc
->dml
.soc
.sr_exit_time_us
= v
->sr_exit_time
;
956 mode_support_and_system_configuration(v
);
959 if (v
->voltage_level
!= 5) {
960 float bw_consumed
= v
->total_bandwidth_consumed_gbyte_per_second
;
961 if (bw_consumed
< v
->fabric_and_dram_bandwidth_vmin0p65
)
962 bw_consumed
= v
->fabric_and_dram_bandwidth_vmin0p65
;
963 else if (bw_consumed
< v
->fabric_and_dram_bandwidth_vmid0p72
)
964 bw_consumed
= v
->fabric_and_dram_bandwidth_vmid0p72
;
965 else if (bw_consumed
< v
->fabric_and_dram_bandwidth_vnom0p8
)
966 bw_consumed
= v
->fabric_and_dram_bandwidth_vnom0p8
;
968 bw_consumed
= v
->fabric_and_dram_bandwidth_vmax0p9
;
970 if (bw_consumed
< v
->fabric_and_dram_bandwidth
)
971 if (dc
->debug
.voltage_align_fclk
)
972 bw_consumed
= v
->fabric_and_dram_bandwidth
;
974 display_pipe_configuration(v
);
975 calc_wm_sets_and_perf_params(context
, v
);
976 context
->bw
.dcn
.calc_clk
.fclk_khz
= (int)(bw_consumed
* 1000000 /
977 (ddr4_dram_factor_single_Channel
* v
->number_of_channels
));
978 if (bw_consumed
== v
->fabric_and_dram_bandwidth_vmin0p65
) {
979 context
->bw
.dcn
.calc_clk
.fclk_khz
= (int)(bw_consumed
* 1000000 / 32);
982 context
->bw
.dcn
.calc_clk
.dram_ccm_us
= (int)(v
->dram_clock_change_margin
);
983 context
->bw
.dcn
.calc_clk
.min_active_dram_ccm_us
= (int)(v
->min_active_dram_clock_change_margin
);
984 context
->bw
.dcn
.calc_clk
.dcfclk_deep_sleep_khz
= (int)(v
->dcf_clk_deep_sleep
* 1000);
985 context
->bw
.dcn
.calc_clk
.dcfclk_khz
= (int)(v
->dcfclk
* 1000);
987 context
->bw
.dcn
.calc_clk
.dispclk_khz
= (int)(v
->dispclk
* 1000);
988 if (dc
->debug
.max_disp_clk
== true)
989 context
->bw
.dcn
.calc_clk
.dispclk_khz
= (int)(dc
->dcn_soc
->max_dispclk_vmax0p9
* 1000);
991 if (context
->bw
.dcn
.calc_clk
.dispclk_khz
<
992 dc
->debug
.min_disp_clk_khz
) {
993 context
->bw
.dcn
.calc_clk
.dispclk_khz
=
994 dc
->debug
.min_disp_clk_khz
;
997 context
->bw
.dcn
.calc_clk
.dppclk_div
= (int)(v
->dispclk_dppclk_ratio
) == 2;
999 for (i
= 0, input_idx
= 0; i
< pool
->pipe_count
; i
++) {
1000 struct pipe_ctx
*pipe
= &context
->res_ctx
.pipe_ctx
[i
];
1002 /* skip inactive pipe */
1005 /* skip all but first of split pipes */
1006 if (pipe
->top_pipe
&& pipe
->top_pipe
->plane_state
== pipe
->plane_state
)
1009 pipe
->pipe_dlg_param
.vupdate_width
= v
->v_update_width
[input_idx
];
1010 pipe
->pipe_dlg_param
.vupdate_offset
= v
->v_update_offset
[input_idx
];
1011 pipe
->pipe_dlg_param
.vready_offset
= v
->v_ready_offset
[input_idx
];
1012 pipe
->pipe_dlg_param
.vstartup_start
= v
->v_startup
[input_idx
];
1014 pipe
->pipe_dlg_param
.htotal
= pipe
->stream
->timing
.h_total
;
1015 pipe
->pipe_dlg_param
.vtotal
= pipe
->stream
->timing
.v_total
;
1016 vesa_sync_start
= pipe
->stream
->timing
.v_addressable
+
1017 pipe
->stream
->timing
.v_border_bottom
+
1018 pipe
->stream
->timing
.v_front_porch
;
1020 asic_blank_end
= (pipe
->stream
->timing
.v_total
-
1022 pipe
->stream
->timing
.v_border_top
)
1023 * (pipe
->stream
->timing
.flags
.INTERLACE
? 1 : 0);
1025 asic_blank_start
= asic_blank_end
+
1026 (pipe
->stream
->timing
.v_border_top
+
1027 pipe
->stream
->timing
.v_addressable
+
1028 pipe
->stream
->timing
.v_border_bottom
)
1029 * (pipe
->stream
->timing
.flags
.INTERLACE
? 1 : 0);
1031 pipe
->pipe_dlg_param
.vblank_start
= asic_blank_start
;
1032 pipe
->pipe_dlg_param
.vblank_end
= asic_blank_end
;
1034 if (pipe
->plane_state
) {
1035 struct pipe_ctx
*hsplit_pipe
= pipe
->bottom_pipe
;
1037 if (v
->dpp_per_plane
[input_idx
] == 2 ||
1038 ((pipe
->stream
->view_format
==
1039 VIEW_3D_FORMAT_SIDE_BY_SIDE
||
1040 pipe
->stream
->view_format
==
1041 VIEW_3D_FORMAT_TOP_AND_BOTTOM
) &&
1042 (pipe
->stream
->timing
.timing_3d_format
==
1043 TIMING_3D_FORMAT_TOP_AND_BOTTOM
||
1044 pipe
->stream
->timing
.timing_3d_format
==
1045 TIMING_3D_FORMAT_SIDE_BY_SIDE
))) {
1046 if (hsplit_pipe
&& hsplit_pipe
->plane_state
== pipe
->plane_state
) {
1047 /* update previously split pipe */
1048 hsplit_pipe
->pipe_dlg_param
.vupdate_width
= v
->v_update_width
[input_idx
];
1049 hsplit_pipe
->pipe_dlg_param
.vupdate_offset
= v
->v_update_offset
[input_idx
];
1050 hsplit_pipe
->pipe_dlg_param
.vready_offset
= v
->v_ready_offset
[input_idx
];
1051 hsplit_pipe
->pipe_dlg_param
.vstartup_start
= v
->v_startup
[input_idx
];
1053 hsplit_pipe
->pipe_dlg_param
.htotal
= pipe
->stream
->timing
.h_total
;
1054 hsplit_pipe
->pipe_dlg_param
.vtotal
= pipe
->stream
->timing
.v_total
;
1055 hsplit_pipe
->pipe_dlg_param
.vblank_start
= pipe
->pipe_dlg_param
.vblank_start
;
1056 hsplit_pipe
->pipe_dlg_param
.vblank_end
= pipe
->pipe_dlg_param
.vblank_end
;
1058 /* pipe not split previously needs split */
1059 hsplit_pipe
= find_idle_secondary_pipe(&context
->res_ctx
, pool
);
1060 ASSERT(hsplit_pipe
);
1061 split_stream_across_pipes(
1062 &context
->res_ctx
, pool
,
1066 dcn_bw_calc_rq_dlg_ttu(dc
, v
, hsplit_pipe
, input_idx
);
1067 } else if (hsplit_pipe
&& hsplit_pipe
->plane_state
== pipe
->plane_state
) {
1068 /* merge previously split pipe */
1069 pipe
->bottom_pipe
= hsplit_pipe
->bottom_pipe
;
1070 if (hsplit_pipe
->bottom_pipe
)
1071 hsplit_pipe
->bottom_pipe
->top_pipe
= pipe
;
1072 hsplit_pipe
->plane_state
= NULL
;
1073 hsplit_pipe
->stream
= NULL
;
1074 hsplit_pipe
->top_pipe
= NULL
;
1075 hsplit_pipe
->bottom_pipe
= NULL
;
1076 resource_build_scaling_params(pipe
);
1078 /* for now important to do this after pipe split for building e2e params */
1079 dcn_bw_calc_rq_dlg_ttu(dc
, v
, pipe
, input_idx
);
1086 if (v
->voltage_level
== 0) {
1088 dc
->dml
.soc
.sr_enter_plus_exit_time_us
=
1089 dc
->dcn_soc
->sr_enter_plus_exit_time
;
1090 dc
->dml
.soc
.sr_exit_time_us
= dc
->dcn_soc
->sr_exit_time
;
1094 * BW limit is set to prevent display from impacting other system functions
1097 bw_limit
= dc
->dcn_soc
->percent_disp_bw_limit
* v
->fabric_and_dram_bandwidth_vmax0p9
;
1098 bw_limit_pass
= (v
->total_data_read_bandwidth
/ 1000.0) < bw_limit
;
1102 PERFORMANCE_TRACE_END();
1104 if (bw_limit_pass
&& v
->voltage_level
!= 5)
1110 static unsigned int dcn_find_normalized_clock_vdd_Level(
1111 const struct dc
*dc
,
1112 enum dm_pp_clock_type clocks_type
,
1115 int vdd_level
= dcn_bw_v_min0p65
;
1117 if (clocks_in_khz
== 0)/*todo some clock not in the considerations*/
1120 switch (clocks_type
) {
1121 case DM_PP_CLOCK_TYPE_DISPLAY_CLK
:
1122 if (clocks_in_khz
> dc
->dcn_soc
->max_dispclk_vmax0p9
*1000) {
1123 vdd_level
= dcn_bw_v_max0p91
;
1124 BREAK_TO_DEBUGGER();
1125 } else if (clocks_in_khz
> dc
->dcn_soc
->max_dispclk_vnom0p8
*1000) {
1126 vdd_level
= dcn_bw_v_max0p9
;
1127 } else if (clocks_in_khz
> dc
->dcn_soc
->max_dispclk_vmid0p72
*1000) {
1128 vdd_level
= dcn_bw_v_nom0p8
;
1129 } else if (clocks_in_khz
> dc
->dcn_soc
->max_dispclk_vmin0p65
*1000) {
1130 vdd_level
= dcn_bw_v_mid0p72
;
1132 vdd_level
= dcn_bw_v_min0p65
;
1134 case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK
:
1135 if (clocks_in_khz
> dc
->dcn_soc
->phyclkv_max0p9
*1000) {
1136 vdd_level
= dcn_bw_v_max0p91
;
1137 BREAK_TO_DEBUGGER();
1138 } else if (clocks_in_khz
> dc
->dcn_soc
->phyclkv_nom0p8
*1000) {
1139 vdd_level
= dcn_bw_v_max0p9
;
1140 } else if (clocks_in_khz
> dc
->dcn_soc
->phyclkv_mid0p72
*1000) {
1141 vdd_level
= dcn_bw_v_nom0p8
;
1142 } else if (clocks_in_khz
> dc
->dcn_soc
->phyclkv_min0p65
*1000) {
1143 vdd_level
= dcn_bw_v_mid0p72
;
1145 vdd_level
= dcn_bw_v_min0p65
;
1148 case DM_PP_CLOCK_TYPE_DPPCLK
:
1149 if (clocks_in_khz
> dc
->dcn_soc
->max_dppclk_vmax0p9
*1000) {
1150 vdd_level
= dcn_bw_v_max0p91
;
1151 BREAK_TO_DEBUGGER();
1152 } else if (clocks_in_khz
> dc
->dcn_soc
->max_dppclk_vnom0p8
*1000) {
1153 vdd_level
= dcn_bw_v_max0p9
;
1154 } else if (clocks_in_khz
> dc
->dcn_soc
->max_dppclk_vmid0p72
*1000) {
1155 vdd_level
= dcn_bw_v_nom0p8
;
1156 } else if (clocks_in_khz
> dc
->dcn_soc
->max_dppclk_vmin0p65
*1000) {
1157 vdd_level
= dcn_bw_v_mid0p72
;
1159 vdd_level
= dcn_bw_v_min0p65
;
1162 case DM_PP_CLOCK_TYPE_MEMORY_CLK
:
1164 unsigned factor
= (ddr4_dram_factor_single_Channel
* dc
->dcn_soc
->number_of_channels
);
1166 if (clocks_in_khz
> dc
->dcn_soc
->fabric_and_dram_bandwidth_vmax0p9
*1000000/factor
) {
1167 vdd_level
= dcn_bw_v_max0p91
;
1168 BREAK_TO_DEBUGGER();
1169 } else if (clocks_in_khz
> dc
->dcn_soc
->fabric_and_dram_bandwidth_vnom0p8
*1000000/factor
) {
1170 vdd_level
= dcn_bw_v_max0p9
;
1171 } else if (clocks_in_khz
> dc
->dcn_soc
->fabric_and_dram_bandwidth_vmid0p72
*1000000/factor
) {
1172 vdd_level
= dcn_bw_v_nom0p8
;
1173 } else if (clocks_in_khz
> dc
->dcn_soc
->fabric_and_dram_bandwidth_vmin0p65
*1000000/factor
) {
1174 vdd_level
= dcn_bw_v_mid0p72
;
1176 vdd_level
= dcn_bw_v_min0p65
;
1180 case DM_PP_CLOCK_TYPE_DCFCLK
:
1181 if (clocks_in_khz
> dc
->dcn_soc
->dcfclkv_max0p9
*1000) {
1182 vdd_level
= dcn_bw_v_max0p91
;
1183 BREAK_TO_DEBUGGER();
1184 } else if (clocks_in_khz
> dc
->dcn_soc
->dcfclkv_nom0p8
*1000) {
1185 vdd_level
= dcn_bw_v_max0p9
;
1186 } else if (clocks_in_khz
> dc
->dcn_soc
->dcfclkv_mid0p72
*1000) {
1187 vdd_level
= dcn_bw_v_nom0p8
;
1188 } else if (clocks_in_khz
> dc
->dcn_soc
->dcfclkv_min0p65
*1000) {
1189 vdd_level
= dcn_bw_v_mid0p72
;
1191 vdd_level
= dcn_bw_v_min0p65
;
1200 unsigned int dcn_find_dcfclk_suits_all(
1201 const struct dc
*dc
,
1202 struct clocks_value
*clocks
)
1204 unsigned vdd_level
, vdd_level_temp
;
1207 /*find a common supported voltage level*/
1208 vdd_level
= dcn_find_normalized_clock_vdd_Level(
1209 dc
, DM_PP_CLOCK_TYPE_DISPLAY_CLK
, clocks
->dispclk_in_khz
);
1210 vdd_level_temp
= dcn_find_normalized_clock_vdd_Level(
1211 dc
, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK
, clocks
->phyclk_in_khz
);
1213 vdd_level
= dcn_bw_max(vdd_level
, vdd_level_temp
);
1214 vdd_level_temp
= dcn_find_normalized_clock_vdd_Level(
1215 dc
, DM_PP_CLOCK_TYPE_DPPCLK
, clocks
->dppclk_in_khz
);
1216 vdd_level
= dcn_bw_max(vdd_level
, vdd_level_temp
);
1218 vdd_level_temp
= dcn_find_normalized_clock_vdd_Level(
1219 dc
, DM_PP_CLOCK_TYPE_MEMORY_CLK
, clocks
->dcfclock_in_khz
);
1220 vdd_level
= dcn_bw_max(vdd_level
, vdd_level_temp
);
1221 vdd_level_temp
= dcn_find_normalized_clock_vdd_Level(
1222 dc
, DM_PP_CLOCK_TYPE_DCFCLK
, clocks
->dcfclock_in_khz
);
1224 /*find that level conresponding dcfclk*/
1225 vdd_level
= dcn_bw_max(vdd_level
, vdd_level_temp
);
1226 if (vdd_level
== dcn_bw_v_max0p91
) {
1227 BREAK_TO_DEBUGGER();
1228 dcf_clk
= dc
->dcn_soc
->dcfclkv_max0p9
*1000;
1229 } else if (vdd_level
== dcn_bw_v_max0p9
)
1230 dcf_clk
= dc
->dcn_soc
->dcfclkv_max0p9
*1000;
1231 else if (vdd_level
== dcn_bw_v_nom0p8
)
1232 dcf_clk
= dc
->dcn_soc
->dcfclkv_nom0p8
*1000;
1233 else if (vdd_level
== dcn_bw_v_mid0p72
)
1234 dcf_clk
= dc
->dcn_soc
->dcfclkv_mid0p72
*1000;
1236 dcf_clk
= dc
->dcn_soc
->dcfclkv_min0p65
*1000;
1238 dm_logger_write(dc
->ctx
->logger
, LOG_BANDWIDTH_CALCS
,
1239 "\tdcf_clk for voltage = %d\n", dcf_clk
);
1243 void dcn_bw_update_from_pplib(struct dc
*dc
)
1245 struct dc_context
*ctx
= dc
->ctx
;
1246 struct dm_pp_clock_levels_with_voltage clks
= {0};
1250 /* TODO: This is not the proper way to obtain fabric_and_dram_bandwidth, should be min(fclk, memclk) */
1252 if (dm_pp_get_clock_levels_by_type_with_voltage(
1253 ctx
, DM_PP_CLOCK_TYPE_FCLK
, &clks
) &&
1254 clks
.num_levels
!= 0) {
1255 ASSERT(clks
.num_levels
>= 3);
1256 dc
->dcn_soc
->fabric_and_dram_bandwidth_vmin0p65
= 32 * (clks
.data
[0].clocks_in_khz
/ 1000.0) / 1000.0;
1257 if (clks
.num_levels
> 2) {
1258 dc
->dcn_soc
->fabric_and_dram_bandwidth_vmid0p72
= dc
->dcn_soc
->number_of_channels
*
1259 (clks
.data
[clks
.num_levels
- 3].clocks_in_khz
/ 1000.0) * ddr4_dram_factor_single_Channel
/ 1000.0;
1261 dc
->dcn_soc
->fabric_and_dram_bandwidth_vmid0p72
= dc
->dcn_soc
->number_of_channels
*
1262 (clks
.data
[clks
.num_levels
- 2].clocks_in_khz
/ 1000.0) * ddr4_dram_factor_single_Channel
/ 1000.0;
1264 dc
->dcn_soc
->fabric_and_dram_bandwidth_vnom0p8
= dc
->dcn_soc
->number_of_channels
*
1265 (clks
.data
[clks
.num_levels
- 2].clocks_in_khz
/ 1000.0) * ddr4_dram_factor_single_Channel
/ 1000.0;
1266 dc
->dcn_soc
->fabric_and_dram_bandwidth_vmax0p9
= dc
->dcn_soc
->number_of_channels
*
1267 (clks
.data
[clks
.num_levels
- 1].clocks_in_khz
/ 1000.0) * ddr4_dram_factor_single_Channel
/ 1000.0;
1269 BREAK_TO_DEBUGGER();
1270 if (dm_pp_get_clock_levels_by_type_with_voltage(
1271 ctx
, DM_PP_CLOCK_TYPE_DCFCLK
, &clks
) &&
1272 clks
.num_levels
>= 3) {
1273 dc
->dcn_soc
->dcfclkv_min0p65
= clks
.data
[0].clocks_in_khz
/ 1000.0;
1274 dc
->dcn_soc
->dcfclkv_mid0p72
= clks
.data
[clks
.num_levels
- 3].clocks_in_khz
/ 1000.0;
1275 dc
->dcn_soc
->dcfclkv_nom0p8
= clks
.data
[clks
.num_levels
- 2].clocks_in_khz
/ 1000.0;
1276 dc
->dcn_soc
->dcfclkv_max0p9
= clks
.data
[clks
.num_levels
- 1].clocks_in_khz
/ 1000.0;
1278 BREAK_TO_DEBUGGER();
1283 void dcn_bw_notify_pplib_of_wm_ranges(struct dc
*dc
)
1285 struct pp_smu_funcs_rv
*pp
= dc
->res_pool
->pp_smu
;
1286 struct pp_smu_wm_range_sets ranges
= {0};
1287 int max_fclk_khz
, nom_fclk_khz
, mid_fclk_khz
, min_fclk_khz
;
1288 int max_dcfclk_khz
, min_dcfclk_khz
;
1290 const int overdrive
= 5000000; /* 5 GHz to cover Overdrive */
1291 unsigned factor
= (ddr4_dram_factor_single_Channel
* dc
->dcn_soc
->number_of_channels
);
1293 if (!pp
->set_wm_ranges
)
1297 max_fclk_khz
= dc
->dcn_soc
->fabric_and_dram_bandwidth_vmax0p9
* 1000000 / factor
;
1298 nom_fclk_khz
= dc
->dcn_soc
->fabric_and_dram_bandwidth_vnom0p8
* 1000000 / factor
;
1299 mid_fclk_khz
= dc
->dcn_soc
->fabric_and_dram_bandwidth_vmid0p72
* 1000000 / factor
;
1300 min_fclk_khz
= dc
->dcn_soc
->fabric_and_dram_bandwidth_vmin0p65
* 1000000 / 32;
1301 max_dcfclk_khz
= dc
->dcn_soc
->dcfclkv_max0p9
* 1000;
1302 min_dcfclk_khz
= dc
->dcn_soc
->dcfclkv_min0p65
* 1000;
1303 socclk_khz
= dc
->dcn_soc
->socclk
* 1000;
1306 /* Now notify PPLib/SMU about which Watermarks sets they should select
1307 * depending on DPM state they are in. And update BW MGR GFX Engine and
1308 * Memory clock member variables for Watermarks calculations for each
1311 /* SOCCLK does not affect anytihng but writeback for DCN so for now we dont
1312 * care what the value is, hence min to overdrive level
1314 ranges
.num_reader_wm_sets
= WM_COUNT
;
1315 ranges
.num_writer_wm_sets
= WM_COUNT
;
1316 ranges
.reader_wm_sets
[0].wm_inst
= WM_A
;
1317 ranges
.reader_wm_sets
[0].min_drain_clk_khz
= min_dcfclk_khz
;
1318 ranges
.reader_wm_sets
[0].max_drain_clk_khz
= max_dcfclk_khz
;
1319 ranges
.reader_wm_sets
[0].min_fill_clk_khz
= min_fclk_khz
;
1320 ranges
.reader_wm_sets
[0].max_fill_clk_khz
= min_fclk_khz
;
1321 ranges
.writer_wm_sets
[0].wm_inst
= WM_A
;
1322 ranges
.writer_wm_sets
[0].min_fill_clk_khz
= socclk_khz
;
1323 ranges
.writer_wm_sets
[0].max_fill_clk_khz
= overdrive
;
1324 ranges
.writer_wm_sets
[0].min_drain_clk_khz
= min_fclk_khz
;
1325 ranges
.writer_wm_sets
[0].max_drain_clk_khz
= min_fclk_khz
;
1327 ranges
.reader_wm_sets
[1].wm_inst
= WM_B
;
1328 ranges
.reader_wm_sets
[1].min_drain_clk_khz
= min_fclk_khz
;
1329 ranges
.reader_wm_sets
[1].max_drain_clk_khz
= max_dcfclk_khz
;
1330 ranges
.reader_wm_sets
[1].min_fill_clk_khz
= mid_fclk_khz
;
1331 ranges
.reader_wm_sets
[1].max_fill_clk_khz
= mid_fclk_khz
;
1332 ranges
.writer_wm_sets
[1].wm_inst
= WM_B
;
1333 ranges
.writer_wm_sets
[1].min_fill_clk_khz
= socclk_khz
;
1334 ranges
.writer_wm_sets
[1].max_fill_clk_khz
= overdrive
;
1335 ranges
.writer_wm_sets
[1].min_drain_clk_khz
= mid_fclk_khz
;
1336 ranges
.writer_wm_sets
[1].max_drain_clk_khz
= mid_fclk_khz
;
1339 ranges
.reader_wm_sets
[2].wm_inst
= WM_C
;
1340 ranges
.reader_wm_sets
[2].min_drain_clk_khz
= min_fclk_khz
;
1341 ranges
.reader_wm_sets
[2].max_drain_clk_khz
= max_dcfclk_khz
;
1342 ranges
.reader_wm_sets
[2].min_fill_clk_khz
= nom_fclk_khz
;
1343 ranges
.reader_wm_sets
[2].max_fill_clk_khz
= nom_fclk_khz
;
1344 ranges
.writer_wm_sets
[2].wm_inst
= WM_C
;
1345 ranges
.writer_wm_sets
[2].min_fill_clk_khz
= socclk_khz
;
1346 ranges
.writer_wm_sets
[2].max_fill_clk_khz
= overdrive
;
1347 ranges
.writer_wm_sets
[2].min_drain_clk_khz
= nom_fclk_khz
;
1348 ranges
.writer_wm_sets
[2].max_drain_clk_khz
= nom_fclk_khz
;
1350 ranges
.reader_wm_sets
[3].wm_inst
= WM_D
;
1351 ranges
.reader_wm_sets
[3].min_drain_clk_khz
= min_fclk_khz
;
1352 ranges
.reader_wm_sets
[3].max_drain_clk_khz
= max_dcfclk_khz
;
1353 ranges
.reader_wm_sets
[3].min_fill_clk_khz
= max_fclk_khz
;
1354 ranges
.reader_wm_sets
[3].max_fill_clk_khz
= max_fclk_khz
;
1355 ranges
.writer_wm_sets
[3].wm_inst
= WM_D
;
1356 ranges
.writer_wm_sets
[3].min_fill_clk_khz
= socclk_khz
;
1357 ranges
.writer_wm_sets
[3].max_fill_clk_khz
= overdrive
;
1358 ranges
.writer_wm_sets
[3].min_drain_clk_khz
= max_fclk_khz
;
1359 ranges
.writer_wm_sets
[3].max_drain_clk_khz
= max_fclk_khz
;
1361 if (dc
->debug
.pplib_wm_report_mode
== WM_REPORT_OVERRIDE
) {
1362 ranges
.reader_wm_sets
[0].wm_inst
= WM_A
;
1363 ranges
.reader_wm_sets
[0].min_drain_clk_khz
= 300000;
1364 ranges
.reader_wm_sets
[0].max_drain_clk_khz
= 654000;
1365 ranges
.reader_wm_sets
[0].min_fill_clk_khz
= 800000;
1366 ranges
.reader_wm_sets
[0].max_fill_clk_khz
= 800000;
1367 ranges
.writer_wm_sets
[0].wm_inst
= WM_A
;
1368 ranges
.writer_wm_sets
[0].min_fill_clk_khz
= 200000;
1369 ranges
.writer_wm_sets
[0].max_fill_clk_khz
= 757000;
1370 ranges
.writer_wm_sets
[0].min_drain_clk_khz
= 800000;
1371 ranges
.writer_wm_sets
[0].max_drain_clk_khz
= 800000;
1373 ranges
.reader_wm_sets
[1].wm_inst
= WM_B
;
1374 ranges
.reader_wm_sets
[1].min_drain_clk_khz
= 300000;
1375 ranges
.reader_wm_sets
[1].max_drain_clk_khz
= 654000;
1376 ranges
.reader_wm_sets
[1].min_fill_clk_khz
= 933000;
1377 ranges
.reader_wm_sets
[1].max_fill_clk_khz
= 933000;
1378 ranges
.writer_wm_sets
[1].wm_inst
= WM_B
;
1379 ranges
.writer_wm_sets
[1].min_fill_clk_khz
= 200000;
1380 ranges
.writer_wm_sets
[1].max_fill_clk_khz
= 757000;
1381 ranges
.writer_wm_sets
[1].min_drain_clk_khz
= 933000;
1382 ranges
.writer_wm_sets
[1].max_drain_clk_khz
= 933000;
1385 ranges
.reader_wm_sets
[2].wm_inst
= WM_C
;
1386 ranges
.reader_wm_sets
[2].min_drain_clk_khz
= 300000;
1387 ranges
.reader_wm_sets
[2].max_drain_clk_khz
= 654000;
1388 ranges
.reader_wm_sets
[2].min_fill_clk_khz
= 1067000;
1389 ranges
.reader_wm_sets
[2].max_fill_clk_khz
= 1067000;
1390 ranges
.writer_wm_sets
[2].wm_inst
= WM_C
;
1391 ranges
.writer_wm_sets
[2].min_fill_clk_khz
= 200000;
1392 ranges
.writer_wm_sets
[2].max_fill_clk_khz
= 757000;
1393 ranges
.writer_wm_sets
[2].min_drain_clk_khz
= 1067000;
1394 ranges
.writer_wm_sets
[2].max_drain_clk_khz
= 1067000;
1396 ranges
.reader_wm_sets
[3].wm_inst
= WM_D
;
1397 ranges
.reader_wm_sets
[3].min_drain_clk_khz
= 300000;
1398 ranges
.reader_wm_sets
[3].max_drain_clk_khz
= 654000;
1399 ranges
.reader_wm_sets
[3].min_fill_clk_khz
= 1200000;
1400 ranges
.reader_wm_sets
[3].max_fill_clk_khz
= 1200000;
1401 ranges
.writer_wm_sets
[3].wm_inst
= WM_D
;
1402 ranges
.writer_wm_sets
[3].min_fill_clk_khz
= 200000;
1403 ranges
.writer_wm_sets
[3].max_fill_clk_khz
= 757000;
1404 ranges
.writer_wm_sets
[3].min_drain_clk_khz
= 1200000;
1405 ranges
.writer_wm_sets
[3].max_drain_clk_khz
= 1200000;
1408 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1409 pp
->set_wm_ranges(&pp
->pp_smu
, &ranges
);
1412 void dcn_bw_sync_calcs_and_dml(struct dc
*dc
)
1415 dm_logger_write(dc
->ctx
->logger
, LOG_BANDWIDTH_CALCS
,
1416 "sr_exit_time: %d ns\n"
1417 "sr_enter_plus_exit_time: %d ns\n"
1418 "urgent_latency: %d ns\n"
1419 "write_back_latency: %d ns\n"
1420 "percent_of_ideal_drambw_received_after_urg_latency: %d %\n"
1421 "max_request_size: %d bytes\n"
1422 "dcfclkv_max0p9: %d kHz\n"
1423 "dcfclkv_nom0p8: %d kHz\n"
1424 "dcfclkv_mid0p72: %d kHz\n"
1425 "dcfclkv_min0p65: %d kHz\n"
1426 "max_dispclk_vmax0p9: %d kHz\n"
1427 "max_dispclk_vnom0p8: %d kHz\n"
1428 "max_dispclk_vmid0p72: %d kHz\n"
1429 "max_dispclk_vmin0p65: %d kHz\n"
1430 "max_dppclk_vmax0p9: %d kHz\n"
1431 "max_dppclk_vnom0p8: %d kHz\n"
1432 "max_dppclk_vmid0p72: %d kHz\n"
1433 "max_dppclk_vmin0p65: %d kHz\n"
1435 "fabric_and_dram_bandwidth_vmax0p9: %d MB/s\n"
1436 "fabric_and_dram_bandwidth_vnom0p8: %d MB/s\n"
1437 "fabric_and_dram_bandwidth_vmid0p72: %d MB/s\n"
1438 "fabric_and_dram_bandwidth_vmin0p65: %d MB/s\n"
1439 "phyclkv_max0p9: %d kHz\n"
1440 "phyclkv_nom0p8: %d kHz\n"
1441 "phyclkv_mid0p72: %d kHz\n"
1442 "phyclkv_min0p65: %d kHz\n"
1443 "downspreading: %d %\n"
1444 "round_trip_ping_latency_cycles: %d DCFCLK Cycles\n"
1445 "urgent_out_of_order_return_per_channel: %d Bytes\n"
1446 "number_of_channels: %d\n"
1447 "vmm_page_size: %d Bytes\n"
1448 "dram_clock_change_latency: %d ns\n"
1449 "return_bus_width: %d Bytes\n",
1450 dc
->dcn_soc
->sr_exit_time
* 1000,
1451 dc
->dcn_soc
->sr_enter_plus_exit_time
* 1000,
1452 dc
->dcn_soc
->urgent_latency
* 1000,
1453 dc
->dcn_soc
->write_back_latency
* 1000,
1454 dc
->dcn_soc
->percent_of_ideal_drambw_received_after_urg_latency
,
1455 dc
->dcn_soc
->max_request_size
,
1456 dc
->dcn_soc
->dcfclkv_max0p9
* 1000,
1457 dc
->dcn_soc
->dcfclkv_nom0p8
* 1000,
1458 dc
->dcn_soc
->dcfclkv_mid0p72
* 1000,
1459 dc
->dcn_soc
->dcfclkv_min0p65
* 1000,
1460 dc
->dcn_soc
->max_dispclk_vmax0p9
* 1000,
1461 dc
->dcn_soc
->max_dispclk_vnom0p8
* 1000,
1462 dc
->dcn_soc
->max_dispclk_vmid0p72
* 1000,
1463 dc
->dcn_soc
->max_dispclk_vmin0p65
* 1000,
1464 dc
->dcn_soc
->max_dppclk_vmax0p9
* 1000,
1465 dc
->dcn_soc
->max_dppclk_vnom0p8
* 1000,
1466 dc
->dcn_soc
->max_dppclk_vmid0p72
* 1000,
1467 dc
->dcn_soc
->max_dppclk_vmin0p65
* 1000,
1468 dc
->dcn_soc
->socclk
* 1000,
1469 dc
->dcn_soc
->fabric_and_dram_bandwidth_vmax0p9
* 1000,
1470 dc
->dcn_soc
->fabric_and_dram_bandwidth_vnom0p8
* 1000,
1471 dc
->dcn_soc
->fabric_and_dram_bandwidth_vmid0p72
* 1000,
1472 dc
->dcn_soc
->fabric_and_dram_bandwidth_vmin0p65
* 1000,
1473 dc
->dcn_soc
->phyclkv_max0p9
* 1000,
1474 dc
->dcn_soc
->phyclkv_nom0p8
* 1000,
1475 dc
->dcn_soc
->phyclkv_mid0p72
* 1000,
1476 dc
->dcn_soc
->phyclkv_min0p65
* 1000,
1477 dc
->dcn_soc
->downspreading
* 100,
1478 dc
->dcn_soc
->round_trip_ping_latency_cycles
,
1479 dc
->dcn_soc
->urgent_out_of_order_return_per_channel
,
1480 dc
->dcn_soc
->number_of_channels
,
1481 dc
->dcn_soc
->vmm_page_size
,
1482 dc
->dcn_soc
->dram_clock_change_latency
* 1000,
1483 dc
->dcn_soc
->return_bus_width
);
1484 dm_logger_write(dc
->ctx
->logger
, LOG_BANDWIDTH_CALCS
,
1485 "rob_buffer_size_in_kbyte: %d\n"
1486 "det_buffer_size_in_kbyte: %d\n"
1487 "dpp_output_buffer_pixels: %d\n"
1488 "opp_output_buffer_lines: %d\n"
1489 "pixel_chunk_size_in_kbyte: %d\n"
1491 "pte_chunk_size: %d kbytes\n"
1492 "meta_chunk_size: %d kbytes\n"
1493 "writeback_chunk_size: %d kbytes\n"
1494 "odm_capability: %d\n"
1495 "dsc_capability: %d\n"
1496 "line_buffer_size: %d bits\n"
1497 "max_line_buffer_lines: %d\n"
1498 "is_line_buffer_bpp_fixed: %d\n"
1499 "line_buffer_fixed_bpp: %d\n"
1500 "writeback_luma_buffer_size: %d kbytes\n"
1501 "writeback_chroma_buffer_size: %d kbytes\n"
1503 "max_num_writeback: %d\n"
1504 "max_dchub_topscl_throughput: %d pixels/dppclk\n"
1505 "max_pscl_tolb_throughput: %d pixels/dppclk\n"
1506 "max_lb_tovscl_throughput: %d pixels/dppclk\n"
1507 "max_vscl_tohscl_throughput: %d pixels/dppclk\n"
1508 "max_hscl_ratio: %d\n"
1509 "max_vscl_ratio: %d\n"
1510 "max_hscl_taps: %d\n"
1511 "max_vscl_taps: %d\n"
1512 "pte_buffer_size_in_requests: %d\n"
1513 "dispclk_ramping_margin: %d %\n"
1514 "under_scan_factor: %d %\n"
1515 "max_inter_dcn_tile_repeaters: %d\n"
1516 "can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n"
1517 "bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n"
1518 "dcfclk_cstate_latency: %d\n",
1519 dc
->dcn_ip
->rob_buffer_size_in_kbyte
,
1520 dc
->dcn_ip
->det_buffer_size_in_kbyte
,
1521 dc
->dcn_ip
->dpp_output_buffer_pixels
,
1522 dc
->dcn_ip
->opp_output_buffer_lines
,
1523 dc
->dcn_ip
->pixel_chunk_size_in_kbyte
,
1524 dc
->dcn_ip
->pte_enable
,
1525 dc
->dcn_ip
->pte_chunk_size
,
1526 dc
->dcn_ip
->meta_chunk_size
,
1527 dc
->dcn_ip
->writeback_chunk_size
,
1528 dc
->dcn_ip
->odm_capability
,
1529 dc
->dcn_ip
->dsc_capability
,
1530 dc
->dcn_ip
->line_buffer_size
,
1531 dc
->dcn_ip
->max_line_buffer_lines
,
1532 dc
->dcn_ip
->is_line_buffer_bpp_fixed
,
1533 dc
->dcn_ip
->line_buffer_fixed_bpp
,
1534 dc
->dcn_ip
->writeback_luma_buffer_size
,
1535 dc
->dcn_ip
->writeback_chroma_buffer_size
,
1536 dc
->dcn_ip
->max_num_dpp
,
1537 dc
->dcn_ip
->max_num_writeback
,
1538 dc
->dcn_ip
->max_dchub_topscl_throughput
,
1539 dc
->dcn_ip
->max_pscl_tolb_throughput
,
1540 dc
->dcn_ip
->max_lb_tovscl_throughput
,
1541 dc
->dcn_ip
->max_vscl_tohscl_throughput
,
1542 dc
->dcn_ip
->max_hscl_ratio
,
1543 dc
->dcn_ip
->max_vscl_ratio
,
1544 dc
->dcn_ip
->max_hscl_taps
,
1545 dc
->dcn_ip
->max_vscl_taps
,
1546 dc
->dcn_ip
->pte_buffer_size_in_requests
,
1547 dc
->dcn_ip
->dispclk_ramping_margin
,
1548 dc
->dcn_ip
->under_scan_factor
* 100,
1549 dc
->dcn_ip
->max_inter_dcn_tile_repeaters
,
1550 dc
->dcn_ip
->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one
,
1551 dc
->dcn_ip
->bug_forcing_luma_and_chroma_request_to_same_size_fixed
,
1552 dc
->dcn_ip
->dcfclk_cstate_latency
);
1553 dc
->dml
.soc
.vmin
.socclk_mhz
= dc
->dcn_soc
->socclk
;
1554 dc
->dml
.soc
.vmid
.socclk_mhz
= dc
->dcn_soc
->socclk
;
1555 dc
->dml
.soc
.vnom
.socclk_mhz
= dc
->dcn_soc
->socclk
;
1556 dc
->dml
.soc
.vmax
.socclk_mhz
= dc
->dcn_soc
->socclk
;
1558 dc
->dml
.soc
.vmin
.dcfclk_mhz
= dc
->dcn_soc
->dcfclkv_min0p65
;
1559 dc
->dml
.soc
.vmid
.dcfclk_mhz
= dc
->dcn_soc
->dcfclkv_mid0p72
;
1560 dc
->dml
.soc
.vnom
.dcfclk_mhz
= dc
->dcn_soc
->dcfclkv_nom0p8
;
1561 dc
->dml
.soc
.vmax
.dcfclk_mhz
= dc
->dcn_soc
->dcfclkv_max0p9
;
1563 dc
->dml
.soc
.vmin
.dispclk_mhz
= dc
->dcn_soc
->max_dispclk_vmin0p65
;
1564 dc
->dml
.soc
.vmid
.dispclk_mhz
= dc
->dcn_soc
->max_dispclk_vmid0p72
;
1565 dc
->dml
.soc
.vnom
.dispclk_mhz
= dc
->dcn_soc
->max_dispclk_vnom0p8
;
1566 dc
->dml
.soc
.vmax
.dispclk_mhz
= dc
->dcn_soc
->max_dispclk_vmax0p9
;
1568 dc
->dml
.soc
.vmin
.dppclk_mhz
= dc
->dcn_soc
->max_dppclk_vmin0p65
;
1569 dc
->dml
.soc
.vmid
.dppclk_mhz
= dc
->dcn_soc
->max_dppclk_vmid0p72
;
1570 dc
->dml
.soc
.vnom
.dppclk_mhz
= dc
->dcn_soc
->max_dppclk_vnom0p8
;
1571 dc
->dml
.soc
.vmax
.dppclk_mhz
= dc
->dcn_soc
->max_dppclk_vmax0p9
;
1573 dc
->dml
.soc
.vmin
.phyclk_mhz
= dc
->dcn_soc
->phyclkv_min0p65
;
1574 dc
->dml
.soc
.vmid
.phyclk_mhz
= dc
->dcn_soc
->phyclkv_mid0p72
;
1575 dc
->dml
.soc
.vnom
.phyclk_mhz
= dc
->dcn_soc
->phyclkv_nom0p8
;
1576 dc
->dml
.soc
.vmax
.phyclk_mhz
= dc
->dcn_soc
->phyclkv_max0p9
;
1578 dc
->dml
.soc
.vmin
.dram_bw_per_chan_gbps
= dc
->dcn_soc
->fabric_and_dram_bandwidth_vmin0p65
;
1579 dc
->dml
.soc
.vmid
.dram_bw_per_chan_gbps
= dc
->dcn_soc
->fabric_and_dram_bandwidth_vmid0p72
;
1580 dc
->dml
.soc
.vnom
.dram_bw_per_chan_gbps
= dc
->dcn_soc
->fabric_and_dram_bandwidth_vnom0p8
;
1581 dc
->dml
.soc
.vmax
.dram_bw_per_chan_gbps
= dc
->dcn_soc
->fabric_and_dram_bandwidth_vmax0p9
;
1583 dc
->dml
.soc
.sr_exit_time_us
= dc
->dcn_soc
->sr_exit_time
;
1584 dc
->dml
.soc
.sr_enter_plus_exit_time_us
= dc
->dcn_soc
->sr_enter_plus_exit_time
;
1585 dc
->dml
.soc
.urgent_latency_us
= dc
->dcn_soc
->urgent_latency
;
1586 dc
->dml
.soc
.writeback_latency_us
= dc
->dcn_soc
->write_back_latency
;
1587 dc
->dml
.soc
.ideal_dram_bw_after_urgent_percent
=
1588 dc
->dcn_soc
->percent_of_ideal_drambw_received_after_urg_latency
;
1589 dc
->dml
.soc
.max_request_size_bytes
= dc
->dcn_soc
->max_request_size
;
1590 dc
->dml
.soc
.downspread_percent
= dc
->dcn_soc
->downspreading
;
1591 dc
->dml
.soc
.round_trip_ping_latency_dcfclk_cycles
=
1592 dc
->dcn_soc
->round_trip_ping_latency_cycles
;
1593 dc
->dml
.soc
.urgent_out_of_order_return_per_channel_bytes
=
1594 dc
->dcn_soc
->urgent_out_of_order_return_per_channel
;
1595 dc
->dml
.soc
.num_chans
= dc
->dcn_soc
->number_of_channels
;
1596 dc
->dml
.soc
.vmm_page_size_bytes
= dc
->dcn_soc
->vmm_page_size
;
1597 dc
->dml
.soc
.dram_clock_change_latency_us
= dc
->dcn_soc
->dram_clock_change_latency
;
1598 dc
->dml
.soc
.return_bus_width_bytes
= dc
->dcn_soc
->return_bus_width
;
1600 dc
->dml
.ip
.rob_buffer_size_kbytes
= dc
->dcn_ip
->rob_buffer_size_in_kbyte
;
1601 dc
->dml
.ip
.det_buffer_size_kbytes
= dc
->dcn_ip
->det_buffer_size_in_kbyte
;
1602 dc
->dml
.ip
.dpp_output_buffer_pixels
= dc
->dcn_ip
->dpp_output_buffer_pixels
;
1603 dc
->dml
.ip
.opp_output_buffer_lines
= dc
->dcn_ip
->opp_output_buffer_lines
;
1604 dc
->dml
.ip
.pixel_chunk_size_kbytes
= dc
->dcn_ip
->pixel_chunk_size_in_kbyte
;
1605 dc
->dml
.ip
.pte_enable
= dc
->dcn_ip
->pte_enable
== dcn_bw_yes
;
1606 dc
->dml
.ip
.pte_chunk_size_kbytes
= dc
->dcn_ip
->pte_chunk_size
;
1607 dc
->dml
.ip
.meta_chunk_size_kbytes
= dc
->dcn_ip
->meta_chunk_size
;
1608 dc
->dml
.ip
.writeback_chunk_size_kbytes
= dc
->dcn_ip
->writeback_chunk_size
;
1609 dc
->dml
.ip
.line_buffer_size_bits
= dc
->dcn_ip
->line_buffer_size
;
1610 dc
->dml
.ip
.max_line_buffer_lines
= dc
->dcn_ip
->max_line_buffer_lines
;
1611 dc
->dml
.ip
.IsLineBufferBppFixed
= dc
->dcn_ip
->is_line_buffer_bpp_fixed
== dcn_bw_yes
;
1612 dc
->dml
.ip
.LineBufferFixedBpp
= dc
->dcn_ip
->line_buffer_fixed_bpp
;
1613 dc
->dml
.ip
.writeback_luma_buffer_size_kbytes
= dc
->dcn_ip
->writeback_luma_buffer_size
;
1614 dc
->dml
.ip
.writeback_chroma_buffer_size_kbytes
= dc
->dcn_ip
->writeback_chroma_buffer_size
;
1615 dc
->dml
.ip
.max_num_dpp
= dc
->dcn_ip
->max_num_dpp
;
1616 dc
->dml
.ip
.max_num_wb
= dc
->dcn_ip
->max_num_writeback
;
1617 dc
->dml
.ip
.max_dchub_pscl_bw_pix_per_clk
= dc
->dcn_ip
->max_dchub_topscl_throughput
;
1618 dc
->dml
.ip
.max_pscl_lb_bw_pix_per_clk
= dc
->dcn_ip
->max_pscl_tolb_throughput
;
1619 dc
->dml
.ip
.max_lb_vscl_bw_pix_per_clk
= dc
->dcn_ip
->max_lb_tovscl_throughput
;
1620 dc
->dml
.ip
.max_vscl_hscl_bw_pix_per_clk
= dc
->dcn_ip
->max_vscl_tohscl_throughput
;
1621 dc
->dml
.ip
.max_hscl_ratio
= dc
->dcn_ip
->max_hscl_ratio
;
1622 dc
->dml
.ip
.max_vscl_ratio
= dc
->dcn_ip
->max_vscl_ratio
;
1623 dc
->dml
.ip
.max_hscl_taps
= dc
->dcn_ip
->max_hscl_taps
;
1624 dc
->dml
.ip
.max_vscl_taps
= dc
->dcn_ip
->max_vscl_taps
;
1625 /*pte_buffer_size_in_requests missing in dml*/
1626 dc
->dml
.ip
.dispclk_ramp_margin_percent
= dc
->dcn_ip
->dispclk_ramping_margin
;
1627 dc
->dml
.ip
.underscan_factor
= dc
->dcn_ip
->under_scan_factor
;
1628 dc
->dml
.ip
.max_inter_dcn_tile_repeaters
= dc
->dcn_ip
->max_inter_dcn_tile_repeaters
;
1629 dc
->dml
.ip
.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one
=
1630 dc
->dcn_ip
->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one
== dcn_bw_yes
;
1631 dc
->dml
.ip
.bug_forcing_LC_req_same_size_fixed
=
1632 dc
->dcn_ip
->bug_forcing_luma_and_chroma_request_to_same_size_fixed
== dcn_bw_yes
;
1633 dc
->dml
.ip
.dcfclk_cstate_latency
= dc
->dcn_ip
->dcfclk_cstate_latency
;