]>
git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/gpu/drm/amd/display/dc/core/dc_debug.c
2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 * Created on: Nov 3, 2016
30 #include "dm_services.h"
34 #include "core_status.h"
35 #include "core_types.h"
36 #include "hw_sequencer.h"
40 #define SURFACE_TRACE(...) do {\
41 if (dc->debug.surface_trace) \
42 dm_logger_write(logger, \
47 #define TIMING_TRACE(...) do {\
48 if (dc->debug.timing_trace) \
49 dm_logger_write(logger, \
54 #define CLOCK_TRACE(...) do {\
55 if (dc->debug.clock_trace) \
56 dm_logger_write(logger, \
57 LOG_BANDWIDTH_CALCS, \
61 void pre_surface_trace(
63 const struct dc_plane_state
*const *plane_states
,
67 struct dc
*core_dc
= dc
;
68 struct dal_logger
*logger
= core_dc
->ctx
->logger
;
70 for (i
= 0; i
< surface_count
; i
++) {
71 const struct dc_plane_state
*plane_state
= plane_states
[i
];
73 SURFACE_TRACE("Planes %d:\n", i
);
76 "plane_state->visible = %d;\n"
77 "plane_state->flip_immediate = %d;\n"
78 "plane_state->address.type = %d;\n"
79 "plane_state->address.grph.addr.quad_part = 0x%X;\n"
80 "plane_state->address.grph.meta_addr.quad_part = 0x%X;\n"
81 "plane_state->scaling_quality.h_taps = %d;\n"
82 "plane_state->scaling_quality.v_taps = %d;\n"
83 "plane_state->scaling_quality.h_taps_c = %d;\n"
84 "plane_state->scaling_quality.v_taps_c = %d;\n",
86 plane_state
->flip_immediate
,
87 plane_state
->address
.type
,
88 plane_state
->address
.grph
.addr
.quad_part
,
89 plane_state
->address
.grph
.meta_addr
.quad_part
,
90 plane_state
->scaling_quality
.h_taps
,
91 plane_state
->scaling_quality
.v_taps
,
92 plane_state
->scaling_quality
.h_taps_c
,
93 plane_state
->scaling_quality
.v_taps_c
);
96 "plane_state->src_rect.x = %d;\n"
97 "plane_state->src_rect.y = %d;\n"
98 "plane_state->src_rect.width = %d;\n"
99 "plane_state->src_rect.height = %d;\n"
100 "plane_state->dst_rect.x = %d;\n"
101 "plane_state->dst_rect.y = %d;\n"
102 "plane_state->dst_rect.width = %d;\n"
103 "plane_state->dst_rect.height = %d;\n"
104 "plane_state->clip_rect.x = %d;\n"
105 "plane_state->clip_rect.y = %d;\n"
106 "plane_state->clip_rect.width = %d;\n"
107 "plane_state->clip_rect.height = %d;\n",
108 plane_state
->src_rect
.x
,
109 plane_state
->src_rect
.y
,
110 plane_state
->src_rect
.width
,
111 plane_state
->src_rect
.height
,
112 plane_state
->dst_rect
.x
,
113 plane_state
->dst_rect
.y
,
114 plane_state
->dst_rect
.width
,
115 plane_state
->dst_rect
.height
,
116 plane_state
->clip_rect
.x
,
117 plane_state
->clip_rect
.y
,
118 plane_state
->clip_rect
.width
,
119 plane_state
->clip_rect
.height
);
122 "plane_state->plane_size.grph.surface_size.x = %d;\n"
123 "plane_state->plane_size.grph.surface_size.y = %d;\n"
124 "plane_state->plane_size.grph.surface_size.width = %d;\n"
125 "plane_state->plane_size.grph.surface_size.height = %d;\n"
126 "plane_state->plane_size.grph.surface_pitch = %d;\n",
127 plane_state
->plane_size
.grph
.surface_size
.x
,
128 plane_state
->plane_size
.grph
.surface_size
.y
,
129 plane_state
->plane_size
.grph
.surface_size
.width
,
130 plane_state
->plane_size
.grph
.surface_size
.height
,
131 plane_state
->plane_size
.grph
.surface_pitch
);
135 "plane_state->tiling_info.gfx8.num_banks = %d;\n"
136 "plane_state->tiling_info.gfx8.bank_width = %d;\n"
137 "plane_state->tiling_info.gfx8.bank_width_c = %d;\n"
138 "plane_state->tiling_info.gfx8.bank_height = %d;\n"
139 "plane_state->tiling_info.gfx8.bank_height_c = %d;\n"
140 "plane_state->tiling_info.gfx8.tile_aspect = %d;\n"
141 "plane_state->tiling_info.gfx8.tile_aspect_c = %d;\n"
142 "plane_state->tiling_info.gfx8.tile_split = %d;\n"
143 "plane_state->tiling_info.gfx8.tile_split_c = %d;\n"
144 "plane_state->tiling_info.gfx8.tile_mode = %d;\n"
145 "plane_state->tiling_info.gfx8.tile_mode_c = %d;\n",
146 plane_state
->tiling_info
.gfx8
.num_banks
,
147 plane_state
->tiling_info
.gfx8
.bank_width
,
148 plane_state
->tiling_info
.gfx8
.bank_width_c
,
149 plane_state
->tiling_info
.gfx8
.bank_height
,
150 plane_state
->tiling_info
.gfx8
.bank_height_c
,
151 plane_state
->tiling_info
.gfx8
.tile_aspect
,
152 plane_state
->tiling_info
.gfx8
.tile_aspect_c
,
153 plane_state
->tiling_info
.gfx8
.tile_split
,
154 plane_state
->tiling_info
.gfx8
.tile_split_c
,
155 plane_state
->tiling_info
.gfx8
.tile_mode
,
156 plane_state
->tiling_info
.gfx8
.tile_mode_c
);
159 "plane_state->tiling_info.gfx8.pipe_config = %d;\n"
160 "plane_state->tiling_info.gfx8.array_mode = %d;\n"
161 "plane_state->color_space = %d;\n"
162 "plane_state->dcc.enable = %d;\n"
163 "plane_state->format = %d;\n"
164 "plane_state->rotation = %d;\n"
165 "plane_state->stereo_format = %d;\n",
166 plane_state
->tiling_info
.gfx8
.pipe_config
,
167 plane_state
->tiling_info
.gfx8
.array_mode
,
168 plane_state
->color_space
,
169 plane_state
->dcc
.enable
,
171 plane_state
->rotation
,
172 plane_state
->stereo_format
);
174 SURFACE_TRACE("plane_state->tiling_info.gfx9.swizzle = %d;\n",
175 plane_state
->tiling_info
.gfx9
.swizzle
);
182 void update_surface_trace(
184 const struct dc_surface_update
*updates
,
188 struct dc
*core_dc
= dc
;
189 struct dal_logger
*logger
= core_dc
->ctx
->logger
;
191 for (i
= 0; i
< surface_count
; i
++) {
192 const struct dc_surface_update
*update
= &updates
[i
];
194 SURFACE_TRACE("Update %d\n", i
);
195 if (update
->flip_addr
) {
196 SURFACE_TRACE("flip_addr->address.type = %d;\n"
197 "flip_addr->address.grph.addr.quad_part = 0x%X;\n"
198 "flip_addr->address.grph.meta_addr.quad_part = 0x%X;\n"
199 "flip_addr->flip_immediate = %d;\n",
200 update
->flip_addr
->address
.type
,
201 update
->flip_addr
->address
.grph
.addr
.quad_part
,
202 update
->flip_addr
->address
.grph
.meta_addr
.quad_part
,
203 update
->flip_addr
->flip_immediate
);
206 if (update
->plane_info
) {
208 "plane_info->color_space = %d;\n"
209 "plane_info->format = %d;\n"
210 "plane_info->plane_size.grph.surface_pitch = %d;\n"
211 "plane_info->plane_size.grph.surface_size.height = %d;\n"
212 "plane_info->plane_size.grph.surface_size.width = %d;\n"
213 "plane_info->plane_size.grph.surface_size.x = %d;\n"
214 "plane_info->plane_size.grph.surface_size.y = %d;\n"
215 "plane_info->rotation = %d;\n",
216 update
->plane_info
->color_space
,
217 update
->plane_info
->format
,
218 update
->plane_info
->plane_size
.grph
.surface_pitch
,
219 update
->plane_info
->plane_size
.grph
.surface_size
.height
,
220 update
->plane_info
->plane_size
.grph
.surface_size
.width
,
221 update
->plane_info
->plane_size
.grph
.surface_size
.x
,
222 update
->plane_info
->plane_size
.grph
.surface_size
.y
,
223 update
->plane_info
->rotation
,
224 update
->plane_info
->stereo_format
);
227 "plane_info->tiling_info.gfx8.num_banks = %d;\n"
228 "plane_info->tiling_info.gfx8.bank_width = %d;\n"
229 "plane_info->tiling_info.gfx8.bank_width_c = %d;\n"
230 "plane_info->tiling_info.gfx8.bank_height = %d;\n"
231 "plane_info->tiling_info.gfx8.bank_height_c = %d;\n"
232 "plane_info->tiling_info.gfx8.tile_aspect = %d;\n"
233 "plane_info->tiling_info.gfx8.tile_aspect_c = %d;\n"
234 "plane_info->tiling_info.gfx8.tile_split = %d;\n"
235 "plane_info->tiling_info.gfx8.tile_split_c = %d;\n"
236 "plane_info->tiling_info.gfx8.tile_mode = %d;\n"
237 "plane_info->tiling_info.gfx8.tile_mode_c = %d;\n",
238 update
->plane_info
->tiling_info
.gfx8
.num_banks
,
239 update
->plane_info
->tiling_info
.gfx8
.bank_width
,
240 update
->plane_info
->tiling_info
.gfx8
.bank_width_c
,
241 update
->plane_info
->tiling_info
.gfx8
.bank_height
,
242 update
->plane_info
->tiling_info
.gfx8
.bank_height_c
,
243 update
->plane_info
->tiling_info
.gfx8
.tile_aspect
,
244 update
->plane_info
->tiling_info
.gfx8
.tile_aspect_c
,
245 update
->plane_info
->tiling_info
.gfx8
.tile_split
,
246 update
->plane_info
->tiling_info
.gfx8
.tile_split_c
,
247 update
->plane_info
->tiling_info
.gfx8
.tile_mode
,
248 update
->plane_info
->tiling_info
.gfx8
.tile_mode_c
);
251 "plane_info->tiling_info.gfx8.pipe_config = %d;\n"
252 "plane_info->tiling_info.gfx8.array_mode = %d;\n"
253 "plane_info->visible = %d;\n"
254 "plane_info->per_pixel_alpha = %d;\n",
255 update
->plane_info
->tiling_info
.gfx8
.pipe_config
,
256 update
->plane_info
->tiling_info
.gfx8
.array_mode
,
257 update
->plane_info
->visible
,
258 update
->plane_info
->per_pixel_alpha
);
260 SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n",
261 update
->plane_info
->tiling_info
.gfx9
.swizzle
);
264 if (update
->scaling_info
) {
266 "scaling_info->src_rect.x = %d;\n"
267 "scaling_info->src_rect.y = %d;\n"
268 "scaling_info->src_rect.width = %d;\n"
269 "scaling_info->src_rect.height = %d;\n"
270 "scaling_info->dst_rect.x = %d;\n"
271 "scaling_info->dst_rect.y = %d;\n"
272 "scaling_info->dst_rect.width = %d;\n"
273 "scaling_info->dst_rect.height = %d;\n"
274 "scaling_info->clip_rect.x = %d;\n"
275 "scaling_info->clip_rect.y = %d;\n"
276 "scaling_info->clip_rect.width = %d;\n"
277 "scaling_info->clip_rect.height = %d;\n"
278 "scaling_info->scaling_quality.h_taps = %d;\n"
279 "scaling_info->scaling_quality.v_taps = %d;\n"
280 "scaling_info->scaling_quality.h_taps_c = %d;\n"
281 "scaling_info->scaling_quality.v_taps_c = %d;\n",
282 update
->scaling_info
->src_rect
.x
,
283 update
->scaling_info
->src_rect
.y
,
284 update
->scaling_info
->src_rect
.width
,
285 update
->scaling_info
->src_rect
.height
,
286 update
->scaling_info
->dst_rect
.x
,
287 update
->scaling_info
->dst_rect
.y
,
288 update
->scaling_info
->dst_rect
.width
,
289 update
->scaling_info
->dst_rect
.height
,
290 update
->scaling_info
->clip_rect
.x
,
291 update
->scaling_info
->clip_rect
.y
,
292 update
->scaling_info
->clip_rect
.width
,
293 update
->scaling_info
->clip_rect
.height
,
294 update
->scaling_info
->scaling_quality
.h_taps
,
295 update
->scaling_info
->scaling_quality
.v_taps
,
296 update
->scaling_info
->scaling_quality
.h_taps_c
,
297 update
->scaling_info
->scaling_quality
.v_taps_c
);
304 void post_surface_trace(struct dc
*dc
)
306 struct dc
*core_dc
= dc
;
307 struct dal_logger
*logger
= core_dc
->ctx
->logger
;
309 SURFACE_TRACE("post surface process.\n");
313 void context_timing_trace(
315 struct resource_context
*res_ctx
)
318 struct dc
*core_dc
= dc
;
319 struct dal_logger
*logger
= core_dc
->ctx
->logger
;
320 int h_pos
[MAX_PIPES
], v_pos
[MAX_PIPES
];
321 struct crtc_position position
;
322 unsigned int underlay_idx
= core_dc
->res_pool
->underlay_pipe_index
;
325 for (i
= 0; i
< core_dc
->res_pool
->pipe_count
; i
++) {
326 struct pipe_ctx
*pipe_ctx
= &res_ctx
->pipe_ctx
[i
];
327 /* get_position() returns CRTC vertical/horizontal counter
328 * hence not applicable for underlay pipe
330 if (pipe_ctx
->stream
== NULL
331 || pipe_ctx
->pipe_idx
== underlay_idx
)
334 pipe_ctx
->stream_res
.tg
->funcs
->get_position(pipe_ctx
->stream_res
.tg
, &position
);
335 h_pos
[i
] = position
.horizontal_count
;
336 v_pos
[i
] = position
.vertical_count
;
338 for (i
= 0; i
< core_dc
->res_pool
->pipe_count
; i
++) {
339 struct pipe_ctx
*pipe_ctx
= &res_ctx
->pipe_ctx
[i
];
341 if (pipe_ctx
->stream
== NULL
)
344 TIMING_TRACE("OTG_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n",
345 pipe_ctx
->stream_res
.tg
->inst
,
346 pipe_ctx
->stream
->timing
.h_total
,
347 pipe_ctx
->stream
->timing
.v_total
,
352 void context_clock_trace(
354 struct dc_state
*context
)
356 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
357 struct dc
*core_dc
= dc
;
358 struct dal_logger
*logger
= core_dc
->ctx
->logger
;
360 CLOCK_TRACE("Current: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n"
361 "dcfclk_deep_sleep_khz:%d fclk_khz:%d\n"
362 "dram_ccm_us:%d min_active_dram_ccm_us:%d\n",
363 context
->bw
.dcn
.calc_clk
.dispclk_khz
,
364 context
->bw
.dcn
.calc_clk
.dppclk_div
,
365 context
->bw
.dcn
.calc_clk
.dcfclk_khz
,
366 context
->bw
.dcn
.calc_clk
.dcfclk_deep_sleep_khz
,
367 context
->bw
.dcn
.calc_clk
.fclk_khz
,
368 context
->bw
.dcn
.calc_clk
.dram_ccm_us
,
369 context
->bw
.dcn
.calc_clk
.min_active_dram_ccm_us
);
370 CLOCK_TRACE("Calculated: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n"
371 "dcfclk_deep_sleep_khz:%d fclk_khz:%d\n"
372 "dram_ccm_us:%d min_active_dram_ccm_us:%d\n",
373 context
->bw
.dcn
.calc_clk
.dispclk_khz
,
374 context
->bw
.dcn
.calc_clk
.dppclk_div
,
375 context
->bw
.dcn
.calc_clk
.dcfclk_khz
,
376 context
->bw
.dcn
.calc_clk
.dcfclk_deep_sleep_khz
,
377 context
->bw
.dcn
.calc_clk
.fclk_khz
,
378 context
->bw
.dcn
.calc_clk
.dram_ccm_us
,
379 context
->bw
.dcn
.calc_clk
.min_active_dram_ccm_us
);