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Merge drm/drm-next into drm-misc-next
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / core / dc_link_dp.c
1 /* Copyright 2015 Advanced Micro Devices, Inc. */
2 #include "dm_services.h"
3 #include "dc.h"
4 #include "dc_link_dp.h"
5 #include "dm_helpers.h"
6 #include "opp.h"
7 #include "dsc.h"
8 #include "resource.h"
9
10 #include "inc/core_types.h"
11 #include "link_hwss.h"
12 #include "dc_link_ddc.h"
13 #include "core_status.h"
14 #include "dpcd_defs.h"
15 #include "dc_dmub_srv.h"
16 #include "dce/dmub_hw_lock_mgr.h"
17
18 /*Travis*/
19 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
20 /*Nutmeg*/
21 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
22
23 #define DC_LOGGER \
24 link->ctx->logger
25 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
26
27 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50
28
29 /* maximum pre emphasis level allowed for each voltage swing level*/
30 static const enum dc_pre_emphasis
31 voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
32 PRE_EMPHASIS_LEVEL2,
33 PRE_EMPHASIS_LEVEL1,
34 PRE_EMPHASIS_DISABLED };
35
36 enum {
37 POST_LT_ADJ_REQ_LIMIT = 6,
38 POST_LT_ADJ_REQ_TIMEOUT = 200
39 };
40
41 enum {
42 LINK_TRAINING_MAX_RETRY_COUNT = 5,
43 /* to avoid infinite loop where-in the receiver
44 * switches between different VS
45 */
46 LINK_TRAINING_MAX_CR_RETRY = 100
47 };
48
49 static bool decide_fallback_link_setting(
50 struct dc_link_settings initial_link_settings,
51 struct dc_link_settings *current_link_setting,
52 enum link_training_result training_result);
53 static struct dc_link_settings get_common_supported_link_settings(
54 struct dc_link_settings link_setting_a,
55 struct dc_link_settings link_setting_b);
56
57 static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
58 const struct dc_link_settings *link_settings)
59 {
60 union training_aux_rd_interval training_rd_interval;
61 uint32_t wait_in_micro_secs = 100;
62
63 memset(&training_rd_interval, 0, sizeof(training_rd_interval));
64 core_link_read_dpcd(
65 link,
66 DP_TRAINING_AUX_RD_INTERVAL,
67 (uint8_t *)&training_rd_interval,
68 sizeof(training_rd_interval));
69 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
70 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
71 return wait_in_micro_secs;
72 }
73
74 static uint32_t get_eq_training_aux_rd_interval(
75 struct dc_link *link,
76 const struct dc_link_settings *link_settings)
77 {
78 union training_aux_rd_interval training_rd_interval;
79 uint32_t wait_in_micro_secs = 400;
80
81 memset(&training_rd_interval, 0, sizeof(training_rd_interval));
82 /* overwrite the delay if rev > 1.1*/
83 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
84 /* DP 1.2 or later - retrieve delay through
85 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
86 core_link_read_dpcd(
87 link,
88 DP_TRAINING_AUX_RD_INTERVAL,
89 (uint8_t *)&training_rd_interval,
90 sizeof(training_rd_interval));
91
92 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
93 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
94 }
95
96 return wait_in_micro_secs;
97 }
98
99 static void wait_for_training_aux_rd_interval(
100 struct dc_link *link,
101 uint32_t wait_in_micro_secs)
102 {
103 udelay(wait_in_micro_secs);
104
105 DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
106 __func__,
107 wait_in_micro_secs);
108 }
109
110 static void dpcd_set_training_pattern(
111 struct dc_link *link,
112 union dpcd_training_pattern dpcd_pattern)
113 {
114 core_link_write_dpcd(
115 link,
116 DP_TRAINING_PATTERN_SET,
117 &dpcd_pattern.raw,
118 1);
119
120 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
121 __func__,
122 DP_TRAINING_PATTERN_SET,
123 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
124 }
125
126 static enum dc_dp_training_pattern decide_cr_training_pattern(
127 const struct dc_link_settings *link_settings)
128 {
129 return DP_TRAINING_PATTERN_SEQUENCE_1;
130 }
131
132 static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
133 const struct dc_link_settings *link_settings)
134 {
135 enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
136 struct encoder_feature_support *features = &link->link_enc->features;
137 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
138
139 if (features->flags.bits.IS_TPS3_CAPABLE)
140 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
141
142 if (features->flags.bits.IS_TPS4_CAPABLE)
143 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
144
145 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
146 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
147 return DP_TRAINING_PATTERN_SEQUENCE_4;
148
149 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
150 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
151 return DP_TRAINING_PATTERN_SEQUENCE_3;
152
153 return DP_TRAINING_PATTERN_SEQUENCE_2;
154 }
155
156 static void dpcd_set_link_settings(
157 struct dc_link *link,
158 const struct link_training_settings *lt_settings)
159 {
160 uint8_t rate;
161
162 union down_spread_ctrl downspread = { {0} };
163 union lane_count_set lane_count_set = { {0} };
164
165 downspread.raw = (uint8_t)
166 (lt_settings->link_settings.link_spread);
167
168 lane_count_set.bits.LANE_COUNT_SET =
169 lt_settings->link_settings.lane_count;
170
171 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
172 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
173
174
175 if (lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
176 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
177 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
178 }
179
180 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
181 &downspread.raw, sizeof(downspread));
182
183 core_link_write_dpcd(link, DP_LANE_COUNT_SET,
184 &lane_count_set.raw, 1);
185
186 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
187 lt_settings->link_settings.use_link_rate_set == true) {
188 rate = 0;
189 /* WA for some MUX chips that will power down with eDP and lose supported
190 * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
191 * MUX chip gets link rate set back before link training.
192 */
193 if (link->connector_signal == SIGNAL_TYPE_EDP) {
194 uint8_t supported_link_rates[16];
195
196 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
197 supported_link_rates, sizeof(supported_link_rates));
198 }
199 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
200 core_link_write_dpcd(link, DP_LINK_RATE_SET,
201 &lt_settings->link_settings.link_rate_set, 1);
202 } else {
203 rate = (uint8_t) (lt_settings->link_settings.link_rate);
204 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
205 }
206
207 if (rate) {
208 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
209 __func__,
210 DP_LINK_BW_SET,
211 lt_settings->link_settings.link_rate,
212 DP_LANE_COUNT_SET,
213 lt_settings->link_settings.lane_count,
214 lt_settings->enhanced_framing,
215 DP_DOWNSPREAD_CTRL,
216 lt_settings->link_settings.link_spread);
217 } else {
218 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
219 __func__,
220 DP_LINK_RATE_SET,
221 lt_settings->link_settings.link_rate_set,
222 DP_LANE_COUNT_SET,
223 lt_settings->link_settings.lane_count,
224 lt_settings->enhanced_framing,
225 DP_DOWNSPREAD_CTRL,
226 lt_settings->link_settings.link_spread);
227 }
228 }
229
230 static enum dpcd_training_patterns
231 dc_dp_training_pattern_to_dpcd_training_pattern(
232 struct dc_link *link,
233 enum dc_dp_training_pattern pattern)
234 {
235 enum dpcd_training_patterns dpcd_tr_pattern =
236 DPCD_TRAINING_PATTERN_VIDEOIDLE;
237
238 switch (pattern) {
239 case DP_TRAINING_PATTERN_SEQUENCE_1:
240 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
241 break;
242 case DP_TRAINING_PATTERN_SEQUENCE_2:
243 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
244 break;
245 case DP_TRAINING_PATTERN_SEQUENCE_3:
246 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
247 break;
248 case DP_TRAINING_PATTERN_SEQUENCE_4:
249 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
250 break;
251 default:
252 ASSERT(0);
253 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
254 __func__, pattern);
255 break;
256 }
257
258 return dpcd_tr_pattern;
259 }
260
261 static uint8_t dc_dp_initialize_scrambling_data_symbols(
262 struct dc_link *link,
263 enum dc_dp_training_pattern pattern)
264 {
265 uint8_t disable_scrabled_data_symbols = 0;
266
267 switch (pattern) {
268 case DP_TRAINING_PATTERN_SEQUENCE_1:
269 case DP_TRAINING_PATTERN_SEQUENCE_2:
270 case DP_TRAINING_PATTERN_SEQUENCE_3:
271 disable_scrabled_data_symbols = 1;
272 break;
273 case DP_TRAINING_PATTERN_SEQUENCE_4:
274 disable_scrabled_data_symbols = 0;
275 break;
276 default:
277 ASSERT(0);
278 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
279 __func__, pattern);
280 break;
281 }
282 return disable_scrabled_data_symbols;
283 }
284
285 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
286 {
287 return (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
288 }
289
290 static void dpcd_set_lt_pattern_and_lane_settings(
291 struct dc_link *link,
292 const struct link_training_settings *lt_settings,
293 enum dc_dp_training_pattern pattern,
294 uint32_t offset)
295 {
296 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
297
298 uint32_t dpcd_base_lt_offset;
299
300 uint8_t dpcd_lt_buffer[5] = {0};
301 union dpcd_training_pattern dpcd_pattern = { {0} };
302 uint32_t lane;
303 uint32_t size_in_bytes;
304 bool edp_workaround = false; /* TODO link_prop.INTERNAL */
305 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
306
307 if (is_repeater(link, offset))
308 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
309 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
310
311 /*****************************************************************
312 * DpcdAddress_TrainingPatternSet
313 *****************************************************************/
314 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
315 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
316
317 dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
318 dc_dp_initialize_scrambling_data_symbols(link, pattern);
319
320 dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
321 = dpcd_pattern.raw;
322
323 if (is_repeater(link, offset)) {
324 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
325 __func__,
326 offset,
327 dpcd_base_lt_offset,
328 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
329 } else {
330 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
331 __func__,
332 dpcd_base_lt_offset,
333 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
334 }
335 /*****************************************************************
336 * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
337 *****************************************************************/
338 for (lane = 0; lane <
339 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
340
341 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
342 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
343 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
344 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
345
346 dpcd_lane[lane].bits.MAX_SWING_REACHED =
347 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
348 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
349 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
350 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
351 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
352 }
353
354 /* concatenate everything into one buffer*/
355
356 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
357
358 // 0x00103 - 0x00102
359 memmove(
360 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
361 dpcd_lane,
362 size_in_bytes);
363
364 if (is_repeater(link, offset)) {
365 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
366 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
367 __func__,
368 offset,
369 dpcd_base_lt_offset,
370 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
371 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
372 dpcd_lane[0].bits.MAX_SWING_REACHED,
373 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
374 } else {
375 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
376 __func__,
377 dpcd_base_lt_offset,
378 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
379 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
380 dpcd_lane[0].bits.MAX_SWING_REACHED,
381 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
382 }
383 if (edp_workaround) {
384 /* for eDP write in 2 parts because the 5-byte burst is
385 * causing issues on some eDP panels (EPR#366724)
386 */
387 core_link_write_dpcd(
388 link,
389 DP_TRAINING_PATTERN_SET,
390 &dpcd_pattern.raw,
391 sizeof(dpcd_pattern.raw));
392
393 core_link_write_dpcd(
394 link,
395 DP_TRAINING_LANE0_SET,
396 (uint8_t *)(dpcd_lane),
397 size_in_bytes);
398
399 } else
400 /* write it all in (1 + number-of-lanes)-byte burst*/
401 core_link_write_dpcd(
402 link,
403 dpcd_base_lt_offset,
404 dpcd_lt_buffer,
405 size_in_bytes + sizeof(dpcd_pattern.raw));
406
407 link->cur_lane_setting = lt_settings->lane_settings[0];
408 }
409
410 static bool is_cr_done(enum dc_lane_count ln_count,
411 union lane_status *dpcd_lane_status)
412 {
413 uint32_t lane;
414 /*LANEx_CR_DONE bits All 1's?*/
415 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
416 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
417 return false;
418 }
419 return true;
420 }
421
422 static bool is_ch_eq_done(enum dc_lane_count ln_count,
423 union lane_status *dpcd_lane_status,
424 union lane_align_status_updated *lane_status_updated)
425 {
426 uint32_t lane;
427 if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
428 return false;
429 else {
430 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
431 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
432 !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
433 return false;
434 }
435 }
436 return true;
437 }
438
439 static void update_drive_settings(
440 struct link_training_settings *dest,
441 struct link_training_settings src)
442 {
443 uint32_t lane;
444 for (lane = 0; lane < src.link_settings.lane_count; lane++) {
445 if (dest->voltage_swing == NULL)
446 dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
447 else
448 dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
449
450 if (dest->pre_emphasis == NULL)
451 dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
452 else
453 dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
454
455 if (dest->post_cursor2 == NULL)
456 dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
457 else
458 dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
459 }
460 }
461
462 static uint8_t get_nibble_at_index(const uint8_t *buf,
463 uint32_t index)
464 {
465 uint8_t nibble;
466 nibble = buf[index / 2];
467
468 if (index % 2)
469 nibble >>= 4;
470 else
471 nibble &= 0x0F;
472
473 return nibble;
474 }
475
476 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
477 enum dc_voltage_swing voltage)
478 {
479 enum dc_pre_emphasis pre_emphasis;
480 pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
481
482 if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
483 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
484
485 return pre_emphasis;
486
487 }
488
489 static void find_max_drive_settings(
490 const struct link_training_settings *link_training_setting,
491 struct link_training_settings *max_lt_setting)
492 {
493 uint32_t lane;
494 struct dc_lane_settings max_requested;
495
496 max_requested.VOLTAGE_SWING =
497 link_training_setting->
498 lane_settings[0].VOLTAGE_SWING;
499 max_requested.PRE_EMPHASIS =
500 link_training_setting->
501 lane_settings[0].PRE_EMPHASIS;
502 /*max_requested.postCursor2 =
503 * link_training_setting->laneSettings[0].postCursor2;*/
504
505 /* Determine what the maximum of the requested settings are*/
506 for (lane = 1; lane < link_training_setting->link_settings.lane_count;
507 lane++) {
508 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
509 max_requested.VOLTAGE_SWING)
510
511 max_requested.VOLTAGE_SWING =
512 link_training_setting->
513 lane_settings[lane].VOLTAGE_SWING;
514
515 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
516 max_requested.PRE_EMPHASIS)
517 max_requested.PRE_EMPHASIS =
518 link_training_setting->
519 lane_settings[lane].PRE_EMPHASIS;
520
521 /*
522 if (link_training_setting->laneSettings[lane].postCursor2 >
523 max_requested.postCursor2)
524 {
525 max_requested.postCursor2 =
526 link_training_setting->laneSettings[lane].postCursor2;
527 }
528 */
529 }
530
531 /* make sure the requested settings are
532 * not higher than maximum settings*/
533 if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
534 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
535
536 if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
537 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
538 /*
539 if (max_requested.postCursor2 > PostCursor2_MaxLevel)
540 max_requested.postCursor2 = PostCursor2_MaxLevel;
541 */
542
543 /* make sure the pre-emphasis matches the voltage swing*/
544 if (max_requested.PRE_EMPHASIS >
545 get_max_pre_emphasis_for_voltage_swing(
546 max_requested.VOLTAGE_SWING))
547 max_requested.PRE_EMPHASIS =
548 get_max_pre_emphasis_for_voltage_swing(
549 max_requested.VOLTAGE_SWING);
550
551 /*
552 * Post Cursor2 levels are completely independent from
553 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
554 * can only be applied to each allowable combination of voltage
555 * swing and pre-emphasis levels */
556 /* if ( max_requested.postCursor2 >
557 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
558 * max_requested.postCursor2 =
559 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
560 */
561
562 max_lt_setting->link_settings.link_rate =
563 link_training_setting->link_settings.link_rate;
564 max_lt_setting->link_settings.lane_count =
565 link_training_setting->link_settings.lane_count;
566 max_lt_setting->link_settings.link_spread =
567 link_training_setting->link_settings.link_spread;
568
569 for (lane = 0; lane <
570 link_training_setting->link_settings.lane_count;
571 lane++) {
572 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
573 max_requested.VOLTAGE_SWING;
574 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
575 max_requested.PRE_EMPHASIS;
576 /*max_lt_setting->laneSettings[lane].postCursor2 =
577 * max_requested.postCursor2;
578 */
579 }
580
581 }
582
583 static void get_lane_status_and_drive_settings(
584 struct dc_link *link,
585 const struct link_training_settings *link_training_setting,
586 union lane_status *ln_status,
587 union lane_align_status_updated *ln_status_updated,
588 struct link_training_settings *req_settings,
589 uint32_t offset)
590 {
591 unsigned int lane01_status_address = DP_LANE0_1_STATUS;
592 uint8_t lane_adjust_offset = 4;
593 unsigned int lane01_adjust_address;
594 uint8_t dpcd_buf[6] = {0};
595 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
596 struct link_training_settings request_settings = { {0} };
597 uint32_t lane;
598
599 memset(req_settings, '\0', sizeof(struct link_training_settings));
600
601 if (is_repeater(link, offset)) {
602 lane01_status_address =
603 DP_LANE0_1_STATUS_PHY_REPEATER1 +
604 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
605 lane_adjust_offset = 3;
606 }
607
608 core_link_read_dpcd(
609 link,
610 lane01_status_address,
611 (uint8_t *)(dpcd_buf),
612 sizeof(dpcd_buf));
613
614 for (lane = 0; lane <
615 (uint32_t)(link_training_setting->link_settings.lane_count);
616 lane++) {
617
618 ln_status[lane].raw =
619 get_nibble_at_index(&dpcd_buf[0], lane);
620 dpcd_lane_adjust[lane].raw =
621 get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
622 }
623
624 ln_status_updated->raw = dpcd_buf[2];
625
626 if (is_repeater(link, offset)) {
627 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
628 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
629 __func__,
630 offset,
631 lane01_status_address, dpcd_buf[0],
632 lane01_status_address + 1, dpcd_buf[1]);
633 } else {
634 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
635 __func__,
636 lane01_status_address, dpcd_buf[0],
637 lane01_status_address + 1, dpcd_buf[1]);
638 }
639 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
640
641 if (is_repeater(link, offset))
642 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
643 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
644
645 if (is_repeater(link, offset)) {
646 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
647 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
648 __func__,
649 offset,
650 lane01_adjust_address,
651 dpcd_buf[lane_adjust_offset],
652 lane01_adjust_address + 1,
653 dpcd_buf[lane_adjust_offset + 1]);
654 } else {
655 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
656 __func__,
657 lane01_adjust_address,
658 dpcd_buf[lane_adjust_offset],
659 lane01_adjust_address + 1,
660 dpcd_buf[lane_adjust_offset + 1]);
661 }
662
663 /*copy to req_settings*/
664 request_settings.link_settings.lane_count =
665 link_training_setting->link_settings.lane_count;
666 request_settings.link_settings.link_rate =
667 link_training_setting->link_settings.link_rate;
668 request_settings.link_settings.link_spread =
669 link_training_setting->link_settings.link_spread;
670
671 for (lane = 0; lane <
672 (uint32_t)(link_training_setting->link_settings.lane_count);
673 lane++) {
674
675 request_settings.lane_settings[lane].VOLTAGE_SWING =
676 (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
677 VOLTAGE_SWING_LANE);
678 request_settings.lane_settings[lane].PRE_EMPHASIS =
679 (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
680 PRE_EMPHASIS_LANE);
681 }
682
683 /*Note: for postcursor2, read adjusted
684 * postcursor2 settings from*/
685 /*DpcdAddress_AdjustRequestPostCursor2 =
686 *0x020C (not implemented yet)*/
687
688 /* we find the maximum of the requested settings across all lanes*/
689 /* and set this maximum for all lanes*/
690 find_max_drive_settings(&request_settings, req_settings);
691
692 /* if post cursor 2 is needed in the future,
693 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
694 */
695
696 }
697
698 static void dpcd_set_lane_settings(
699 struct dc_link *link,
700 const struct link_training_settings *link_training_setting,
701 uint32_t offset)
702 {
703 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
704 uint32_t lane;
705 unsigned int lane0_set_address;
706
707 lane0_set_address = DP_TRAINING_LANE0_SET;
708
709 if (is_repeater(link, offset))
710 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
711 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
712
713 for (lane = 0; lane <
714 (uint32_t)(link_training_setting->
715 link_settings.lane_count);
716 lane++) {
717 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
718 (uint8_t)(link_training_setting->
719 lane_settings[lane].VOLTAGE_SWING);
720 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
721 (uint8_t)(link_training_setting->
722 lane_settings[lane].PRE_EMPHASIS);
723 dpcd_lane[lane].bits.MAX_SWING_REACHED =
724 (link_training_setting->
725 lane_settings[lane].VOLTAGE_SWING ==
726 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
727 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
728 (link_training_setting->
729 lane_settings[lane].PRE_EMPHASIS ==
730 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
731 }
732
733 core_link_write_dpcd(link,
734 lane0_set_address,
735 (uint8_t *)(dpcd_lane),
736 link_training_setting->link_settings.lane_count);
737
738 /*
739 if (LTSettings.link.rate == LinkRate_High2)
740 {
741 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
742 for ( uint32_t lane = 0;
743 lane < lane_count_DPMax; lane++)
744 {
745 dpcd_lane2[lane].bits.post_cursor2_set =
746 static_cast<unsigned char>(
747 LTSettings.laneSettings[lane].postCursor2);
748 dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
749 }
750 m_pDpcdAccessSrv->WriteDpcdData(
751 DpcdAddress_Lane0Set2,
752 reinterpret_cast<unsigned char*>(dpcd_lane2),
753 LTSettings.link.lanes);
754 }
755 */
756
757 if (is_repeater(link, offset)) {
758 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
759 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
760 __func__,
761 offset,
762 lane0_set_address,
763 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
764 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
765 dpcd_lane[0].bits.MAX_SWING_REACHED,
766 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
767
768 } else {
769 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
770 __func__,
771 lane0_set_address,
772 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
773 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
774 dpcd_lane[0].bits.MAX_SWING_REACHED,
775 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
776 }
777 link->cur_lane_setting = link_training_setting->lane_settings[0];
778
779 }
780
781 static bool is_max_vs_reached(
782 const struct link_training_settings *lt_settings)
783 {
784 uint32_t lane;
785 for (lane = 0; lane <
786 (uint32_t)(lt_settings->link_settings.lane_count);
787 lane++) {
788 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
789 == VOLTAGE_SWING_MAX_LEVEL)
790 return true;
791 }
792 return false;
793
794 }
795
796 static bool perform_post_lt_adj_req_sequence(
797 struct dc_link *link,
798 struct link_training_settings *lt_settings)
799 {
800 enum dc_lane_count lane_count =
801 lt_settings->link_settings.lane_count;
802
803 uint32_t adj_req_count;
804 uint32_t adj_req_timer;
805 bool req_drv_setting_changed;
806 uint32_t lane;
807
808 req_drv_setting_changed = false;
809 for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
810 adj_req_count++) {
811
812 req_drv_setting_changed = false;
813
814 for (adj_req_timer = 0;
815 adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
816 adj_req_timer++) {
817
818 struct link_training_settings req_settings;
819 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
820 union lane_align_status_updated
821 dpcd_lane_status_updated;
822
823 get_lane_status_and_drive_settings(
824 link,
825 lt_settings,
826 dpcd_lane_status,
827 &dpcd_lane_status_updated,
828 &req_settings,
829 DPRX);
830
831 if (dpcd_lane_status_updated.bits.
832 POST_LT_ADJ_REQ_IN_PROGRESS == 0)
833 return true;
834
835 if (!is_cr_done(lane_count, dpcd_lane_status))
836 return false;
837
838 if (!is_ch_eq_done(
839 lane_count,
840 dpcd_lane_status,
841 &dpcd_lane_status_updated))
842 return false;
843
844 for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
845
846 if (lt_settings->
847 lane_settings[lane].VOLTAGE_SWING !=
848 req_settings.lane_settings[lane].
849 VOLTAGE_SWING ||
850 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
851 req_settings.lane_settings[lane].PRE_EMPHASIS) {
852
853 req_drv_setting_changed = true;
854 break;
855 }
856 }
857
858 if (req_drv_setting_changed) {
859 update_drive_settings(
860 lt_settings, req_settings);
861
862 dc_link_dp_set_drive_settings(link,
863 lt_settings);
864 break;
865 }
866
867 msleep(1);
868 }
869
870 if (!req_drv_setting_changed) {
871 DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
872 __func__);
873
874 ASSERT(0);
875 return true;
876 }
877 }
878 DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
879 __func__);
880
881 ASSERT(0);
882 return true;
883
884 }
885
886 /* Only used for channel equalization */
887 static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
888 {
889 unsigned int aux_rd_interval_us = 400;
890
891 switch (dpcd_aux_read_interval) {
892 case 0x01:
893 aux_rd_interval_us = 4000;
894 break;
895 case 0x02:
896 aux_rd_interval_us = 8000;
897 break;
898 case 0x03:
899 aux_rd_interval_us = 12000;
900 break;
901 case 0x04:
902 aux_rd_interval_us = 16000;
903 break;
904 default:
905 break;
906 }
907
908 return aux_rd_interval_us;
909 }
910
911 static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
912 union lane_status *dpcd_lane_status)
913 {
914 enum link_training_result result = LINK_TRAINING_SUCCESS;
915
916 if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
917 result = LINK_TRAINING_CR_FAIL_LANE0;
918 else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
919 result = LINK_TRAINING_CR_FAIL_LANE1;
920 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
921 result = LINK_TRAINING_CR_FAIL_LANE23;
922 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
923 result = LINK_TRAINING_CR_FAIL_LANE23;
924 return result;
925 }
926
927 static enum link_training_result perform_channel_equalization_sequence(
928 struct dc_link *link,
929 struct link_training_settings *lt_settings,
930 uint32_t offset)
931 {
932 struct link_training_settings req_settings;
933 enum dc_dp_training_pattern tr_pattern;
934 uint32_t retries_ch_eq;
935 uint32_t wait_time_microsec;
936 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
937 union lane_align_status_updated dpcd_lane_status_updated = { {0} };
938 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
939
940 /* Note: also check that TPS4 is a supported feature*/
941
942 tr_pattern = lt_settings->pattern_for_eq;
943
944 if (is_repeater(link, offset))
945 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
946
947 dp_set_hw_training_pattern(link, tr_pattern, offset);
948
949 for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
950 retries_ch_eq++) {
951
952 dp_set_hw_lane_settings(link, lt_settings, offset);
953
954 /* 2. update DPCD*/
955 if (!retries_ch_eq)
956 /* EPR #361076 - write as a 5-byte burst,
957 * but only for the 1-st iteration
958 */
959
960 dpcd_set_lt_pattern_and_lane_settings(
961 link,
962 lt_settings,
963 tr_pattern, offset);
964 else
965 dpcd_set_lane_settings(link, lt_settings, offset);
966
967 /* 3. wait for receiver to lock-on*/
968 wait_time_microsec = lt_settings->eq_pattern_time;
969
970 if (is_repeater(link, offset))
971 wait_time_microsec =
972 translate_training_aux_read_interval(
973 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
974
975 wait_for_training_aux_rd_interval(
976 link,
977 wait_time_microsec);
978
979 /* 4. Read lane status and requested
980 * drive settings as set by the sink*/
981
982 get_lane_status_and_drive_settings(
983 link,
984 lt_settings,
985 dpcd_lane_status,
986 &dpcd_lane_status_updated,
987 &req_settings,
988 offset);
989
990 /* 5. check CR done*/
991 if (!is_cr_done(lane_count, dpcd_lane_status))
992 return LINK_TRAINING_EQ_FAIL_CR;
993
994 /* 6. check CHEQ done*/
995 if (is_ch_eq_done(lane_count,
996 dpcd_lane_status,
997 &dpcd_lane_status_updated))
998 return LINK_TRAINING_SUCCESS;
999
1000 /* 7. update VS/PE/PC2 in lt_settings*/
1001 update_drive_settings(lt_settings, req_settings);
1002 }
1003
1004 return LINK_TRAINING_EQ_FAIL_EQ;
1005
1006 }
1007 #define TRAINING_AUX_RD_INTERVAL 100 //us
1008
1009 static void start_clock_recovery_pattern_early(struct dc_link *link,
1010 struct link_training_settings *lt_settings,
1011 uint32_t offset)
1012 {
1013 DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1014 __func__);
1015 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1016 dp_set_hw_lane_settings(link, lt_settings, offset);
1017 udelay(400);
1018 }
1019
1020 static enum link_training_result perform_clock_recovery_sequence(
1021 struct dc_link *link,
1022 struct link_training_settings *lt_settings,
1023 uint32_t offset)
1024 {
1025 uint32_t retries_cr;
1026 uint32_t retry_count;
1027 uint32_t wait_time_microsec;
1028 struct link_training_settings req_settings;
1029 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
1030 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1031 union lane_align_status_updated dpcd_lane_status_updated;
1032
1033 retries_cr = 0;
1034 retry_count = 0;
1035
1036 if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
1037 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1038
1039 /* najeeb - The synaptics MST hub can put the LT in
1040 * infinite loop by switching the VS
1041 */
1042 /* between level 0 and level 1 continuously, here
1043 * we try for CR lock for LinkTrainingMaxCRRetry count*/
1044 while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
1045 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
1046
1047 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1048 memset(&dpcd_lane_status_updated, '\0',
1049 sizeof(dpcd_lane_status_updated));
1050
1051 /* 1. call HWSS to set lane settings*/
1052 dp_set_hw_lane_settings(
1053 link,
1054 lt_settings,
1055 offset);
1056
1057 /* 2. update DPCD of the receiver*/
1058 if (!retry_count)
1059 /* EPR #361076 - write as a 5-byte burst,
1060 * but only for the 1-st iteration.*/
1061 dpcd_set_lt_pattern_and_lane_settings(
1062 link,
1063 lt_settings,
1064 lt_settings->pattern_for_cr,
1065 offset);
1066 else
1067 dpcd_set_lane_settings(
1068 link,
1069 lt_settings,
1070 offset);
1071
1072 /* 3. wait receiver to lock-on*/
1073 wait_time_microsec = lt_settings->cr_pattern_time;
1074
1075 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1076 wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1077
1078 wait_for_training_aux_rd_interval(
1079 link,
1080 wait_time_microsec);
1081
1082 /* 4. Read lane status and requested drive
1083 * settings as set by the sink
1084 */
1085 get_lane_status_and_drive_settings(
1086 link,
1087 lt_settings,
1088 dpcd_lane_status,
1089 &dpcd_lane_status_updated,
1090 &req_settings,
1091 offset);
1092
1093 /* 5. check CR done*/
1094 if (is_cr_done(lane_count, dpcd_lane_status))
1095 return LINK_TRAINING_SUCCESS;
1096
1097 /* 6. max VS reached*/
1098 if (is_max_vs_reached(lt_settings))
1099 break;
1100
1101 /* 7. same lane settings*/
1102 /* Note: settings are the same for all lanes,
1103 * so comparing first lane is sufficient*/
1104 if ((lt_settings->lane_settings[0].VOLTAGE_SWING ==
1105 req_settings.lane_settings[0].VOLTAGE_SWING)
1106 && (lt_settings->lane_settings[0].PRE_EMPHASIS ==
1107 req_settings.lane_settings[0].PRE_EMPHASIS))
1108 retries_cr++;
1109 else
1110 retries_cr = 0;
1111
1112 /* 8. update VS/PE/PC2 in lt_settings*/
1113 update_drive_settings(lt_settings, req_settings);
1114
1115 retry_count++;
1116 }
1117
1118 if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1119 ASSERT(0);
1120 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1121 __func__,
1122 LINK_TRAINING_MAX_CR_RETRY);
1123
1124 }
1125
1126 return get_cr_failure(lane_count, dpcd_lane_status);
1127 }
1128
1129 static inline enum link_training_result perform_link_training_int(
1130 struct dc_link *link,
1131 struct link_training_settings *lt_settings,
1132 enum link_training_result status)
1133 {
1134 union lane_count_set lane_count_set = { {0} };
1135
1136 /* 4. mainlink output idle pattern*/
1137 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1138
1139 /*
1140 * 5. post training adjust if required
1141 * If the upstream DPTX and downstream DPRX both support TPS4,
1142 * TPS4 must be used instead of POST_LT_ADJ_REQ.
1143 */
1144 if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1145 lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4)
1146 return status;
1147
1148 if (status == LINK_TRAINING_SUCCESS &&
1149 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1150 status = LINK_TRAINING_LQA_FAIL;
1151
1152 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1153 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1154 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1155
1156 core_link_write_dpcd(
1157 link,
1158 DP_LANE_COUNT_SET,
1159 &lane_count_set.raw,
1160 sizeof(lane_count_set));
1161
1162 return status;
1163 }
1164
1165 static enum link_training_result check_link_loss_status(
1166 struct dc_link *link,
1167 const struct link_training_settings *link_training_setting)
1168 {
1169 enum link_training_result status = LINK_TRAINING_SUCCESS;
1170 union lane_status lane_status;
1171 uint8_t dpcd_buf[6] = {0};
1172 uint32_t lane;
1173
1174 core_link_read_dpcd(
1175 link,
1176 DP_SINK_COUNT,
1177 (uint8_t *)(dpcd_buf),
1178 sizeof(dpcd_buf));
1179
1180 /*parse lane status*/
1181 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1182 /*
1183 * check lanes status
1184 */
1185 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
1186
1187 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1188 !lane_status.bits.CR_DONE_0 ||
1189 !lane_status.bits.SYMBOL_LOCKED_0) {
1190 /* if one of the channel equalization, clock
1191 * recovery or symbol lock is dropped
1192 * consider it as (link has been
1193 * dropped) dp sink status has changed
1194 */
1195 status = LINK_TRAINING_LINK_LOSS;
1196 break;
1197 }
1198 }
1199
1200 return status;
1201 }
1202
1203 static void initialize_training_settings(
1204 struct dc_link *link,
1205 const struct dc_link_settings *link_setting,
1206 const struct dc_link_training_overrides *overrides,
1207 struct link_training_settings *lt_settings)
1208 {
1209 uint32_t lane;
1210
1211 memset(lt_settings, '\0', sizeof(struct link_training_settings));
1212
1213 /* Initialize link settings */
1214 lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1215 lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
1216
1217 if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1218 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1219 else
1220 lt_settings->link_settings.link_rate = link_setting->link_rate;
1221
1222 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1223 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1224 else
1225 lt_settings->link_settings.lane_count = link_setting->lane_count;
1226
1227 /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1228
1229 /* TODO hard coded to SS for now
1230 * lt_settings.link_settings.link_spread =
1231 * dal_display_path_is_ss_supported(
1232 * path_mode->display_path) ?
1233 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1234 * LINK_SPREAD_DISABLED;
1235 */
1236 /* Initialize link spread */
1237 if (link->dp_ss_off)
1238 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
1239 else if (overrides->downspread != NULL)
1240 lt_settings->link_settings.link_spread
1241 = *overrides->downspread
1242 ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1243 : LINK_SPREAD_DISABLED;
1244 else
1245 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1246
1247 /* Initialize lane settings overrides */
1248 if (overrides->voltage_swing != NULL)
1249 lt_settings->voltage_swing = overrides->voltage_swing;
1250
1251 if (overrides->pre_emphasis != NULL)
1252 lt_settings->pre_emphasis = overrides->pre_emphasis;
1253
1254 if (overrides->post_cursor2 != NULL)
1255 lt_settings->post_cursor2 = overrides->post_cursor2;
1256
1257 /* Initialize lane settings (VS/PE/PC2) */
1258 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1259 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1260 lt_settings->voltage_swing != NULL ?
1261 *lt_settings->voltage_swing :
1262 VOLTAGE_SWING_LEVEL0;
1263 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1264 lt_settings->pre_emphasis != NULL ?
1265 *lt_settings->pre_emphasis
1266 : PRE_EMPHASIS_DISABLED;
1267 lt_settings->lane_settings[lane].POST_CURSOR2 =
1268 lt_settings->post_cursor2 != NULL ?
1269 *lt_settings->post_cursor2
1270 : POST_CURSOR2_DISABLED;
1271 }
1272
1273 /* Initialize training timings */
1274 if (overrides->cr_pattern_time != NULL)
1275 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
1276 else
1277 lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);
1278
1279 if (overrides->eq_pattern_time != NULL)
1280 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
1281 else
1282 lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
1283
1284 if (overrides->pattern_for_cr != NULL)
1285 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
1286 else
1287 lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
1288 if (overrides->pattern_for_eq != NULL)
1289 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
1290 else
1291 lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
1292
1293 if (overrides->enhanced_framing != NULL)
1294 lt_settings->enhanced_framing = *overrides->enhanced_framing;
1295 else
1296 lt_settings->enhanced_framing = 1;
1297 }
1298
1299 static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
1300 {
1301 switch (lttpr_repeater_count) {
1302 case 0x80: // 1 lttpr repeater
1303 return 1;
1304 case 0x40: // 2 lttpr repeaters
1305 return 2;
1306 case 0x20: // 3 lttpr repeaters
1307 return 3;
1308 case 0x10: // 4 lttpr repeaters
1309 return 4;
1310 case 0x08: // 5 lttpr repeaters
1311 return 5;
1312 case 0x04: // 6 lttpr repeaters
1313 return 6;
1314 case 0x02: // 7 lttpr repeaters
1315 return 7;
1316 case 0x01: // 8 lttpr repeaters
1317 return 8;
1318 default:
1319 break;
1320 }
1321 return 0; // invalid value
1322 }
1323
1324 static void configure_lttpr_mode_transparent(struct dc_link *link)
1325 {
1326 uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1327
1328 core_link_write_dpcd(link,
1329 DP_PHY_REPEATER_MODE,
1330 (uint8_t *)&repeater_mode,
1331 sizeof(repeater_mode));
1332 }
1333
1334 static void configure_lttpr_mode_non_transparent(struct dc_link *link)
1335 {
1336 /* aux timeout is already set to extended */
1337 /* RESET/SET lttpr mode to enable non transparent mode */
1338 uint8_t repeater_cnt;
1339 uint32_t aux_interval_address;
1340 uint8_t repeater_id;
1341 enum dc_status result = DC_ERROR_UNEXPECTED;
1342 uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1343
1344 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1345 result = core_link_write_dpcd(link,
1346 DP_PHY_REPEATER_MODE,
1347 (uint8_t *)&repeater_mode,
1348 sizeof(repeater_mode));
1349
1350 if (result == DC_OK) {
1351 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1352 }
1353
1354 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1355
1356 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
1357
1358 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
1359 result = core_link_write_dpcd(link,
1360 DP_PHY_REPEATER_MODE,
1361 (uint8_t *)&repeater_mode,
1362 sizeof(repeater_mode));
1363
1364 if (result == DC_OK) {
1365 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1366 }
1367
1368 repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1369 for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1370 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1371 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1372 core_link_read_dpcd(
1373 link,
1374 aux_interval_address,
1375 (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1376 sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1377 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1378 }
1379 }
1380 }
1381
1382 static void repeater_training_done(struct dc_link *link, uint32_t offset)
1383 {
1384 union dpcd_training_pattern dpcd_pattern = { {0} };
1385
1386 const uint32_t dpcd_base_lt_offset =
1387 DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1388 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1389 /* Set training not in progress*/
1390 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1391
1392 core_link_write_dpcd(
1393 link,
1394 dpcd_base_lt_offset,
1395 &dpcd_pattern.raw,
1396 1);
1397
1398 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1399 __func__,
1400 offset,
1401 dpcd_base_lt_offset,
1402 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1403 }
1404
1405 static void print_status_message(
1406 struct dc_link *link,
1407 const struct link_training_settings *lt_settings,
1408 enum link_training_result status)
1409 {
1410 char *link_rate = "Unknown";
1411 char *lt_result = "Unknown";
1412 char *lt_spread = "Disabled";
1413
1414 switch (lt_settings->link_settings.link_rate) {
1415 case LINK_RATE_LOW:
1416 link_rate = "RBR";
1417 break;
1418 case LINK_RATE_RATE_2:
1419 link_rate = "R2";
1420 break;
1421 case LINK_RATE_RATE_3:
1422 link_rate = "R3";
1423 break;
1424 case LINK_RATE_HIGH:
1425 link_rate = "HBR";
1426 break;
1427 case LINK_RATE_RBR2:
1428 link_rate = "RBR2";
1429 break;
1430 case LINK_RATE_RATE_6:
1431 link_rate = "R6";
1432 break;
1433 case LINK_RATE_HIGH2:
1434 link_rate = "HBR2";
1435 break;
1436 case LINK_RATE_HIGH3:
1437 link_rate = "HBR3";
1438 break;
1439 default:
1440 break;
1441 }
1442
1443 switch (status) {
1444 case LINK_TRAINING_SUCCESS:
1445 lt_result = "pass";
1446 break;
1447 case LINK_TRAINING_CR_FAIL_LANE0:
1448 lt_result = "CR failed lane0";
1449 break;
1450 case LINK_TRAINING_CR_FAIL_LANE1:
1451 lt_result = "CR failed lane1";
1452 break;
1453 case LINK_TRAINING_CR_FAIL_LANE23:
1454 lt_result = "CR failed lane23";
1455 break;
1456 case LINK_TRAINING_EQ_FAIL_CR:
1457 lt_result = "CR failed in EQ";
1458 break;
1459 case LINK_TRAINING_EQ_FAIL_EQ:
1460 lt_result = "EQ failed";
1461 break;
1462 case LINK_TRAINING_LQA_FAIL:
1463 lt_result = "LQA failed";
1464 break;
1465 case LINK_TRAINING_LINK_LOSS:
1466 lt_result = "Link loss";
1467 break;
1468 default:
1469 break;
1470 }
1471
1472 switch (lt_settings->link_settings.link_spread) {
1473 case LINK_SPREAD_DISABLED:
1474 lt_spread = "Disabled";
1475 break;
1476 case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1477 lt_spread = "0.5% 30KHz";
1478 break;
1479 case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1480 lt_spread = "0.5% 33KHz";
1481 break;
1482 default:
1483 break;
1484 }
1485
1486 /* Connectivity log: link training */
1487 CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1488 link_rate,
1489 lt_settings->link_settings.lane_count,
1490 lt_result,
1491 lt_settings->lane_settings[0].VOLTAGE_SWING,
1492 lt_settings->lane_settings[0].PRE_EMPHASIS,
1493 lt_spread);
1494 }
1495
1496 void dc_link_dp_set_drive_settings(
1497 struct dc_link *link,
1498 struct link_training_settings *lt_settings)
1499 {
1500 /* program ASIC PHY settings*/
1501 dp_set_hw_lane_settings(link, lt_settings, DPRX);
1502
1503 /* Notify DP sink the PHY settings from source */
1504 dpcd_set_lane_settings(link, lt_settings, DPRX);
1505 }
1506
1507 bool dc_link_dp_perform_link_training_skip_aux(
1508 struct dc_link *link,
1509 const struct dc_link_settings *link_setting)
1510 {
1511 struct link_training_settings lt_settings;
1512
1513 initialize_training_settings(
1514 link,
1515 link_setting,
1516 &link->preferred_training_settings,
1517 &lt_settings);
1518
1519 /* 1. Perform_clock_recovery_sequence. */
1520
1521 /* transmit training pattern for clock recovery */
1522 dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
1523
1524 /* call HWSS to set lane settings*/
1525 dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1526
1527 /* wait receiver to lock-on*/
1528 wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1529
1530 /* 2. Perform_channel_equalization_sequence. */
1531
1532 /* transmit training pattern for channel equalization. */
1533 dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
1534
1535 /* call HWSS to set lane settings*/
1536 dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1537
1538 /* wait receiver to lock-on. */
1539 wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1540
1541 /* 3. Perform_link_training_int. */
1542
1543 /* Mainlink output idle pattern. */
1544 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1545
1546 print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
1547
1548 return true;
1549 }
1550
1551 enum link_training_result dc_link_dp_perform_link_training(
1552 struct dc_link *link,
1553 const struct dc_link_settings *link_setting,
1554 bool skip_video_pattern)
1555 {
1556 enum link_training_result status = LINK_TRAINING_SUCCESS;
1557 struct link_training_settings lt_settings;
1558 union dpcd_training_pattern dpcd_pattern = { { 0 } };
1559
1560 bool fec_enable;
1561 uint8_t repeater_cnt;
1562 uint8_t repeater_id;
1563
1564 initialize_training_settings(
1565 link,
1566 link_setting,
1567 &link->preferred_training_settings,
1568 &lt_settings);
1569
1570 /* Configure lttpr mode */
1571 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1572 configure_lttpr_mode_non_transparent(link);
1573 else if (link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
1574 configure_lttpr_mode_transparent(link);
1575
1576 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1577 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1578
1579 /* 1. set link rate, lane count and spread. */
1580 dpcd_set_link_settings(link, &lt_settings);
1581
1582 if (link->preferred_training_settings.fec_enable != NULL)
1583 fec_enable = *link->preferred_training_settings.fec_enable;
1584 else
1585 fec_enable = true;
1586
1587 dp_set_fec_ready(link, fec_enable);
1588
1589 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1590
1591 /* 2. perform link training (set link training done
1592 * to false is done as well)
1593 */
1594 repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1595
1596 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1597 repeater_id--) {
1598 status = perform_clock_recovery_sequence(link, &lt_settings, repeater_id);
1599
1600 if (status != LINK_TRAINING_SUCCESS)
1601 break;
1602
1603 status = perform_channel_equalization_sequence(link,
1604 &lt_settings,
1605 repeater_id);
1606
1607 if (status != LINK_TRAINING_SUCCESS)
1608 break;
1609
1610 repeater_training_done(link, repeater_id);
1611 }
1612 }
1613
1614 if (status == LINK_TRAINING_SUCCESS) {
1615 status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
1616 if (status == LINK_TRAINING_SUCCESS) {
1617 status = perform_channel_equalization_sequence(link,
1618 &lt_settings,
1619 DPRX);
1620 }
1621 }
1622
1623 /* 3. set training not in progress*/
1624 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1625 dpcd_set_training_pattern(link, dpcd_pattern);
1626 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
1627 status = perform_link_training_int(link,
1628 &lt_settings,
1629 status);
1630 }
1631
1632 /* delay 5ms after Main Link output idle pattern and then check
1633 * DPCD 0202h.
1634 */
1635 if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1636 msleep(5);
1637 status = check_link_loss_status(link, &lt_settings);
1638 }
1639
1640 /* 6. print status message*/
1641 print_status_message(link, &lt_settings, status);
1642
1643 if (status != LINK_TRAINING_SUCCESS)
1644 link->ctx->dc->debug_data.ltFailCount++;
1645
1646 return status;
1647 }
1648
1649 static enum dp_panel_mode try_enable_assr(struct dc_stream_state *stream)
1650 {
1651 struct dc_link *link = stream->link;
1652 enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1653 #ifdef CONFIG_DRM_AMD_DC_HDCP
1654 struct cp_psp *cp_psp = &stream->ctx->cp_psp;
1655 #endif
1656
1657 /* ASSR must be supported on the panel */
1658 if (panel_mode == DP_PANEL_MODE_DEFAULT)
1659 return panel_mode;
1660
1661 /* eDP or internal DP only */
1662 if (link->connector_signal != SIGNAL_TYPE_EDP &&
1663 !(link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1664 link->is_internal_display))
1665 return DP_PANEL_MODE_DEFAULT;
1666
1667 #ifdef CONFIG_DRM_AMD_DC_HDCP
1668 if (cp_psp && cp_psp->funcs.enable_assr) {
1669 if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
1670 /* since eDP implies ASSR on, change panel
1671 * mode to disable ASSR
1672 */
1673 panel_mode = DP_PANEL_MODE_DEFAULT;
1674 }
1675 } else
1676 panel_mode = DP_PANEL_MODE_DEFAULT;
1677
1678 #else
1679 /* turn off ASSR if the implementation is not compiled in */
1680 panel_mode = DP_PANEL_MODE_DEFAULT;
1681 #endif
1682 return panel_mode;
1683 }
1684
1685 bool perform_link_training_with_retries(
1686 const struct dc_link_settings *link_setting,
1687 bool skip_video_pattern,
1688 int attempts,
1689 struct pipe_ctx *pipe_ctx,
1690 enum signal_type signal)
1691 {
1692 uint8_t j;
1693 uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1694 struct dc_stream_state *stream = pipe_ctx->stream;
1695 struct dc_link *link = stream->link;
1696 enum dp_panel_mode panel_mode;
1697
1698 /* We need to do this before the link training to ensure the idle pattern in SST
1699 * mode will be sent right after the link training
1700 */
1701 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
1702 pipe_ctx->stream_res.stream_enc->id, true);
1703
1704 for (j = 0; j < attempts; ++j) {
1705
1706 DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
1707 __func__, (unsigned int)j + 1, attempts);
1708
1709 dp_enable_link_phy(
1710 link,
1711 signal,
1712 pipe_ctx->clock_source->id,
1713 link_setting);
1714
1715 if (stream->sink_patches.dppowerup_delay > 0) {
1716 int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1717
1718 msleep(delay_dp_power_up_in_ms);
1719 }
1720
1721 panel_mode = try_enable_assr(stream);
1722 dp_set_panel_mode(link, panel_mode);
1723 DC_LOG_DETECTION_DP_CAPS("Link: %d ASSR enabled: %d\n",
1724 link->link_index,
1725 panel_mode != DP_PANEL_MODE_DEFAULT);
1726
1727 if (link->aux_access_disabled) {
1728 dc_link_dp_perform_link_training_skip_aux(link, link_setting);
1729 return true;
1730 } else {
1731 enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
1732
1733 status = dc_link_dp_perform_link_training(
1734 link,
1735 link_setting,
1736 skip_video_pattern);
1737 if (status == LINK_TRAINING_SUCCESS)
1738 return true;
1739 }
1740
1741 /* latest link training still fail, skip delay and keep PHY on
1742 */
1743 if (j == (attempts - 1))
1744 break;
1745
1746 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
1747 __func__, (unsigned int)j + 1, attempts);
1748
1749 dp_disable_link_phy(link, signal);
1750
1751 msleep(delay_between_attempts);
1752
1753 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1754 }
1755
1756 return false;
1757 }
1758
1759 static enum clock_source_id get_clock_source_id(struct dc_link *link)
1760 {
1761 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1762 struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1763
1764 if (dp_cs != NULL) {
1765 dp_cs_id = dp_cs->id;
1766 } else {
1767 /*
1768 * dp clock source is not initialized for some reason.
1769 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1770 */
1771 ASSERT(dp_cs);
1772 }
1773
1774 return dp_cs_id;
1775 }
1776
1777 static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1778 {
1779 if (mst_enable == false &&
1780 link->type == dc_connection_mst_branch) {
1781 /* Disable MST on link. Use only local sink. */
1782 dp_disable_link_phy_mst(link, link->connector_signal);
1783
1784 link->type = dc_connection_single;
1785 link->local_sink = link->remote_sinks[0];
1786 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1787 } else if (mst_enable == true &&
1788 link->type == dc_connection_single &&
1789 link->remote_sinks[0] != NULL) {
1790 /* Re-enable MST on link. */
1791 dp_disable_link_phy(link, link->connector_signal);
1792 dp_enable_mst_on_sink(link, true);
1793
1794 link->type = dc_connection_mst_branch;
1795 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1796 }
1797 }
1798
1799 bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1800 {
1801 /* Begin Sync LT. During this time,
1802 * DPCD:600h must not be powered down.
1803 */
1804 link->sync_lt_in_progress = true;
1805
1806 /*Clear any existing preferred settings.*/
1807 memset(&link->preferred_training_settings, 0,
1808 sizeof(struct dc_link_training_overrides));
1809 memset(&link->preferred_link_setting, 0,
1810 sizeof(struct dc_link_settings));
1811
1812 return true;
1813 }
1814
1815 enum link_training_result dc_link_dp_sync_lt_attempt(
1816 struct dc_link *link,
1817 struct dc_link_settings *link_settings,
1818 struct dc_link_training_overrides *lt_overrides)
1819 {
1820 struct link_training_settings lt_settings;
1821 enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1822 enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1823 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1824 bool fec_enable = false;
1825
1826 initialize_training_settings(
1827 link,
1828 link_settings,
1829 lt_overrides,
1830 &lt_settings);
1831
1832 /* Setup MST Mode */
1833 if (lt_overrides->mst_enable)
1834 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1835
1836 /* Disable link */
1837 dp_disable_link_phy(link, link->connector_signal);
1838
1839 /* Enable link */
1840 dp_cs_id = get_clock_source_id(link);
1841 dp_enable_link_phy(link, link->connector_signal,
1842 dp_cs_id, link_settings);
1843
1844 /* Set FEC enable */
1845 fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1846 dp_set_fec_ready(link, fec_enable);
1847
1848 if (lt_overrides->alternate_scrambler_reset) {
1849 if (*lt_overrides->alternate_scrambler_reset)
1850 panel_mode = DP_PANEL_MODE_EDP;
1851 else
1852 panel_mode = DP_PANEL_MODE_DEFAULT;
1853 } else
1854 panel_mode = dp_get_panel_mode(link);
1855
1856 dp_set_panel_mode(link, panel_mode);
1857
1858 /* Attempt to train with given link training settings */
1859 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1860 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1861
1862 /* Set link rate, lane count and spread. */
1863 dpcd_set_link_settings(link, &lt_settings);
1864
1865 /* 2. perform link training (set link training done
1866 * to false is done as well)
1867 */
1868 lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
1869 if (lt_status == LINK_TRAINING_SUCCESS) {
1870 lt_status = perform_channel_equalization_sequence(link,
1871 &lt_settings,
1872 DPRX);
1873 }
1874
1875 /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
1876 /* 4. print status message*/
1877 print_status_message(link, &lt_settings, lt_status);
1878
1879 return lt_status;
1880 }
1881
1882 bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
1883 {
1884 /* If input parameter is set, shut down phy.
1885 * Still shouldn't turn off dp_receiver (DPCD:600h)
1886 */
1887 if (link_down == true) {
1888 dp_disable_link_phy(link, link->connector_signal);
1889 dp_set_fec_ready(link, false);
1890 }
1891
1892 link->sync_lt_in_progress = false;
1893 return true;
1894 }
1895
1896 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
1897 {
1898 if (!max_link_enc_cap) {
1899 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
1900 return false;
1901 }
1902
1903 if (link->link_enc->funcs->get_max_link_cap) {
1904 link->link_enc->funcs->get_max_link_cap(link->link_enc, max_link_enc_cap);
1905 return true;
1906 }
1907
1908 DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
1909 max_link_enc_cap->lane_count = 1;
1910 max_link_enc_cap->link_rate = 6;
1911 return false;
1912 }
1913
1914 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
1915 {
1916 struct dc_link_settings max_link_cap = {0};
1917
1918 /* get max link encoder capability */
1919 link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
1920
1921 /* Lower link settings based on sink's link cap */
1922 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
1923 max_link_cap.lane_count =
1924 link->reported_link_cap.lane_count;
1925 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
1926 max_link_cap.link_rate =
1927 link->reported_link_cap.link_rate;
1928 if (link->reported_link_cap.link_spread <
1929 max_link_cap.link_spread)
1930 max_link_cap.link_spread =
1931 link->reported_link_cap.link_spread;
1932 /*
1933 * account for lttpr repeaters cap
1934 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
1935 */
1936 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1937 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
1938 max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
1939
1940 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
1941 max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
1942
1943 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n",
1944 __func__,
1945 max_link_cap.lane_count,
1946 max_link_cap.link_rate);
1947 }
1948 return max_link_cap;
1949 }
1950
1951 enum dc_status read_hpd_rx_irq_data(
1952 struct dc_link *link,
1953 union hpd_irq_data *irq_data)
1954 {
1955 static enum dc_status retval;
1956
1957 /* The HW reads 16 bytes from 200h on HPD,
1958 * but if we get an AUX_DEFER, the HW cannot retry
1959 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1960 * fail, so we now explicitly read 6 bytes which is
1961 * the req from the above mentioned test cases.
1962 *
1963 * For DP 1.4 we need to read those from 2002h range.
1964 */
1965 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
1966 retval = core_link_read_dpcd(
1967 link,
1968 DP_SINK_COUNT,
1969 irq_data->raw,
1970 sizeof(union hpd_irq_data));
1971 else {
1972 /* Read 14 bytes in a single read and then copy only the required fields.
1973 * This is more efficient than doing it in two separate AUX reads. */
1974
1975 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
1976
1977 retval = core_link_read_dpcd(
1978 link,
1979 DP_SINK_COUNT_ESI,
1980 tmp,
1981 sizeof(tmp));
1982
1983 if (retval != DC_OK)
1984 return retval;
1985
1986 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
1987 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
1988 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
1989 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
1990 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
1991 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
1992 }
1993
1994 return retval;
1995 }
1996
1997 static bool hpd_rx_irq_check_link_loss_status(
1998 struct dc_link *link,
1999 union hpd_irq_data *hpd_irq_dpcd_data)
2000 {
2001 uint8_t irq_reg_rx_power_state = 0;
2002 enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
2003 union lane_status lane_status;
2004 uint32_t lane;
2005 bool sink_status_changed;
2006 bool return_code;
2007
2008 sink_status_changed = false;
2009 return_code = false;
2010
2011 if (link->cur_link_settings.lane_count == 0)
2012 return return_code;
2013
2014 /*1. Check that Link Status changed, before re-training.*/
2015
2016 /*parse lane status*/
2017 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
2018 /* check status of lanes 0,1
2019 * changed DpcdAddress_Lane01Status (0x202)
2020 */
2021 lane_status.raw = get_nibble_at_index(
2022 &hpd_irq_dpcd_data->bytes.lane01_status.raw,
2023 lane);
2024
2025 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
2026 !lane_status.bits.CR_DONE_0 ||
2027 !lane_status.bits.SYMBOL_LOCKED_0) {
2028 /* if one of the channel equalization, clock
2029 * recovery or symbol lock is dropped
2030 * consider it as (link has been
2031 * dropped) dp sink status has changed
2032 */
2033 sink_status_changed = true;
2034 break;
2035 }
2036 }
2037
2038 /* Check interlane align.*/
2039 if (sink_status_changed ||
2040 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
2041
2042 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
2043
2044 return_code = true;
2045
2046 /*2. Check that we can handle interrupt: Not in FS DOS,
2047 * Not in "Display Timeout" state, Link is trained.
2048 */
2049 dpcd_result = core_link_read_dpcd(link,
2050 DP_SET_POWER,
2051 &irq_reg_rx_power_state,
2052 sizeof(irq_reg_rx_power_state));
2053
2054 if (dpcd_result != DC_OK) {
2055 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
2056 __func__);
2057 } else {
2058 if (irq_reg_rx_power_state != DP_SET_POWER_D0)
2059 return_code = false;
2060 }
2061 }
2062
2063 return return_code;
2064 }
2065
2066 bool dp_verify_link_cap(
2067 struct dc_link *link,
2068 struct dc_link_settings *known_limit_link_setting,
2069 int *fail_count)
2070 {
2071 struct dc_link_settings max_link_cap = {0};
2072 struct dc_link_settings cur_link_setting = {0};
2073 struct dc_link_settings *cur = &cur_link_setting;
2074 struct dc_link_settings initial_link_settings = {0};
2075 bool success;
2076 bool skip_link_training;
2077 bool skip_video_pattern;
2078 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
2079 enum link_training_result status;
2080 union hpd_irq_data irq_data;
2081
2082 if (link->dc->debug.skip_detection_link_training) {
2083 link->verified_link_cap = *known_limit_link_setting;
2084 return true;
2085 }
2086
2087 memset(&irq_data, 0, sizeof(irq_data));
2088 success = false;
2089 skip_link_training = false;
2090
2091 max_link_cap = get_max_link_cap(link);
2092
2093 /* Grant extended timeout request */
2094 if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (link->dpcd_caps.lttpr_caps.max_ext_timeout > 0)) {
2095 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2096
2097 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2098 }
2099
2100 /* TODO implement override and monitor patch later */
2101
2102 /* try to train the link from high to low to
2103 * find the physical link capability
2104 */
2105 /* disable PHY done possible by BIOS, will be done by driver itself */
2106 dp_disable_link_phy(link, link->connector_signal);
2107
2108 dp_cs_id = get_clock_source_id(link);
2109
2110 /* link training starts with the maximum common settings
2111 * supported by both sink and ASIC.
2112 */
2113 initial_link_settings = get_common_supported_link_settings(
2114 *known_limit_link_setting,
2115 max_link_cap);
2116 cur_link_setting = initial_link_settings;
2117
2118 /* Temporary Renoir-specific workaround for SWDEV-215184;
2119 * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
2120 * so add extra cycle of enabling and disabling the PHY before first link training.
2121 */
2122 if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
2123 link->dc->debug.usbc_combo_phy_reset_wa) {
2124 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
2125 dp_disable_link_phy(link, link->connector_signal);
2126 }
2127
2128 do {
2129 skip_video_pattern = true;
2130
2131 if (cur->link_rate == LINK_RATE_LOW)
2132 skip_video_pattern = false;
2133
2134 dp_enable_link_phy(
2135 link,
2136 link->connector_signal,
2137 dp_cs_id,
2138 cur);
2139
2140
2141 if (skip_link_training)
2142 success = true;
2143 else {
2144 status = dc_link_dp_perform_link_training(
2145 link,
2146 cur,
2147 skip_video_pattern);
2148 if (status == LINK_TRAINING_SUCCESS)
2149 success = true;
2150 else
2151 (*fail_count)++;
2152 }
2153
2154 if (success) {
2155 link->verified_link_cap = *cur;
2156 udelay(1000);
2157 if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
2158 if (hpd_rx_irq_check_link_loss_status(
2159 link,
2160 &irq_data))
2161 (*fail_count)++;
2162 }
2163 /* always disable the link before trying another
2164 * setting or before returning we'll enable it later
2165 * based on the actual mode we're driving
2166 */
2167 dp_disable_link_phy(link, link->connector_signal);
2168 } while (!success && decide_fallback_link_setting(
2169 initial_link_settings, cur, status));
2170
2171 /* Link Training failed for all Link Settings
2172 * (Lane Count is still unknown)
2173 */
2174 if (!success) {
2175 /* If all LT fails for all settings,
2176 * set verified = failed safe (1 lane low)
2177 */
2178 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2179 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2180
2181 link->verified_link_cap.link_spread =
2182 LINK_SPREAD_DISABLED;
2183 }
2184
2185
2186 return success;
2187 }
2188
2189 bool dp_verify_link_cap_with_retries(
2190 struct dc_link *link,
2191 struct dc_link_settings *known_limit_link_setting,
2192 int attempts)
2193 {
2194 uint8_t i = 0;
2195 bool success = false;
2196
2197 for (i = 0; i < attempts; i++) {
2198 int fail_count = 0;
2199 enum dc_connection_type type = dc_connection_none;
2200
2201 memset(&link->verified_link_cap, 0,
2202 sizeof(struct dc_link_settings));
2203 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2204 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2205 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2206 link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
2207 break;
2208 } else if (dp_verify_link_cap(link,
2209 &link->reported_link_cap,
2210 &fail_count) && fail_count == 0) {
2211 success = true;
2212 break;
2213 }
2214 msleep(10);
2215 }
2216 return success;
2217 }
2218
2219 bool dp_verify_mst_link_cap(
2220 struct dc_link *link)
2221 {
2222 struct dc_link_settings max_link_cap = {0};
2223
2224 max_link_cap = get_max_link_cap(link);
2225 link->verified_link_cap = get_common_supported_link_settings(
2226 link->reported_link_cap,
2227 max_link_cap);
2228
2229 return true;
2230 }
2231
2232 static struct dc_link_settings get_common_supported_link_settings(
2233 struct dc_link_settings link_setting_a,
2234 struct dc_link_settings link_setting_b)
2235 {
2236 struct dc_link_settings link_settings = {0};
2237
2238 link_settings.lane_count =
2239 (link_setting_a.lane_count <=
2240 link_setting_b.lane_count) ?
2241 link_setting_a.lane_count :
2242 link_setting_b.lane_count;
2243 link_settings.link_rate =
2244 (link_setting_a.link_rate <=
2245 link_setting_b.link_rate) ?
2246 link_setting_a.link_rate :
2247 link_setting_b.link_rate;
2248 link_settings.link_spread = LINK_SPREAD_DISABLED;
2249
2250 /* in DP compliance test, DPR-120 may have
2251 * a random value in its MAX_LINK_BW dpcd field.
2252 * We map it to the maximum supported link rate that
2253 * is smaller than MAX_LINK_BW in this case.
2254 */
2255 if (link_settings.link_rate > LINK_RATE_HIGH3) {
2256 link_settings.link_rate = LINK_RATE_HIGH3;
2257 } else if (link_settings.link_rate < LINK_RATE_HIGH3
2258 && link_settings.link_rate > LINK_RATE_HIGH2) {
2259 link_settings.link_rate = LINK_RATE_HIGH2;
2260 } else if (link_settings.link_rate < LINK_RATE_HIGH2
2261 && link_settings.link_rate > LINK_RATE_HIGH) {
2262 link_settings.link_rate = LINK_RATE_HIGH;
2263 } else if (link_settings.link_rate < LINK_RATE_HIGH
2264 && link_settings.link_rate > LINK_RATE_LOW) {
2265 link_settings.link_rate = LINK_RATE_LOW;
2266 } else if (link_settings.link_rate < LINK_RATE_LOW) {
2267 link_settings.link_rate = LINK_RATE_UNKNOWN;
2268 }
2269
2270 return link_settings;
2271 }
2272
2273 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
2274 {
2275 return lane_count <= LANE_COUNT_ONE;
2276 }
2277
2278 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
2279 {
2280 return link_rate <= LINK_RATE_LOW;
2281 }
2282
2283 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
2284 {
2285 switch (lane_count) {
2286 case LANE_COUNT_FOUR:
2287 return LANE_COUNT_TWO;
2288 case LANE_COUNT_TWO:
2289 return LANE_COUNT_ONE;
2290 case LANE_COUNT_ONE:
2291 return LANE_COUNT_UNKNOWN;
2292 default:
2293 return LANE_COUNT_UNKNOWN;
2294 }
2295 }
2296
2297 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
2298 {
2299 switch (link_rate) {
2300 case LINK_RATE_HIGH3:
2301 return LINK_RATE_HIGH2;
2302 case LINK_RATE_HIGH2:
2303 return LINK_RATE_HIGH;
2304 case LINK_RATE_HIGH:
2305 return LINK_RATE_LOW;
2306 case LINK_RATE_LOW:
2307 return LINK_RATE_UNKNOWN;
2308 default:
2309 return LINK_RATE_UNKNOWN;
2310 }
2311 }
2312
2313 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
2314 {
2315 switch (lane_count) {
2316 case LANE_COUNT_ONE:
2317 return LANE_COUNT_TWO;
2318 case LANE_COUNT_TWO:
2319 return LANE_COUNT_FOUR;
2320 default:
2321 return LANE_COUNT_UNKNOWN;
2322 }
2323 }
2324
2325 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
2326 {
2327 switch (link_rate) {
2328 case LINK_RATE_LOW:
2329 return LINK_RATE_HIGH;
2330 case LINK_RATE_HIGH:
2331 return LINK_RATE_HIGH2;
2332 case LINK_RATE_HIGH2:
2333 return LINK_RATE_HIGH3;
2334 default:
2335 return LINK_RATE_UNKNOWN;
2336 }
2337 }
2338
2339 /*
2340 * function: set link rate and lane count fallback based
2341 * on current link setting and last link training result
2342 * return value:
2343 * true - link setting could be set
2344 * false - has reached minimum setting
2345 * and no further fallback could be done
2346 */
2347 static bool decide_fallback_link_setting(
2348 struct dc_link_settings initial_link_settings,
2349 struct dc_link_settings *current_link_setting,
2350 enum link_training_result training_result)
2351 {
2352 if (!current_link_setting)
2353 return false;
2354
2355 switch (training_result) {
2356 case LINK_TRAINING_CR_FAIL_LANE0:
2357 case LINK_TRAINING_CR_FAIL_LANE1:
2358 case LINK_TRAINING_CR_FAIL_LANE23:
2359 case LINK_TRAINING_LQA_FAIL:
2360 {
2361 if (!reached_minimum_link_rate
2362 (current_link_setting->link_rate)) {
2363 current_link_setting->link_rate =
2364 reduce_link_rate(
2365 current_link_setting->link_rate);
2366 } else if (!reached_minimum_lane_count
2367 (current_link_setting->lane_count)) {
2368 current_link_setting->link_rate =
2369 initial_link_settings.link_rate;
2370 if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2371 return false;
2372 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2373 current_link_setting->lane_count =
2374 LANE_COUNT_ONE;
2375 else if (training_result ==
2376 LINK_TRAINING_CR_FAIL_LANE23)
2377 current_link_setting->lane_count =
2378 LANE_COUNT_TWO;
2379 else
2380 current_link_setting->lane_count =
2381 reduce_lane_count(
2382 current_link_setting->lane_count);
2383 } else {
2384 return false;
2385 }
2386 break;
2387 }
2388 case LINK_TRAINING_EQ_FAIL_EQ:
2389 {
2390 if (!reached_minimum_lane_count
2391 (current_link_setting->lane_count)) {
2392 current_link_setting->lane_count =
2393 reduce_lane_count(
2394 current_link_setting->lane_count);
2395 } else if (!reached_minimum_link_rate
2396 (current_link_setting->link_rate)) {
2397 current_link_setting->link_rate =
2398 reduce_link_rate(
2399 current_link_setting->link_rate);
2400 } else {
2401 return false;
2402 }
2403 break;
2404 }
2405 case LINK_TRAINING_EQ_FAIL_CR:
2406 {
2407 if (!reached_minimum_link_rate
2408 (current_link_setting->link_rate)) {
2409 current_link_setting->link_rate =
2410 reduce_link_rate(
2411 current_link_setting->link_rate);
2412 } else {
2413 return false;
2414 }
2415 break;
2416 }
2417 default:
2418 return false;
2419 }
2420 return true;
2421 }
2422
2423 bool dp_validate_mode_timing(
2424 struct dc_link *link,
2425 const struct dc_crtc_timing *timing)
2426 {
2427 uint32_t req_bw;
2428 uint32_t max_bw;
2429
2430 const struct dc_link_settings *link_setting;
2431
2432 /*always DP fail safe mode*/
2433 if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
2434 timing->h_addressable == (uint32_t) 640 &&
2435 timing->v_addressable == (uint32_t) 480)
2436 return true;
2437
2438 link_setting = dc_link_get_link_cap(link);
2439
2440 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2441 /*if (flags.DYNAMIC_VALIDATION == 1 &&
2442 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2443 link_setting = &link->verified_link_cap;
2444 */
2445
2446 req_bw = dc_bandwidth_in_kbps_from_timing(timing);
2447 max_bw = dc_link_bandwidth_kbps(link, link_setting);
2448
2449 if (req_bw <= max_bw) {
2450 /* remember the biggest mode here, during
2451 * initial link training (to get
2452 * verified_link_cap), LS sends event about
2453 * cannot train at reported cap to upper
2454 * layer and upper layer will re-enumerate modes.
2455 * this is not necessary if the lower
2456 * verified_link_cap is enough to drive
2457 * all the modes */
2458
2459 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2460 /* if (flags.DYNAMIC_VALIDATION == 1)
2461 dpsst->max_req_bw_for_verified_linkcap = dal_max(
2462 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2463 return true;
2464 } else
2465 return false;
2466 }
2467
2468 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2469 {
2470 struct dc_link_settings initial_link_setting = {
2471 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
2472 struct dc_link_settings current_link_setting =
2473 initial_link_setting;
2474 uint32_t link_bw;
2475
2476 if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))
2477 return false;
2478
2479 /* search for the minimum link setting that:
2480 * 1. is supported according to the link training result
2481 * 2. could support the b/w requested by the timing
2482 */
2483 while (current_link_setting.link_rate <=
2484 link->verified_link_cap.link_rate) {
2485 link_bw = dc_link_bandwidth_kbps(
2486 link,
2487 &current_link_setting);
2488 if (req_bw <= link_bw) {
2489 *link_setting = current_link_setting;
2490 return true;
2491 }
2492
2493 if (current_link_setting.lane_count <
2494 link->verified_link_cap.lane_count) {
2495 current_link_setting.lane_count =
2496 increase_lane_count(
2497 current_link_setting.lane_count);
2498 } else {
2499 current_link_setting.link_rate =
2500 increase_link_rate(
2501 current_link_setting.link_rate);
2502 current_link_setting.lane_count =
2503 initial_link_setting.lane_count;
2504 }
2505 }
2506
2507 return false;
2508 }
2509
2510 bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2511 {
2512 struct dc_link_settings initial_link_setting;
2513 struct dc_link_settings current_link_setting;
2514 uint32_t link_bw;
2515
2516 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 ||
2517 link->dpcd_caps.edp_supported_link_rates_count == 0) {
2518 *link_setting = link->verified_link_cap;
2519 return true;
2520 }
2521
2522 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2523 initial_link_setting.lane_count = LANE_COUNT_ONE;
2524 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2525 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2526 initial_link_setting.use_link_rate_set = true;
2527 initial_link_setting.link_rate_set = 0;
2528 current_link_setting = initial_link_setting;
2529
2530 /* search for the minimum link setting that:
2531 * 1. is supported according to the link training result
2532 * 2. could support the b/w requested by the timing
2533 */
2534 while (current_link_setting.link_rate <=
2535 link->verified_link_cap.link_rate) {
2536 link_bw = dc_link_bandwidth_kbps(
2537 link,
2538 &current_link_setting);
2539 if (req_bw <= link_bw) {
2540 *link_setting = current_link_setting;
2541 return true;
2542 }
2543
2544 if (current_link_setting.lane_count <
2545 link->verified_link_cap.lane_count) {
2546 current_link_setting.lane_count =
2547 increase_lane_count(
2548 current_link_setting.lane_count);
2549 } else {
2550 if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2551 current_link_setting.link_rate_set++;
2552 current_link_setting.link_rate =
2553 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2554 current_link_setting.lane_count =
2555 initial_link_setting.lane_count;
2556 } else
2557 break;
2558 }
2559 }
2560 return false;
2561 }
2562
2563 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
2564 {
2565 *link_setting = link->verified_link_cap;
2566 return true;
2567 }
2568
2569 void decide_link_settings(struct dc_stream_state *stream,
2570 struct dc_link_settings *link_setting)
2571 {
2572 struct dc_link *link;
2573 uint32_t req_bw;
2574
2575 req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
2576
2577 link = stream->link;
2578
2579 /* if preferred is specified through AMDDP, use it, if it's enough
2580 * to drive the mode
2581 */
2582 if (link->preferred_link_setting.lane_count !=
2583 LANE_COUNT_UNKNOWN &&
2584 link->preferred_link_setting.link_rate !=
2585 LINK_RATE_UNKNOWN) {
2586 *link_setting = link->preferred_link_setting;
2587 return;
2588 }
2589
2590 /* MST doesn't perform link training for now
2591 * TODO: add MST specific link training routine
2592 */
2593 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2594 if (decide_mst_link_settings(link, link_setting))
2595 return;
2596 } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
2597 if (decide_edp_link_settings(link, link_setting, req_bw))
2598 return;
2599 } else if (decide_dp_link_settings(link, link_setting, req_bw))
2600 return;
2601
2602 BREAK_TO_DEBUGGER();
2603 ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
2604
2605 *link_setting = link->verified_link_cap;
2606 }
2607
2608 /*************************Short Pulse IRQ***************************/
2609 static bool allow_hpd_rx_irq(const struct dc_link *link)
2610 {
2611 /*
2612 * Don't handle RX IRQ unless one of following is met:
2613 * 1) The link is established (cur_link_settings != unknown)
2614 * 2) We kicked off MST detection
2615 * 3) We know we're dealing with an active dongle
2616 */
2617
2618 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2619 (link->type == dc_connection_mst_branch) ||
2620 is_dp_active_dongle(link))
2621 return true;
2622
2623 return false;
2624 }
2625
2626 static bool handle_hpd_irq_psr_sink(struct dc_link *link)
2627 {
2628 union dpcd_psr_configuration psr_configuration;
2629
2630 if (!link->psr_settings.psr_feature_enabled)
2631 return false;
2632
2633 dm_helpers_dp_read_dpcd(
2634 link->ctx,
2635 link,
2636 368,/*DpcdAddress_PSR_Enable_Cfg*/
2637 &psr_configuration.raw,
2638 sizeof(psr_configuration.raw));
2639
2640
2641 if (psr_configuration.bits.ENABLE) {
2642 unsigned char dpcdbuf[3] = {0};
2643 union psr_error_status psr_error_status;
2644 union psr_sink_psr_status psr_sink_psr_status;
2645
2646 dm_helpers_dp_read_dpcd(
2647 link->ctx,
2648 link,
2649 0x2006, /*DpcdAddress_PSR_Error_Status*/
2650 (unsigned char *) dpcdbuf,
2651 sizeof(dpcdbuf));
2652
2653 /*DPCD 2006h ERROR STATUS*/
2654 psr_error_status.raw = dpcdbuf[0];
2655 /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/
2656 psr_sink_psr_status.raw = dpcdbuf[2];
2657
2658 if (psr_error_status.bits.LINK_CRC_ERROR ||
2659 psr_error_status.bits.RFB_STORAGE_ERROR ||
2660 psr_error_status.bits.VSC_SDP_ERROR) {
2661 /* Acknowledge and clear error bits */
2662 dm_helpers_dp_write_dpcd(
2663 link->ctx,
2664 link,
2665 8198,/*DpcdAddress_PSR_Error_Status*/
2666 &psr_error_status.raw,
2667 sizeof(psr_error_status.raw));
2668
2669 /* PSR error, disable and re-enable PSR */
2670 dc_link_set_psr_allow_active(link, false, true, false);
2671 dc_link_set_psr_allow_active(link, true, true, false);
2672
2673 return true;
2674 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2675 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2676 /* No error is detect, PSR is active.
2677 * We should return with IRQ_HPD handled without
2678 * checking for loss of sync since PSR would have
2679 * powered down main link.
2680 */
2681 return true;
2682 }
2683 }
2684 return false;
2685 }
2686
2687 static void dp_test_send_link_training(struct dc_link *link)
2688 {
2689 struct dc_link_settings link_settings = {0};
2690
2691 core_link_read_dpcd(
2692 link,
2693 DP_TEST_LANE_COUNT,
2694 (unsigned char *)(&link_settings.lane_count),
2695 1);
2696 core_link_read_dpcd(
2697 link,
2698 DP_TEST_LINK_RATE,
2699 (unsigned char *)(&link_settings.link_rate),
2700 1);
2701
2702 /* Set preferred link settings */
2703 link->verified_link_cap.lane_count = link_settings.lane_count;
2704 link->verified_link_cap.link_rate = link_settings.link_rate;
2705
2706 dp_retrain_link_dp_test(link, &link_settings, false);
2707 }
2708
2709 /* TODO Raven hbr2 compliance eye output is unstable
2710 * (toggling on and off) with debugger break
2711 * This caueses intermittent PHY automation failure
2712 * Need to look into the root cause */
2713 static void dp_test_send_phy_test_pattern(struct dc_link *link)
2714 {
2715 union phy_test_pattern dpcd_test_pattern;
2716 union lane_adjust dpcd_lane_adjustment[2];
2717 unsigned char dpcd_post_cursor_2_adjustment = 0;
2718 unsigned char test_80_bit_pattern[
2719 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2720 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
2721 enum dp_test_pattern test_pattern;
2722 struct dc_link_training_settings link_settings;
2723 union lane_adjust dpcd_lane_adjust;
2724 unsigned int lane;
2725 struct link_training_settings link_training_settings;
2726 int i = 0;
2727
2728 dpcd_test_pattern.raw = 0;
2729 memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2730 memset(&link_settings, 0, sizeof(link_settings));
2731
2732 /* get phy test pattern and pattern parameters from DP receiver */
2733 core_link_read_dpcd(
2734 link,
2735 DP_PHY_TEST_PATTERN,
2736 &dpcd_test_pattern.raw,
2737 sizeof(dpcd_test_pattern));
2738 core_link_read_dpcd(
2739 link,
2740 DP_ADJUST_REQUEST_LANE0_1,
2741 &dpcd_lane_adjustment[0].raw,
2742 sizeof(dpcd_lane_adjustment));
2743
2744 /*get post cursor 2 parameters
2745 * For DP 1.1a or eariler, this DPCD register's value is 0
2746 * For DP 1.2 or later:
2747 * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2748 * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2749 */
2750 core_link_read_dpcd(
2751 link,
2752 DP_ADJUST_REQUEST_POST_CURSOR2,
2753 &dpcd_post_cursor_2_adjustment,
2754 sizeof(dpcd_post_cursor_2_adjustment));
2755
2756 /* translate request */
2757 switch (dpcd_test_pattern.bits.PATTERN) {
2758 case PHY_TEST_PATTERN_D10_2:
2759 test_pattern = DP_TEST_PATTERN_D102;
2760 break;
2761 case PHY_TEST_PATTERN_SYMBOL_ERROR:
2762 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
2763 break;
2764 case PHY_TEST_PATTERN_PRBS7:
2765 test_pattern = DP_TEST_PATTERN_PRBS7;
2766 break;
2767 case PHY_TEST_PATTERN_80BIT_CUSTOM:
2768 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
2769 break;
2770 case PHY_TEST_PATTERN_CP2520_1:
2771 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2772 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2773 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2774 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2775 break;
2776 case PHY_TEST_PATTERN_CP2520_2:
2777 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2778 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2779 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2780 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2781 break;
2782 case PHY_TEST_PATTERN_CP2520_3:
2783 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
2784 break;
2785 default:
2786 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2787 break;
2788 }
2789
2790 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
2791 core_link_read_dpcd(
2792 link,
2793 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2794 test_80_bit_pattern,
2795 sizeof(test_80_bit_pattern));
2796
2797 /* prepare link training settings */
2798 link_settings.link = link->cur_link_settings;
2799
2800 for (lane = 0; lane <
2801 (unsigned int)(link->cur_link_settings.lane_count);
2802 lane++) {
2803 dpcd_lane_adjust.raw =
2804 get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2805 link_settings.lane_settings[lane].VOLTAGE_SWING =
2806 (enum dc_voltage_swing)
2807 (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2808 link_settings.lane_settings[lane].PRE_EMPHASIS =
2809 (enum dc_pre_emphasis)
2810 (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2811 link_settings.lane_settings[lane].POST_CURSOR2 =
2812 (enum dc_post_cursor2)
2813 ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2814 }
2815
2816 for (i = 0; i < 4; i++)
2817 link_training_settings.lane_settings[i] =
2818 link_settings.lane_settings[i];
2819 link_training_settings.link_settings = link_settings.link;
2820 link_training_settings.allow_invalid_msa_timing_param = false;
2821 /*Usage: Measure DP physical lane signal
2822 * by DP SI test equipment automatically.
2823 * PHY test pattern request is generated by equipment via HPD interrupt.
2824 * HPD needs to be active all the time. HPD should be active
2825 * all the time. Do not touch it.
2826 * forward request to DS
2827 */
2828 dc_link_dp_set_test_pattern(
2829 link,
2830 test_pattern,
2831 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
2832 &link_training_settings,
2833 test_80_bit_pattern,
2834 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2835 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
2836 }
2837
2838 static void dp_test_send_link_test_pattern(struct dc_link *link)
2839 {
2840 union link_test_pattern dpcd_test_pattern;
2841 union test_misc dpcd_test_params;
2842 enum dp_test_pattern test_pattern;
2843 enum dp_test_pattern_color_space test_pattern_color_space =
2844 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
2845 enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
2846 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2847 struct pipe_ctx *pipe_ctx = NULL;
2848 int i;
2849
2850 memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2851 memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2852
2853 for (i = 0; i < MAX_PIPES; i++) {
2854 if (pipes[i].stream == NULL)
2855 continue;
2856
2857 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
2858 pipe_ctx = &pipes[i];
2859 break;
2860 }
2861 }
2862
2863 if (pipe_ctx == NULL)
2864 return;
2865
2866 /* get link test pattern and pattern parameters */
2867 core_link_read_dpcd(
2868 link,
2869 DP_TEST_PATTERN,
2870 &dpcd_test_pattern.raw,
2871 sizeof(dpcd_test_pattern));
2872 core_link_read_dpcd(
2873 link,
2874 DP_TEST_MISC0,
2875 &dpcd_test_params.raw,
2876 sizeof(dpcd_test_params));
2877
2878 switch (dpcd_test_pattern.bits.PATTERN) {
2879 case LINK_TEST_PATTERN_COLOR_RAMP:
2880 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
2881 break;
2882 case LINK_TEST_PATTERN_VERTICAL_BARS:
2883 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
2884 break; /* black and white */
2885 case LINK_TEST_PATTERN_COLOR_SQUARES:
2886 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
2887 TEST_DYN_RANGE_VESA ?
2888 DP_TEST_PATTERN_COLOR_SQUARES :
2889 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
2890 break;
2891 default:
2892 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2893 break;
2894 }
2895
2896 if (dpcd_test_params.bits.CLR_FORMAT == 0)
2897 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
2898 else
2899 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
2900 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
2901 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
2902
2903 switch (dpcd_test_params.bits.BPC) {
2904 case 0: // 6 bits
2905 requestColorDepth = COLOR_DEPTH_666;
2906 break;
2907 case 1: // 8 bits
2908 requestColorDepth = COLOR_DEPTH_888;
2909 break;
2910 case 2: // 10 bits
2911 requestColorDepth = COLOR_DEPTH_101010;
2912 break;
2913 case 3: // 12 bits
2914 requestColorDepth = COLOR_DEPTH_121212;
2915 break;
2916 default:
2917 break;
2918 }
2919
2920 if (requestColorDepth != COLOR_DEPTH_UNDEFINED
2921 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) {
2922 DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n",
2923 __func__,
2924 pipe_ctx->stream->timing.display_color_depth,
2925 requestColorDepth);
2926 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
2927 dp_update_dsc_config(pipe_ctx);
2928 }
2929
2930 dc_link_dp_set_test_pattern(
2931 link,
2932 test_pattern,
2933 test_pattern_color_space,
2934 NULL,
2935 NULL,
2936 0);
2937 }
2938
2939 static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
2940 {
2941 union audio_test_mode dpcd_test_mode = {0};
2942 struct audio_test_pattern_type dpcd_pattern_type = {0};
2943 union audio_test_pattern_period dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
2944 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
2945
2946 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2947 struct pipe_ctx *pipe_ctx = &pipes[0];
2948 unsigned int channel_count;
2949 unsigned int channel = 0;
2950 unsigned int modes = 0;
2951 unsigned int sampling_rate_in_hz = 0;
2952
2953 // get audio test mode and test pattern parameters
2954 core_link_read_dpcd(
2955 link,
2956 DP_TEST_AUDIO_MODE,
2957 &dpcd_test_mode.raw,
2958 sizeof(dpcd_test_mode));
2959
2960 core_link_read_dpcd(
2961 link,
2962 DP_TEST_AUDIO_PATTERN_TYPE,
2963 &dpcd_pattern_type.value,
2964 sizeof(dpcd_pattern_type));
2965
2966 channel_count = dpcd_test_mode.bits.channel_count + 1;
2967
2968 // read pattern periods for requested channels when sawTooth pattern is requested
2969 if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
2970 dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
2971
2972 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
2973 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
2974 // read period for each channel
2975 for (channel = 0; channel < channel_count; channel++) {
2976 core_link_read_dpcd(
2977 link,
2978 DP_TEST_AUDIO_PERIOD_CH1 + channel,
2979 &dpcd_pattern_period[channel].raw,
2980 sizeof(dpcd_pattern_period[channel]));
2981 }
2982 }
2983
2984 // translate sampling rate
2985 switch (dpcd_test_mode.bits.sampling_rate) {
2986 case AUDIO_SAMPLING_RATE_32KHZ:
2987 sampling_rate_in_hz = 32000;
2988 break;
2989 case AUDIO_SAMPLING_RATE_44_1KHZ:
2990 sampling_rate_in_hz = 44100;
2991 break;
2992 case AUDIO_SAMPLING_RATE_48KHZ:
2993 sampling_rate_in_hz = 48000;
2994 break;
2995 case AUDIO_SAMPLING_RATE_88_2KHZ:
2996 sampling_rate_in_hz = 88200;
2997 break;
2998 case AUDIO_SAMPLING_RATE_96KHZ:
2999 sampling_rate_in_hz = 96000;
3000 break;
3001 case AUDIO_SAMPLING_RATE_176_4KHZ:
3002 sampling_rate_in_hz = 176400;
3003 break;
3004 case AUDIO_SAMPLING_RATE_192KHZ:
3005 sampling_rate_in_hz = 192000;
3006 break;
3007 default:
3008 sampling_rate_in_hz = 0;
3009 break;
3010 }
3011
3012 link->audio_test_data.flags.test_requested = 1;
3013 link->audio_test_data.flags.disable_video = disable_video;
3014 link->audio_test_data.sampling_rate = sampling_rate_in_hz;
3015 link->audio_test_data.channel_count = channel_count;
3016 link->audio_test_data.pattern_type = test_pattern;
3017
3018 if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
3019 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
3020 link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
3021 }
3022 }
3023 }
3024
3025 static void handle_automated_test(struct dc_link *link)
3026 {
3027 union test_request test_request;
3028 union test_response test_response;
3029
3030 memset(&test_request, 0, sizeof(test_request));
3031 memset(&test_response, 0, sizeof(test_response));
3032
3033 core_link_read_dpcd(
3034 link,
3035 DP_TEST_REQUEST,
3036 &test_request.raw,
3037 sizeof(union test_request));
3038 if (test_request.bits.LINK_TRAINING) {
3039 /* ACK first to let DP RX test box monitor LT sequence */
3040 test_response.bits.ACK = 1;
3041 core_link_write_dpcd(
3042 link,
3043 DP_TEST_RESPONSE,
3044 &test_response.raw,
3045 sizeof(test_response));
3046 dp_test_send_link_training(link);
3047 /* no acknowledge request is needed again */
3048 test_response.bits.ACK = 0;
3049 }
3050 if (test_request.bits.LINK_TEST_PATTRN) {
3051 dp_test_send_link_test_pattern(link);
3052 test_response.bits.ACK = 1;
3053 }
3054
3055 if (test_request.bits.AUDIO_TEST_PATTERN) {
3056 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
3057 test_response.bits.ACK = 1;
3058 }
3059
3060 if (test_request.bits.PHY_TEST_PATTERN) {
3061 dp_test_send_phy_test_pattern(link);
3062 test_response.bits.ACK = 1;
3063 }
3064
3065 /* send request acknowledgment */
3066 if (test_response.bits.ACK)
3067 core_link_write_dpcd(
3068 link,
3069 DP_TEST_RESPONSE,
3070 &test_response.raw,
3071 sizeof(test_response));
3072 }
3073
3074 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
3075 {
3076 union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
3077 union device_service_irq device_service_clear = { { 0 } };
3078 enum dc_status result;
3079 bool status = false;
3080 struct pipe_ctx *pipe_ctx;
3081 int i;
3082
3083 if (out_link_loss)
3084 *out_link_loss = false;
3085 /* For use cases related to down stream connection status change,
3086 * PSR and device auto test, refer to function handle_sst_hpd_irq
3087 * in DAL2.1*/
3088
3089 DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
3090 __func__, link->link_index);
3091
3092
3093 /* All the "handle_hpd_irq_xxx()" methods
3094 * should be called only after
3095 * dal_dpsst_ls_read_hpd_irq_data
3096 * Order of calls is important too
3097 */
3098 result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
3099 if (out_hpd_irq_dpcd_data)
3100 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
3101
3102 if (result != DC_OK) {
3103 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
3104 __func__);
3105 return false;
3106 }
3107
3108 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3109 device_service_clear.bits.AUTOMATED_TEST = 1;
3110 core_link_write_dpcd(
3111 link,
3112 DP_DEVICE_SERVICE_IRQ_VECTOR,
3113 &device_service_clear.raw,
3114 sizeof(device_service_clear.raw));
3115 device_service_clear.raw = 0;
3116 handle_automated_test(link);
3117 return false;
3118 }
3119
3120 if (!allow_hpd_rx_irq(link)) {
3121 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
3122 __func__, link->link_index);
3123 return false;
3124 }
3125
3126 if (handle_hpd_irq_psr_sink(link))
3127 /* PSR-related error was detected and handled */
3128 return true;
3129
3130 /* If PSR-related error handled, Main link may be off,
3131 * so do not handle as a normal sink status change interrupt.
3132 */
3133
3134 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
3135 return true;
3136
3137 /* check if we have MST msg and return since we poll for it */
3138 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
3139 return false;
3140
3141 /* For now we only handle 'Downstream port status' case.
3142 * If we got sink count changed it means
3143 * Downstream port status changed,
3144 * then DM should call DC to do the detection.
3145 * NOTE: Do not handle link loss on eDP since it is internal link*/
3146 if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
3147 hpd_rx_irq_check_link_loss_status(
3148 link,
3149 &hpd_irq_dpcd_data)) {
3150 /* Connectivity log: link loss */
3151 CONN_DATA_LINK_LOSS(link,
3152 hpd_irq_dpcd_data.raw,
3153 sizeof(hpd_irq_dpcd_data),
3154 "Status: ");
3155
3156 for (i = 0; i < MAX_PIPES; i++) {
3157 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3158 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
3159 break;
3160 }
3161
3162 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
3163 return false;
3164
3165
3166 for (i = 0; i < MAX_PIPES; i++) {
3167 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3168 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3169 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3170 core_link_disable_stream(pipe_ctx);
3171 }
3172
3173 for (i = 0; i < MAX_PIPES; i++) {
3174 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3175 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3176 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3177 core_link_enable_stream(link->dc->current_state, pipe_ctx);
3178 }
3179
3180 status = false;
3181 if (out_link_loss)
3182 *out_link_loss = true;
3183 }
3184
3185 if (link->type == dc_connection_active_dongle &&
3186 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
3187 != link->dpcd_sink_count)
3188 status = true;
3189
3190 /* reasons for HPD RX:
3191 * 1. Link Loss - ie Re-train the Link
3192 * 2. MST sideband message
3193 * 3. Automated Test - ie. Internal Commit
3194 * 4. CP (copy protection) - (not interesting for DM???)
3195 * 5. DRR
3196 * 6. Downstream Port status changed
3197 * -ie. Detect - this the only one
3198 * which is interesting for DM because
3199 * it must call dc_link_detect.
3200 */
3201 return status;
3202 }
3203
3204 /*query dpcd for version and mst cap addresses*/
3205 bool is_mst_supported(struct dc_link *link)
3206 {
3207 bool mst = false;
3208 enum dc_status st = DC_OK;
3209 union dpcd_rev rev;
3210 union mstm_cap cap;
3211
3212 if (link->preferred_training_settings.mst_enable &&
3213 *link->preferred_training_settings.mst_enable == false) {
3214 return false;
3215 }
3216
3217 rev.raw = 0;
3218 cap.raw = 0;
3219
3220 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
3221 sizeof(rev));
3222
3223 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
3224
3225 st = core_link_read_dpcd(link, DP_MSTM_CAP,
3226 &cap.raw, sizeof(cap));
3227 if (st == DC_OK && cap.bits.MST_CAP == 1)
3228 mst = true;
3229 }
3230 return mst;
3231
3232 }
3233
3234 bool is_dp_active_dongle(const struct dc_link *link)
3235 {
3236 return link->dpcd_caps.is_branch_dev;
3237 }
3238
3239 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
3240 {
3241 switch (bpc) {
3242 case DOWN_STREAM_MAX_8BPC:
3243 return 8;
3244 case DOWN_STREAM_MAX_10BPC:
3245 return 10;
3246 case DOWN_STREAM_MAX_12BPC:
3247 return 12;
3248 case DOWN_STREAM_MAX_16BPC:
3249 return 16;
3250 default:
3251 break;
3252 }
3253
3254 return -1;
3255 }
3256
3257 static void read_dp_device_vendor_id(struct dc_link *link)
3258 {
3259 struct dp_device_vendor_id dp_id;
3260
3261 /* read IEEE branch device id */
3262 core_link_read_dpcd(
3263 link,
3264 DP_BRANCH_OUI,
3265 (uint8_t *)&dp_id,
3266 sizeof(dp_id));
3267
3268 link->dpcd_caps.branch_dev_id =
3269 (dp_id.ieee_oui[0] << 16) +
3270 (dp_id.ieee_oui[1] << 8) +
3271 dp_id.ieee_oui[2];
3272
3273 memmove(
3274 link->dpcd_caps.branch_dev_name,
3275 dp_id.ieee_device_id,
3276 sizeof(dp_id.ieee_device_id));
3277 }
3278
3279
3280
3281 static void get_active_converter_info(
3282 uint8_t data, struct dc_link *link)
3283 {
3284 union dp_downstream_port_present ds_port = { .byte = data };
3285 memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
3286
3287 /* decode converter info*/
3288 if (!ds_port.fields.PORT_PRESENT) {
3289 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3290 ddc_service_set_dongle_type(link->ddc,
3291 link->dpcd_caps.dongle_type);
3292 link->dpcd_caps.is_branch_dev = false;
3293 return;
3294 }
3295
3296 /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
3297 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3298
3299 switch (ds_port.fields.PORT_TYPE) {
3300 case DOWNSTREAM_VGA:
3301 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3302 break;
3303 case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3304 /* At this point we don't know is it DVI or HDMI or DP++,
3305 * assume DVI.*/
3306 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3307 break;
3308 default:
3309 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3310 break;
3311 }
3312
3313 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
3314 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
3315 union dwnstream_port_caps_byte0 *port_caps =
3316 (union dwnstream_port_caps_byte0 *)det_caps;
3317 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3318 det_caps, sizeof(det_caps)) == DC_OK) {
3319
3320 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3321 /*Handle DP case as DONGLE_NONE*/
3322 case DOWN_STREAM_DETAILED_DP:
3323 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3324 break;
3325 case DOWN_STREAM_DETAILED_VGA:
3326 link->dpcd_caps.dongle_type =
3327 DISPLAY_DONGLE_DP_VGA_CONVERTER;
3328 break;
3329 case DOWN_STREAM_DETAILED_DVI:
3330 link->dpcd_caps.dongle_type =
3331 DISPLAY_DONGLE_DP_DVI_CONVERTER;
3332 break;
3333 case DOWN_STREAM_DETAILED_HDMI:
3334 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3335 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3336 link->dpcd_caps.dongle_type =
3337 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3338
3339 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3340 if (ds_port.fields.DETAILED_CAPS) {
3341
3342 union dwnstream_port_caps_byte3_hdmi
3343 hdmi_caps = {.raw = det_caps[3] };
3344 union dwnstream_port_caps_byte2
3345 hdmi_color_caps = {.raw = det_caps[2] };
3346 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3347 det_caps[1] * 2500;
3348
3349 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3350 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3351 /*YCBCR capability only for HDMI case*/
3352 if (port_caps->bits.DWN_STRM_PORTX_TYPE
3353 == DOWN_STREAM_DETAILED_HDMI) {
3354 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3355 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3356 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3357 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3358 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3359 hdmi_caps.bits.YCrCr422_CONVERSION;
3360 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3361 hdmi_caps.bits.YCrCr420_CONVERSION;
3362 }
3363
3364 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3365 translate_dpcd_max_bpc(
3366 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3367
3368 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3369 link->dpcd_caps.dongle_caps.extendedCapValid = true;
3370 }
3371
3372 break;
3373 }
3374 }
3375 }
3376
3377 ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
3378
3379 {
3380 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3381
3382 core_link_read_dpcd(
3383 link,
3384 DP_BRANCH_REVISION_START,
3385 (uint8_t *)&dp_hw_fw_revision,
3386 sizeof(dp_hw_fw_revision));
3387
3388 link->dpcd_caps.branch_hw_revision =
3389 dp_hw_fw_revision.ieee_hw_rev;
3390
3391 memmove(
3392 link->dpcd_caps.branch_fw_revision,
3393 dp_hw_fw_revision.ieee_fw_rev,
3394 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3395 }
3396 }
3397
3398 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
3399 int length)
3400 {
3401 int retry = 0;
3402
3403 if (!link->dpcd_caps.dpcd_rev.raw) {
3404 do {
3405 dp_receiver_power_ctrl(link, true);
3406 core_link_read_dpcd(link, DP_DPCD_REV,
3407 dpcd_data, length);
3408 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3409 DP_DPCD_REV -
3410 DP_DPCD_REV];
3411 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3412 }
3413
3414 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3415 switch (link->dpcd_caps.branch_dev_id) {
3416 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
3417 * all internal circuits including AUX communication preventing
3418 * reading DPCD table and EDID (spec violation).
3419 * Encoder will skip DP RX power down on disable_output to
3420 * keep receiver powered all the time.*/
3421 case DP_BRANCH_DEVICE_ID_0010FA:
3422 case DP_BRANCH_DEVICE_ID_0080E1:
3423 case DP_BRANCH_DEVICE_ID_00E04C:
3424 link->wa_flags.dp_keep_receiver_powered = true;
3425 break;
3426
3427 /* TODO: May need work around for other dongles. */
3428 default:
3429 link->wa_flags.dp_keep_receiver_powered = false;
3430 break;
3431 }
3432 } else
3433 link->wa_flags.dp_keep_receiver_powered = false;
3434 }
3435
3436 /* Read additional sink caps defined in source specific DPCD area
3437 * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3438 */
3439 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3440 {
3441 uint8_t dpcd_data;
3442
3443 if (!link)
3444 return false;
3445
3446 if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3447 return false;
3448
3449 link->dpcd_sink_ext_caps.raw = dpcd_data;
3450 return true;
3451 }
3452
3453 static bool retrieve_link_cap(struct dc_link *link)
3454 {
3455 /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3456 * which means size 16 will be good for both of those DPCD register block reads
3457 */
3458 uint8_t dpcd_data[16];
3459 uint8_t lttpr_dpcd_data[6];
3460
3461 /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3462 */
3463 uint8_t dpcd_dprx_data = '\0';
3464 uint8_t dpcd_power_state = '\0';
3465
3466 struct dp_device_vendor_id sink_id;
3467 union down_stream_port_count down_strm_port_count;
3468 union edp_configuration_cap edp_config_cap;
3469 union dp_downstream_port_present ds_port = { 0 };
3470 enum dc_status status = DC_ERROR_UNEXPECTED;
3471 uint32_t read_dpcd_retry_cnt = 3;
3472 int i;
3473 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3474 bool is_lttpr_present = false;
3475 const uint32_t post_oui_delay = 30; // 30ms
3476 bool vbios_lttpr_enable = false;
3477 bool vbios_lttpr_interop = false;
3478 struct dc_bios *bios = link->dc->ctx->dc_bios;
3479
3480 memset(dpcd_data, '\0', sizeof(dpcd_data));
3481 memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
3482 memset(&down_strm_port_count,
3483 '\0', sizeof(union down_stream_port_count));
3484 memset(&edp_config_cap, '\0',
3485 sizeof(union edp_configuration_cap));
3486
3487 /* if extended timeout is supported in hardware,
3488 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
3489 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
3490 */
3491 dc_link_aux_try_to_configure_timeout(link->ddc,
3492 LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
3493
3494 status = core_link_read_dpcd(link, DP_SET_POWER,
3495 &dpcd_power_state, sizeof(dpcd_power_state));
3496
3497 /* Delay 1 ms if AUX CH is in power down state. Based on spec
3498 * section 2.3.1.2, if AUX CH may be powered down due to
3499 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3500 * signal and may need up to 1 ms before being able to reply.
3501 */
3502 if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3503 udelay(1000);
3504
3505 dpcd_set_source_specific_data(link);
3506 /* Sink may need to configure internals based on vendor, so allow some
3507 * time before proceeding with possibly vendor specific transactions
3508 */
3509 msleep(post_oui_delay);
3510
3511 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3512 status = core_link_read_dpcd(
3513 link,
3514 DP_DPCD_REV,
3515 dpcd_data,
3516 sizeof(dpcd_data));
3517 if (status == DC_OK)
3518 break;
3519 }
3520
3521 if (status != DC_OK) {
3522 dm_error("%s: Read dpcd data failed.\n", __func__);
3523 return false;
3524 }
3525
3526 /* Query BIOS to determine if LTTPR functionality is forced on by system */
3527 if (bios->funcs->get_lttpr_caps) {
3528 enum bp_result bp_query_result;
3529 uint8_t is_vbios_lttpr_enable = 0;
3530
3531 bp_query_result = bios->funcs->get_lttpr_caps(bios, &is_vbios_lttpr_enable);
3532 vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
3533 }
3534
3535 if (bios->funcs->get_lttpr_interop) {
3536 enum bp_result bp_query_result;
3537 uint8_t is_vbios_interop_enabled = 0;
3538
3539 bp_query_result = bios->funcs->get_lttpr_interop(bios, &is_vbios_interop_enabled);
3540 vbios_lttpr_interop = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
3541 }
3542
3543 /*
3544 * Logic to determine LTTPR mode
3545 */
3546 link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3547 if (vbios_lttpr_enable && vbios_lttpr_interop)
3548 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3549 else if (!vbios_lttpr_enable && vbios_lttpr_interop) {
3550 if (link->dc->config.allow_lttpr_non_transparent_mode)
3551 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3552 else
3553 link->lttpr_mode = LTTPR_MODE_TRANSPARENT;
3554 } else if (!vbios_lttpr_enable && !vbios_lttpr_interop) {
3555 if (!link->dc->config.allow_lttpr_non_transparent_mode
3556 || !link->dc->caps.extended_aux_timeout_support)
3557 link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3558 else
3559 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3560 }
3561
3562 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
3563 /* By reading LTTPR capability, RX assumes that we will enable
3564 * LTTPR extended aux timeout if LTTPR is present.
3565 */
3566 status = core_link_read_dpcd(
3567 link,
3568 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3569 lttpr_dpcd_data,
3570 sizeof(lttpr_dpcd_data));
3571
3572 link->dpcd_caps.lttpr_caps.revision.raw =
3573 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3574 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3575
3576 link->dpcd_caps.lttpr_caps.max_link_rate =
3577 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3578 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3579
3580 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3581 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3582 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3583
3584 link->dpcd_caps.lttpr_caps.max_lane_count =
3585 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3586 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3587
3588 link->dpcd_caps.lttpr_caps.mode =
3589 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3590 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3591
3592 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3593 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3594 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3595
3596 is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
3597 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3598 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3599 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
3600 if (is_lttpr_present)
3601 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
3602 else
3603 link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3604 }
3605
3606 if (!is_lttpr_present)
3607 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3608
3609
3610 {
3611 union training_aux_rd_interval aux_rd_interval;
3612
3613 aux_rd_interval.raw =
3614 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
3615
3616 link->dpcd_caps.ext_receiver_cap_field_present =
3617 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3618
3619 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
3620 uint8_t ext_cap_data[16];
3621
3622 memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3623 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3624 status = core_link_read_dpcd(
3625 link,
3626 DP_DP13_DPCD_REV,
3627 ext_cap_data,
3628 sizeof(ext_cap_data));
3629 if (status == DC_OK) {
3630 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3631 break;
3632 }
3633 }
3634 if (status != DC_OK)
3635 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
3636 }
3637 }
3638
3639 link->dpcd_caps.dpcd_rev.raw =
3640 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3641
3642 if (link->dpcd_caps.ext_receiver_cap_field_present) {
3643 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3644 status = core_link_read_dpcd(
3645 link,
3646 DP_DPRX_FEATURE_ENUMERATION_LIST,
3647 &dpcd_dprx_data,
3648 sizeof(dpcd_dprx_data));
3649 if (status == DC_OK)
3650 break;
3651 }
3652
3653 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3654
3655 if (status != DC_OK)
3656 dm_error("%s: Read DPRX caps data failed.\n", __func__);
3657 }
3658
3659 else {
3660 link->dpcd_caps.dprx_feature.raw = 0;
3661 }
3662
3663
3664 /* Error condition checking...
3665 * It is impossible for Sink to report Max Lane Count = 0.
3666 * It is possible for Sink to report Max Link Rate = 0, if it is
3667 * an eDP device that is reporting specialized link rates in the
3668 * SUPPORTED_LINK_RATE table.
3669 */
3670 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3671 return false;
3672
3673 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3674 DP_DPCD_REV];
3675
3676 read_dp_device_vendor_id(link);
3677
3678 get_active_converter_info(ds_port.byte, link);
3679
3680 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3681
3682 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3683 DP_DPCD_REV];
3684
3685 link->dpcd_caps.allow_invalid_MSA_timing_param =
3686 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3687
3688 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3689 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3690
3691 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3692 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3693
3694 link->reported_link_cap.lane_count =
3695 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3696 link->reported_link_cap.link_rate = dpcd_data[
3697 DP_MAX_LINK_RATE - DP_DPCD_REV];
3698 link->reported_link_cap.link_spread =
3699 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3700 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3701
3702 edp_config_cap.raw = dpcd_data[
3703 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3704 link->dpcd_caps.panel_mode_edp =
3705 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3706 link->dpcd_caps.dpcd_display_control_capable =
3707 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3708
3709 link->test_pattern_enabled = false;
3710 link->compliance_test_state.raw = 0;
3711
3712 /* read sink count */
3713 core_link_read_dpcd(link,
3714 DP_SINK_COUNT,
3715 &link->dpcd_caps.sink_count.raw,
3716 sizeof(link->dpcd_caps.sink_count.raw));
3717
3718 /* read sink ieee oui */
3719 core_link_read_dpcd(link,
3720 DP_SINK_OUI,
3721 (uint8_t *)(&sink_id),
3722 sizeof(sink_id));
3723
3724 link->dpcd_caps.sink_dev_id =
3725 (sink_id.ieee_oui[0] << 16) +
3726 (sink_id.ieee_oui[1] << 8) +
3727 (sink_id.ieee_oui[2]);
3728
3729 memmove(
3730 link->dpcd_caps.sink_dev_id_str,
3731 sink_id.ieee_device_id,
3732 sizeof(sink_id.ieee_device_id));
3733
3734 /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3735 {
3736 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3737
3738 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3739 !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3740 sizeof(str_mbp_2017))) {
3741 link->reported_link_cap.link_rate = 0x0c;
3742 }
3743 }
3744
3745 core_link_read_dpcd(
3746 link,
3747 DP_SINK_HW_REVISION_START,
3748 (uint8_t *)&dp_hw_fw_revision,
3749 sizeof(dp_hw_fw_revision));
3750
3751 link->dpcd_caps.sink_hw_revision =
3752 dp_hw_fw_revision.ieee_hw_rev;
3753
3754 memmove(
3755 link->dpcd_caps.sink_fw_revision,
3756 dp_hw_fw_revision.ieee_fw_rev,
3757 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3758
3759 memset(&link->dpcd_caps.dsc_caps, '\0',
3760 sizeof(link->dpcd_caps.dsc_caps));
3761 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3762 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3763 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
3764 status = core_link_read_dpcd(
3765 link,
3766 DP_FEC_CAPABILITY,
3767 &link->dpcd_caps.fec_cap.raw,
3768 sizeof(link->dpcd_caps.fec_cap.raw));
3769 status = core_link_read_dpcd(
3770 link,
3771 DP_DSC_SUPPORT,
3772 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3773 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3774 status = core_link_read_dpcd(
3775 link,
3776 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
3777 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
3778 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
3779 }
3780
3781 if (!dpcd_read_sink_ext_caps(link))
3782 link->dpcd_sink_ext_caps.raw = 0;
3783
3784 /* Connectivity log: detection */
3785 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
3786
3787 return true;
3788 }
3789
3790 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3791 {
3792 uint8_t dpcd_data[16];
3793 uint32_t read_dpcd_retry_cnt = 3;
3794 enum dc_status status = DC_ERROR_UNEXPECTED;
3795 union dp_downstream_port_present ds_port = { 0 };
3796 union down_stream_port_count down_strm_port_count;
3797 union edp_configuration_cap edp_config_cap;
3798
3799 int i;
3800
3801 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3802 status = core_link_read_dpcd(
3803 link,
3804 DP_DPCD_REV,
3805 dpcd_data,
3806 sizeof(dpcd_data));
3807 if (status == DC_OK)
3808 break;
3809 }
3810
3811 link->dpcd_caps.dpcd_rev.raw =
3812 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3813
3814 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3815 return false;
3816
3817 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3818 DP_DPCD_REV];
3819
3820 get_active_converter_info(ds_port.byte, link);
3821
3822 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3823 DP_DPCD_REV];
3824
3825 link->dpcd_caps.allow_invalid_MSA_timing_param =
3826 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3827
3828 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3829 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3830
3831 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3832 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3833
3834 link->reported_link_cap.lane_count =
3835 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3836 link->reported_link_cap.link_rate = dpcd_data[
3837 DP_MAX_LINK_RATE - DP_DPCD_REV];
3838 link->reported_link_cap.link_spread =
3839 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3840 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3841
3842 edp_config_cap.raw = dpcd_data[
3843 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3844 link->dpcd_caps.panel_mode_edp =
3845 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3846 link->dpcd_caps.dpcd_display_control_capable =
3847 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3848
3849 return true;
3850 }
3851
3852 bool detect_dp_sink_caps(struct dc_link *link)
3853 {
3854 return retrieve_link_cap(link);
3855
3856 /* dc init_hw has power encoder using default
3857 * signal for connector. For native DP, no
3858 * need to power up encoder again. If not native
3859 * DP, hw_init may need check signal or power up
3860 * encoder here.
3861 */
3862 /* TODO save sink caps in link->sink */
3863 }
3864
3865 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
3866 {
3867 enum dc_link_rate link_rate;
3868 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
3869 switch (link_rate_in_khz) {
3870 case 1620000:
3871 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane
3872 break;
3873 case 2160000:
3874 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane
3875 break;
3876 case 2430000:
3877 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane
3878 break;
3879 case 2700000:
3880 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane
3881 break;
3882 case 3240000:
3883 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2) - 3.24 Gbps/Lane
3884 break;
3885 case 4320000:
3886 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane
3887 break;
3888 case 5400000:
3889 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2) - 5.40 Gbps/Lane
3890 break;
3891 case 8100000:
3892 link_rate = LINK_RATE_HIGH3; // Rate_8 (HBR3) - 8.10 Gbps/Lane
3893 break;
3894 default:
3895 link_rate = LINK_RATE_UNKNOWN;
3896 break;
3897 }
3898 return link_rate;
3899 }
3900
3901 void detect_edp_sink_caps(struct dc_link *link)
3902 {
3903 uint8_t supported_link_rates[16];
3904 uint32_t entry;
3905 uint32_t link_rate_in_khz;
3906 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
3907 uint8_t backlight_adj_cap;
3908
3909 retrieve_link_cap(link);
3910 link->dpcd_caps.edp_supported_link_rates_count = 0;
3911 memset(supported_link_rates, 0, sizeof(supported_link_rates));
3912
3913 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
3914 (link->dc->debug.optimize_edp_link_rate ||
3915 link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
3916 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
3917 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
3918 supported_link_rates, sizeof(supported_link_rates));
3919
3920 for (entry = 0; entry < 16; entry += 2) {
3921 // DPCD register reports per-lane link rate = 16-bit link rate capability
3922 // value X 200 kHz. Need multiplier to find link rate in kHz.
3923 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
3924 supported_link_rates[entry]) * 200;
3925
3926 if (link_rate_in_khz != 0) {
3927 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
3928 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
3929 link->dpcd_caps.edp_supported_link_rates_count++;
3930
3931 if (link->reported_link_cap.link_rate < link_rate)
3932 link->reported_link_cap.link_rate = link_rate;
3933 }
3934 }
3935 }
3936 link->verified_link_cap = link->reported_link_cap;
3937
3938 core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
3939 &backlight_adj_cap, sizeof(backlight_adj_cap));
3940
3941 link->dpcd_caps.dynamic_backlight_capable_edp =
3942 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
3943
3944 dc_link_set_default_brightness_aux(link);
3945 }
3946
3947 void dc_link_dp_enable_hpd(const struct dc_link *link)
3948 {
3949 struct link_encoder *encoder = link->link_enc;
3950
3951 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
3952 encoder->funcs->enable_hpd(encoder);
3953 }
3954
3955 void dc_link_dp_disable_hpd(const struct dc_link *link)
3956 {
3957 struct link_encoder *encoder = link->link_enc;
3958
3959 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
3960 encoder->funcs->disable_hpd(encoder);
3961 }
3962
3963 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
3964 {
3965 if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
3966 test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
3967 test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
3968 return true;
3969 else
3970 return false;
3971 }
3972
3973 static void set_crtc_test_pattern(struct dc_link *link,
3974 struct pipe_ctx *pipe_ctx,
3975 enum dp_test_pattern test_pattern,
3976 enum dp_test_pattern_color_space test_pattern_color_space)
3977 {
3978 enum controller_dp_test_pattern controller_test_pattern;
3979 enum dc_color_depth color_depth = pipe_ctx->
3980 stream->timing.display_color_depth;
3981 struct bit_depth_reduction_params params;
3982 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
3983 int width = pipe_ctx->stream->timing.h_addressable +
3984 pipe_ctx->stream->timing.h_border_left +
3985 pipe_ctx->stream->timing.h_border_right;
3986 int height = pipe_ctx->stream->timing.v_addressable +
3987 pipe_ctx->stream->timing.v_border_bottom +
3988 pipe_ctx->stream->timing.v_border_top;
3989
3990 memset(&params, 0, sizeof(params));
3991
3992 switch (test_pattern) {
3993 case DP_TEST_PATTERN_COLOR_SQUARES:
3994 controller_test_pattern =
3995 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
3996 break;
3997 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
3998 controller_test_pattern =
3999 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
4000 break;
4001 case DP_TEST_PATTERN_VERTICAL_BARS:
4002 controller_test_pattern =
4003 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
4004 break;
4005 case DP_TEST_PATTERN_HORIZONTAL_BARS:
4006 controller_test_pattern =
4007 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
4008 break;
4009 case DP_TEST_PATTERN_COLOR_RAMP:
4010 controller_test_pattern =
4011 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
4012 break;
4013 default:
4014 controller_test_pattern =
4015 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
4016 break;
4017 }
4018
4019 switch (test_pattern) {
4020 case DP_TEST_PATTERN_COLOR_SQUARES:
4021 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4022 case DP_TEST_PATTERN_VERTICAL_BARS:
4023 case DP_TEST_PATTERN_HORIZONTAL_BARS:
4024 case DP_TEST_PATTERN_COLOR_RAMP:
4025 {
4026 /* disable bit depth reduction */
4027 pipe_ctx->stream->bit_depth_params = params;
4028 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4029 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4030 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4031 controller_test_pattern, color_depth);
4032 else if (link->dc->hwss.set_disp_pattern_generator) {
4033 struct pipe_ctx *odm_pipe;
4034 enum controller_dp_color_space controller_color_space;
4035 int opp_cnt = 1;
4036 int offset = 0;
4037 int dpg_width = width;
4038
4039 switch (test_pattern_color_space) {
4040 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4041 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
4042 break;
4043 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4044 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
4045 break;
4046 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4047 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
4048 break;
4049 case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
4050 default:
4051 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
4052 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
4053 ASSERT(0);
4054 break;
4055 }
4056
4057 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4058 opp_cnt++;
4059 dpg_width = width / opp_cnt;
4060 offset = dpg_width;
4061
4062 link->dc->hwss.set_disp_pattern_generator(link->dc,
4063 pipe_ctx,
4064 controller_test_pattern,
4065 controller_color_space,
4066 color_depth,
4067 NULL,
4068 dpg_width,
4069 height,
4070 0);
4071
4072 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4073 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4074
4075 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4076 link->dc->hwss.set_disp_pattern_generator(link->dc,
4077 odm_pipe,
4078 controller_test_pattern,
4079 controller_color_space,
4080 color_depth,
4081 NULL,
4082 dpg_width,
4083 height,
4084 offset);
4085 offset += offset;
4086 }
4087 }
4088 }
4089 break;
4090 case DP_TEST_PATTERN_VIDEO_MODE:
4091 {
4092 /* restore bitdepth reduction */
4093 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
4094 pipe_ctx->stream->bit_depth_params = params;
4095 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4096 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4097 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4098 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4099 color_depth);
4100 else if (link->dc->hwss.set_disp_pattern_generator) {
4101 struct pipe_ctx *odm_pipe;
4102 int opp_cnt = 1;
4103 int dpg_width = width;
4104
4105 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4106 opp_cnt++;
4107
4108 dpg_width = width / opp_cnt;
4109 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4110 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4111
4112 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4113 link->dc->hwss.set_disp_pattern_generator(link->dc,
4114 odm_pipe,
4115 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4116 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4117 color_depth,
4118 NULL,
4119 dpg_width,
4120 height,
4121 0);
4122 }
4123 link->dc->hwss.set_disp_pattern_generator(link->dc,
4124 pipe_ctx,
4125 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4126 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4127 color_depth,
4128 NULL,
4129 dpg_width,
4130 height,
4131 0);
4132 }
4133 }
4134 break;
4135
4136 default:
4137 break;
4138 }
4139 }
4140
4141 bool dc_link_dp_set_test_pattern(
4142 struct dc_link *link,
4143 enum dp_test_pattern test_pattern,
4144 enum dp_test_pattern_color_space test_pattern_color_space,
4145 const struct link_training_settings *p_link_settings,
4146 const unsigned char *p_custom_pattern,
4147 unsigned int cust_pattern_size)
4148 {
4149 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
4150 struct pipe_ctx *pipe_ctx = NULL;
4151 unsigned int lane;
4152 unsigned int i;
4153 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
4154 union dpcd_training_pattern training_pattern;
4155 enum dpcd_phy_test_patterns pattern;
4156
4157 memset(&training_pattern, 0, sizeof(training_pattern));
4158
4159 for (i = 0; i < MAX_PIPES; i++) {
4160 if (pipes[i].stream == NULL)
4161 continue;
4162
4163 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
4164 pipe_ctx = &pipes[i];
4165 break;
4166 }
4167 }
4168
4169 if (pipe_ctx == NULL)
4170 return false;
4171
4172 /* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
4173 if (link->test_pattern_enabled && test_pattern ==
4174 DP_TEST_PATTERN_VIDEO_MODE) {
4175 /* Set CRTC Test Pattern */
4176 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4177 dp_set_hw_test_pattern(link, test_pattern,
4178 (uint8_t *)p_custom_pattern,
4179 (uint32_t)cust_pattern_size);
4180
4181 /* Unblank Stream */
4182 link->dc->hwss.unblank_stream(
4183 pipe_ctx,
4184 &link->verified_link_cap);
4185 /* TODO:m_pHwss->MuteAudioEndpoint
4186 * (pPathMode->pDisplayPath, false);
4187 */
4188
4189 /* Reset Test Pattern state */
4190 link->test_pattern_enabled = false;
4191
4192 return true;
4193 }
4194
4195 /* Check for PHY Test Patterns */
4196 if (is_dp_phy_pattern(test_pattern)) {
4197 /* Set DPCD Lane Settings before running test pattern */
4198 if (p_link_settings != NULL) {
4199 dp_set_hw_lane_settings(link, p_link_settings, DPRX);
4200 dpcd_set_lane_settings(link, p_link_settings, DPRX);
4201 }
4202
4203 /* Blank stream if running test pattern */
4204 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4205 /*TODO:
4206 * m_pHwss->
4207 * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
4208 */
4209 /* Blank stream */
4210 pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4211 }
4212
4213 dp_set_hw_test_pattern(link, test_pattern,
4214 (uint8_t *)p_custom_pattern,
4215 (uint32_t)cust_pattern_size);
4216
4217 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4218 /* Set Test Pattern state */
4219 link->test_pattern_enabled = true;
4220 if (p_link_settings != NULL)
4221 dpcd_set_link_settings(link,
4222 p_link_settings);
4223 }
4224
4225 switch (test_pattern) {
4226 case DP_TEST_PATTERN_VIDEO_MODE:
4227 pattern = PHY_TEST_PATTERN_NONE;
4228 break;
4229 case DP_TEST_PATTERN_D102:
4230 pattern = PHY_TEST_PATTERN_D10_2;
4231 break;
4232 case DP_TEST_PATTERN_SYMBOL_ERROR:
4233 pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
4234 break;
4235 case DP_TEST_PATTERN_PRBS7:
4236 pattern = PHY_TEST_PATTERN_PRBS7;
4237 break;
4238 case DP_TEST_PATTERN_80BIT_CUSTOM:
4239 pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
4240 break;
4241 case DP_TEST_PATTERN_CP2520_1:
4242 pattern = PHY_TEST_PATTERN_CP2520_1;
4243 break;
4244 case DP_TEST_PATTERN_CP2520_2:
4245 pattern = PHY_TEST_PATTERN_CP2520_2;
4246 break;
4247 case DP_TEST_PATTERN_CP2520_3:
4248 pattern = PHY_TEST_PATTERN_CP2520_3;
4249 break;
4250 default:
4251 return false;
4252 }
4253
4254 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
4255 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
4256 return false;
4257
4258 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4259 /* tell receiver that we are sending qualification
4260 * pattern DP 1.2 or later - DP receiver's link quality
4261 * pattern is set using DPCD LINK_QUAL_LANEx_SET
4262 * register (0x10B~0x10E)\
4263 */
4264 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
4265 link_qual_pattern[lane] =
4266 (unsigned char)(pattern);
4267
4268 core_link_write_dpcd(link,
4269 DP_LINK_QUAL_LANE0_SET,
4270 link_qual_pattern,
4271 sizeof(link_qual_pattern));
4272 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
4273 link->dpcd_caps.dpcd_rev.raw == 0) {
4274 /* tell receiver that we are sending qualification
4275 * pattern DP 1.1a or earlier - DP receiver's link
4276 * quality pattern is set using
4277 * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
4278 * register (0x102). We will use v_1.3 when we are
4279 * setting test pattern for DP 1.1.
4280 */
4281 core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
4282 &training_pattern.raw,
4283 sizeof(training_pattern));
4284 training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
4285 core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
4286 &training_pattern.raw,
4287 sizeof(training_pattern));
4288 }
4289 } else {
4290 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4291
4292 switch (test_pattern_color_space) {
4293 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4294 color_space = COLOR_SPACE_SRGB;
4295 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4296 color_space = COLOR_SPACE_SRGB_LIMITED;
4297 break;
4298
4299 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4300 color_space = COLOR_SPACE_YCBCR601;
4301 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4302 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4303 break;
4304 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4305 color_space = COLOR_SPACE_YCBCR709;
4306 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4307 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4308 break;
4309 default:
4310 break;
4311 }
4312
4313 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
4314 if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4315 union dmub_hw_lock_flags hw_locks = { 0 };
4316 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4317
4318 hw_locks.bits.lock_dig = 1;
4319 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4320
4321 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4322 true,
4323 &hw_locks,
4324 &inst_flags);
4325 } else
4326 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4327 pipe_ctx->stream_res.tg);
4328 }
4329
4330 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
4331 /* update MSA to requested color space */
4332 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4333 &pipe_ctx->stream->timing,
4334 color_space,
4335 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4336 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4337
4338 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4339 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4340 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4341 else
4342 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4343 resource_build_info_frame(pipe_ctx);
4344 link->dc->hwss.update_info_frame(pipe_ctx);
4345 }
4346
4347 /* CRTC Patterns */
4348 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4349 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4350 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4351 CRTC_STATE_VACTIVE);
4352 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4353 CRTC_STATE_VBLANK);
4354 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4355 CRTC_STATE_VACTIVE);
4356
4357 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
4358 if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4359 union dmub_hw_lock_flags hw_locks = { 0 };
4360 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4361
4362 hw_locks.bits.lock_dig = 1;
4363 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4364
4365 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4366 false,
4367 &hw_locks,
4368 &inst_flags);
4369 } else
4370 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4371 pipe_ctx->stream_res.tg);
4372 }
4373
4374 /* Set Test Pattern state */
4375 link->test_pattern_enabled = true;
4376 }
4377
4378 return true;
4379 }
4380
4381 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
4382 {
4383 unsigned char mstmCntl;
4384
4385 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4386 if (enable)
4387 mstmCntl |= DP_MST_EN;
4388 else
4389 mstmCntl &= (~DP_MST_EN);
4390
4391 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4392 }
4393
4394 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4395 {
4396 union dpcd_edp_config edp_config_set;
4397 bool panel_mode_edp = false;
4398
4399 memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4400
4401 if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4402
4403 switch (panel_mode) {
4404 case DP_PANEL_MODE_EDP:
4405 case DP_PANEL_MODE_SPECIAL:
4406 panel_mode_edp = true;
4407 break;
4408
4409 default:
4410 break;
4411 }
4412
4413 /*set edp panel mode in receiver*/
4414 core_link_read_dpcd(
4415 link,
4416 DP_EDP_CONFIGURATION_SET,
4417 &edp_config_set.raw,
4418 sizeof(edp_config_set.raw));
4419
4420 if (edp_config_set.bits.PANEL_MODE_EDP
4421 != panel_mode_edp) {
4422 enum dc_status result;
4423
4424 edp_config_set.bits.PANEL_MODE_EDP =
4425 panel_mode_edp;
4426 result = core_link_write_dpcd(
4427 link,
4428 DP_EDP_CONFIGURATION_SET,
4429 &edp_config_set.raw,
4430 sizeof(edp_config_set.raw));
4431
4432 ASSERT(result == DC_OK);
4433 }
4434 }
4435 DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4436 "eDP panel mode enabled: %d \n",
4437 link->link_index,
4438 link->dpcd_caps.panel_mode_edp,
4439 panel_mode_edp);
4440 }
4441
4442 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4443 {
4444 /* We need to explicitly check that connector
4445 * is not DP. Some Travis_VGA get reported
4446 * by video bios as DP.
4447 */
4448 if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4449
4450 switch (link->dpcd_caps.branch_dev_id) {
4451 case DP_BRANCH_DEVICE_ID_0022B9:
4452 /* alternate scrambler reset is required for Travis
4453 * for the case when external chip does not
4454 * provide sink device id, alternate scrambler
4455 * scheme will be overriden later by querying
4456 * Encoder features
4457 */
4458 if (strncmp(
4459 link->dpcd_caps.branch_dev_name,
4460 DP_VGA_LVDS_CONVERTER_ID_2,
4461 sizeof(
4462 link->dpcd_caps.
4463 branch_dev_name)) == 0) {
4464 return DP_PANEL_MODE_SPECIAL;
4465 }
4466 break;
4467 case DP_BRANCH_DEVICE_ID_00001A:
4468 /* alternate scrambler reset is required for Travis
4469 * for the case when external chip does not provide
4470 * sink device id, alternate scrambler scheme will
4471 * be overriden later by querying Encoder feature
4472 */
4473 if (strncmp(link->dpcd_caps.branch_dev_name,
4474 DP_VGA_LVDS_CONVERTER_ID_3,
4475 sizeof(
4476 link->dpcd_caps.
4477 branch_dev_name)) == 0) {
4478 return DP_PANEL_MODE_SPECIAL;
4479 }
4480 break;
4481 default:
4482 break;
4483 }
4484 }
4485
4486 if (link->dpcd_caps.panel_mode_edp) {
4487 return DP_PANEL_MODE_EDP;
4488 }
4489
4490 return DP_PANEL_MODE_DEFAULT;
4491 }
4492
4493 void dp_set_fec_ready(struct dc_link *link, bool ready)
4494 {
4495 /* FEC has to be "set ready" before the link training.
4496 * The policy is to always train with FEC
4497 * if the sink supports it and leave it enabled on link.
4498 * If FEC is not supported, disable it.
4499 */
4500 struct link_encoder *link_enc = link->link_enc;
4501 uint8_t fec_config = 0;
4502
4503 if (!dc_link_should_enable_fec(link))
4504 return;
4505
4506 if (link_enc->funcs->fec_set_ready &&
4507 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4508 if (ready) {
4509 fec_config = 1;
4510 if (core_link_write_dpcd(link,
4511 DP_FEC_CONFIGURATION,
4512 &fec_config,
4513 sizeof(fec_config)) == DC_OK) {
4514 link_enc->funcs->fec_set_ready(link_enc, true);
4515 link->fec_state = dc_link_fec_ready;
4516 } else {
4517 link->link_enc->funcs->fec_set_ready(link->link_enc, false);
4518 link->fec_state = dc_link_fec_not_ready;
4519 dm_error("dpcd write failed to set fec_ready");
4520 }
4521 } else if (link->fec_state == dc_link_fec_ready) {
4522 fec_config = 0;
4523 core_link_write_dpcd(link,
4524 DP_FEC_CONFIGURATION,
4525 &fec_config,
4526 sizeof(fec_config));
4527 link->link_enc->funcs->fec_set_ready(
4528 link->link_enc, false);
4529 link->fec_state = dc_link_fec_not_ready;
4530 }
4531 }
4532 }
4533
4534 void dp_set_fec_enable(struct dc_link *link, bool enable)
4535 {
4536 struct link_encoder *link_enc = link->link_enc;
4537
4538 if (!dc_link_should_enable_fec(link))
4539 return;
4540
4541 if (link_enc->funcs->fec_set_enable &&
4542 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4543 if (link->fec_state == dc_link_fec_ready && enable) {
4544 /* Accord to DP spec, FEC enable sequence can first
4545 * be transmitted anytime after 1000 LL codes have
4546 * been transmitted on the link after link training
4547 * completion. Using 1 lane RBR should have the maximum
4548 * time for transmitting 1000 LL codes which is 6.173 us.
4549 * So use 7 microseconds delay instead.
4550 */
4551 udelay(7);
4552 link_enc->funcs->fec_set_enable(link_enc, true);
4553 link->fec_state = dc_link_fec_enabled;
4554 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4555 link_enc->funcs->fec_set_enable(link_enc, false);
4556 link->fec_state = dc_link_fec_ready;
4557 }
4558 }
4559 }
4560
4561 void dpcd_set_source_specific_data(struct dc_link *link)
4562 {
4563 if (!link->dc->vendor_signature.is_valid) {
4564 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
4565 struct dpcd_amd_signature amd_signature = {0};
4566 struct dpcd_amd_device_id amd_device_id = {0};
4567
4568 amd_device_id.device_id_byte1 =
4569 (uint8_t)(link->ctx->asic_id.chip_id);
4570 amd_device_id.device_id_byte2 =
4571 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
4572 amd_device_id.dce_version =
4573 (uint8_t)(link->ctx->dce_version);
4574 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
4575 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
4576
4577 core_link_read_dpcd(link, DP_SOURCE_OUI,
4578 (uint8_t *)(&amd_signature),
4579 sizeof(amd_signature));
4580
4581 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
4582 (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
4583 (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
4584
4585 amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4586 amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4587 amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4588
4589 core_link_write_dpcd(link, DP_SOURCE_OUI,
4590 (uint8_t *)(&amd_signature),
4591 sizeof(amd_signature));
4592 }
4593
4594 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
4595 (uint8_t *)(&amd_device_id),
4596 sizeof(amd_device_id));
4597
4598 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
4599 link->dc->caps.min_horizontal_blanking_period != 0) {
4600
4601 uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
4602
4603 result_write_min_hblank = core_link_write_dpcd(link,
4604 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
4605 sizeof(hblank_size));
4606 }
4607 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
4608 WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
4609 "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
4610 result_write_min_hblank,
4611 link->link_index,
4612 link->ctx->dce_version,
4613 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
4614 link->dc->caps.min_horizontal_blanking_period,
4615 link->dpcd_caps.branch_dev_id,
4616 link->dpcd_caps.branch_dev_name[0],
4617 link->dpcd_caps.branch_dev_name[1],
4618 link->dpcd_caps.branch_dev_name[2],
4619 link->dpcd_caps.branch_dev_name[3],
4620 link->dpcd_caps.branch_dev_name[4],
4621 link->dpcd_caps.branch_dev_name[5]);
4622 } else {
4623 core_link_write_dpcd(link, DP_SOURCE_OUI,
4624 link->dc->vendor_signature.data.raw,
4625 sizeof(link->dc->vendor_signature.data.raw));
4626 }
4627 }
4628
4629 bool dc_link_set_backlight_level_nits(struct dc_link *link,
4630 bool isHDR,
4631 uint32_t backlight_millinits,
4632 uint32_t transition_time_in_ms)
4633 {
4634 struct dpcd_source_backlight_set dpcd_backlight_set;
4635 uint8_t backlight_control = isHDR ? 1 : 0;
4636
4637 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4638 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4639 return false;
4640
4641 // OLEDs have no PWM, they can only use AUX
4642 if (link->dpcd_sink_ext_caps.bits.oled == 1)
4643 backlight_control = 1;
4644
4645 *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4646 *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4647
4648
4649 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4650 (uint8_t *)(&dpcd_backlight_set),
4651 sizeof(dpcd_backlight_set)) != DC_OK)
4652 return false;
4653
4654 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4655 &backlight_control, 1) != DC_OK)
4656 return false;
4657
4658 return true;
4659 }
4660
4661 bool dc_link_get_backlight_level_nits(struct dc_link *link,
4662 uint32_t *backlight_millinits_avg,
4663 uint32_t *backlight_millinits_peak)
4664 {
4665 union dpcd_source_backlight_get dpcd_backlight_get;
4666
4667 memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4668
4669 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4670 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4671 return false;
4672
4673 if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
4674 dpcd_backlight_get.raw,
4675 sizeof(union dpcd_source_backlight_get)) != DC_OK)
4676 return false;
4677
4678 *backlight_millinits_avg =
4679 dpcd_backlight_get.bytes.backlight_millinits_avg;
4680 *backlight_millinits_peak =
4681 dpcd_backlight_get.bytes.backlight_millinits_peak;
4682
4683 /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4684 if (*backlight_millinits_avg == 0 ||
4685 *backlight_millinits_avg > *backlight_millinits_peak)
4686 return false;
4687
4688 return true;
4689 }
4690
4691 bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4692 {
4693 uint8_t backlight_enable = enable ? 1 : 0;
4694
4695 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4696 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4697 return false;
4698
4699 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4700 &backlight_enable, 1) != DC_OK)
4701 return false;
4702
4703 return true;
4704 }
4705
4706 // we read default from 0x320 because we expect BIOS wrote it there
4707 // regular get_backlight_nit reads from panel set at 0x326
4708 bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4709 {
4710 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4711 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4712 return false;
4713
4714 if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4715 (uint8_t *) backlight_millinits,
4716 sizeof(uint32_t)) != DC_OK)
4717 return false;
4718
4719 return true;
4720 }
4721
4722 bool dc_link_set_default_brightness_aux(struct dc_link *link)
4723 {
4724 uint32_t default_backlight;
4725
4726 if (link &&
4727 (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
4728 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
4729 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4730 default_backlight = 150000;
4731 // if < 5 nits or > 5000, it might be wrong readback
4732 if (default_backlight < 5000 || default_backlight > 5000000)
4733 default_backlight = 150000; //
4734
4735 return dc_link_set_backlight_level_nits(link, true,
4736 default_backlight, 0);
4737 }
4738 return false;
4739 }
4740
4741 bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing)
4742 {
4743 struct dc_link_settings link_setting;
4744 uint8_t link_bw_set;
4745 uint8_t link_rate_set;
4746 uint32_t req_bw;
4747 union lane_count_set lane_count_set = { {0} };
4748
4749 ASSERT(link || crtc_timing); // invalid input
4750
4751 if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
4752 !link->dc->debug.optimize_edp_link_rate)
4753 return false;
4754
4755
4756 // Read DPCD 00100h to find if standard link rates are set
4757 core_link_read_dpcd(link, DP_LINK_BW_SET,
4758 &link_bw_set, sizeof(link_bw_set));
4759
4760 if (link_bw_set) {
4761 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
4762 return true;
4763 }
4764
4765 // Read DPCD 00115h to find the edp link rate set used
4766 core_link_read_dpcd(link, DP_LINK_RATE_SET,
4767 &link_rate_set, sizeof(link_rate_set));
4768
4769 // Read DPCD 00101h to find out the number of lanes currently set
4770 core_link_read_dpcd(link, DP_LANE_COUNT_SET,
4771 &lane_count_set.raw, sizeof(lane_count_set));
4772
4773 req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing);
4774
4775 decide_edp_link_settings(link, &link_setting, req_bw);
4776
4777 if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
4778 lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
4779 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
4780 return true;
4781 }
4782
4783 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
4784 return false;
4785 }
4786
4787
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