drivers/gpu/drm/amd/display/dc/dc.h

   1 /*
   2  * Copyright 2012-14 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef DC_INTERFACE_H_
  27 #define DC_INTERFACE_H_
  28
  29 #include "dc_types.h"
  30 #include "grph_object_defs.h"
  31 #include "logger_types.h"
  32 #include "gpio_types.h"
  33 #include "link_service_types.h"
  34 #include "grph_object_ctrl_defs.h"
  35 #include <inc/hw/opp.h>
  36
  37 #define MAX_SURFACES 3
  38 #define MAX_STREAMS 6
  39 #define MAX_SINKS_PER_LINK 4
  40
  41 /*******************************************************************************
  42  * Display Core Interfaces
  43  ******************************************************************************/
  44
  45 struct dc_caps {
  46         uint32_t max_streams;
  47         uint32_t max_links;
  48         uint32_t max_audios;
  49         uint32_t max_slave_planes;
  50         uint32_t max_surfaces;
  51         uint32_t max_downscale_ratio;
  52         uint32_t i2c_speed_in_khz;
  53
  54         unsigned int max_cursor_size;
  55 };
  56
  57
  58 struct dc_dcc_surface_param {
  59         struct dc_size surface_size;
  60         enum surface_pixel_format format;
  61         enum swizzle_mode_values swizzle_mode;
  62         enum dc_scan_direction scan;
  63 };
  64
  65 struct dc_dcc_setting {
  66         unsigned int max_compressed_blk_size;
  67         unsigned int max_uncompressed_blk_size;
  68         bool independent_64b_blks;
  69 };
  70
  71 struct dc_surface_dcc_cap {
  72         union {
  73                 struct {
  74                         struct dc_dcc_setting rgb;
  75                 } grph;
  76
  77                 struct {
  78                         struct dc_dcc_setting luma;
  79                         struct dc_dcc_setting chroma;
  80                 } video;
  81         };
  82
  83         bool capable;
  84         bool const_color_support;
  85 };
  86
  87 struct dc_static_screen_events {
  88         bool cursor_update;
  89         bool surface_update;
  90         bool overlay_update;
  91 };
  92
  93 /* Forward declaration*/
  94 struct dc;
  95 struct dc_surface;
  96 struct validate_context;
  97
  98 struct dc_cap_funcs {
  99 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 100         bool (*get_dcc_compression_cap)(const struct dc *dc,
 101                         const struct dc_dcc_surface_param *input,
 102                         struct dc_surface_dcc_cap *output);
 103 #else
 104         int i;
 105 #endif
 106 };
 107
 108 struct dc_stream_funcs {
 109         bool (*adjust_vmin_vmax)(struct dc *dc,
 110                         struct dc_stream **stream,
 111                         int num_streams,
 112                         int vmin,
 113                         int vmax);
 114         bool (*get_crtc_position)(struct dc *dc,
 115                         struct dc_stream **stream,
 116                         int num_streams,
 117                         unsigned int *v_pos,
 118                         unsigned int *nom_v_pos);
 119
 120         bool (*set_gamut_remap)(struct dc *dc,
 121                         const struct dc_stream *stream);
 122
 123         bool (*program_csc_matrix)(struct dc *dc,
 124                         struct dc_stream *stream);
 125
 126         void (*set_static_screen_events)(struct dc *dc,
 127                         struct dc_stream **stream,
 128                         int num_streams,
 129                         const struct dc_static_screen_events *events);
 130
 131         void (*set_dither_option)(struct dc_stream *stream,
 132                         enum dc_dither_option option);
 133 };
 134
 135 struct link_training_settings;
 136
 137 struct dc_link_funcs {
 138         void (*set_drive_settings)(struct dc *dc,
 139                         struct link_training_settings *lt_settings,
 140                         const struct dc_link *link);
 141         void (*perform_link_training)(struct dc *dc,
 142                         struct dc_link_settings *link_setting,
 143                         bool skip_video_pattern);
 144         void (*set_preferred_link_settings)(struct dc *dc,
 145                         struct dc_link_settings *link_setting,
 146                         struct dc_link *link);
 147         void (*enable_hpd)(const struct dc_link *link);
 148         void (*disable_hpd)(const struct dc_link *link);
 149         void (*set_test_pattern)(
 150                         struct dc_link *link,
 151                         enum dp_test_pattern test_pattern,
 152                         const struct link_training_settings *p_link_settings,
 153                         const unsigned char *p_custom_pattern,
 154                         unsigned int cust_pattern_size);
 155 };
 156
 157 /* Structure to hold configuration flags set by dm at dc creation. */
 158 struct dc_config {
 159         bool gpu_vm_support;
 160         bool disable_disp_pll_sharing;
 161 };
 162
 163 struct dc_debug {
 164         bool surface_visual_confirm;
 165         bool sanity_checks;
 166         bool max_disp_clk;
 167         bool surface_trace;
 168         bool timing_trace;
 169         bool clock_trace;
 170         bool validation_trace;
 171         bool disable_stutter;
 172         bool disable_dcc;
 173         bool disable_dfs_bypass;
 174 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 175         bool disable_dpp_power_gate;
 176         bool disable_hubp_power_gate;
 177         bool disable_pplib_wm_range;
 178         bool use_dml_wm;
 179         bool disable_pipe_split;
 180         int sr_exit_time_dpm0_ns;
 181         int sr_enter_plus_exit_time_dpm0_ns;
 182         int sr_exit_time_ns;
 183         int sr_enter_plus_exit_time_ns;
 184         int urgent_latency_ns;
 185         int percent_of_ideal_drambw;
 186         int dram_clock_change_latency_ns;
 187         int always_scale;
 188 #endif
 189         bool disable_pplib_clock_request;
 190         bool disable_clock_gate;
 191         bool disable_dmcu;
 192         bool disable_psr;
 193         bool force_abm_enable;
 194 };
 195
 196 struct dc {
 197         struct dc_caps caps;
 198         struct dc_cap_funcs cap_funcs;
 199         struct dc_stream_funcs stream_funcs;
 200         struct dc_link_funcs link_funcs;
 201         struct dc_config config;
 202         struct dc_debug debug;
 203 };
 204
 205 enum frame_buffer_mode {
 206         FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
 207         FRAME_BUFFER_MODE_ZFB_ONLY,
 208         FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
 209 } ;
 210
 211 struct dchub_init_data {
 212         int64_t zfb_phys_addr_base;
 213         int64_t zfb_mc_base_addr;
 214         uint64_t zfb_size_in_byte;
 215         enum frame_buffer_mode fb_mode;
 216         bool dchub_initialzied;
 217         bool dchub_info_valid;
 218 };
 219
 220 struct dc_init_data {
 221         struct hw_asic_id asic_id;
 222         void *driver; /* ctx */
 223         struct cgs_device *cgs_device;
 224
 225         int num_virtual_links;
 226         /*
 227          * If 'vbios_override' not NULL, it will be called instead
 228          * of the real VBIOS. Intended use is Diagnostics on FPGA.
 229          */
 230         struct dc_bios *vbios_override;
 231         enum dce_environment dce_environment;
 232
 233         struct dc_config flags;
 234 };
 235
 236 struct dc *dc_create(const struct dc_init_data *init_params);
 237
 238 void dc_destroy(struct dc **dc);
 239
 240 bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data);
 241
 242 void dc_log_hw_state(struct dc *dc);
 243
 244 /*******************************************************************************
 245  * Surface Interfaces
 246  ******************************************************************************/
 247
 248 enum {
 249         TRANSFER_FUNC_POINTS = 1025
 250 };
 251
 252 struct dc_hdr_static_metadata {
 253         /* display chromaticities and white point in units of 0.00001 */
 254         unsigned int chromaticity_green_x;
 255         unsigned int chromaticity_green_y;
 256         unsigned int chromaticity_blue_x;
 257         unsigned int chromaticity_blue_y;
 258         unsigned int chromaticity_red_x;
 259         unsigned int chromaticity_red_y;
 260         unsigned int chromaticity_white_point_x;
 261         unsigned int chromaticity_white_point_y;
 262
 263         uint32_t min_luminance;
 264         uint32_t max_luminance;
 265         uint32_t maximum_content_light_level;
 266         uint32_t maximum_frame_average_light_level;
 267
 268         bool hdr_supported;
 269         bool is_hdr;
 270 };
 271
 272 enum dc_transfer_func_type {
 273         TF_TYPE_PREDEFINED,
 274         TF_TYPE_DISTRIBUTED_POINTS,
 275         TF_TYPE_BYPASS
 276 };
 277
 278 struct dc_transfer_func_distributed_points {
 279         struct fixed31_32 red[TRANSFER_FUNC_POINTS];
 280         struct fixed31_32 green[TRANSFER_FUNC_POINTS];
 281         struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
 282
 283         uint16_t end_exponent;
 284         uint16_t x_point_at_y1_red;
 285         uint16_t x_point_at_y1_green;
 286         uint16_t x_point_at_y1_blue;
 287 };
 288
 289 enum dc_transfer_func_predefined {
 290         TRANSFER_FUNCTION_SRGB,
 291         TRANSFER_FUNCTION_BT709,
 292         TRANSFER_FUNCTION_PQ,
 293         TRANSFER_FUNCTION_LINEAR,
 294 };
 295
 296 struct dc_transfer_func {
 297         struct dc_transfer_func_distributed_points tf_pts;
 298         enum dc_transfer_func_type type;
 299         enum dc_transfer_func_predefined tf;
 300         struct dc_context *ctx;
 301         int ref_count;
 302 };
 303
 304 /*
 305  * This structure is filled in by dc_surface_get_status and contains
 306  * the last requested address and the currently active address so the called
 307  * can determine if there are any outstanding flips
 308  */
 309 struct dc_surface_status {
 310         struct dc_plane_address requested_address;
 311         struct dc_plane_address current_address;
 312         bool is_flip_pending;
 313         bool is_right_eye;
 314 };
 315
 316 struct dc_surface {
 317         struct dc_plane_address address;
 318
 319         struct scaling_taps scaling_quality;
 320         struct rect src_rect;
 321         struct rect dst_rect;
 322         struct rect clip_rect;
 323
 324         union plane_size plane_size;
 325         union dc_tiling_info tiling_info;
 326
 327         struct dc_plane_dcc_param dcc;
 328         struct dc_hdr_static_metadata hdr_static_ctx;
 329
 330         struct dc_gamma *gamma_correction;
 331         struct dc_transfer_func *in_transfer_func;
 332
 333         enum dc_color_space color_space;
 334         enum surface_pixel_format format;
 335         enum dc_rotation_angle rotation;
 336         enum plane_stereo_format stereo_format;
 337
 338         bool per_pixel_alpha;
 339         bool visible;
 340         bool flip_immediate;
 341         bool horizontal_mirror;
 342
 343         /* private to DC core */
 344         struct dc_surface_status status;
 345         struct dc_context *ctx;
 346
 347         /* private to dc_surface.c */
 348         enum dc_irq_source irq_source;
 349         int ref_count;
 350 };
 351
 352 struct dc_plane_info {
 353         union plane_size plane_size;
 354         union dc_tiling_info tiling_info;
 355         struct dc_plane_dcc_param dcc;
 356         enum surface_pixel_format format;
 357         enum dc_rotation_angle rotation;
 358         enum plane_stereo_format stereo_format;
 359         enum dc_color_space color_space; /*todo: wrong place, fits in scaling info*/
 360         bool horizontal_mirror;
 361         bool visible;
 362         bool per_pixel_alpha;
 363 };
 364
 365 struct dc_scaling_info {
 366         struct rect src_rect;
 367         struct rect dst_rect;
 368         struct rect clip_rect;
 369         struct scaling_taps scaling_quality;
 370 };
 371
 372 struct dc_surface_update {
 373         struct dc_surface *surface;
 374
 375         /* isr safe update parameters.  null means no updates */
 376         struct dc_flip_addrs *flip_addr;
 377         struct dc_plane_info *plane_info;
 378         struct dc_scaling_info *scaling_info;
 379         /* following updates require alloc/sleep/spin that is not isr safe,
 380          * null means no updates
 381          */
 382         /* gamma TO BE REMOVED */
 383         struct dc_gamma *gamma;
 384         struct dc_transfer_func *in_transfer_func;
 385         struct dc_hdr_static_metadata *hdr_static_metadata;
 386 };
 387
 388 /*
 389  * Create a new surface with default parameters;
 390  */
 391 struct dc_surface *dc_create_surface(const struct dc *dc);
 392 const struct dc_surface_status *dc_surface_get_status(
 393                 const struct dc_surface *dc_surface);
 394
 395 void dc_surface_retain(struct dc_surface *dc_surface);
 396 void dc_surface_release(struct dc_surface *dc_surface);
 397
 398 void dc_gamma_retain(struct dc_gamma *dc_gamma);
 399 void dc_gamma_release(struct dc_gamma **dc_gamma);
 400 struct dc_gamma *dc_create_gamma(void);
 401
 402 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
 403 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
 404 struct dc_transfer_func *dc_create_transfer_func(void);
 405
 406 /*
 407  * This structure holds a surface address.  There could be multiple addresses
 408  * in cases such as Stereo 3D, Planar YUV, etc.  Other per-flip attributes such
 409  * as frame durations and DCC format can also be set.
 410  */
 411 struct dc_flip_addrs {
 412         struct dc_plane_address address;
 413         bool flip_immediate;
 414         /* TODO: add flip duration for FreeSync */
 415 };
 416
 417 /*
 418  * Set up surface attributes and associate to a stream
 419  * The surfaces parameter is an absolute set of all surface active for the stream.
 420  * If no surfaces are provided, the stream will be blanked; no memory read.
 421  * Any flip related attribute changes must be done through this interface.
 422  *
 423  * After this call:
 424  *   Surfaces attributes are programmed and configured to be composed into stream.
 425  *   This does not trigger a flip.  No surface address is programmed.
 426  */
 427
 428 bool dc_commit_surfaces_to_stream(
 429                 struct dc *dc,
 430                 struct dc_surface **dc_surfaces,
 431                 uint8_t surface_count,
 432                 struct dc_stream *stream);
 433
 434 bool dc_post_update_surfaces_to_stream(
 435                 struct dc *dc);
 436
 437 /* Surface update type is used by dc_update_surfaces_and_stream
 438  * The update type is determined at the very beginning of the function based
 439  * on parameters passed in and decides how much programming (or updating) is
 440  * going to be done during the call.
 441  *
 442  * UPDATE_TYPE_FAST is used for really fast updates that do not require much
 443  * logical calculations or hardware register programming. This update MUST be
 444  * ISR safe on windows. Currently fast update will only be used to flip surface
 445  * address.
 446  *
 447  * UPDATE_TYPE_MED is used for slower updates which require significant hw
 448  * re-programming however do not affect bandwidth consumption or clock
 449  * requirements. At present, this is the level at which front end updates
 450  * that do not require us to run bw_calcs happen. These are in/out transfer func
 451  * updates, viewport offset changes, recout size changes and pixel depth changes.
 452  * This update can be done at ISR, but we want to minimize how often this happens.
 453  *
 454  * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
 455  * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
 456  * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
 457  * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
 458  * a full update. This cannot be done at ISR level and should be a rare event.
 459  * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
 460  * underscan we don't expect to see this call at all.
 461  */
 462
 463 enum surface_update_type {
 464         UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
 465         UPDATE_TYPE_MED,  /* ISR safe, most of programming needed, no bw/clk change*/
 466         UPDATE_TYPE_FULL, /* may need to shuffle resources */
 467 };
 468
 469 /*******************************************************************************
 470  * Stream Interfaces
 471  ******************************************************************************/
 472
 473 struct dc_stream_status {
 474         int primary_otg_inst;
 475         int surface_count;
 476         struct dc_surface *surfaces[MAX_SURFACE_NUM];
 477
 478         /*
 479          * link this stream passes through
 480          */
 481         struct dc_link *link;
 482 };
 483
 484 struct dc_stream {
 485         struct dc_sink *sink;
 486         struct dc_crtc_timing timing;
 487
 488         struct rect src; /* composition area */
 489         struct rect dst; /* stream addressable area */
 490
 491         struct audio_info audio_info;
 492
 493         struct freesync_context freesync_ctx;
 494
 495         struct dc_transfer_func *out_transfer_func;
 496         struct colorspace_transform gamut_remap_matrix;
 497         struct csc_transform csc_color_matrix;
 498
 499         enum signal_type output_signal;
 500
 501         enum dc_color_space output_color_space;
 502         enum dc_dither_option dither_option;
 503
 504         enum view_3d_format view_format;
 505
 506         bool ignore_msa_timing_param;
 507         /* TODO: custom INFO packets */
 508         /* TODO: ABM info (DMCU) */
 509         /* TODO: PSR info */
 510         /* TODO: CEA VIC */
 511
 512         /* from core_stream struct */
 513         struct dc_context *ctx;
 514
 515         /* used by DCP and FMT */
 516         struct bit_depth_reduction_params bit_depth_params;
 517         struct clamping_and_pixel_encoding_params clamping;
 518
 519         int phy_pix_clk;
 520         enum signal_type signal;
 521
 522         struct dc_stream_status status;
 523
 524         /* from stream struct */
 525         int ref_count;
 526 };
 527
 528 struct dc_stream_update {
 529         struct rect src;
 530         struct rect dst;
 531         struct dc_transfer_func *out_transfer_func;
 532 };
 533
 534
 535 /*
 536  * Setup stream attributes if no stream updates are provided
 537  * there will be no impact on the stream parameters
 538  *
 539  * Set up surface attributes and associate to a stream
 540  * The surfaces parameter is an absolute set of all surface active for the stream.
 541  * If no surfaces are provided, the stream will be blanked; no memory read.
 542  * Any flip related attribute changes must be done through this interface.
 543  *
 544  * After this call:
 545  *   Surfaces attributes are programmed and configured to be composed into stream.
 546  *   This does not trigger a flip.  No surface address is programmed.
 547  *
 548  */
 549
 550 void dc_update_surfaces_and_stream(struct dc *dc,
 551                 struct dc_surface_update *surface_updates, int surface_count,
 552                 struct dc_stream *dc_stream,
 553                 struct dc_stream_update *stream_update);
 554
 555 /*
 556  * Log the current stream state.
 557  */
 558 void dc_stream_log(
 559         const struct dc_stream *stream,
 560         struct dal_logger *dc_logger,
 561         enum dc_log_type log_type);
 562
 563 uint8_t dc_get_current_stream_count(const struct dc *dc);
 564 struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i);
 565
 566 /*
 567  * Return the current frame counter.
 568  */
 569 uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream);
 570
 571 /* TODO: Return parsed values rather than direct register read
 572  * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos)
 573  * being refactored properly to be dce-specific
 574  */
 575 bool dc_stream_get_scanoutpos(const struct dc_stream *stream,
 576                                   uint32_t *v_blank_start,
 577                                   uint32_t *v_blank_end,
 578                                   uint32_t *h_position,
 579                                   uint32_t *v_position);
 580
 581 /*
 582  * Structure to store surface/stream associations for validation
 583  */
 584 struct dc_validation_set {
 585         struct dc_stream *stream;
 586         struct dc_surface *surfaces[MAX_SURFACES];
 587         uint8_t surface_count;
 588 };
 589
 590 bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream);
 591
 592 bool dc_validate_surface(const struct dc *dc, const struct dc_surface *surface);
 593 /*
 594  * This function takes a set of resources and checks that they are cofunctional.
 595  *
 596  * After this call:
 597  *   No hardware is programmed for call.  Only validation is done.
 598  */
 599 struct validate_context *dc_get_validate_context(
 600                 const struct dc *dc,
 601                 const struct dc_validation_set set[],
 602                 uint8_t set_count);
 603
 604 bool dc_validate_resources(
 605                 const struct dc *dc,
 606                 const struct dc_validation_set set[],
 607                 uint8_t set_count);
 608
 609 /*
 610  * This function takes a stream and checks if it is guaranteed to be supported.
 611  * Guaranteed means that MAX_COFUNC similar streams are supported.
 612  *
 613  * After this call:
 614  *   No hardware is programmed for call.  Only validation is done.
 615  */
 616
 617 bool dc_validate_guaranteed(
 618                 const struct dc *dc,
 619                 struct dc_stream *stream);
 620
 621 void dc_resource_validate_ctx_copy_construct(
 622                 const struct validate_context *src_ctx,
 623                 struct validate_context *dst_ctx);
 624
 625 void dc_resource_validate_ctx_destruct(struct validate_context *context);
 626
 627 /*
 628  * TODO update to make it about validation sets
 629  * Set up streams and links associated to drive sinks
 630  * The streams parameter is an absolute set of all active streams.
 631  *
 632  * After this call:
 633  *   Phy, Encoder, Timing Generator are programmed and enabled.
 634  *   New streams are enabled with blank stream; no memory read.
 635  */
 636 bool dc_commit_context(struct dc *dc, struct validate_context *context);
 637
 638 /*
 639  * Set up streams and links associated to drive sinks
 640  * The streams parameter is an absolute set of all active streams.
 641  *
 642  * After this call:
 643  *   Phy, Encoder, Timing Generator are programmed and enabled.
 644  *   New streams are enabled with blank stream; no memory read.
 645  */
 646 bool dc_commit_streams(
 647                 struct dc *dc,
 648                 struct dc_stream *streams[],
 649                 uint8_t stream_count);
 650 /*
 651  * Enable stereo when commit_streams is not required,
 652  * for example, frame alternate.
 653  */
 654 bool dc_enable_stereo(
 655         struct dc *dc,
 656         struct validate_context *context,
 657         struct dc_stream *streams[],
 658         uint8_t stream_count);
 659
 660 /**
 661  * Create a new default stream for the requested sink
 662  */
 663 struct dc_stream *dc_create_stream_for_sink(struct dc_sink *dc_sink);
 664
 665 void dc_stream_retain(struct dc_stream *dc_stream);
 666 void dc_stream_release(struct dc_stream *dc_stream);
 667
 668 struct dc_stream_status *dc_stream_get_status(
 669         struct dc_stream *dc_stream);
 670
 671 enum surface_update_type dc_check_update_surfaces_for_stream(
 672                 struct dc *dc,
 673                 struct dc_surface_update *updates,
 674                 int surface_count,
 675                 struct dc_stream_update *stream_update,
 676                 const struct dc_stream_status *stream_status);
 677
 678
 679 void dc_retain_validate_context(struct validate_context *context);
 680 void dc_release_validate_context(struct validate_context *context);
 681
 682 /*******************************************************************************
 683  * Link Interfaces
 684  ******************************************************************************/
 685
 686 struct dpcd_caps {
 687         union dpcd_rev dpcd_rev;
 688         union max_lane_count max_ln_count;
 689         union max_down_spread max_down_spread;
 690
 691         /* dongle type (DP converter, CV smart dongle) */
 692         enum display_dongle_type dongle_type;
 693         /* Dongle's downstream count. */
 694         union sink_count sink_count;
 695         /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
 696         indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
 697         struct dc_dongle_caps dongle_caps;
 698
 699         uint32_t sink_dev_id;
 700         uint32_t branch_dev_id;
 701         int8_t branch_dev_name[6];
 702         int8_t branch_hw_revision;
 703
 704         bool allow_invalid_MSA_timing_param;
 705         bool panel_mode_edp;
 706 };
 707
 708 struct dc_link_status {
 709         struct dpcd_caps *dpcd_caps;
 710 };
 711
 712 /* DP MST stream allocation (payload bandwidth number) */
 713 struct link_mst_stream_allocation {
 714         /* DIG front */
 715         const struct stream_encoder *stream_enc;
 716         /* associate DRM payload table with DC stream encoder */
 717         uint8_t vcp_id;
 718         /* number of slots required for the DP stream in transport packet */
 719         uint8_t slot_count;
 720 };
 721
 722 /* DP MST stream allocation table */
 723 struct link_mst_stream_allocation_table {
 724         /* number of DP video streams */
 725         int stream_count;
 726         /* array of stream allocations */
 727         struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
 728 };
 729
 730 /*
 731  * A link contains one or more sinks and their connected status.
 732  * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
 733  */
 734 struct dc_link {
 735         struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
 736         unsigned int sink_count;
 737         struct dc_sink *local_sink;
 738         unsigned int link_index;
 739         enum dc_connection_type type;
 740         enum signal_type connector_signal;
 741         enum dc_irq_source irq_source_hpd;
 742         enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse  */
 743         /* caps is the same as reported_link_cap. link_traing use
 744          * reported_link_cap. Will clean up.  TODO
 745          */
 746         struct dc_link_settings reported_link_cap;
 747         struct dc_link_settings verified_link_cap;
 748         struct dc_link_settings cur_link_settings;
 749         struct dc_lane_settings cur_lane_setting;
 750         struct dc_link_settings preferred_link_setting;
 751
 752         uint8_t ddc_hw_inst;
 753
 754         uint8_t hpd_src;
 755
 756         uint8_t link_enc_hw_inst;
 757
 758         bool test_pattern_enabled;
 759         union compliance_test_state compliance_test_state;
 760
 761         void *priv;
 762
 763         struct ddc_service *ddc;
 764
 765         bool aux_mode;
 766
 767         /* Private to DC core */
 768
 769         const struct core_dc *dc;
 770
 771         struct dc_context *ctx;
 772
 773         struct link_encoder *link_enc;
 774         struct graphics_object_id link_id;
 775         union ddi_channel_mapping ddi_channel_mapping;
 776         struct connector_device_tag_info device_tag;
 777         struct dpcd_caps dpcd_caps;
 778         unsigned int dpcd_sink_count;
 779
 780         enum edp_revision edp_revision;
 781         bool psr_enabled;
 782
 783         /* MST record stream using this link */
 784         struct link_flags {
 785                 bool dp_keep_receiver_powered;
 786         } wa_flags;
 787         struct link_mst_stream_allocation_table mst_stream_alloc_table;
 788
 789         struct dc_link_status link_status;
 790
 791 };
 792
 793 const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
 794
 795 /*
 796  * Return an enumerated dc_link.  dc_link order is constant and determined at
 797  * boot time.  They cannot be created or destroyed.
 798  * Use dc_get_caps() to get number of links.
 799  */
 800 struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index);
 801
 802 /* Return id of physical connector represented by a dc_link at link_index.*/
 803 const struct graphics_object_id dc_get_link_id_at_index(
 804                 struct dc *dc, uint32_t link_index);
 805
 806 /* Set backlight level of an embedded panel (eDP, LVDS). */
 807 bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level,
 808                 uint32_t frame_ramp, const struct dc_stream *stream);
 809
 810 bool dc_link_set_abm_disable(const struct dc_link *dc_link);
 811
 812 bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable);
 813
 814 bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state);
 815
 816 bool dc_link_setup_psr(struct dc_link *dc_link,
 817                 const struct dc_stream *stream, struct psr_config *psr_config,
 818                 struct psr_context *psr_context);
 819
 820 /* Request DC to detect if there is a Panel connected.
 821  * boot - If this call is during initial boot.
 822  * Return false for any type of detection failure or MST detection
 823  * true otherwise. True meaning further action is required (status update
 824  * and OS notification).
 825  */
 826 bool dc_link_detect(struct dc_link *dc_link, bool boot);
 827
 828 /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
 829  * Return:
 830  * true - Downstream port status changed. DM should call DC to do the
 831  * detection.
 832  * false - no change in Downstream port status. No further action required
 833  * from DM. */
 834 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
 835                 union hpd_irq_data *hpd_irq_dpcd_data);
 836
 837 struct dc_sink_init_data;
 838
 839 struct dc_sink *dc_link_add_remote_sink(
 840                 struct dc_link *dc_link,
 841                 const uint8_t *edid,
 842                 int len,
 843                 struct dc_sink_init_data *init_data);
 844
 845 void dc_link_remove_remote_sink(
 846         struct dc_link *link,
 847         struct dc_sink *sink);
 848
 849 /* Used by diagnostics for virtual link at the moment */
 850 void dc_link_set_sink(struct dc_link *link, struct dc_sink *sink);
 851
 852 void dc_link_dp_set_drive_settings(
 853         struct dc_link *link,
 854         struct link_training_settings *lt_settings);
 855
 856 enum link_training_result dc_link_dp_perform_link_training(
 857         struct dc_link *link,
 858         const struct dc_link_settings *link_setting,
 859         bool skip_video_pattern);
 860
 861 void dc_link_dp_enable_hpd(const struct dc_link *link);
 862
 863 void dc_link_dp_disable_hpd(const struct dc_link *link);
 864
 865 bool dc_link_dp_set_test_pattern(
 866         struct dc_link *link,
 867         enum dp_test_pattern test_pattern,
 868         const struct link_training_settings *p_link_settings,
 869         const unsigned char *p_custom_pattern,
 870         unsigned int cust_pattern_size);
 871
 872 /*******************************************************************************
 873  * Sink Interfaces - A sink corresponds to a display output device
 874  ******************************************************************************/
 875
 876 struct dc_container_id {
 877         // 128bit GUID in binary form
 878         unsigned char  guid[16];
 879         // 8 byte port ID -> ELD.PortID
 880         unsigned int   portId[2];
 881         // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
 882         unsigned short manufacturerName;
 883         // 2 byte product code -> ELD.ProductCode
 884         unsigned short productCode;
 885 };
 886
 887
 888
 889 /*
 890  * The sink structure contains EDID and other display device properties
 891  */
 892 struct dc_sink {
 893         enum signal_type sink_signal;
 894         struct dc_edid dc_edid; /* raw edid */
 895         struct dc_edid_caps edid_caps; /* parse display caps */
 896         struct dc_container_id *dc_container_id;
 897         uint32_t dongle_max_pix_clk;
 898         void *priv;
 899         struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
 900         bool converter_disable_audio;
 901
 902         /* private to DC core */
 903         struct dc_link *link;
 904         struct dc_context *ctx;
 905
 906         /* private to dc_sink.c */
 907         int ref_count;
 908 };
 909
 910 void dc_sink_retain(struct dc_sink *sink);
 911 void dc_sink_release(struct dc_sink *sink);
 912
 913 const struct audio **dc_get_audios(struct dc *dc);
 914
 915 struct dc_sink_init_data {
 916         enum signal_type sink_signal;
 917         struct dc_link *link;
 918         uint32_t dongle_max_pix_clk;
 919         bool converter_disable_audio;
 920 };
 921
 922 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
 923 bool dc_sink_get_container_id(struct dc_sink *dc_sink, struct dc_container_id *container_id);
 924 bool dc_sink_set_container_id(struct dc_sink *dc_sink, const struct dc_container_id *container_id);
 925
 926 /*******************************************************************************
 927  * Cursor interfaces - To manages the cursor within a stream
 928  ******************************************************************************/
 929 /* TODO: Deprecated once we switch to dc_set_cursor_position */
 930 bool dc_stream_set_cursor_attributes(
 931         const struct dc_stream *stream,
 932         const struct dc_cursor_attributes *attributes);
 933
 934 bool dc_stream_set_cursor_position(
 935         struct dc_stream *stream,
 936         const struct dc_cursor_position *position);
 937
 938 /* Newer interfaces  */
 939 struct dc_cursor {
 940         struct dc_plane_address address;
 941         struct dc_cursor_attributes attributes;
 942 };
 943
 944 /*******************************************************************************
 945  * Interrupt interfaces
 946  ******************************************************************************/
 947 enum dc_irq_source dc_interrupt_to_irq_source(
 948                 struct dc *dc,
 949                 uint32_t src_id,
 950                 uint32_t ext_id);
 951 void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable);
 952 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
 953 enum dc_irq_source dc_get_hpd_irq_source_at_index(
 954                 struct dc *dc, uint32_t link_index);
 955
 956 /*******************************************************************************
 957  * Power Interfaces
 958  ******************************************************************************/
 959
 960 void dc_set_power_state(
 961                 struct dc *dc,
 962                 enum dc_acpi_cm_power_state power_state);
 963 void dc_resume(const struct dc *dc);
 964
 965 /*
 966  * DPCD access interfaces
 967  */
 968
 969 bool dc_read_aux_dpcd(
 970                 struct dc *dc,
 971                 uint32_t link_index,
 972                 uint32_t address,
 973                 uint8_t *data,
 974                 uint32_t size);
 975
 976 bool dc_write_aux_dpcd(
 977                 struct dc *dc,
 978                 uint32_t link_index,
 979                 uint32_t address,
 980                 const uint8_t *data,
 981                 uint32_t size);
 982
 983 bool dc_read_aux_i2c(
 984                 struct dc *dc,
 985                 uint32_t link_index,
 986                 enum i2c_mot_mode mot,
 987                 uint32_t address,
 988                 uint8_t *data,
 989                 uint32_t size);
 990
 991 bool dc_write_aux_i2c(
 992                 struct dc *dc,
 993                 uint32_t link_index,
 994                 enum i2c_mot_mode mot,
 995                 uint32_t address,
 996                 const uint8_t *data,
 997                 uint32_t size);
 998
 999 bool dc_query_ddc_data(
1000                 struct dc *dc,
1001                 uint32_t link_index,
1002                 uint32_t address,
1003                 uint8_t *write_buf,
1004                 uint32_t write_size,
1005                 uint8_t *read_buf,
1006                 uint32_t read_size);
1007
1008 bool dc_submit_i2c(
1009                 struct dc *dc,
1010                 uint32_t link_index,
1011                 struct i2c_command *cmd);
1012
1013
1014 #endif /* DC_INTERFACE_H_ */