drivers/gpu/drm/amd/display/dc/dc.h

   1 /*
   2  * Copyright 2012-14 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef DC_INTERFACE_H_
  27 #define DC_INTERFACE_H_
  28
  29 #include "dc_types.h"
  30 #include "grph_object_defs.h"
  31 #include "logger_types.h"
  32 #include "gpio_types.h"
  33 #include "link_service_types.h"
  34
  35 #define MAX_SURFACES 3
  36 #define MAX_STREAMS 6
  37 #define MAX_SINKS_PER_LINK 4
  38
  39 /*******************************************************************************
  40  * Display Core Interfaces
  41  ******************************************************************************/
  42
  43 struct dc_caps {
  44         uint32_t max_streams;
  45         uint32_t max_links;
  46         uint32_t max_audios;
  47         uint32_t max_slave_planes;
  48         uint32_t max_surfaces;
  49         uint32_t max_downscale_ratio;
  50         uint32_t i2c_speed_in_khz;
  51
  52         unsigned int max_cursor_size;
  53 };
  54
  55
  56 struct dc_dcc_surface_param {
  57         struct dc_size surface_size;
  58         enum surface_pixel_format format;
  59         enum swizzle_mode_values swizzle_mode;
  60         enum dc_scan_direction scan;
  61 };
  62
  63 struct dc_dcc_setting {
  64         unsigned int max_compressed_blk_size;
  65         unsigned int max_uncompressed_blk_size;
  66         bool independent_64b_blks;
  67 };
  68
  69 struct dc_surface_dcc_cap {
  70         union {
  71                 struct {
  72                         struct dc_dcc_setting rgb;
  73                 } grph;
  74
  75                 struct {
  76                         struct dc_dcc_setting luma;
  77                         struct dc_dcc_setting chroma;
  78                 } video;
  79         };
  80
  81         bool capable;
  82         bool const_color_support;
  83 };
  84
  85 struct dc_static_screen_events {
  86         bool cursor_update;
  87         bool surface_update;
  88         bool overlay_update;
  89 };
  90
  91 /* Forward declaration*/
  92 struct dc;
  93 struct dc_surface;
  94 struct validate_context;
  95
  96 struct dc_cap_funcs {
  97 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  98         bool (*get_dcc_compression_cap)(const struct dc *dc,
  99                         const struct dc_dcc_surface_param *input,
 100                         struct dc_surface_dcc_cap *output);
 101 #else
 102         int i;
 103 #endif
 104 };
 105
 106 struct dc_stream_funcs {
 107         bool (*adjust_vmin_vmax)(struct dc *dc,
 108                         const struct dc_stream **stream,
 109                         int num_streams,
 110                         int vmin,
 111                         int vmax);
 112         bool (*get_crtc_position)(struct dc *dc,
 113                         const struct dc_stream **stream,
 114                         int num_streams,
 115                         unsigned int *v_pos,
 116                         unsigned int *nom_v_pos);
 117
 118         bool (*set_gamut_remap)(struct dc *dc,
 119                         const struct dc_stream *stream);
 120
 121         bool (*program_csc_matrix)(struct dc *dc,
 122                         const struct dc_stream *stream);
 123
 124         void (*set_static_screen_events)(struct dc *dc,
 125                         const struct dc_stream **stream,
 126                         int num_streams,
 127                         const struct dc_static_screen_events *events);
 128
 129         void (*set_dither_option)(const struct dc_stream *stream,
 130                         enum dc_dither_option option);
 131 };
 132
 133 struct link_training_settings;
 134
 135 struct dc_link_funcs {
 136         void (*set_drive_settings)(struct dc *dc,
 137                         struct link_training_settings *lt_settings,
 138                         const struct dc_link *link);
 139         void (*perform_link_training)(struct dc *dc,
 140                         struct dc_link_settings *link_setting,
 141                         bool skip_video_pattern);
 142         void (*set_preferred_link_settings)(struct dc *dc,
 143                         struct dc_link_settings *link_setting,
 144                         const struct dc_link *link);
 145         void (*enable_hpd)(const struct dc_link *link);
 146         void (*disable_hpd)(const struct dc_link *link);
 147         void (*set_test_pattern)(
 148                         const struct dc_link *link,
 149                         enum dp_test_pattern test_pattern,
 150                         const struct link_training_settings *p_link_settings,
 151                         const unsigned char *p_custom_pattern,
 152                         unsigned int cust_pattern_size);
 153 };
 154
 155 /* Structure to hold configuration flags set by dm at dc creation. */
 156 struct dc_config {
 157         bool gpu_vm_support;
 158         bool disable_disp_pll_sharing;
 159 };
 160
 161 struct dc_debug {
 162         bool surface_visual_confirm;
 163         bool sanity_checks;
 164         bool max_disp_clk;
 165         bool surface_trace;
 166         bool timing_trace;
 167         bool clock_trace;
 168         bool validation_trace;
 169         bool disable_stutter;
 170         bool disable_dcc;
 171         bool disable_dfs_bypass;
 172 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 173         bool disable_dpp_power_gate;
 174         bool disable_hubp_power_gate;
 175         bool disable_pplib_wm_range;
 176         bool use_dml_wm;
 177         bool disable_pipe_split;
 178         int sr_exit_time_dpm0_ns;
 179         int sr_enter_plus_exit_time_dpm0_ns;
 180         int sr_exit_time_ns;
 181         int sr_enter_plus_exit_time_ns;
 182         int urgent_latency_ns;
 183         int percent_of_ideal_drambw;
 184         int dram_clock_change_latency_ns;
 185         int always_scale;
 186 #endif
 187         bool disable_pplib_clock_request;
 188         bool disable_clock_gate;
 189         bool disable_dmcu;
 190         bool disable_psr;
 191         bool force_abm_enable;
 192 };
 193
 194 struct dc {
 195         struct dc_caps caps;
 196         struct dc_cap_funcs cap_funcs;
 197         struct dc_stream_funcs stream_funcs;
 198         struct dc_link_funcs link_funcs;
 199         struct dc_config config;
 200         struct dc_debug debug;
 201 };
 202
 203 enum frame_buffer_mode {
 204         FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
 205         FRAME_BUFFER_MODE_ZFB_ONLY,
 206         FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
 207 } ;
 208
 209 struct dchub_init_data {
 210         int64_t zfb_phys_addr_base;
 211         int64_t zfb_mc_base_addr;
 212         uint64_t zfb_size_in_byte;
 213         enum frame_buffer_mode fb_mode;
 214         bool dchub_initialzied;
 215         bool dchub_info_valid;
 216 };
 217
 218 struct dc_init_data {
 219         struct hw_asic_id asic_id;
 220         void *driver; /* ctx */
 221         struct cgs_device *cgs_device;
 222
 223         int num_virtual_links;
 224         /*
 225          * If 'vbios_override' not NULL, it will be called instead
 226          * of the real VBIOS. Intended use is Diagnostics on FPGA.
 227          */
 228         struct dc_bios *vbios_override;
 229         enum dce_environment dce_environment;
 230
 231         struct dc_config flags;
 232 };
 233
 234 struct dc *dc_create(const struct dc_init_data *init_params);
 235
 236 void dc_destroy(struct dc **dc);
 237
 238 bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data);
 239
 240 void dc_log_hw_state(struct dc *dc);
 241
 242 /*******************************************************************************
 243  * Surface Interfaces
 244  ******************************************************************************/
 245
 246 enum {
 247         TRANSFER_FUNC_POINTS = 1025
 248 };
 249
 250 struct dc_hdr_static_metadata {
 251         /* display chromaticities and white point in units of 0.00001 */
 252         unsigned int chromaticity_green_x;
 253         unsigned int chromaticity_green_y;
 254         unsigned int chromaticity_blue_x;
 255         unsigned int chromaticity_blue_y;
 256         unsigned int chromaticity_red_x;
 257         unsigned int chromaticity_red_y;
 258         unsigned int chromaticity_white_point_x;
 259         unsigned int chromaticity_white_point_y;
 260
 261         uint32_t min_luminance;
 262         uint32_t max_luminance;
 263         uint32_t maximum_content_light_level;
 264         uint32_t maximum_frame_average_light_level;
 265
 266         bool hdr_supported;
 267         bool is_hdr;
 268 };
 269
 270 enum dc_transfer_func_type {
 271         TF_TYPE_PREDEFINED,
 272         TF_TYPE_DISTRIBUTED_POINTS,
 273         TF_TYPE_BYPASS
 274 };
 275
 276 struct dc_transfer_func_distributed_points {
 277         struct fixed31_32 red[TRANSFER_FUNC_POINTS];
 278         struct fixed31_32 green[TRANSFER_FUNC_POINTS];
 279         struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
 280
 281         uint16_t end_exponent;
 282         uint16_t x_point_at_y1_red;
 283         uint16_t x_point_at_y1_green;
 284         uint16_t x_point_at_y1_blue;
 285 };
 286
 287 enum dc_transfer_func_predefined {
 288         TRANSFER_FUNCTION_SRGB,
 289         TRANSFER_FUNCTION_BT709,
 290         TRANSFER_FUNCTION_PQ,
 291         TRANSFER_FUNCTION_LINEAR,
 292 };
 293
 294 struct dc_transfer_func {
 295         struct dc_transfer_func_distributed_points tf_pts;
 296         enum dc_transfer_func_type type;
 297         enum dc_transfer_func_predefined tf;
 298         struct dc_context *ctx;
 299         int ref_count;
 300 };
 301
 302 struct dc_surface {
 303         struct dc_plane_address address;
 304
 305         struct scaling_taps scaling_quality;
 306         struct rect src_rect;
 307         struct rect dst_rect;
 308         struct rect clip_rect;
 309
 310         union plane_size plane_size;
 311         union dc_tiling_info tiling_info;
 312
 313         struct dc_plane_dcc_param dcc;
 314         struct dc_hdr_static_metadata hdr_static_ctx;
 315
 316         const struct dc_gamma *gamma_correction;
 317         struct dc_transfer_func *in_transfer_func;
 318
 319         enum dc_color_space color_space;
 320         enum surface_pixel_format format;
 321         enum dc_rotation_angle rotation;
 322         enum plane_stereo_format stereo_format;
 323
 324         bool per_pixel_alpha;
 325         bool visible;
 326         bool flip_immediate;
 327         bool horizontal_mirror;
 328 };
 329
 330 struct dc_plane_info {
 331         union plane_size plane_size;
 332         union dc_tiling_info tiling_info;
 333         struct dc_plane_dcc_param dcc;
 334         enum surface_pixel_format format;
 335         enum dc_rotation_angle rotation;
 336         enum plane_stereo_format stereo_format;
 337         enum dc_color_space color_space; /*todo: wrong place, fits in scaling info*/
 338         bool horizontal_mirror;
 339         bool visible;
 340         bool per_pixel_alpha;
 341 };
 342
 343 struct dc_scaling_info {
 344         struct rect src_rect;
 345         struct rect dst_rect;
 346         struct rect clip_rect;
 347         struct scaling_taps scaling_quality;
 348 };
 349
 350 struct dc_surface_update {
 351         const struct dc_surface *surface;
 352
 353         /* isr safe update parameters.  null means no updates */
 354         struct dc_flip_addrs *flip_addr;
 355         struct dc_plane_info *plane_info;
 356         struct dc_scaling_info *scaling_info;
 357         /* following updates require alloc/sleep/spin that is not isr safe,
 358          * null means no updates
 359          */
 360         /* gamma TO BE REMOVED */
 361         struct dc_gamma *gamma;
 362         struct dc_transfer_func *in_transfer_func;
 363         struct dc_hdr_static_metadata *hdr_static_metadata;
 364 };
 365 /*
 366  * This structure is filled in by dc_surface_get_status and contains
 367  * the last requested address and the currently active address so the called
 368  * can determine if there are any outstanding flips
 369  */
 370 struct dc_surface_status {
 371         struct dc_plane_address requested_address;
 372         struct dc_plane_address current_address;
 373         bool is_flip_pending;
 374         bool is_right_eye;
 375 };
 376
 377 /*
 378  * Create a new surface with default parameters;
 379  */
 380 struct dc_surface *dc_create_surface(const struct dc *dc);
 381 const struct dc_surface_status *dc_surface_get_status(
 382                 const struct dc_surface *dc_surface);
 383
 384 void dc_surface_retain(const struct dc_surface *dc_surface);
 385 void dc_surface_release(const struct dc_surface *dc_surface);
 386
 387 void dc_gamma_retain(const struct dc_gamma *dc_gamma);
 388 void dc_gamma_release(const struct dc_gamma **dc_gamma);
 389 struct dc_gamma *dc_create_gamma(void);
 390
 391 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
 392 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
 393 struct dc_transfer_func *dc_create_transfer_func(void);
 394
 395 /*
 396  * This structure holds a surface address.  There could be multiple addresses
 397  * in cases such as Stereo 3D, Planar YUV, etc.  Other per-flip attributes such
 398  * as frame durations and DCC format can also be set.
 399  */
 400 struct dc_flip_addrs {
 401         struct dc_plane_address address;
 402         bool flip_immediate;
 403         /* TODO: add flip duration for FreeSync */
 404 };
 405
 406 /*
 407  * Set up surface attributes and associate to a stream
 408  * The surfaces parameter is an absolute set of all surface active for the stream.
 409  * If no surfaces are provided, the stream will be blanked; no memory read.
 410  * Any flip related attribute changes must be done through this interface.
 411  *
 412  * After this call:
 413  *   Surfaces attributes are programmed and configured to be composed into stream.
 414  *   This does not trigger a flip.  No surface address is programmed.
 415  */
 416
 417 bool dc_commit_surfaces_to_stream(
 418                 struct dc *dc,
 419                 const struct dc_surface **dc_surfaces,
 420                 uint8_t surface_count,
 421                 const struct dc_stream *stream);
 422
 423 bool dc_post_update_surfaces_to_stream(
 424                 struct dc *dc);
 425
 426 /* Surface update type is used by dc_update_surfaces_and_stream
 427  * The update type is determined at the very beginning of the function based
 428  * on parameters passed in and decides how much programming (or updating) is
 429  * going to be done during the call.
 430  *
 431  * UPDATE_TYPE_FAST is used for really fast updates that do not require much
 432  * logical calculations or hardware register programming. This update MUST be
 433  * ISR safe on windows. Currently fast update will only be used to flip surface
 434  * address.
 435  *
 436  * UPDATE_TYPE_MED is used for slower updates which require significant hw
 437  * re-programming however do not affect bandwidth consumption or clock
 438  * requirements. At present, this is the level at which front end updates
 439  * that do not require us to run bw_calcs happen. These are in/out transfer func
 440  * updates, viewport offset changes, recout size changes and pixel depth changes.
 441  * This update can be done at ISR, but we want to minimize how often this happens.
 442  *
 443  * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
 444  * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
 445  * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
 446  * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
 447  * a full update. This cannot be done at ISR level and should be a rare event.
 448  * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
 449  * underscan we don't expect to see this call at all.
 450  */
 451
 452 enum surface_update_type {
 453         UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
 454         UPDATE_TYPE_MED,  /* ISR safe, most of programming needed, no bw/clk change*/
 455         UPDATE_TYPE_FULL, /* may need to shuffle resources */
 456 };
 457
 458 /*******************************************************************************
 459  * Stream Interfaces
 460  ******************************************************************************/
 461 struct dc_stream {
 462         const struct dc_sink *sink;
 463         struct dc_crtc_timing timing;
 464
 465         struct rect src; /* composition area */
 466         struct rect dst; /* stream addressable area */
 467
 468         struct audio_info audio_info;
 469
 470         struct freesync_context freesync_ctx;
 471
 472         struct dc_transfer_func *out_transfer_func;
 473         struct colorspace_transform gamut_remap_matrix;
 474         struct csc_transform csc_color_matrix;
 475
 476         enum signal_type output_signal;
 477
 478         enum dc_color_space output_color_space;
 479         enum dc_dither_option dither_option;
 480
 481         enum view_3d_format view_format;
 482
 483         bool ignore_msa_timing_param;
 484         /* TODO: custom INFO packets */
 485         /* TODO: ABM info (DMCU) */
 486         /* TODO: PSR info */
 487         /* TODO: CEA VIC */
 488 };
 489
 490 struct dc_stream_update {
 491         struct rect src;
 492         struct rect dst;
 493         struct dc_transfer_func *out_transfer_func;
 494 };
 495
 496
 497 /*
 498  * Setup stream attributes if no stream updates are provided
 499  * there will be no impact on the stream parameters
 500  *
 501  * Set up surface attributes and associate to a stream
 502  * The surfaces parameter is an absolute set of all surface active for the stream.
 503  * If no surfaces are provided, the stream will be blanked; no memory read.
 504  * Any flip related attribute changes must be done through this interface.
 505  *
 506  * After this call:
 507  *   Surfaces attributes are programmed and configured to be composed into stream.
 508  *   This does not trigger a flip.  No surface address is programmed.
 509  *
 510  */
 511
 512 void dc_update_surfaces_and_stream(struct dc *dc,
 513                 struct dc_surface_update *surface_updates, int surface_count,
 514                 const struct dc_stream *dc_stream,
 515                 struct dc_stream_update *stream_update);
 516
 517 /*
 518  * Log the current stream state.
 519  */
 520 void dc_stream_log(
 521         const struct dc_stream *stream,
 522         struct dal_logger *dc_logger,
 523         enum dc_log_type log_type);
 524
 525 uint8_t dc_get_current_stream_count(const struct dc *dc);
 526 struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i);
 527
 528 /*
 529  * Return the current frame counter.
 530  */
 531 uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream);
 532
 533 /* TODO: Return parsed values rather than direct register read
 534  * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos)
 535  * being refactored properly to be dce-specific
 536  */
 537 bool dc_stream_get_scanoutpos(const struct dc_stream *stream,
 538                                   uint32_t *v_blank_start,
 539                                   uint32_t *v_blank_end,
 540                                   uint32_t *h_position,
 541                                   uint32_t *v_position);
 542
 543 /*
 544  * Structure to store surface/stream associations for validation
 545  */
 546 struct dc_validation_set {
 547         const struct dc_stream *stream;
 548         const struct dc_surface *surfaces[MAX_SURFACES];
 549         uint8_t surface_count;
 550 };
 551
 552 /*
 553  * This function takes a set of resources and checks that they are cofunctional.
 554  *
 555  * After this call:
 556  *   No hardware is programmed for call.  Only validation is done.
 557  */
 558 struct validate_context *dc_get_validate_context(
 559                 const struct dc *dc,
 560                 const struct dc_validation_set set[],
 561                 uint8_t set_count);
 562
 563 bool dc_validate_resources(
 564                 const struct dc *dc,
 565                 const struct dc_validation_set set[],
 566                 uint8_t set_count);
 567
 568 /*
 569  * This function takes a stream and checks if it is guaranteed to be supported.
 570  * Guaranteed means that MAX_COFUNC similar streams are supported.
 571  *
 572  * After this call:
 573  *   No hardware is programmed for call.  Only validation is done.
 574  */
 575
 576 bool dc_validate_guaranteed(
 577                 const struct dc *dc,
 578                 const struct dc_stream *stream);
 579
 580 void dc_resource_validate_ctx_copy_construct(
 581                 const struct validate_context *src_ctx,
 582                 struct validate_context *dst_ctx);
 583
 584 void dc_resource_validate_ctx_destruct(struct validate_context *context);
 585
 586 /*
 587  * TODO update to make it about validation sets
 588  * Set up streams and links associated to drive sinks
 589  * The streams parameter is an absolute set of all active streams.
 590  *
 591  * After this call:
 592  *   Phy, Encoder, Timing Generator are programmed and enabled.
 593  *   New streams are enabled with blank stream; no memory read.
 594  */
 595 bool dc_commit_context(struct dc *dc, struct validate_context *context);
 596
 597 /*
 598  * Set up streams and links associated to drive sinks
 599  * The streams parameter is an absolute set of all active streams.
 600  *
 601  * After this call:
 602  *   Phy, Encoder, Timing Generator are programmed and enabled.
 603  *   New streams are enabled with blank stream; no memory read.
 604  */
 605 bool dc_commit_streams(
 606                 struct dc *dc,
 607                 const struct dc_stream *streams[],
 608                 uint8_t stream_count);
 609 /*
 610  * Enable stereo when commit_streams is not required,
 611  * for example, frame alternate.
 612  */
 613 bool dc_enable_stereo(
 614         struct dc *dc,
 615         struct validate_context *context,
 616         const struct dc_stream *streams[],
 617         uint8_t stream_count);
 618
 619 /**
 620  * Create a new default stream for the requested sink
 621  */
 622 struct dc_stream *dc_create_stream_for_sink(const struct dc_sink *dc_sink);
 623
 624 void dc_stream_retain(const struct dc_stream *dc_stream);
 625 void dc_stream_release(const struct dc_stream *dc_stream);
 626
 627 struct dc_stream_status {
 628         int primary_otg_inst;
 629         int surface_count;
 630         const struct dc_surface *surfaces[MAX_SURFACE_NUM];
 631
 632         /*
 633          * link this stream passes through
 634          */
 635         const struct dc_link *link;
 636 };
 637
 638 const struct dc_stream_status *dc_stream_get_status(
 639         const struct dc_stream *dc_stream);
 640
 641 enum surface_update_type dc_check_update_surfaces_for_stream(
 642                 struct dc *dc,
 643                 struct dc_surface_update *updates,
 644                 int surface_count,
 645                 struct dc_stream_update *stream_update,
 646                 const struct dc_stream_status *stream_status);
 647
 648
 649 void dc_retain_validate_context(struct validate_context *context);
 650 void dc_release_validate_context(struct validate_context *context);
 651
 652 /*******************************************************************************
 653  * Link Interfaces
 654  ******************************************************************************/
 655
 656 /*
 657  * A link contains one or more sinks and their connected status.
 658  * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
 659  */
 660 struct dc_link {
 661         const struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
 662         unsigned int sink_count;
 663         const struct dc_sink *local_sink;
 664         unsigned int link_index;
 665         enum dc_connection_type type;
 666         enum signal_type connector_signal;
 667         enum dc_irq_source irq_source_hpd;
 668         enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse  */
 669         /* caps is the same as reported_link_cap. link_traing use
 670          * reported_link_cap. Will clean up.  TODO
 671          */
 672         struct dc_link_settings reported_link_cap;
 673         struct dc_link_settings verified_link_cap;
 674         struct dc_link_settings max_link_setting;
 675         struct dc_link_settings cur_link_settings;
 676         struct dc_lane_settings cur_lane_setting;
 677         struct dc_link_settings preferred_link_setting;
 678
 679         uint8_t ddc_hw_inst;
 680
 681         uint8_t hpd_src;
 682
 683         uint8_t link_enc_hw_inst;
 684
 685         bool test_pattern_enabled;
 686         union compliance_test_state compliance_test_state;
 687
 688         void *priv;
 689
 690         struct ddc_service *ddc;
 691
 692         bool aux_mode;
 693 };
 694
 695 struct dpcd_caps {
 696         union dpcd_rev dpcd_rev;
 697         union max_lane_count max_ln_count;
 698         union max_down_spread max_down_spread;
 699
 700         /* dongle type (DP converter, CV smart dongle) */
 701         enum display_dongle_type dongle_type;
 702         /* Dongle's downstream count. */
 703         union sink_count sink_count;
 704         /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
 705         indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
 706         struct dc_dongle_caps dongle_caps;
 707
 708         uint32_t sink_dev_id;
 709         uint32_t branch_dev_id;
 710         int8_t branch_dev_name[6];
 711         int8_t branch_hw_revision;
 712
 713         bool allow_invalid_MSA_timing_param;
 714         bool panel_mode_edp;
 715 };
 716
 717 struct dc_link_status {
 718         struct dpcd_caps *dpcd_caps;
 719 };
 720
 721 const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
 722
 723 /*
 724  * Return an enumerated dc_link.  dc_link order is constant and determined at
 725  * boot time.  They cannot be created or destroyed.
 726  * Use dc_get_caps() to get number of links.
 727  */
 728 const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index);
 729
 730 /* Return id of physical connector represented by a dc_link at link_index.*/
 731 const struct graphics_object_id dc_get_link_id_at_index(
 732                 struct dc *dc, uint32_t link_index);
 733
 734 /* Set backlight level of an embedded panel (eDP, LVDS). */
 735 bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level,
 736                 uint32_t frame_ramp, const struct dc_stream *stream);
 737
 738 bool dc_link_set_abm_disable(const struct dc_link *dc_link);
 739
 740 bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable);
 741
 742 bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state);
 743
 744 bool dc_link_setup_psr(const struct dc_link *dc_link,
 745                 const struct dc_stream *stream, struct psr_config *psr_config,
 746                 struct psr_context *psr_context);
 747
 748 /* Request DC to detect if there is a Panel connected.
 749  * boot - If this call is during initial boot.
 750  * Return false for any type of detection failure or MST detection
 751  * true otherwise. True meaning further action is required (status update
 752  * and OS notification).
 753  */
 754 bool dc_link_detect(const struct dc_link *dc_link, bool boot);
 755
 756 /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
 757  * Return:
 758  * true - Downstream port status changed. DM should call DC to do the
 759  * detection.
 760  * false - no change in Downstream port status. No further action required
 761  * from DM. */
 762 bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link,
 763                 union hpd_irq_data *hpd_irq_dpcd_data);
 764
 765 struct dc_sink_init_data;
 766
 767 struct dc_sink *dc_link_add_remote_sink(
 768                 const struct dc_link *dc_link,
 769                 const uint8_t *edid,
 770                 int len,
 771                 struct dc_sink_init_data *init_data);
 772
 773 void dc_link_remove_remote_sink(
 774         const struct dc_link *link,
 775         const struct dc_sink *sink);
 776
 777 /* Used by diagnostics for virtual link at the moment */
 778 void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink);
 779
 780 void dc_link_dp_set_drive_settings(
 781         const struct dc_link *link,
 782         struct link_training_settings *lt_settings);
 783
 784 enum link_training_result dc_link_dp_perform_link_training(
 785         struct dc_link *link,
 786         const struct dc_link_settings *link_setting,
 787         bool skip_video_pattern);
 788
 789 void dc_link_dp_enable_hpd(const struct dc_link *link);
 790
 791 void dc_link_dp_disable_hpd(const struct dc_link *link);
 792
 793 bool dc_link_dp_set_test_pattern(
 794         const struct dc_link *link,
 795         enum dp_test_pattern test_pattern,
 796         const struct link_training_settings *p_link_settings,
 797         const unsigned char *p_custom_pattern,
 798         unsigned int cust_pattern_size);
 799
 800 /*******************************************************************************
 801  * Sink Interfaces - A sink corresponds to a display output device
 802  ******************************************************************************/
 803
 804 struct dc_container_id {
 805         // 128bit GUID in binary form
 806         unsigned char  guid[16];
 807         // 8 byte port ID -> ELD.PortID
 808         unsigned int   portId[2];
 809         // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
 810         unsigned short manufacturerName;
 811         // 2 byte product code -> ELD.ProductCode
 812         unsigned short productCode;
 813 };
 814
 815
 816
 817 /*
 818  * The sink structure contains EDID and other display device properties
 819  */
 820 struct dc_sink {
 821         enum signal_type sink_signal;
 822         struct dc_edid dc_edid; /* raw edid */
 823         struct dc_edid_caps edid_caps; /* parse display caps */
 824         struct dc_container_id *dc_container_id;
 825         uint32_t dongle_max_pix_clk;
 826         void *priv;
 827         struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
 828         bool converter_disable_audio;
 829 };
 830
 831 void dc_sink_retain(const struct dc_sink *sink);
 832 void dc_sink_release(const struct dc_sink *sink);
 833
 834 const struct audio **dc_get_audios(struct dc *dc);
 835
 836 struct dc_sink_init_data {
 837         enum signal_type sink_signal;
 838         const struct dc_link *link;
 839         uint32_t dongle_max_pix_clk;
 840         bool converter_disable_audio;
 841 };
 842
 843 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
 844 bool dc_sink_get_container_id(struct dc_sink *dc_sink, struct dc_container_id *container_id);
 845 bool dc_sink_set_container_id(struct dc_sink *dc_sink, const struct dc_container_id *container_id);
 846
 847 /*******************************************************************************
 848  * Cursor interfaces - To manages the cursor within a stream
 849  ******************************************************************************/
 850 /* TODO: Deprecated once we switch to dc_set_cursor_position */
 851 bool dc_stream_set_cursor_attributes(
 852         const struct dc_stream *stream,
 853         const struct dc_cursor_attributes *attributes);
 854
 855 bool dc_stream_set_cursor_position(
 856         const struct dc_stream *stream,
 857         const struct dc_cursor_position *position);
 858
 859 /* Newer interfaces  */
 860 struct dc_cursor {
 861         struct dc_plane_address address;
 862         struct dc_cursor_attributes attributes;
 863 };
 864
 865 /*******************************************************************************
 866  * Interrupt interfaces
 867  ******************************************************************************/
 868 enum dc_irq_source dc_interrupt_to_irq_source(
 869                 struct dc *dc,
 870                 uint32_t src_id,
 871                 uint32_t ext_id);
 872 void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable);
 873 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
 874 enum dc_irq_source dc_get_hpd_irq_source_at_index(
 875                 struct dc *dc, uint32_t link_index);
 876
 877 /*******************************************************************************
 878  * Power Interfaces
 879  ******************************************************************************/
 880
 881 void dc_set_power_state(
 882                 struct dc *dc,
 883                 enum dc_acpi_cm_power_state power_state);
 884 void dc_resume(const struct dc *dc);
 885
 886 /*
 887  * DPCD access interfaces
 888  */
 889
 890 bool dc_read_aux_dpcd(
 891                 struct dc *dc,
 892                 uint32_t link_index,
 893                 uint32_t address,
 894                 uint8_t *data,
 895                 uint32_t size);
 896
 897 bool dc_write_aux_dpcd(
 898                 struct dc *dc,
 899                 uint32_t link_index,
 900                 uint32_t address,
 901                 const uint8_t *data,
 902                 uint32_t size);
 903
 904 bool dc_read_aux_i2c(
 905                 struct dc *dc,
 906                 uint32_t link_index,
 907                 enum i2c_mot_mode mot,
 908                 uint32_t address,
 909                 uint8_t *data,
 910                 uint32_t size);
 911
 912 bool dc_write_aux_i2c(
 913                 struct dc *dc,
 914                 uint32_t link_index,
 915                 enum i2c_mot_mode mot,
 916                 uint32_t address,
 917                 const uint8_t *data,
 918                 uint32_t size);
 919
 920 bool dc_query_ddc_data(
 921                 struct dc *dc,
 922                 uint32_t link_index,
 923                 uint32_t address,
 924                 uint8_t *write_buf,
 925                 uint32_t write_size,
 926                 uint8_t *read_buf,
 927                 uint32_t read_size);
 928
 929 bool dc_submit_i2c(
 930                 struct dc *dc,
 931                 uint32_t link_index,
 932                 struct i2c_command *cmd);
 933
 934
 935 #endif /* DC_INTERFACE_H_ */