drivers/gpu/drm/amd/display/dc/dc.h

   1 /*
   2  * Copyright 2012-14 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef DC_INTERFACE_H_
  27 #define DC_INTERFACE_H_
  28
  29 #include "dc_types.h"
  30 #include "grph_object_defs.h"
  31 #include "logger_types.h"
  32 #include "gpio_types.h"
  33 #include "link_service_types.h"
  34 #include "grph_object_ctrl_defs.h"
  35
  36 #define MAX_SURFACES 3
  37 #define MAX_STREAMS 6
  38 #define MAX_SINKS_PER_LINK 4
  39
  40 /*******************************************************************************
  41  * Display Core Interfaces
  42  ******************************************************************************/
  43
  44 struct dc_caps {
  45         uint32_t max_streams;
  46         uint32_t max_links;
  47         uint32_t max_audios;
  48         uint32_t max_slave_planes;
  49         uint32_t max_surfaces;
  50         uint32_t max_downscale_ratio;
  51         uint32_t i2c_speed_in_khz;
  52
  53         unsigned int max_cursor_size;
  54 };
  55
  56
  57 struct dc_dcc_surface_param {
  58         struct dc_size surface_size;
  59         enum surface_pixel_format format;
  60         enum swizzle_mode_values swizzle_mode;
  61         enum dc_scan_direction scan;
  62 };
  63
  64 struct dc_dcc_setting {
  65         unsigned int max_compressed_blk_size;
  66         unsigned int max_uncompressed_blk_size;
  67         bool independent_64b_blks;
  68 };
  69
  70 struct dc_surface_dcc_cap {
  71         union {
  72                 struct {
  73                         struct dc_dcc_setting rgb;
  74                 } grph;
  75
  76                 struct {
  77                         struct dc_dcc_setting luma;
  78                         struct dc_dcc_setting chroma;
  79                 } video;
  80         };
  81
  82         bool capable;
  83         bool const_color_support;
  84 };
  85
  86 struct dc_static_screen_events {
  87         bool cursor_update;
  88         bool surface_update;
  89         bool overlay_update;
  90 };
  91
  92 /* Forward declaration*/
  93 struct dc;
  94 struct dc_surface;
  95 struct validate_context;
  96
  97 struct dc_cap_funcs {
  98 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  99         bool (*get_dcc_compression_cap)(const struct dc *dc,
 100                         const struct dc_dcc_surface_param *input,
 101                         struct dc_surface_dcc_cap *output);
 102 #else
 103         int i;
 104 #endif
 105 };
 106
 107 struct dc_stream_funcs {
 108         bool (*adjust_vmin_vmax)(struct dc *dc,
 109                         const struct dc_stream **stream,
 110                         int num_streams,
 111                         int vmin,
 112                         int vmax);
 113         bool (*get_crtc_position)(struct dc *dc,
 114                         const struct dc_stream **stream,
 115                         int num_streams,
 116                         unsigned int *v_pos,
 117                         unsigned int *nom_v_pos);
 118
 119         bool (*set_gamut_remap)(struct dc *dc,
 120                         const struct dc_stream *stream);
 121
 122         bool (*program_csc_matrix)(struct dc *dc,
 123                         const struct dc_stream *stream);
 124
 125         void (*set_static_screen_events)(struct dc *dc,
 126                         const struct dc_stream **stream,
 127                         int num_streams,
 128                         const struct dc_static_screen_events *events);
 129
 130         void (*set_dither_option)(const struct dc_stream *stream,
 131                         enum dc_dither_option option);
 132 };
 133
 134 struct link_training_settings;
 135
 136 struct dc_link_funcs {
 137         void (*set_drive_settings)(struct dc *dc,
 138                         struct link_training_settings *lt_settings,
 139                         const struct dc_link *link);
 140         void (*perform_link_training)(struct dc *dc,
 141                         struct dc_link_settings *link_setting,
 142                         bool skip_video_pattern);
 143         void (*set_preferred_link_settings)(struct dc *dc,
 144                         struct dc_link_settings *link_setting,
 145                         struct dc_link *link);
 146         void (*enable_hpd)(const struct dc_link *link);
 147         void (*disable_hpd)(const struct dc_link *link);
 148         void (*set_test_pattern)(
 149                         struct dc_link *link,
 150                         enum dp_test_pattern test_pattern,
 151                         const struct link_training_settings *p_link_settings,
 152                         const unsigned char *p_custom_pattern,
 153                         unsigned int cust_pattern_size);
 154 };
 155
 156 /* Structure to hold configuration flags set by dm at dc creation. */
 157 struct dc_config {
 158         bool gpu_vm_support;
 159         bool disable_disp_pll_sharing;
 160 };
 161
 162 struct dc_debug {
 163         bool surface_visual_confirm;
 164         bool sanity_checks;
 165         bool max_disp_clk;
 166         bool surface_trace;
 167         bool timing_trace;
 168         bool clock_trace;
 169         bool validation_trace;
 170         bool disable_stutter;
 171         bool disable_dcc;
 172         bool disable_dfs_bypass;
 173 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 174         bool disable_dpp_power_gate;
 175         bool disable_hubp_power_gate;
 176         bool disable_pplib_wm_range;
 177         bool use_dml_wm;
 178         bool disable_pipe_split;
 179         int sr_exit_time_dpm0_ns;
 180         int sr_enter_plus_exit_time_dpm0_ns;
 181         int sr_exit_time_ns;
 182         int sr_enter_plus_exit_time_ns;
 183         int urgent_latency_ns;
 184         int percent_of_ideal_drambw;
 185         int dram_clock_change_latency_ns;
 186         int always_scale;
 187 #endif
 188         bool disable_pplib_clock_request;
 189         bool disable_clock_gate;
 190         bool disable_dmcu;
 191         bool disable_psr;
 192         bool force_abm_enable;
 193 };
 194
 195 struct dc {
 196         struct dc_caps caps;
 197         struct dc_cap_funcs cap_funcs;
 198         struct dc_stream_funcs stream_funcs;
 199         struct dc_link_funcs link_funcs;
 200         struct dc_config config;
 201         struct dc_debug debug;
 202 };
 203
 204 enum frame_buffer_mode {
 205         FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
 206         FRAME_BUFFER_MODE_ZFB_ONLY,
 207         FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
 208 } ;
 209
 210 struct dchub_init_data {
 211         int64_t zfb_phys_addr_base;
 212         int64_t zfb_mc_base_addr;
 213         uint64_t zfb_size_in_byte;
 214         enum frame_buffer_mode fb_mode;
 215         bool dchub_initialzied;
 216         bool dchub_info_valid;
 217 };
 218
 219 struct dc_init_data {
 220         struct hw_asic_id asic_id;
 221         void *driver; /* ctx */
 222         struct cgs_device *cgs_device;
 223
 224         int num_virtual_links;
 225         /*
 226          * If 'vbios_override' not NULL, it will be called instead
 227          * of the real VBIOS. Intended use is Diagnostics on FPGA.
 228          */
 229         struct dc_bios *vbios_override;
 230         enum dce_environment dce_environment;
 231
 232         struct dc_config flags;
 233 };
 234
 235 struct dc *dc_create(const struct dc_init_data *init_params);
 236
 237 void dc_destroy(struct dc **dc);
 238
 239 bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data);
 240
 241 void dc_log_hw_state(struct dc *dc);
 242
 243 /*******************************************************************************
 244  * Surface Interfaces
 245  ******************************************************************************/
 246
 247 enum {
 248         TRANSFER_FUNC_POINTS = 1025
 249 };
 250
 251 struct dc_hdr_static_metadata {
 252         /* display chromaticities and white point in units of 0.00001 */
 253         unsigned int chromaticity_green_x;
 254         unsigned int chromaticity_green_y;
 255         unsigned int chromaticity_blue_x;
 256         unsigned int chromaticity_blue_y;
 257         unsigned int chromaticity_red_x;
 258         unsigned int chromaticity_red_y;
 259         unsigned int chromaticity_white_point_x;
 260         unsigned int chromaticity_white_point_y;
 261
 262         uint32_t min_luminance;
 263         uint32_t max_luminance;
 264         uint32_t maximum_content_light_level;
 265         uint32_t maximum_frame_average_light_level;
 266
 267         bool hdr_supported;
 268         bool is_hdr;
 269 };
 270
 271 enum dc_transfer_func_type {
 272         TF_TYPE_PREDEFINED,
 273         TF_TYPE_DISTRIBUTED_POINTS,
 274         TF_TYPE_BYPASS
 275 };
 276
 277 struct dc_transfer_func_distributed_points {
 278         struct fixed31_32 red[TRANSFER_FUNC_POINTS];
 279         struct fixed31_32 green[TRANSFER_FUNC_POINTS];
 280         struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
 281
 282         uint16_t end_exponent;
 283         uint16_t x_point_at_y1_red;
 284         uint16_t x_point_at_y1_green;
 285         uint16_t x_point_at_y1_blue;
 286 };
 287
 288 enum dc_transfer_func_predefined {
 289         TRANSFER_FUNCTION_SRGB,
 290         TRANSFER_FUNCTION_BT709,
 291         TRANSFER_FUNCTION_PQ,
 292         TRANSFER_FUNCTION_LINEAR,
 293 };
 294
 295 struct dc_transfer_func {
 296         struct dc_transfer_func_distributed_points tf_pts;
 297         enum dc_transfer_func_type type;
 298         enum dc_transfer_func_predefined tf;
 299         struct dc_context *ctx;
 300         int ref_count;
 301 };
 302
 303 /*
 304  * This structure is filled in by dc_surface_get_status and contains
 305  * the last requested address and the currently active address so the called
 306  * can determine if there are any outstanding flips
 307  */
 308 struct dc_surface_status {
 309         struct dc_plane_address requested_address;
 310         struct dc_plane_address current_address;
 311         bool is_flip_pending;
 312         bool is_right_eye;
 313 };
 314
 315 struct dc_surface {
 316         struct dc_plane_address address;
 317
 318         struct scaling_taps scaling_quality;
 319         struct rect src_rect;
 320         struct rect dst_rect;
 321         struct rect clip_rect;
 322
 323         union plane_size plane_size;
 324         union dc_tiling_info tiling_info;
 325
 326         struct dc_plane_dcc_param dcc;
 327         struct dc_hdr_static_metadata hdr_static_ctx;
 328
 329         struct dc_gamma *gamma_correction;
 330         struct dc_transfer_func *in_transfer_func;
 331
 332         enum dc_color_space color_space;
 333         enum surface_pixel_format format;
 334         enum dc_rotation_angle rotation;
 335         enum plane_stereo_format stereo_format;
 336
 337         bool per_pixel_alpha;
 338         bool visible;
 339         bool flip_immediate;
 340         bool horizontal_mirror;
 341
 342         /* private to DC core */
 343         struct dc_surface_status status;
 344         struct dc_context *ctx;
 345
 346         /* private to dc_surface.c */
 347         enum dc_irq_source irq_source;
 348         int ref_count;
 349 };
 350
 351 struct dc_plane_info {
 352         union plane_size plane_size;
 353         union dc_tiling_info tiling_info;
 354         struct dc_plane_dcc_param dcc;
 355         enum surface_pixel_format format;
 356         enum dc_rotation_angle rotation;
 357         enum plane_stereo_format stereo_format;
 358         enum dc_color_space color_space; /*todo: wrong place, fits in scaling info*/
 359         bool horizontal_mirror;
 360         bool visible;
 361         bool per_pixel_alpha;
 362 };
 363
 364 struct dc_scaling_info {
 365         struct rect src_rect;
 366         struct rect dst_rect;
 367         struct rect clip_rect;
 368         struct scaling_taps scaling_quality;
 369 };
 370
 371 struct dc_surface_update {
 372         struct dc_surface *surface;
 373
 374         /* isr safe update parameters.  null means no updates */
 375         struct dc_flip_addrs *flip_addr;
 376         struct dc_plane_info *plane_info;
 377         struct dc_scaling_info *scaling_info;
 378         /* following updates require alloc/sleep/spin that is not isr safe,
 379          * null means no updates
 380          */
 381         /* gamma TO BE REMOVED */
 382         struct dc_gamma *gamma;
 383         struct dc_transfer_func *in_transfer_func;
 384         struct dc_hdr_static_metadata *hdr_static_metadata;
 385 };
 386
 387 /*
 388  * Create a new surface with default parameters;
 389  */
 390 struct dc_surface *dc_create_surface(const struct dc *dc);
 391 const struct dc_surface_status *dc_surface_get_status(
 392                 const struct dc_surface *dc_surface);
 393
 394 void dc_surface_retain(struct dc_surface *dc_surface);
 395 void dc_surface_release(struct dc_surface *dc_surface);
 396
 397 void dc_gamma_retain(struct dc_gamma *dc_gamma);
 398 void dc_gamma_release(struct dc_gamma **dc_gamma);
 399 struct dc_gamma *dc_create_gamma(void);
 400
 401 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
 402 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
 403 struct dc_transfer_func *dc_create_transfer_func(void);
 404
 405 /*
 406  * This structure holds a surface address.  There could be multiple addresses
 407  * in cases such as Stereo 3D, Planar YUV, etc.  Other per-flip attributes such
 408  * as frame durations and DCC format can also be set.
 409  */
 410 struct dc_flip_addrs {
 411         struct dc_plane_address address;
 412         bool flip_immediate;
 413         /* TODO: add flip duration for FreeSync */
 414 };
 415
 416 /*
 417  * Set up surface attributes and associate to a stream
 418  * The surfaces parameter is an absolute set of all surface active for the stream.
 419  * If no surfaces are provided, the stream will be blanked; no memory read.
 420  * Any flip related attribute changes must be done through this interface.
 421  *
 422  * After this call:
 423  *   Surfaces attributes are programmed and configured to be composed into stream.
 424  *   This does not trigger a flip.  No surface address is programmed.
 425  */
 426
 427 bool dc_commit_surfaces_to_stream(
 428                 struct dc *dc,
 429                 struct dc_surface **dc_surfaces,
 430                 uint8_t surface_count,
 431                 const struct dc_stream *stream);
 432
 433 bool dc_post_update_surfaces_to_stream(
 434                 struct dc *dc);
 435
 436 /* Surface update type is used by dc_update_surfaces_and_stream
 437  * The update type is determined at the very beginning of the function based
 438  * on parameters passed in and decides how much programming (or updating) is
 439  * going to be done during the call.
 440  *
 441  * UPDATE_TYPE_FAST is used for really fast updates that do not require much
 442  * logical calculations or hardware register programming. This update MUST be
 443  * ISR safe on windows. Currently fast update will only be used to flip surface
 444  * address.
 445  *
 446  * UPDATE_TYPE_MED is used for slower updates which require significant hw
 447  * re-programming however do not affect bandwidth consumption or clock
 448  * requirements. At present, this is the level at which front end updates
 449  * that do not require us to run bw_calcs happen. These are in/out transfer func
 450  * updates, viewport offset changes, recout size changes and pixel depth changes.
 451  * This update can be done at ISR, but we want to minimize how often this happens.
 452  *
 453  * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
 454  * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
 455  * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
 456  * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
 457  * a full update. This cannot be done at ISR level and should be a rare event.
 458  * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
 459  * underscan we don't expect to see this call at all.
 460  */
 461
 462 enum surface_update_type {
 463         UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
 464         UPDATE_TYPE_MED,  /* ISR safe, most of programming needed, no bw/clk change*/
 465         UPDATE_TYPE_FULL, /* may need to shuffle resources */
 466 };
 467
 468 /*******************************************************************************
 469  * Stream Interfaces
 470  ******************************************************************************/
 471 struct dc_stream {
 472         const struct dc_sink *sink;
 473         struct dc_crtc_timing timing;
 474
 475         struct rect src; /* composition area */
 476         struct rect dst; /* stream addressable area */
 477
 478         struct audio_info audio_info;
 479
 480         struct freesync_context freesync_ctx;
 481
 482         struct dc_transfer_func *out_transfer_func;
 483         struct colorspace_transform gamut_remap_matrix;
 484         struct csc_transform csc_color_matrix;
 485
 486         enum signal_type output_signal;
 487
 488         enum dc_color_space output_color_space;
 489         enum dc_dither_option dither_option;
 490
 491         enum view_3d_format view_format;
 492
 493         bool ignore_msa_timing_param;
 494         /* TODO: custom INFO packets */
 495         /* TODO: ABM info (DMCU) */
 496         /* TODO: PSR info */
 497         /* TODO: CEA VIC */
 498 };
 499
 500 struct dc_stream_update {
 501         struct rect src;
 502         struct rect dst;
 503         struct dc_transfer_func *out_transfer_func;
 504 };
 505
 506
 507 /*
 508  * Setup stream attributes if no stream updates are provided
 509  * there will be no impact on the stream parameters
 510  *
 511  * Set up surface attributes and associate to a stream
 512  * The surfaces parameter is an absolute set of all surface active for the stream.
 513  * If no surfaces are provided, the stream will be blanked; no memory read.
 514  * Any flip related attribute changes must be done through this interface.
 515  *
 516  * After this call:
 517  *   Surfaces attributes are programmed and configured to be composed into stream.
 518  *   This does not trigger a flip.  No surface address is programmed.
 519  *
 520  */
 521
 522 void dc_update_surfaces_and_stream(struct dc *dc,
 523                 struct dc_surface_update *surface_updates, int surface_count,
 524                 const struct dc_stream *dc_stream,
 525                 struct dc_stream_update *stream_update);
 526
 527 /*
 528  * Log the current stream state.
 529  */
 530 void dc_stream_log(
 531         const struct dc_stream *stream,
 532         struct dal_logger *dc_logger,
 533         enum dc_log_type log_type);
 534
 535 uint8_t dc_get_current_stream_count(const struct dc *dc);
 536 struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i);
 537
 538 /*
 539  * Return the current frame counter.
 540  */
 541 uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream);
 542
 543 /* TODO: Return parsed values rather than direct register read
 544  * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos)
 545  * being refactored properly to be dce-specific
 546  */
 547 bool dc_stream_get_scanoutpos(const struct dc_stream *stream,
 548                                   uint32_t *v_blank_start,
 549                                   uint32_t *v_blank_end,
 550                                   uint32_t *h_position,
 551                                   uint32_t *v_position);
 552
 553 /*
 554  * Structure to store surface/stream associations for validation
 555  */
 556 struct dc_validation_set {
 557         const struct dc_stream *stream;
 558         struct dc_surface *surfaces[MAX_SURFACES];
 559         uint8_t surface_count;
 560 };
 561
 562 bool dc_validate_stream(const struct dc *dc, const struct dc_stream *stream);
 563
 564 /*
 565  * This function takes a set of resources and checks that they are cofunctional.
 566  *
 567  * After this call:
 568  *   No hardware is programmed for call.  Only validation is done.
 569  */
 570 struct validate_context *dc_get_validate_context(
 571                 const struct dc *dc,
 572                 const struct dc_validation_set set[],
 573                 uint8_t set_count);
 574
 575 bool dc_validate_resources(
 576                 const struct dc *dc,
 577                 const struct dc_validation_set set[],
 578                 uint8_t set_count);
 579
 580 /*
 581  * This function takes a stream and checks if it is guaranteed to be supported.
 582  * Guaranteed means that MAX_COFUNC similar streams are supported.
 583  *
 584  * After this call:
 585  *   No hardware is programmed for call.  Only validation is done.
 586  */
 587
 588 bool dc_validate_guaranteed(
 589                 const struct dc *dc,
 590                 const struct dc_stream *stream);
 591
 592 void dc_resource_validate_ctx_copy_construct(
 593                 const struct validate_context *src_ctx,
 594                 struct validate_context *dst_ctx);
 595
 596 void dc_resource_validate_ctx_destruct(struct validate_context *context);
 597
 598 /*
 599  * TODO update to make it about validation sets
 600  * Set up streams and links associated to drive sinks
 601  * The streams parameter is an absolute set of all active streams.
 602  *
 603  * After this call:
 604  *   Phy, Encoder, Timing Generator are programmed and enabled.
 605  *   New streams are enabled with blank stream; no memory read.
 606  */
 607 bool dc_commit_context(struct dc *dc, struct validate_context *context);
 608
 609 /*
 610  * Set up streams and links associated to drive sinks
 611  * The streams parameter is an absolute set of all active streams.
 612  *
 613  * After this call:
 614  *   Phy, Encoder, Timing Generator are programmed and enabled.
 615  *   New streams are enabled with blank stream; no memory read.
 616  */
 617 bool dc_commit_streams(
 618                 struct dc *dc,
 619                 const struct dc_stream *streams[],
 620                 uint8_t stream_count);
 621 /*
 622  * Enable stereo when commit_streams is not required,
 623  * for example, frame alternate.
 624  */
 625 bool dc_enable_stereo(
 626         struct dc *dc,
 627         struct validate_context *context,
 628         const struct dc_stream *streams[],
 629         uint8_t stream_count);
 630
 631 /**
 632  * Create a new default stream for the requested sink
 633  */
 634 struct dc_stream *dc_create_stream_for_sink(struct dc_sink *dc_sink);
 635
 636 void dc_stream_retain(const struct dc_stream *dc_stream);
 637 void dc_stream_release(const struct dc_stream *dc_stream);
 638
 639 struct dc_stream_status {
 640         int primary_otg_inst;
 641         int surface_count;
 642         struct dc_surface *surfaces[MAX_SURFACE_NUM];
 643
 644         /*
 645          * link this stream passes through
 646          */
 647         struct dc_link *link;
 648 };
 649
 650 struct dc_stream_status *dc_stream_get_status(
 651         const struct dc_stream *dc_stream);
 652
 653 enum surface_update_type dc_check_update_surfaces_for_stream(
 654                 struct dc *dc,
 655                 struct dc_surface_update *updates,
 656                 int surface_count,
 657                 struct dc_stream_update *stream_update,
 658                 const struct dc_stream_status *stream_status);
 659
 660
 661 void dc_retain_validate_context(struct validate_context *context);
 662 void dc_release_validate_context(struct validate_context *context);
 663
 664 /*******************************************************************************
 665  * Link Interfaces
 666  ******************************************************************************/
 667
 668 struct dpcd_caps {
 669         union dpcd_rev dpcd_rev;
 670         union max_lane_count max_ln_count;
 671         union max_down_spread max_down_spread;
 672
 673         /* dongle type (DP converter, CV smart dongle) */
 674         enum display_dongle_type dongle_type;
 675         /* Dongle's downstream count. */
 676         union sink_count sink_count;
 677         /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
 678         indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
 679         struct dc_dongle_caps dongle_caps;
 680
 681         uint32_t sink_dev_id;
 682         uint32_t branch_dev_id;
 683         int8_t branch_dev_name[6];
 684         int8_t branch_hw_revision;
 685
 686         bool allow_invalid_MSA_timing_param;
 687         bool panel_mode_edp;
 688 };
 689
 690 struct dc_link_status {
 691         struct dpcd_caps *dpcd_caps;
 692 };
 693
 694 /* DP MST stream allocation (payload bandwidth number) */
 695 struct link_mst_stream_allocation {
 696         /* DIG front */
 697         const struct stream_encoder *stream_enc;
 698         /* associate DRM payload table with DC stream encoder */
 699         uint8_t vcp_id;
 700         /* number of slots required for the DP stream in transport packet */
 701         uint8_t slot_count;
 702 };
 703
 704 /* DP MST stream allocation table */
 705 struct link_mst_stream_allocation_table {
 706         /* number of DP video streams */
 707         int stream_count;
 708         /* array of stream allocations */
 709         struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
 710 };
 711
 712 /*
 713  * A link contains one or more sinks and their connected status.
 714  * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
 715  */
 716 struct dc_link {
 717         struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
 718         unsigned int sink_count;
 719         struct dc_sink *local_sink;
 720         unsigned int link_index;
 721         enum dc_connection_type type;
 722         enum signal_type connector_signal;
 723         enum dc_irq_source irq_source_hpd;
 724         enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse  */
 725         /* caps is the same as reported_link_cap. link_traing use
 726          * reported_link_cap. Will clean up.  TODO
 727          */
 728         struct dc_link_settings reported_link_cap;
 729         struct dc_link_settings verified_link_cap;
 730         struct dc_link_settings max_link_setting;
 731         struct dc_link_settings cur_link_settings;
 732         struct dc_lane_settings cur_lane_setting;
 733         struct dc_link_settings preferred_link_setting;
 734
 735         uint8_t ddc_hw_inst;
 736
 737         uint8_t hpd_src;
 738
 739         uint8_t link_enc_hw_inst;
 740
 741         bool test_pattern_enabled;
 742         union compliance_test_state compliance_test_state;
 743
 744         void *priv;
 745
 746         struct ddc_service *ddc;
 747
 748         bool aux_mode;
 749
 750         /* Private to DC core */
 751
 752         const struct core_dc *dc;
 753
 754         struct dc_context *ctx;
 755
 756         struct link_encoder *link_enc;
 757         struct graphics_object_id link_id;
 758         union ddi_channel_mapping ddi_channel_mapping;
 759         struct connector_device_tag_info device_tag;
 760         struct dpcd_caps dpcd_caps;
 761         unsigned int dpcd_sink_count;
 762
 763         enum edp_revision edp_revision;
 764         bool psr_enabled;
 765
 766         /* MST record stream using this link */
 767         struct link_flags {
 768                 bool dp_keep_receiver_powered;
 769         } wa_flags;
 770         struct link_mst_stream_allocation_table mst_stream_alloc_table;
 771
 772         struct dc_link_status link_status;
 773
 774 };
 775
 776 const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
 777
 778 /*
 779  * Return an enumerated dc_link.  dc_link order is constant and determined at
 780  * boot time.  They cannot be created or destroyed.
 781  * Use dc_get_caps() to get number of links.
 782  */
 783 struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index);
 784
 785 /* Return id of physical connector represented by a dc_link at link_index.*/
 786 const struct graphics_object_id dc_get_link_id_at_index(
 787                 struct dc *dc, uint32_t link_index);
 788
 789 /* Set backlight level of an embedded panel (eDP, LVDS). */
 790 bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level,
 791                 uint32_t frame_ramp, const struct dc_stream *stream);
 792
 793 bool dc_link_set_abm_disable(const struct dc_link *dc_link);
 794
 795 bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable);
 796
 797 bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state);
 798
 799 bool dc_link_setup_psr(struct dc_link *dc_link,
 800                 const struct dc_stream *stream, struct psr_config *psr_config,
 801                 struct psr_context *psr_context);
 802
 803 /* Request DC to detect if there is a Panel connected.
 804  * boot - If this call is during initial boot.
 805  * Return false for any type of detection failure or MST detection
 806  * true otherwise. True meaning further action is required (status update
 807  * and OS notification).
 808  */
 809 bool dc_link_detect(struct dc_link *dc_link, bool boot);
 810
 811 /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
 812  * Return:
 813  * true - Downstream port status changed. DM should call DC to do the
 814  * detection.
 815  * false - no change in Downstream port status. No further action required
 816  * from DM. */
 817 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
 818                 union hpd_irq_data *hpd_irq_dpcd_data);
 819
 820 struct dc_sink_init_data;
 821
 822 struct dc_sink *dc_link_add_remote_sink(
 823                 struct dc_link *dc_link,
 824                 const uint8_t *edid,
 825                 int len,
 826                 struct dc_sink_init_data *init_data);
 827
 828 void dc_link_remove_remote_sink(
 829         struct dc_link *link,
 830         struct dc_sink *sink);
 831
 832 /* Used by diagnostics for virtual link at the moment */
 833 void dc_link_set_sink(struct dc_link *link, struct dc_sink *sink);
 834
 835 void dc_link_dp_set_drive_settings(
 836         struct dc_link *link,
 837         struct link_training_settings *lt_settings);
 838
 839 enum link_training_result dc_link_dp_perform_link_training(
 840         struct dc_link *link,
 841         const struct dc_link_settings *link_setting,
 842         bool skip_video_pattern);
 843
 844 void dc_link_dp_enable_hpd(const struct dc_link *link);
 845
 846 void dc_link_dp_disable_hpd(const struct dc_link *link);
 847
 848 bool dc_link_dp_set_test_pattern(
 849         struct dc_link *link,
 850         enum dp_test_pattern test_pattern,
 851         const struct link_training_settings *p_link_settings,
 852         const unsigned char *p_custom_pattern,
 853         unsigned int cust_pattern_size);
 854
 855 /*******************************************************************************
 856  * Sink Interfaces - A sink corresponds to a display output device
 857  ******************************************************************************/
 858
 859 struct dc_container_id {
 860         // 128bit GUID in binary form
 861         unsigned char  guid[16];
 862         // 8 byte port ID -> ELD.PortID
 863         unsigned int   portId[2];
 864         // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
 865         unsigned short manufacturerName;
 866         // 2 byte product code -> ELD.ProductCode
 867         unsigned short productCode;
 868 };
 869
 870
 871
 872 /*
 873  * The sink structure contains EDID and other display device properties
 874  */
 875 struct dc_sink {
 876         enum signal_type sink_signal;
 877         struct dc_edid dc_edid; /* raw edid */
 878         struct dc_edid_caps edid_caps; /* parse display caps */
 879         struct dc_container_id *dc_container_id;
 880         uint32_t dongle_max_pix_clk;
 881         void *priv;
 882         struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
 883         bool converter_disable_audio;
 884
 885         /* private to DC core */
 886         struct dc_link *link;
 887         struct dc_context *ctx;
 888
 889         /* private to dc_sink.c */
 890         int ref_count;
 891 };
 892
 893 void dc_sink_retain(struct dc_sink *sink);
 894 void dc_sink_release(struct dc_sink *sink);
 895
 896 const struct audio **dc_get_audios(struct dc *dc);
 897
 898 struct dc_sink_init_data {
 899         enum signal_type sink_signal;
 900         struct dc_link *link;
 901         uint32_t dongle_max_pix_clk;
 902         bool converter_disable_audio;
 903 };
 904
 905 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
 906 bool dc_sink_get_container_id(struct dc_sink *dc_sink, struct dc_container_id *container_id);
 907 bool dc_sink_set_container_id(struct dc_sink *dc_sink, const struct dc_container_id *container_id);
 908
 909 /*******************************************************************************
 910  * Cursor interfaces - To manages the cursor within a stream
 911  ******************************************************************************/
 912 /* TODO: Deprecated once we switch to dc_set_cursor_position */
 913 bool dc_stream_set_cursor_attributes(
 914         const struct dc_stream *stream,
 915         const struct dc_cursor_attributes *attributes);
 916
 917 bool dc_stream_set_cursor_position(
 918         const struct dc_stream *stream,
 919         const struct dc_cursor_position *position);
 920
 921 /* Newer interfaces  */
 922 struct dc_cursor {
 923         struct dc_plane_address address;
 924         struct dc_cursor_attributes attributes;
 925 };
 926
 927 /*******************************************************************************
 928  * Interrupt interfaces
 929  ******************************************************************************/
 930 enum dc_irq_source dc_interrupt_to_irq_source(
 931                 struct dc *dc,
 932                 uint32_t src_id,
 933                 uint32_t ext_id);
 934 void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable);
 935 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
 936 enum dc_irq_source dc_get_hpd_irq_source_at_index(
 937                 struct dc *dc, uint32_t link_index);
 938
 939 /*******************************************************************************
 940  * Power Interfaces
 941  ******************************************************************************/
 942
 943 void dc_set_power_state(
 944                 struct dc *dc,
 945                 enum dc_acpi_cm_power_state power_state);
 946 void dc_resume(const struct dc *dc);
 947
 948 /*
 949  * DPCD access interfaces
 950  */
 951
 952 bool dc_read_aux_dpcd(
 953                 struct dc *dc,
 954                 uint32_t link_index,
 955                 uint32_t address,
 956                 uint8_t *data,
 957                 uint32_t size);
 958
 959 bool dc_write_aux_dpcd(
 960                 struct dc *dc,
 961                 uint32_t link_index,
 962                 uint32_t address,
 963                 const uint8_t *data,
 964                 uint32_t size);
 965
 966 bool dc_read_aux_i2c(
 967                 struct dc *dc,
 968                 uint32_t link_index,
 969                 enum i2c_mot_mode mot,
 970                 uint32_t address,
 971                 uint8_t *data,
 972                 uint32_t size);
 973
 974 bool dc_write_aux_i2c(
 975                 struct dc *dc,
 976                 uint32_t link_index,
 977                 enum i2c_mot_mode mot,
 978                 uint32_t address,
 979                 const uint8_t *data,
 980                 uint32_t size);
 981
 982 bool dc_query_ddc_data(
 983                 struct dc *dc,
 984                 uint32_t link_index,
 985                 uint32_t address,
 986                 uint8_t *write_buf,
 987                 uint32_t write_size,
 988                 uint8_t *read_buf,
 989                 uint32_t read_size);
 990
 991 bool dc_submit_i2c(
 992                 struct dc *dc,
 993                 uint32_t link_index,
 994                 struct i2c_command *cmd);
 995
 996
 997 #endif /* DC_INTERFACE_H_ */